#ifndef CPUEMU_68000_ONLY
{ op_f800_0_ff, NULL, 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_0 */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_1[] = {
{ op_f610_0_ff, NULL, 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ op_f618_0_ff, NULL, 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ op_f620_0_ff, NULL, 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_2[] = {
{ op_f379_0_ff, NULL, 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37a_0_ff, NULL, 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37b_0_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_3[] = {
{ op_f379_0_ff, NULL, 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37a_0_ff, NULL, 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37b_0_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_4[] = {
{ op_e7f0_4_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_0_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_0_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_5[] = {
{ op_e7f0_4_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_0_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_0_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifdef CPUEMU_11
const struct cputbl op_smalltbl_11[] = {
{ op_e7f0_11_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_11_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_11_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_11 */
const struct cputbl op_smalltbl_12[] = {
{ op_0000_12_ff, NULL, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ op_e7f0_12_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_12_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_12_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#ifdef CPUEMU_13
const struct cputbl op_smalltbl_13[] = {
{ NULL, op_0000_13_ff, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ NULL, op_e7f0_13_ff, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ NULL, op_e7f8_13_ff, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ NULL, op_e7f9_13_ff, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_13 */
const struct cputbl op_smalltbl_14[] = {
{ NULL, op_0000_14_ff, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ NULL, op_e7f0_14_ff, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ NULL, op_e7f8_14_ff, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ NULL, op_e7f9_14_ff, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#ifdef CPUEMU_20
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_20[] = {
#ifndef CPUEMU_68000_ONLY
{ op_f37b_20_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_20 */
#ifdef CPUEMU_21
#ifndef CPUEMU_68000_ONLY
{ NULL, op_f37b_21_ff, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_21 */
#ifdef CPUEMU_22
#ifndef CPUEMU_68000_ONLY
{ op_f37b_22_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_22 */
#ifdef CPUEMU_23
#ifndef CPUEMU_68000_ONLY
{ NULL, op_f37b_23_ff, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_23 */
#ifdef CPUEMU_24
#ifndef CPUEMU_68000_ONLY
{ NULL, op_f800_24_ff, 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_24 */
#ifndef CPUEMU_68000_ONLY
{ NULL, op_f610_24_ff, 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ NULL, op_f618_24_ff, 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ NULL, op_f620_24_ff, 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifdef CPUEMU_31
#ifndef CPUEMU_68000_ONLY
#ifndef CPUEMU_68000_ONLY
{ op_f620_31_ff, NULL, 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_31 */
#ifdef CPUEMU_32
#ifndef CPUEMU_68000_ONLY
{ op_f37b_32_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_32 */
#ifdef CPUEMU_33
#ifndef CPUEMU_68000_ONLY
{ op_f800_33_ff, NULL, 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_33 */
#ifdef CPUEMU_34
#ifndef CPUEMU_68000_ONLY
{ op_f37b_34_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_34 */
#ifdef CPUEMU_35
#ifndef CPUEMU_68000_ONLY
{ NULL, op_f37b_35_ff, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#endif /* CPUEMU_35 */
#ifdef CPUEMU_40
#ifndef CPUEMU_68000_ONLY
{ op_f800_40_ff, NULL, 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_40 */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_41[] = {
{ op_f610_40_ff, NULL, 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ op_f618_40_ff, NULL, 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ op_f620_40_ff, NULL, 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_42[] = {
{ op_f379_40_ff, NULL, 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37a_40_ff, NULL, 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37b_40_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_43[] = {
{ op_f379_40_ff, NULL, 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37a_40_ff, NULL, 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37b_40_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_44[] = {
{ op_e7f0_44_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_40_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_40_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_45[] = {
{ op_e7f0_44_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_40_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_40_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
const struct cputbl op_smalltbl_46[] = {
{ op_0000_40_ff, NULL, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ op_e7f0_44_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_40_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_40_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
const struct cputbl op_smalltbl_47[] = {
{ op_0000_40_ff, NULL, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ op_0010_40_ff, NULL, 0x0010, 4, { 0, 0 }, 0 }, /* OR */
{ op_e7f0_44_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_40_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_40_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
const struct cputbl op_smalltbl_48[] = {
{ op_0000_40_ff, NULL, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ op_0010_40_ff, NULL, 0x0010, 4, { 0, 0 }, 0 }, /* OR */
{ op_e7f0_44_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_40_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_40_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
const struct cputbl op_smalltbl_49[] = {
{ op_0000_40_ff, NULL, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
{ op_0010_40_ff, NULL, 0x0010, 4, { 0, 0 }, 0 }, /* OR */
{ op_e7f0_44_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_40_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_40_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#ifdef CPUEMU_50
const struct cputbl op_smalltbl_50[] = {
{ op_0000_50_ff, NULL, 0x0000, 4, { 0, 0 }, 0 }, /* OR */
#ifndef CPUEMU_68000_ONLY
{ op_f800_50_ff, NULL, 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
#endif
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_50 */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_51[] = {
{ op_f610_50_ff, NULL, 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ op_f618_50_ff, NULL, 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
{ op_f620_50_ff, NULL, 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_52[] = {
{ op_f379_50_ff, NULL, 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37a_50_ff, NULL, 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37b_50_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_53[] = {
{ op_f379_50_ff, NULL, 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37a_50_ff, NULL, 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
{ op_f37b_50_ff, NULL, 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_54[] = {
{ op_e7f0_54_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_50_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_50_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */
#ifndef CPUEMU_68000_ONLY
const struct cputbl op_smalltbl_55[] = {
{ op_e7f0_54_ff, NULL, 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
{ op_e7f8_50_ff, NULL, 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
{ op_e7f9_50_ff, NULL, 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
-{ 0, 0 }};
+{ NULL, NULL, 0, 0, { 0, 0 }, 0 } };
#endif /* CPUEMU_68000_ONLY */