}
}
-STATIC_INLINE void record_dma_blit (uae_u16 reg, uae_u16 dat, uae_u32 addr, int hpos)
+static void record_dma_blit_val(uae_u32 v)
{
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (reg, dat, addr, hpos, vpos, DMARECORD_BLITTER, blitline ? 2 : (blitfill ? 1 : 0));
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(v);
+ }
+#endif
+}
+
+static void record_dma_blit(uae_u16 reg, uae_u16 v, uae_u32 addr, int hpos)
+{
+#ifdef DEBUGGER
+ if (debug_dma) {
+ if (reg == 0) {
+ record_dma_write(reg, v, addr, hpos, vpos, DMARECORD_BLITTER, blitline ? 2 : (blitfill ? 1 : 0));
+ } else {
+ record_dma_read(reg, addr, hpos, vpos, DMARECORD_BLITTER, blitline ? 2 : (blitfill ? 1 : 0));
+ }
+ }
if (memwatch_enabled) {
if (reg == 0) {
uae_u32 mask = MW_MASK_BLITTER_D_N;
mask = MW_MASK_BLITTER_D_F;
if (blitline)
mask = MW_MASK_BLITTER_D_L;
- debug_wputpeekdma_chipram(addr, dat, mask, reg, 0x054);
+ debug_putpeekdma_chipram(addr, v, mask, reg, 0x054);
} else if (reg == 0x70) {
- debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_C, reg, 0x48);
+ debug_getpeekdma_chipram(addr, MW_MASK_BLITTER_C, reg, 0x48);
} else if (reg == 0x72) {
- debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_B, reg, 0x4c);
+ debug_getpeekdma_chipram(addr, MW_MASK_BLITTER_B, reg, 0x4c);
} else if (reg == 0x74) {
- debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_A, reg, 0x52);
+ debug_getpeekdma_chipram(addr, MW_MASK_BLITTER_A, reg, 0x52);
}
}
#endif
{
//last_custom_value1 = w; blitter writes are not stored
if (!(log_blitter & 4)) {
+ debug_putpeekdma_chipram(addr, w, MW_MASK_BLITTER_D_N, 0x000, 0x054);
chipmem_wput_indirect (addr, w);
- debug_wputpeekdma_chipram (addr, w, MW_MASK_BLITTER_D_N, 0x000, 0x054);
}
}
if (!dmaen (DMA_BLITTER))
return;
blt_info.bltcdat = chipmem_wget_indirect (bltcpt);
- debug_wgetpeekdma_chipram (bltcpt, blt_info.bltcdat, MW_MASK_BLITTER_C, 0x070, 0x048);
last_custom_value1 = blt_info.bltcdat;
}
bltstate = BLT_work;
if (bltcon0 & 0x200) {
if (!dmaen (DMA_BLITTER))
return;
- //last_custom_value1 = blt_info.bltddat; blitter writes are not stored
chipmem_wput_indirect (bltdpt, blt_info.bltddat);
- debug_wputpeekdma_chipram (bltdpt, blt_info.bltddat, MW_MASK_BLITTER_D_N, 0x000, 0x054);
}
bltstate = BLT_next;
}
if (c == 3) {
- blitter_read ();
+ record_dma_blit(0x70, 0, bltcpt, last_blitter_hpos);
+ blitter_read();
+ record_dma_blit_val(blt_info.bltcdat);
alloc_cycle_blitter (last_blitter_hpos, &bltcpt, 3);
- record_dma_blit (0x70, blt_info.bltcdat, bltcpt, last_blitter_hpos);
} else if (c == 5) {
/* onedot mode and no pixel = bus write access is skipped */
if (blitlinepixel) {
+ record_dma_blit(0x00, blt_info.bltddat, bltdpt, last_blitter_hpos);
blitter_write ();
alloc_cycle_blitter (last_blitter_hpos, &bltdpt, 4);
- record_dma_blit (0x00, blt_info.bltddat, bltdpt, last_blitter_hpos);
blitlinepixel = 0;
}
if (blt_info.vblitsize == 0) {
{
if (blitline) {
do {
+ record_dma_blit(0x70, 0, bltcpt, last_blitter_hpos);
blitter_read ();
+ record_dma_blit_val(blt_info.bltcdat);
if (ddat1use)
bltdpt = bltcpt;
ddat1use = 1;
blitter_line_proc ();
blitter_nxline ();
if (blitlinepixel) {
+ record_dma_blit(0x00, blt_info.bltddat, bltdpt, last_blitter_hpos);
blitter_write ();
blitlinepixel = 0;
}
}
return;
}
- record_dma_blit (0x00, d, bltdpt, hpos);
- //last_custom_value1 = d; blitter writes are not stored
+ record_dma_blit(0x00, d, bltdpt, hpos);
chipmem_agnus_wput2 (bltdpt, d);
alloc_cycle_blitter (hpos, &bltdpt, 4);
bltdpt += blit_add;
switch (ch)
{
case 1:
+ reg = 0x74;
+ record_dma_blit(reg, 0, bltapt, hpos);
blt_info.bltadat = dat = chipmem_wget_indirect (bltapt);
+ record_dma_blit_val(dat);
last_custom_value1 = blt_info.bltadat;
addr = bltapt;
bltapt += blit_add;
- reg = 0x74;
alloc_cycle_blitter (hpos, &bltapt, 1);
break;
case 2:
+ reg = 0x72;
+ record_dma_blit(reg, 0, bltbpt, hpos);
blt_info.bltbdat = dat = chipmem_wget_indirect (bltbpt);
+ record_dma_blit_val(dat);
last_custom_value1 = blt_info.bltbdat;
addr = bltbpt;
bltbpt += blit_add;
else
blt_info.bltbhold = (((uae_u32)blt_info.bltbold << 16) | blt_info.bltbdat) >> blt_info.blitbshift;
blt_info.bltbold = blt_info.bltbdat;
- reg = 0x72;
alloc_cycle_blitter (hpos, &bltbpt, 2);
break;
case 3:
+ reg = 0x70;
+ record_dma_blit(reg, 0, bltcpt, hpos);
blt_info.bltcdat = dat = chipmem_wget_indirect (bltcpt);
+ record_dma_blit_val(dat);
last_custom_value1 = blt_info.bltcdat;
addr = bltcpt;
bltcpt += blit_add;
- reg = 0x70;
alloc_cycle_blitter (hpos, &bltcpt, 3);
break;
default:
blitfc = !!(bltcon1 & 0x4);
}
}
- record_dma_blit (reg, dat, addr, hpos);
}
int blitter_need (int hpos)
bpl1dat_written = true;
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0x110 + nr * 2, chipmem_wget_indirect (p), p, hpos, vpos, DMARECORD_BITPLANE, nr);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(p, chipmem_wget_indirect (p), MW_MASK_BPL_0 << nr, 0x110 + nr * 2, 0xe0 + nr * 4);
+ if (debug_dma) {
+ record_dma_read(0x110 + nr * 2, p, hpos, vpos, DMARECORD_BITPLANE, nr);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(p, MW_MASK_BPL_0 << nr, 0x110 + nr * 2, 0xe0 + nr * 4);
+ }
+ uae_u32 v = aga_mode ? chipmem_lget_indirect(p & ~3) : chipmem_wget_indirect(p);
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(v);
+ }
#endif
switch (fm)
{
#ifdef DEBUGGER
if (debug_dma) {
record_dma_event(DMA_EVENT_NOONEGETS, hpos, vpos);
- record_dma (0x1fe, chipmem_wget_indirect (cop_state.ip), cop_state.ip, hpos, vpos, DMARECORD_COPPER, 2);
+ record_dma_read(0x1fe, cop_state.ip, hpos, vpos, DMARECORD_COPPER, 2);
+ uae_u16 v = chipmem_wget_indirect(cop_state.ip);
+ record_dma_read_value(v);
}
#endif
}
int v;
hpos += hack_delay_shift;
- value = debug_wputpeekdma_chipset (0xdff000 + addr, value, MW_MASK_COPPER, 0x08c);
+ value = debug_putpeekdma_chipset(0xdff000 + addr, value, MW_MASK_COPPER, 0x08c);
copper_access = 1;
v = custom_wput_1 (hpos, addr, value, noget);
copper_access = 0;
if (!copper_cant_read(old_hpos, 0)) {
alloc_cycle(old_hpos, CYCLE_COPPER);
#ifdef DEBUGGER
- if (debug_dma)
- record_dma(0x8c, chipmem_wget_indirect(cop_state.ip), cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect(cop_state.ip), MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ if (debug_dma) {
+ record_dma_read(0x8c, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ }
+ uae_u16 v = chipmem_wget_indirect(cop_state.ip);
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(v);
+ }
#endif
// copper pointer is only increased if cycle was free
cop_state.ip += 2;
continue;
alloc_cycle (old_hpos, CYCLE_COPPER);
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0x1fe, chipmem_wget_indirect (cop_state.ip), cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x1fe, 0x1fe);
+ {
+ if (debug_dma) {
+ record_dma_read(0x1fe, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip, MW_MASK_COPPER, 0x1fe, 0x1fe);
+ }
+ uae_u16 v = chipmem_wget_indirect(cop_state.ip);
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(v);
+ }
+ }
#endif
cop_state.state = COP_read1;
// Next cycle finally reads from new pointer
// If Blitter uses this cycle = Copper's PC gets copied to blitter DMA pointer..
if (copper_cant_read (old_hpos, 1))
continue;
- if (debug_dma)
+ if (debug_dma) {
record_dma_event(DMA_EVENT_SPECIAL, old_hpos, vpos);
+ }
cycle_line[old_hpos] |= CYCLE_COPPER_SPECIAL;
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0x1fe, chipmem_wget_indirect (cop_state.ip), cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x1fe, 0x1fe);
+ {
+ if (debug_dma) {
+ record_dma_read(0x1fe, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip, MW_MASK_COPPER, 0x1fe, 0x1fe);
+ }
+ uae_u16 v = chipmem_wget_indirect(cop_state.ip);
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(v);
+ }
+ }
#endif
cop_state.state = COP_read1;
// Next cycle finally reads from new pointer
if (copper_cant_read (old_hpos, 1))
continue;
cop_state.state = COP_read1;
- cop_state.i1 = last_custom_value1 = last_custom_value2 = chipmem_wget_indirect (cop_state.ip);
- alloc_cycle (old_hpos, CYCLE_COPPER);
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0x1fe, cop_state.i1, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip, cop_state.i1, MW_MASK_COPPER, 0x1fe, 0x1fe);
+ if (debug_dma) {
+ record_dma_read(0x1fe, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip, MW_MASK_COPPER, 0x1fe, 0x1fe);
+ }
#endif
+ cop_state.i1 = last_custom_value1 = last_custom_value2 = chipmem_wget_indirect(cop_state.ip);
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read_value(cop_state.i1);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(cop_state.i1);
+ }
+#endif
+ alloc_cycle(old_hpos, CYCLE_COPPER);
cop_state.ip = cop1lc;
break;
case COP_read1:
if (copper_cant_read (old_hpos, 1))
continue;
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read(0x8c, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ }
+#endif
cop_state.i1 = last_custom_value1 = last_custom_value2 = chipmem_wget_indirect (cop_state.ip);
- alloc_cycle (old_hpos, CYCLE_COPPER);
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0x8c, cop_state.i1, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip, cop_state.i1, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ if (debug_dma) {
+ record_dma_read_value(cop_state.i1);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(cop_state.i1);
+ }
#endif
+ alloc_cycle (old_hpos, CYCLE_COPPER);
cop_state.ip += 2;
cop_state.state = COP_read2;
break;
case COP_read2:
if (copper_cant_read (old_hpos, 1))
continue;
- cop_state.i2 = chipmem_wget_indirect (cop_state.ip);
- alloc_cycle (old_hpos, CYCLE_COPPER);
- cop_state.ip += 2;
- cop_state.saved_i1 = cop_state.i1;
- cop_state.saved_i2 = cop_state.i2;
- cop_state.saved_ip = cop_state.ip;
-
if (cop_state.i1 & 1) { // WAIT or SKIP
+
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read(0x8c, cop_state.ip - 2, old_hpos, vpos, DMARECORD_COPPER, (cop_state.i1 & 1) ? 1 : 0);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip - 2, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ }
+#endif
+ cop_state.i2 = chipmem_wget_indirect(cop_state.ip);
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read_value(cop_state.i2);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(cop_state.i2);
+ }
+#endif
+ alloc_cycle(old_hpos, CYCLE_COPPER);
+ cop_state.ip += 2;
+ cop_state.saved_i1 = cop_state.i1;
+ cop_state.saved_i2 = cop_state.i2;
+ cop_state.saved_ip = cop_state.ip;
+
cop_state.ignore_next = 0;
if (cop_state.i2 & 1)
cop_state.state = COP_skip_in2;
else
cop_state.state = COP_wait_in2;
+
+ } else { // MOVE
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0x8c, cop_state.i2, cop_state.ip - 2, old_hpos, vpos, DMARECORD_COPPER, (cop_state.i1 & 1) ? 1 : 0);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip - 2, cop_state.i2, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ if (debug_dma) {
+ record_dma_read(0x8c, cop_state.ip - 2, old_hpos, vpos, DMARECORD_COPPER, 0);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(cop_state.ip - 2, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
+ }
#endif
- } else { // MOVE
+ cop_state.i2 = chipmem_wget_indirect(cop_state.ip);
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read_value(cop_state.i2);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(cop_state.i2);
+ }
+#endif
+ alloc_cycle(old_hpos, CYCLE_COPPER);
+ cop_state.ip += 2;
+ cop_state.saved_i1 = cop_state.i1;
+ cop_state.saved_i2 = cop_state.i2;
+ cop_state.saved_ip = cop_state.ip;
+
#ifdef DEBUGGER
uaecptr debugip = cop_state.ip;
#endif
unsigned int reg = cop_state.i1 & 0x1FE;
uae_u16 data = cop_state.i2;
cop_state.state = COP_read1;
-#ifdef DEBUGGER
- if (debug_dma)
- record_dma (reg, data, cop_state.ip - 2, old_hpos, vpos, DMARECORD_COPPER, 0);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(cop_state.ip - 2, data, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80);
-#endif
+
test_copper_dangerous (reg);
if (! copper_enabled_thisline)
goto out; // was "dangerous" register -> copper stopped
}
#ifdef DEBUGGER
if (debug_copper && !cop_state.ignore_next)
- record_copper (debugip - 4, cop_state.saved_i1, cop_state.saved_i2, old_hpos, vpos);
+ record_copper(debugip - 4, cop_state.saved_i1, cop_state.saved_i2, old_hpos, vpos);
#endif
cop_state.ignore_next = 0;
}
if (dma) {
if (cycle && currprefs.cpu_memory_cycle_exact)
s->ptxhpos = hpos;
- data = last_custom_value1 = chipmem_wget_indirect (pt);
- alloc_cycle (hpos, CYCLE_SPRITE);
#ifdef DEBUGGER
int num = s - &spr[0];
- if (debug_dma)
- record_dma (num * 8 + 0x140 + mode * 4 + cycle * 2, data, pt, hpos, vpos, DMARECORD_SPRITE, num);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(pt, data, MW_MASK_SPR_0 << num, num * 8 + 0x140 + mode * 4 + cycle * 2, num * 4 + 0x120);
+ if (debug_dma) {
+ record_dma_read(num * 8 + 0x140 + mode * 4 + cycle * 2, pt, hpos, vpos, DMARECORD_SPRITE, num);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(pt, MW_MASK_SPR_0 << num, num * 8 + 0x140 + mode * 4 + cycle * 2, num * 4 + 0x120);
+ }
#endif
+ data = last_custom_value1 = chipmem_wget_indirect(pt);
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read_value(data);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(data);
+ }
+#endif
+ alloc_cycle (hpos, CYCLE_SPRITE);
}
return data;
}
v -= 6;
int nr = v / 2;
uaecptr pt = audio_getpt (nr, (v & 1) != 0);
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read(0xaa + nr * 16, pt, hpos, vpos, DMARECORD_AUDIO, nr);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(pt, MW_MASK_AUDIO_0 << nr, 0xaa + nr * 16, 0xa0 + nr * 16);
+ }
+#endif
uae_u16 dat = chipmem_wget_indirect (pt);
#ifdef DEBUGGER
- if (debug_dma)
- record_dma (0xaa + nr * 16, dat, pt, hpos, vpos, DMARECORD_AUDIO, nr);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(pt, dat, MW_MASK_AUDIO_0 << nr, 0xaa + nr * 16, 0xa0 + nr * 16);
+ if (debug_dma) {
+ record_dma_read_value(dat);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(dat);
+ }
#endif
last_custom_value1 = last_custom_value2 = dat;
AUDxDAT (nr, dat, pt);
if (w) {
// write to disk
if (disk_fifostatus () <= 0) {
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read(0x26, pt, hpos, vpos, DMARECORD_DISK, v / 2);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_chipram(pt, MW_MASK_DISK, 0x26, 0x20);
+ }
+#endif
dat = chipmem_wget_indirect (pt);
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_read_value(dat);
+ }
+ if (memwatch_enabled) {
+ debug_getpeekdma_value(dat);
+ }
+#endif
last_custom_value1 = last_custom_value2 = dat;
DSKDAT (dat);
}
// read from disk
if (disk_fifostatus () >= 0) {
dat = DSKDATR ();
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_dma_write(0x08, dat, pt, hpos, vpos, DMARECORD_DISK, v / 2);
+ }
+ if (memwatch_enabled) {
+ debug_putpeekdma_chipram(pt, dat, MW_MASK_DISK, 0x08, 0x20);
+ }
+#endif
chipmem_wput_indirect (pt, dat);
}
}
-#ifdef DEBUGGER
- if (debug_dma)
- record_dma (w ? 0x26 : 0x08, dat, pt, hpos, vpos, DMARECORD_DISK, v / 2);
- if (memwatch_enabled)
- debug_wgetpeekdma_chipram(pt, dat, MW_MASK_DISK, w ? 0x26 : 0x08, 0x20);
-#endif
}
}
while (!currprefs.turbo_emulation && sync_timeout_check(maxtime)) {
maybe_process_pull_audio();
vp = target_get_display_scanline(-1);
- if (vp >= 0)
+ if (vp >= 0 && vp < vp < vsync_activeheight / 2)
break;
if (currprefs.m68k_speed < 0 && !was_syncline) {
is_syncline = -3;
strobe = 0x38;
else if ((currprefs.chipset_mask & CSMASK_ECS_AGNUS) && lol)
strobe = 0x3e;
- record_dma (i == 0 ? strobe : 0x1fe, 0xffff, 0xffffffff, hp, vpos, DMARECORD_REFRESH, i);
+ record_dma_read(i == 0 ? strobe : 0x1fe, 0xffffffff, hp, vpos, DMARECORD_REFRESH, i);
+ record_dma_read_value(0xffff);
}
#endif
hp += 2;
int i, dummy;
uae_u32 dskpt;
uae_u16 dsklen, dsksync, dskbytr;
+ uae_u16 v;
DISK_save_custom (&dskpt, &dsklen, &dsksync, &dskbytr);
SW (ADKCONR ()); /* 010 ADKCONR */
SW (POT0DAT ()); /* 012 POT0DAT */
SW (POT1DAT ()); /* 014 POT1DAT */
- SW (0) ; /* 016 POTINP * */
+ SW (0); /* 016 POTINP * */
SW (0); /* 018 SERDATR * */
SW (dskbytr); /* 01A DSKBYTR */
SW (INTENAR ()); /* 01C INTENAR */
SL (bltbpt); /* 04C-04F BLTCPT */
SL (bltapt); /* 050-053 BLTCPT */
SL (bltdpt); /* 054-057 BLTCPT */
- SW (0); /* 058 BLTSIZE */
- SW (0); /* 05A BLTCON0L (use BLTCON0 instead) */
+ if (blt_info.vblitsize > 1024 || blt_info.hblitsize > 64) {
+ v = 0;
+ } else {
+ v = (blt_info.vblitsize << 6) | (blt_info.hblitsize & 63);
+ }
+ SW (v); /* 058 BLTSIZE */
+ SW (bltcon0 & 0xff); /* 05A BLTCON0L (use BLTCON0 instead) */
SW (blt_info.vblitsize);/* 05C BLTSIZV */
SW (blt_info.hblitsize);/* 05E BLTSIZH */
SW (blt_info.bltcmod); /* 060 BLTCMOD */
x_do_cycles_pre (CYCLE_UNIT);
#ifdef DEBUGGER
- struct dma_rec *dr = NULL;
if (debug_dma) {
int reg = 0x1000;
if (mode < 0)
reg |= 2;
else
reg |= 1;
- dr = record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU, mode == -2 || mode == 2 ? 0 : 1);
+ record_dma_read(reg, addr, hpos, vpos, DMARECORD_CPU, mode == -2 || mode == 2 ? 0 : 1);
checknasty (hpos, vpos);
}
+ peekdma_data.mask = 0;
#endif
switch(mode)
{
}
#ifdef DEBUGGER
- if (debug_dma)
- dr->dat = v;
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
#endif
x_do_cycles_post (CYCLE_UNIT, v);
x_do_cycles_pre (CYCLE_UNIT);
#ifdef DEBUGGER
- struct dma_rec *dr = NULL;
if (debug_dma) {
int reg = 0x1000;
if (mode < 0)
reg |= 2;
else
reg |= 1;
- dr = record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU, mode == -2 || mode == 2 ? 0 : 1);
+ record_dma_read(reg, addr, hpos, vpos, DMARECORD_CPU, mode == -2 || mode == 2 ? 0 : 1);
checknasty (hpos, vpos);
}
+ peekdma_data.mask = 0;
#endif
switch (mode) {
case -1:
}
#ifdef DEBUGGER
- if (debug_dma)
- dr->dat = v;
+ if (debug_dma) {
+ record_dma_read_value(v);
+ }
#endif
x_do_cycles_post (CYCLE_UNIT, v);
reg |= 2;
else
reg |= 1;
- record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU, 1);
+ record_dma_write(reg, v, addr, hpos, vpos, DMARECORD_CPU, 1);
checknasty (hpos, vpos);
}
+ peekdma_data.mask = 0;
#endif
if (mode < 0)
reg |= 2;
else
reg |= 1;
- record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU, 1);
+ record_dma_write(reg, v, addr, hpos, vpos, DMARECORD_CPU, 1);
checknasty (hpos, vpos);
}
+ peekdma_data.mask = 0;
#endif
if (mode < 0)
dr->extra = extra;
}
-struct dma_rec *record_dma (uae_u16 reg, uae_u16 dat, uae_u32 addr, int hpos, int vpos, int type, int extra)
+void record_dma_write(uae_u16 reg, uae_u32 dat, uae_u32 addr, int hpos, int vpos, int type, int extra)
+{
+ struct dma_rec* dr;
+
+ if (!dma_record[0]) {
+ dma_record[0] = xmalloc(struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
+ dma_record[1] = xmalloc(struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
+ dma_record_toggle = 0;
+ record_dma_reset();
+ dma_record_frame[0] = -1;
+ dma_record_frame[1] = -1;
+ }
+
+ if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
+ return;
+
+ dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
+ dma_record_frame[dma_record_toggle] = timeframes;
+ if (dr->reg != 0xffff) {
+ write_log(_T("DMA conflict: v=%d h=%d OREG=%04X NREG=%04X\n"), vpos, hpos, dr->reg, reg);
+ return;
+ }
+ dr->reg = reg;
+ dr->dat = dat;
+ dr->addr = addr;
+ dr->type = type;
+ dr->extra = extra;
+ dr->intlev = regs.intmask;
+ last_dma_rec = dr;
+}
+struct dma_rec *last_dma_rec;
+void record_dma_read_value(uae_u32 v)
+{
+ if (last_dma_rec) {
+ last_dma_rec->dat = v;
+ }
+}
+void record_dma_read(uae_u16 reg, uae_u32 addr, int hpos, int vpos, int type, int extra)
{
struct dma_rec *dr;
}
if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
- return NULL;
+ return;
dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
dma_record_frame[dma_record_toggle] = timeframes;
if (dr->reg != 0xffff) {
write_log (_T("DMA conflict: v=%d h=%d OREG=%04X NREG=%04X\n"), vpos, hpos, dr->reg, reg);
- return dr;
+ return;
}
dr->reg = reg;
- dr->dat = dat;
+ dr->dat = 0;
dr->addr = addr;
dr->type = type;
dr->extra = extra;
dr->intlev = regs.intmask;
- return dr;
+ last_dma_rec = dr;
}
return debug_mem_banks[munge24 (addr) >> 16]->xlateaddr (addr);
}
-uae_u16 debug_wputpeekdma_chipset (uaecptr addr, uae_u32 v, uae_u32 mask, int reg)
+struct peekdma peekdma_data;
+
+static void peekdma_save(int type, uaecptr addr, uae_u32 mask, int reg, int ptrreg)
{
- if (!memwatch_enabled)
- return v;
- addr &= 0x1fe;
- addr += 0xdff000;
- memwatch_func (addr, 2, 2, &v, mask, reg);
- return v;
+ peekdma_data.type = type;
+ peekdma_data.addr = addr;
+ peekdma_data.mask = mask;
+ peekdma_data.reg = reg;
+ peekdma_data.ptrreg = ptrreg;
}
-uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg)
+
+uae_u32 debug_getpeekdma_value(uae_u32 v)
{
+ uae_u32 vv = v;
if (!memwatch_enabled)
return v;
- is_valid_dma(reg, ptrreg, addr);
- if (debug_mem_banks[addr >> 16] == NULL)
+ is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr);
+ if (debug_mem_banks[peekdma_data.addr >> 16] == NULL)
return v;
if (!currprefs.z3chipmem.size)
- addr &= chipmem_bank.mask;
- memwatch_func (addr & chipmem_bank.mask, 2, 2, &v, mask, reg);
+ peekdma_data.addr &= chipmem_bank.mask;
+ memwatch_func(peekdma_data.addr, 1, 2, &vv, peekdma_data.mask, peekdma_data.reg);
+ return vv;
+}
+
+uae_u32 debug_putpeekdma_chipset(uaecptr addr, uae_u32 v, uae_u32 mask, int reg)
+{
+ peekdma_save(0, addr, mask, reg, 0);
+ if (!memwatch_enabled)
+ return v;
+ peekdma_data.addr &= 0x1fe;
+ peekdma_data.addr += 0xdff000;
+ memwatch_func(peekdma_data.addr, 2, 2, &v, peekdma_data.mask, peekdma_data.reg);
return v;
}
-uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg)
+
+uae_u32 debug_putpeekdma_chipram(uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg)
{
- uae_u32 vv = v;
+ peekdma_save(1, addr, mask, reg, ptrreg);
if (!memwatch_enabled)
return v;
- is_valid_dma(reg, ptrreg, addr);
- if (debug_mem_banks[addr >> 16] == NULL)
+ is_valid_dma(peekdma_data.reg, peekdma_data.ptrreg, peekdma_data.addr);
+ if (debug_mem_banks[peekdma_data.addr >> 16] == NULL)
return v;
if (!currprefs.z3chipmem.size)
- addr &= chipmem_bank.mask;
- memwatch_func (addr, 1, 2, &vv, mask, reg);
- return vv;
+ peekdma_data.addr &= chipmem_bank.mask;
+ memwatch_func(peekdma_data.addr & chipmem_bank.mask, 2, 2, &v, peekdma_data.mask, peekdma_data.reg);
+}
+void debug_getpeekdma_chipram(uaecptr addr, uae_u32 mask, int reg, int ptrreg)
+{
+ peekdma_save(2, addr, mask, reg, ptrreg);
}
static void debug_putlpeek (uaecptr addr, uae_u32 v)
projects / francis / winuae.git / commitdiff