M-Tec E-Matrix 530.

diff --git a/cpuboard.cpp b/cpuboard.cpp
index f7e43f7e32da1ee20541c86dc4e0940f806cb502..262dfe4d123af9391d7b8eacd68bbed65d7f0c2a 100644 (file)
--- a/cpuboard.cpp
+++ b/cpuboard.cpp
@@ -282,6 +282,10 @@ static bool is_dkb_wildfire(void)
 {
        return ISCPUBOARD(BOARD_DKB, BOARD_DKB_SUB_WILDFIRE);
 }
+static bool is_mtec_ematrix530(void)
+{
+       return ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530);
+}
 static bool is_fusionforty(void)
 {
        return ISCPUBOARD(BOARD_RCS, BOARD_RCS_SUB_FUSIONFORTY);
@@ -709,6 +713,28 @@ static uae_u32 REGPARAM2 blizzardea_bget(uaecptr addr)
                } else {
                        v = blizzardea_bank.baseaddr[addr];
                }
+       } else if (is_mtec_ematrix530()) {
+               v = blizzardea_bank.baseaddr[addr];
+               if ((addr & 0xf800) == 0xe800) {
+                       if ((addr & 3) < 2) {
+                               map_banks(&dummy_bank, 0x10000000 >> 16, 0x8000000 >> 16, 0);
+                               if (custmem1_bank.allocated) {
+                                       map_banks(&custmem1_bank, (0x18000000 - custmem1_bank.allocated) >> 16, custmem1_bank.allocated >> 16, 0);
+                                       if (custmem1_bank.allocated < 128 * 1024 * 1024) {
+                                               map_banks(&custmem1_bank, (0x18000000 - 2 * custmem1_bank.allocated) >> 16, custmem1_bank.allocated >> 16, 0);
+                                       }
+                               }
+                       }
+                       if ((addr & 3) >= 2) {
+                               map_banks(&dummy_bank, 0x18000000 >> 16, 0x8000000 >> 16, 0);
+                               if (custmem2_bank.allocated) {
+                                       map_banks(&custmem2_bank, 0x18000000 >> 16, custmem2_bank.allocated >> 16, 0);
+                                       if (custmem2_bank.allocated < 128 * 1024 * 1024) {
+                                               map_banks(&custmem2_bank, (0x18000000 + custmem2_bank.allocated) >> 16, custmem2_bank.allocated >> 16, 0);
+                                       }
+                               }
+                       }
+               }
        } else {
                v = blizzardea_bank.baseaddr[addr];
        }
@@ -765,6 +791,19 @@ static void REGPARAM2 blizzardea_bput(uaecptr addr, uae_u32 b)
                        addr |= csmk2_flashaddressing;
                        flash_write(flashrom, addr, b);
                }
+       } else if (is_mtec_ematrix530()) {
+               if ((addr & 0xf800) == 0xe800) {
+                       if ((addr & 3) < 2) {
+                               map_banks(&dummy_bank, 0x10000000 >> 16, 0x8000000 >> 16, 0);
+                               if (custmem1_bank.allocated)
+                                       map_banks(&custmem1_bank, (0x18000000 - custmem1_bank.allocated) >> 16, custmem1_bank.allocated >> 16, 0);
+                       }
+                       if ((addr & 3) >= 2) {
+                               map_banks(&dummy_bank, 0x18000000 >> 16, 0x8000000 >> 16, 0);
+                               if (custmem2_bank.allocated)
+                                       map_banks(&custmem2_bank, 0x18000000 >> 16, custmem2_bank.allocated >> 16, 0);
+                       }
+               }
        }
 }
 
@@ -1518,7 +1557,7 @@ void cpuboard_init(void)
                blizzardf0_bank.mask = blizzardf0_bank.allocated - 1;
                mapped_malloc(&blizzardf0_bank);
 
-       } else if (is_kupke()) {
+       } else if (is_kupke() || is_mtec_ematrix530()) {
 
                blizzardea_bank.allocated = 65536;
                blizzardea_bank.mask = blizzardea_bank.allocated - 1;
@@ -1800,7 +1839,8 @@ bool cpuboard_32bit(struct uae_prefs *p)
                b == BOARD_MEMORY_BLIZZARD_12xx ||
                b == BOARD_MEMORY_BLIZZARD_PPC ||
                b == BOARD_MEMORY_Z3 ||
-               b == BOARD_MEMORY_25BITMEM;
+               b == BOARD_MEMORY_25BITMEM ||
+               b == BOARD_MEMORY_EMATRIX;
 }
 
 int cpuboard_memorytype(struct uae_prefs *p)
@@ -2065,6 +2105,15 @@ addrbank *cpuboard_autoconfig_init(struct romconfig *rc)
                }
                break;
 
+               case BOARD_MTEC:
+               switch (currprefs.cpuboard_subtype)
+               {
+                       case BOARD_MTEC_SUB_EMATRIX530:
+                       roms[0] = 144;
+                       break;
+               }
+               break;
+
                case BOARD_MACROSYSTEM:
                switch(currprefs.cpuboard_subtype)
                {
@@ -2217,7 +2266,15 @@ addrbank *cpuboard_autoconfig_init(struct romconfig *rc)
 
        protect_roms(false);
        cpuboard_non_byte_ea = true;
-       if (is_dkb_wildfire()) {
+       if (is_mtec_ematrix530()) {
+               earom_size = 65536;
+               for (int i = 0; i < 32768; i++) {
+                       uae_u8 b = 0xff;
+                       zfile_fread(&b, 1, 1, autoconfig_rom);
+                       blizzardea_bank.baseaddr[i * 2 + 0] = b;
+                       blizzardea_bank.baseaddr[i * 2 + 1] = 0xff;
+               }
+       } else if (is_dkb_wildfire()) {
                f0rom_size = 65536;
                zfile_fread(blizzardf0_bank.baseaddr, 1, f0rom_size, autoconfig_rom);
                flashrom = flash_new(blizzardf0_bank.baseaddr + 0, 32768, 65536, 0x20, flashrom_file, FLASHROM_EVERY_OTHER_BYTE | FLASHROM_PARALLEL_EEPROM);

diff --git a/expansion.cpp b/expansion.cpp
index 8104d917db1a966ae81b0ebf467dbd0f7065c54b..fd66645370c64f3b4f74eba2ed367ebb2d75587c 100644 (file)
--- a/expansion.cpp
+++ b/expansion.cpp
@@ -3171,6 +3171,31 @@ static const struct cpuboardsubtype warpengine_sub[] = {
                NULL
        }
 };
+static const struct expansionboardsettings mtec_settings[] = {
+       {
+               _T("SCSI disabled"),
+               _T("scsioff")
+       },
+       {
+               NULL
+       }
+};
+static const struct cpuboardsubtype mtec_sub[] = {
+       {
+               _T("E-Matrix 530"),
+               _T("e-matrix530"),
+               ROMTYPE_CB_EMATRIX, 0,
+               ematrix_add_scsi_unit, EXPANSIONTYPE_SCSI,
+               BOARD_MEMORY_EMATRIX,
+               128 * 1024 * 1024,
+               0,
+               ncr_ematrix_autoconfig_init, NULL, BOARD_AUTOCONFIG_Z2, 1,
+               mtec_settings
+       },
+       {
+               NULL
+       }
+};
 static const struct expansionboardsettings a26x0board_settings[] = {
        {
                _T("OSMODE (J304)"),
@@ -3315,6 +3340,11 @@ const struct cpuboardtype cpuboards[] = {
                _T("MacroSystem"),
                warpengine_sub, 0
        },
+       {
+               BOARD_MTEC,
+               _T("M-Tec"),
+               mtec_sub, 0
+       },
        {
                BOARD_BLIZZARD,
                _T("Phase 5 - Blizzard"),

diff --git a/include/cpuboard.h b/include/cpuboard.h
index 8d0c3f36585502a68001f3b84a8ff2b04bfcaf27..6eaf4367783986956f6e815bfc7db710e79be40c 100644 (file)
--- a/include/cpuboard.h
+++ b/include/cpuboard.h
@@ -33,6 +33,7 @@ extern uae_u8 *REGPARAM3 cyberstorm_scsi_ram_xlate(uaecptr addr) REGPARAM;
 #define BOARD_MEMORY_BLIZZARD_12xx 4
 #define BOARD_MEMORY_BLIZZARD_PPC 5
 #define BOARD_MEMORY_25BITMEM 6
+#define BOARD_MEMORY_EMATRIX 7
 
 #define ISCPUBOARD(type,subtype) (cpuboards[currprefs.cpuboard_type].id == type && (type < 0 || currprefs.cpuboard_subtype == subtype))
 
@@ -76,4 +77,5 @@ extern uae_u8 *REGPARAM3 cyberstorm_scsi_ram_xlate(uaecptr addr) REGPARAM;
 #define BOARD_IC 10
 #define BOARD_IC_ACA500 0
 
-
+#define BOARD_MTEC 11
+#define BOARD_MTEC_SUB_EMATRIX530 0

diff --git a/include/ncr9x_scsi.h b/include/ncr9x_scsi.h
index c0bcbafac571e2f06cac1bd875397badc4db0d68..95b023ea8f25a1dc5d6f0aa2aa8effd7d94bb1d0 100644 (file)
--- a/include/ncr9x_scsi.h
+++ b/include/ncr9x_scsi.h
@@ -10,10 +10,12 @@ extern void cpuboard_dkb_add_scsi_unit(int ch, struct uaedev_config_info *ci, st
 extern void fastlane_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
 extern void oktagon_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
 extern void masoboshi_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+extern void ematrix_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
 
 extern addrbank *ncr_fastlane_autoconfig_init(struct romconfig*);
 extern addrbank *ncr_oktagon_autoconfig_init(struct romconfig*);
 extern addrbank *ncr_dkb_autoconfig_init(struct romconfig*);
+extern addrbank *ncr_ematrix_autoconfig_init(struct romconfig *rc);
 
 extern void cpuboard_ncr9x_scsi_put(uaecptr, uae_u32);
 extern uae_u32 cpuboard_ncr9x_scsi_get(uaecptr);

diff --git a/include/rommgr.h b/include/rommgr.h
index d2d0767b0deee31bc564aea980094dc21caa2d02..047c7fd5025292027fa101c147cb706774185dda 100644 (file)
--- a/include/rommgr.h
+++ b/include/rommgr.h
@@ -34,6 +34,7 @@ extern int decode_cloanto_rom_do (uae_u8 *mem, int size, int real_size);
 #define ROMTYPE_CB_GOLEM030    0x00040010
 #define ROMTYPE_CB_ACA500      0x00040011
 #define ROMTYPE_CB_DBK_WF      0x00040012
+#define ROMTYPE_CB_EMATRIX     0x00040013
 
 #define ROMTYPE_FREEZER                0x00080000
 #define ROMTYPE_AR                     0x00080001

diff --git a/main.cpp b/main.cpp
index 2d78ee5c4ad294642cf5421645b61eabb1af481e..5e77da30f8c3d9bfef8803dbf314867cd0980439 100644 (file)
--- a/main.cpp
+++ b/main.cpp
@@ -336,6 +336,19 @@ void fixup_prefs (struct uae_prefs *p)
                p->fastmem2_size = p->cpuboardmem1_size;
        } else if (cpuboard_memorytype(p) == BOARD_MEMORY_25BITMEM) {
                p->mem25bit_size = p->cpuboardmem1_size;
+       } else if (cpuboard_memorytype(p) == BOARD_MEMORY_EMATRIX) {
+               int size = p->cpuboardmem1_size / (1024 * 1024);
+               if (size == 32 || size == 8 || size == 2) {
+                       p->custom_memory_sizes[0] = p->cpuboardmem1_size / 2;
+                       p->custom_memory_sizes[1] = p->cpuboardmem1_size / 2;
+                       p->custom_memory_addrs[0] = 0x18000000 - p->custom_memory_sizes[0];
+                       p->custom_memory_addrs[1] = 0x18000000;
+               } else {
+                       p->custom_memory_sizes[0] = p->cpuboardmem1_size;
+                       p->custom_memory_sizes[1] = 0;
+                       p->custom_memory_addrs[0] = 0x18000000 - p->custom_memory_sizes[0];
+                       p->custom_memory_addrs[1] = 0;
+               }
        }
 
        if (((p->chipmem_size & (p->chipmem_size - 1)) != 0 && p->chipmem_size != 0x180000)
@@ -454,7 +467,7 @@ void fixup_prefs (struct uae_prefs *p)
        }
        if (p->mem25bit_size > 128 * 1024 * 1024 || (p->mem25bit_size & 0xfffff)) {
                p->mem25bit_size = 0;
-               error_log (_T("Unsupported 25bit RAM size"));
+               error_log(_T("Unsupported 25bit RAM size"));
        }
        if (p->mbresmem_low_size > 0x04000000 || (p->mbresmem_low_size & 0xfffff)) {
                p->mbresmem_low_size = 0;

diff --git a/ncr9x_scsi.cpp b/ncr9x_scsi.cpp
index 0db3bd36491d10d481f8bd03c35acad3a45bc6b6..fbeda730d2fb2aa0a7b8708a6e836f7f25bac54e 100644 (file)
--- a/ncr9x_scsi.cpp
+++ b/ncr9x_scsi.cpp
@@ -158,6 +158,7 @@ static struct ncr9x_state *ncr_fastlane_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
 static struct ncr9x_state *ncr_oktagon2008_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
 static struct ncr9x_state *ncr_masoboshi_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
 static struct ncr9x_state *ncr_dkb1200_scsi;
+static struct ncr9x_state *ncr_ematrix530_scsi;
 
 static struct ncr9x_state *ncr_units[MAX_NCR9X_UNITS + 1];
 
@@ -332,11 +333,40 @@ static void fakedma_buffer_size(struct ncr9x_state *ncr, int size)
 }
 
 /* Fake DMA */
+
+static int fake_dma_read_ematrix(void *opaque, uint8_t *buf, int len)
+{
+       struct ncr9x_state *ncr = (struct ncr9x_state*)opaque;
+       ncr->states[0] = 1;
+       ncr->chipirq = true;
+       set_irq2(ncr);
+       ncr->fakedma_data_offset = 0;
+       ncr->fakedma_data_write_buffer = buf;
+       ncr->fakedma_data_size = len;
+       fakedma_buffer_size(ncr, len);
+       return 0;
+}
+static int fake_dma_write_ematrix(void *opaque, uint8_t *buf, int len)
+{
+       struct ncr9x_state *ncr = (struct ncr9x_state*)opaque;
+       ncr->states[0] = 1;
+       ncr->chipirq = true;
+       set_irq2(ncr);
+       ncr->fakedma_data_offset = 0;
+       fakedma_buffer_size(ncr, len);
+       memcpy(ncr->fakedma_data_buf, buf, len);
+       if (len & 1)
+               ncr->fakedma_data_buf[len] = 0;
+       ncr->fakedma_data_size = len;
+       return 0;
+}
+
 static int fake_dma_read(void *opaque, uint8_t *buf, int len)
 {
        struct ncr9x_state *ncr = (struct ncr9x_state*)opaque;
        ncr->fakedma_data_offset = 0;
        ncr->fakedma_data_write_buffer = buf;
+       ncr->fakedma_data_size = len;
        fakedma_buffer_size(ncr, len);
        return 0;
 }
@@ -352,7 +382,6 @@ static int fake_dma_write(void *opaque, uint8_t *buf, int len)
        return 0;
 }
 
-/* Fake DMA */
 static int fake2_dma_read(void *opaque, uint8_t *buf, int len)
 {
        struct ncr9x_state *ncr = (struct ncr9x_state*)opaque;
@@ -829,6 +858,27 @@ static void ncr9x_io_bput(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val)
                        write_log(_T("DKB IO %08X PUT %02x %08x\n"), addr, val & 0xff, M68K_GETPC);
                        return;
                }
+       } else if (ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530)) {
+               if ((addr & 0xf000) >= 0xe000) {
+                       if ((addr & 0x3ff) <= 7) {
+                               if (ncr->fakedma_data_offset < ncr->fakedma_data_size) {
+                                       ncr->fakedma_data_buf[ncr->fakedma_data_offset++] = val;
+                                       if (ncr->fakedma_data_offset == ncr->fakedma_data_size) {
+                                               memcpy(ncr->fakedma_data_write_buffer, ncr->fakedma_data_buf, ncr->fakedma_data_size);
+                                               esp_fake_dma_done(ncr->devobject.lsistate);
+                                               ncr->states[0] = 0;
+                                       }
+                               }
+                       }
+                       return;
+               }
+               if (addr < 0xc000 || addr >= 0xe000)
+                       return;
+               if (addr & 1)
+                       return;
+               if (currprefs.cpuboard_settings & 1)
+                       return;
+               reg_shift = 3;
        }
        if (!ncr->devobject.lsistate)
                return;
@@ -1002,6 +1052,36 @@ uae_u32 ncr9x_io_bget(struct ncr9x_state *ncr, uaecptr addr)
                        write_log(_T("DKB IO GET %08x %08x\n"), addr, M68K_GETPC);
                        return 0;
                }
+       } else if (ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530)) {
+               if ((addr & 0xf000) >= 0xe000) {
+                       if ((addr & 0x3ff) <= 7) {
+                               if (ncr->fakedma_data_offset >= ncr->fakedma_data_size) {
+                                       ncr->states[0] = 0;
+                                       return 0;
+                               }
+                               if (ncr->fakedma_data_offset == ncr->fakedma_data_size - 1) {
+                                       esp_fake_dma_done(ncr->devobject.lsistate);
+                                       ncr->states[0] = 0;
+                               }
+                               return ncr->fakedma_data_buf[ncr->fakedma_data_offset++];
+                       }
+                       return 0xff;
+               }
+               if ((addr & 1) && !(addr & 0x0800)) {
+                       // dma request
+                       return ncr->states[0] ? 0xff : 0x7f;
+               }
+               if ((addr & 1) && (addr & 0x0800)) {
+                       // hardware revision?
+                       return 0x7f;
+               }
+               if (addr & 1)
+                       return 0x7f;
+               if (currprefs.cpuboard_settings & 1)
+                       return 0x7f;
+               if (addr < 0xc000 || addr >= 0xe000)
+                       return 0x7f;
+               reg_shift = 3;
        }
        if (!ncr->devobject.lsistate)
                return v;
@@ -1162,16 +1242,10 @@ static void REGPARAM2 ncr9x_bput(struct ncr9x_state *ncr, uaecptr addr, uae_u32
                switch (addr)
                {
                        case 0x48:
-                       if (isncr(ncr, ncr_oktagon2008_scsi)) {
-                               map_banks_z2(ncr->bank, expamem_z2_pointer >> 16, OKTAGON_BOARD_SIZE >> 16);
-                               ncr->configured = 1;
-                               expamem_next (ncr->bank, NULL);
-                       } else if (ncr == ncr_dkb1200_scsi) {
-                               map_banks_z2(ncr->bank, expamem_z2_pointer >> 16, DKB_BOARD_SIZE >> 16);
-                               ncr->configured = 1;
-                               expamem_next (ncr->bank, NULL);
-                       }
+                       map_banks_z2(ncr->bank, expamem_z2_pointer >> 16, expamem_z2_size >> 16);
+                       ncr->configured = 1;
                        ncr->baseaddress = expamem_z2_pointer;
+                       expamem_next (ncr->bank, NULL);
                        break;
                        case 0x4c:
                        ncr->configured = 1;
@@ -1462,6 +1536,56 @@ addrbank *ncr_dkb_autoconfig_init(struct romconfig *rc)
        return ncr->bank;
 }
 
+addrbank *ncr_ematrix_autoconfig_init(struct romconfig *rc)
+{
+       int roms[2];
+       struct ncr9x_state *ncr = getscsi(rc);
+
+       if (!ncr)
+               return &expamem_null;
+
+       xfree(ncr->rom);
+       ncr->rom = NULL;
+
+       roms[0] = 144;
+       roms[1] = -1;
+
+       ncr->enabled = true;
+       memset(ncr->acmemory, 0xff, sizeof ncr->acmemory);
+       ncr->rom_start = 0;
+       ncr->rom_offset = 0;
+       ncr->rom_end = 0x8000;
+       ncr->io_start = 0x8000;
+       ncr->io_end = 0x10000;
+       ncr->bank = &ncr9x_bank_generic;
+       ncr->board_mask = 65535;
+
+       ncr9x_reset_board(ncr);
+
+       struct zfile *z = read_device_from_romconfig(rc, roms);
+       ncr->rom = xcalloc(uae_u8, 65536);
+       if (z) {
+               int i;
+               memset(ncr->rom, 0xff, 65536);
+
+               zfile_fseek(z, 32768, SEEK_SET);
+               for (i = 0; i < (sizeof ncr->acmemory) / 2; i++) {
+                       uae_u8 b;
+                       zfile_fread(&b, 1, 1, z);
+                       ncr->acmemory[i * 2] = b;
+               }
+               for (;;) {
+                       uae_u8 b;
+                       if (!zfile_fread(&b, 1, 1, z))
+                               break;
+                       ncr->rom[i * 2] = b;
+                       i++;
+               }
+               zfile_fclose(z);
+       }
+
+       return ncr->bank;
+}
 
 void ncr_masoboshi_autoconfig_init(struct romconfig *rc, uaecptr baseaddress)
 {
@@ -1594,5 +1718,11 @@ void masoboshi_add_scsi_unit (int ch, struct uaedev_config_info *ci, struct romc
        ncr9x_esp_scsi_init(ncr_masoboshi_scsi[ci->controller_type_unit], fake2_dma_read, fake2_dma_write, set_irq2_masoboshi);
 }
 
+void ematrix_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
+{
+       ncr9x_add_scsi_unit(&ncr_ematrix530_scsi, ch, ci, rc);
+       ncr9x_esp_scsi_init(ncr_ematrix530_scsi, fake_dma_read_ematrix, fake_dma_write_ematrix, set_irq2);
+       esp_dma_enable(ncr_ematrix530_scsi->devobject.lsistate, 1);
+}
 
 #endif

diff --git a/rommgr.cpp b/rommgr.cpp
index f8c8546ba9680ee56b1db93252bcabfe4da93e39..a96d8f62a7dcde0de44456404251c98cd1b969c9 100644 (file)
--- a/rommgr.cpp
+++ b/rommgr.cpp
@@ -95,7 +95,7 @@ struct romdata *getromdatabypath (const TCHAR *path)
        return NULL;
 }
 
-#define NEXT_ROM_ID 144
+#define NEXT_ROM_ID 145
 
 static struct romheader romheaders[] = {
        { _T("Freezer Cartridges"), 1 },
@@ -372,6 +372,8 @@ static struct romdata roms[] = {
        0x05d473f4, 0x574ec567, 0xcc67e06f, 0x91dcecb9, 0x8c204399, 0x5fe2a09f, NULL, NULL },
        { _T("DKB WildFire"), 1, 1, 1, 1, _T("WILDFIRE\0"), 18352, 143, 0, 0, ROMTYPE_CB_DBK_WF, 0, 0, NULL,
        0xb2dae8c4, 0xcdfe2d96, 0xe44d4f8d, 0x3833a5e8, 0xb6c832fd, 0xc7b341a9, NULL, NULL },
+       { _T("M-Tec E-Matrix 530"), 0, 0, 0, 0, _T("EMATRIX530\0"), 65536, 144, 0, 0, ROMTYPE_CB_EMATRIX, 0, 0, NULL,
+       0x3942d827, 0x5aaf118f, 0x61fc3083, 0x1435b87c, 0x8bdab6a4, 0x59b4ee22, NULL, NULL },
 
        { _T("Preferred Technologies Nexus"), 1, 0, 1, 0, _T("PTNEXUS\0"), 8192, 139, 0, 0, ROMTYPE_PTNEXUS, 0, 0, NULL,
        0xf495879a, 0xa3bd0202, 0xe14aa5b6, 0x49d3ce88, 0x22975950, 0x6500dbc2, NULL, NULL },
@@ -1137,7 +1139,7 @@ struct romlist *getromlistbyromdata (const struct romdata *rd)
        int ids[2];
 
        ids[0] = rd->id;
-       ids[1] = 0;
+       ids[1] = -1;
        return getromlistbyids(ids, NULL);
 }