else
get_word_mmu030(a7 + 32 - 2);
+ // Movem write data
+ uae_u32 mdata = get_long_mmu030(a7 + 0x18);
// Internal register, misc flags
uae_u32 ps = get_long_mmu030(a7 + 0x28);
// Internal register, our opcode storage area
}
}
+ // Retried data access is the only memory access that can be done after this.
+
m68k_areg(regs, 7) += 92;
regs.sr = sr;
MakeFromSR_T0();
mmu030_ad[idxsize + 1].done = false;
}
} else {
- uae_u32 val = mmu030_ad[idxsize].val;
+ uae_u32 val;
+ if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1)
+ val = mdata;
+ else
+ val = mmu030_ad[idxsize].val;
switch (size)
{
case 1:
else
get_word_mmu030c(a7 + 32 - 2);
+ // Movem write data
+ uae_u32 mdata = get_long_mmu030c(a7 + 0x18);
// Internal register, misc flags
uae_u32 ps = get_long_mmu030c(a7 + 0x28);
// Internal register, our opcode storage area
write_log (_T("Software fixed stage C! opcode = %04x\n"), regs.prefetch020[1]);
}
+ // Retried data access is the only memory access that can be done after this.
+
m68k_areg (regs, 7) += 92;
regs.sr = sr;
MakeFromSR_T0();
bool read = (ssw & MMU030_SSW_RW) != 0;
int size = (ssw & MMU030_SSW_SIZE_B) ? 1 : ((ssw & MMU030_SSW_SIZE_W) ? 2 : 4);
int fc = ssw & 7;
+
if (read) {
uae_u32 val = 0;
switch (size)
mmu030_ad[idxsize + 1].done = false;
}
} else {
- uae_u32 val = mmu030_ad[idxsize].val;
+ uae_u32 val;
+ if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1)
+ val = mdata;
+ else
+ val = mmu030_ad[idxsize].val;
switch (size)
{
case 1: