Generate fastest possible CPU mode 020/030 LINK´special case.

diff --git a/cpuemu_0.cpp b/cpuemu_0.cpp
index 5ebbbf7fac70024bbd647880b73fd192c8cc099f..304068a3bf5f03e97c2a214abacd4e6af6ee3466 100644 (file)
--- a/cpuemu_0.cpp
+++ b/cpuemu_0.cpp
@@ -44333,6 +44333,28 @@ uae_u32 REGPARAM2 op_4800_2_ff(uae_u32 opcode)
 }
 /* 2 0,0   */
 
+/* LINK.L An,#<data>.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 op_4808_2_ff(uae_u32 opcode)
+{
+       int count_cycles = 0;
+       uae_u32 real_opcode = opcode;
+       uae_u32 srcreg = (real_opcode & 7);
+       uae_s32 src = m68k_areg(regs, srcreg);
+       uaecptr olda;
+       olda = m68k_areg(regs, 7) - 4;
+       m68k_areg(regs, 7) = olda;
+       uae_s32 offs;
+       offs = get_dilong(2);
+       put_long(olda, src);
+       m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
+       m68k_areg(regs, 7) += offs;
+       m68k_incpc(6);
+       return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
+}
+/* 6 0,0   */
+
+#endif
 /* NBCD.B (An) */
 uae_u32 REGPARAM2 op_4810_2_ff(uae_u32 opcode)
 {
@@ -45290,6 +45312,25 @@ uae_u32 REGPARAM2 op_4cfb_2_ff(uae_u32 opcode)
 }
 /* 4 2,0   */
 
+/* LINK.W An,#<data>.W */
+uae_u32 REGPARAM2 op_4e50_2_ff(uae_u32 opcode)
+{
+       int count_cycles = 0;
+       uae_u32 real_opcode = opcode;
+       uae_u32 srcreg = (real_opcode & 7);
+       uae_s32 src = m68k_areg(regs, srcreg);
+       uaecptr olda;
+       olda = m68k_areg(regs, 7) - 4;
+       m68k_areg(regs, 7) = olda;
+       uae_s16 offs = get_diword(2);
+       put_long(olda, src);
+       m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
+       m68k_areg(regs, 7) += offs;
+       m68k_incpc(4);
+       return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
+}
+/* 4 0,0   */
+
 /* MVR2USP.L An */
 uae_u32 REGPARAM2 op_4e60_2_ff(uae_u32 opcode)
 {

diff --git a/cpuemu_40.cpp b/cpuemu_40.cpp
index ee691796d6ee502d458c69d7eb4cf9545a029b83..88a29dff7fb693e7cc2e2d34b4990ec6d8ef300e 100644 (file)
--- a/cpuemu_40.cpp
+++ b/cpuemu_40.cpp
@@ -42334,6 +42334,27 @@ uae_u32 REGPARAM2 op_4800_42_ff(uae_u32 opcode)
 }
 /* 2 0,0   */
 
+/* LINK.L An,#<data>.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 op_4808_42_ff(uae_u32 opcode)
+{
+       uae_u32 real_opcode = opcode;
+       uae_u32 srcreg = (real_opcode & 7);
+       uae_s32 src = m68k_areg(regs, srcreg);
+       uaecptr olda;
+       olda = m68k_areg(regs, 7) - 4;
+       m68k_areg(regs, 7) = olda;
+       uae_s32 offs;
+       offs = get_dilong(2);
+       put_long_jit(olda, src);
+       m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
+       m68k_areg(regs, 7) += offs;
+       m68k_incpc(6);
+       return 0;
+}
+/* 6 0,0   */
+
+#endif
 /* NBCD.B (An) */
 uae_u32 REGPARAM2 op_4810_42_ff(uae_u32 opcode)
 {
@@ -43198,6 +43219,24 @@ uae_u32 REGPARAM2 op_4cfb_42_ff(uae_u32 opcode)
 }
 /* 4 2,0   */
 
+/* LINK.W An,#<data>.W */
+uae_u32 REGPARAM2 op_4e50_42_ff(uae_u32 opcode)
+{
+       uae_u32 real_opcode = opcode;
+       uae_u32 srcreg = (real_opcode & 7);
+       uae_s32 src = m68k_areg(regs, srcreg);
+       uaecptr olda;
+       olda = m68k_areg(regs, 7) - 4;
+       m68k_areg(regs, 7) = olda;
+       uae_s16 offs = get_diword(2);
+       put_long_jit(olda, src);
+       m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
+       m68k_areg(regs, 7) += offs;
+       m68k_incpc(4);
+       return 0;
+}
+/* 4 0,0   */
+
 /* MVR2USP.L An */
 uae_u32 REGPARAM2 op_4e60_42_ff(uae_u32 opcode)
 {

diff --git a/cpuemu_50.cpp b/cpuemu_50.cpp
index 8f3b7453294e761f2ee747d10b9eeb7eb284028f..4df898cc3d34e62e3d65375ba47d818c1bd99927 100644 (file)
--- a/cpuemu_50.cpp
+++ b/cpuemu_50.cpp
@@ -42424,6 +42424,27 @@ uae_u32 REGPARAM2 op_4800_52_ff(uae_u32 opcode)
 }
 /* 2 0,0   */
 
+/* LINK.L An,#<data>.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 op_4808_52_ff(uae_u32 opcode)
+{
+       uae_u32 real_opcode = opcode;
+       uae_u32 srcreg = (real_opcode & 7);
+       uae_s32 src = m68k_areg(regs, srcreg);
+       uaecptr olda;
+       olda = m68k_areg(regs, 7) - 4;
+       m68k_areg(regs, 7) = olda;
+       uae_s32 offs;
+       offs = get_iilong_jit(2);
+       x_put_long(olda, src);
+       m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
+       m68k_areg(regs, 7) += offs;
+       m68k_incpc(6);
+       return 0;
+}
+/* 6 0,0   */
+
+#endif
 /* NBCD.B (An) */
 uae_u32 REGPARAM2 op_4810_52_ff(uae_u32 opcode)
 {
@@ -43288,6 +43309,24 @@ uae_u32 REGPARAM2 op_4cfb_52_ff(uae_u32 opcode)
 }
 /* 4 2,0   */
 
+/* LINK.W An,#<data>.W */
+uae_u32 REGPARAM2 op_4e50_52_ff(uae_u32 opcode)
+{
+       uae_u32 real_opcode = opcode;
+       uae_u32 srcreg = (real_opcode & 7);
+       uae_s32 src = m68k_areg(regs, srcreg);
+       uaecptr olda;
+       olda = m68k_areg(regs, 7) - 4;
+       m68k_areg(regs, 7) = olda;
+       uae_s16 offs = get_iiword_jit(2);
+       x_put_long(olda, src);
+       m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
+       m68k_areg(regs, 7) += offs;
+       m68k_incpc(4);
+       return 0;
+}
+/* 4 0,0   */
+
 /* MVR2USP.L An */
 uae_u32 REGPARAM2 op_4e60_52_ff(uae_u32 opcode)
 {

diff --git a/cpustbl.cpp b/cpustbl.cpp
index 957b5e2bd16e867cd64d7f0cc3c1975b67b17c19..8d6b1f92901cc43b6126f5f7607eadc7a421ecc8 100644 (file)
--- a/cpustbl.cpp
+++ b/cpustbl.cpp
@@ -5383,7 +5383,9 @@ const struct cputbl op_smalltbl_2[] = {
 { op_46fb_0_ff, NULL, 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
 { op_46fc_0_ff, NULL, 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
 { op_4800_2_ff, NULL, 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
-{ op_4808_1_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#ifndef CPUEMU_68000_ONLY
+{ op_4808_2_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
 { op_4810_2_ff, NULL, 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4818_2_ff, NULL, 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4820_2_ff, NULL, 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
@@ -5497,7 +5499,7 @@ const struct cputbl op_smalltbl_2[] = {
 { op_4cfa_2_ff, NULL, 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
 { op_4cfb_2_ff, NULL, 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
 { op_4e40_0_ff, NULL, 0x4e40, 2, { 0, 0 }, 0 }, /* TRAP */
-{ op_4e50_1_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ op_4e50_2_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
 { op_4e58_0_ff, NULL, 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
 { op_4e60_2_ff, NULL, 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
 { op_4e68_0_ff, NULL, 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
@@ -7227,7 +7229,7 @@ const struct cputbl op_smalltbl_3[] = {
 { op_46fb_0_ff, NULL, 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
 { op_46fc_0_ff, NULL, 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
 { op_4800_2_ff, NULL, 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
-{ op_4808_1_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ op_4808_2_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
 { op_4810_2_ff, NULL, 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4818_2_ff, NULL, 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4820_2_ff, NULL, 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
@@ -7341,7 +7343,7 @@ const struct cputbl op_smalltbl_3[] = {
 { op_4cfa_2_ff, NULL, 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
 { op_4cfb_2_ff, NULL, 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
 { op_4e40_0_ff, NULL, 0x4e40, 2, { 0, 0 }, 0 }, /* TRAP */
-{ op_4e50_1_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ op_4e50_2_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
 { op_4e58_0_ff, NULL, 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
 { op_4e60_2_ff, NULL, 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
 { op_4e68_0_ff, NULL, 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
@@ -49714,7 +49716,9 @@ const struct cputbl op_smalltbl_42[] = {
 { op_46fb_40_ff, NULL, 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
 { op_46fc_40_ff, NULL, 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
 { op_4800_42_ff, NULL, 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
-{ op_4808_41_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#ifndef CPUEMU_68000_ONLY
+{ op_4808_42_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
 { op_4810_42_ff, NULL, 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4818_42_ff, NULL, 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4820_42_ff, NULL, 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
@@ -49828,7 +49832,7 @@ const struct cputbl op_smalltbl_42[] = {
 { op_4cfa_42_ff, NULL, 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
 { op_4cfb_42_ff, NULL, 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
 { op_4e40_40_ff, NULL, 0x4e40, 2, { 0, 0 }, 0 }, /* TRAP */
-{ op_4e50_41_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ op_4e50_42_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
 { op_4e58_40_ff, NULL, 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
 { op_4e60_42_ff, NULL, 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
 { op_4e68_40_ff, NULL, 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
@@ -51558,7 +51562,7 @@ const struct cputbl op_smalltbl_43[] = {
 { op_46fb_40_ff, NULL, 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
 { op_46fc_40_ff, NULL, 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
 { op_4800_42_ff, NULL, 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
-{ op_4808_41_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ op_4808_42_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
 { op_4810_42_ff, NULL, 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4818_42_ff, NULL, 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4820_42_ff, NULL, 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
@@ -51672,7 +51676,7 @@ const struct cputbl op_smalltbl_43[] = {
 { op_4cfa_42_ff, NULL, 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
 { op_4cfb_42_ff, NULL, 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
 { op_4e40_40_ff, NULL, 0x4e40, 2, { 0, 0 }, 0 }, /* TRAP */
-{ op_4e50_41_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ op_4e50_42_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
 { op_4e58_40_ff, NULL, 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
 { op_4e60_42_ff, NULL, 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
 { op_4e68_40_ff, NULL, 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
@@ -67293,7 +67297,9 @@ const struct cputbl op_smalltbl_52[] = {
 { op_46fb_50_ff, NULL, 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
 { op_46fc_50_ff, NULL, 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
 { op_4800_52_ff, NULL, 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
-{ op_4808_51_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#ifndef CPUEMU_68000_ONLY
+{ op_4808_52_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
 { op_4810_52_ff, NULL, 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4818_52_ff, NULL, 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4820_52_ff, NULL, 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
@@ -67407,7 +67413,7 @@ const struct cputbl op_smalltbl_52[] = {
 { op_4cfa_52_ff, NULL, 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
 { op_4cfb_52_ff, NULL, 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
 { op_4e40_50_ff, NULL, 0x4e40, 2, { 0, 0 }, 0 }, /* TRAP */
-{ op_4e50_51_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ op_4e50_52_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
 { op_4e58_50_ff, NULL, 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
 { op_4e60_52_ff, NULL, 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
 { op_4e68_50_ff, NULL, 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
@@ -69137,7 +69143,7 @@ const struct cputbl op_smalltbl_53[] = {
 { op_46fb_50_ff, NULL, 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
 { op_46fc_50_ff, NULL, 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
 { op_4800_52_ff, NULL, 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
-{ op_4808_51_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ op_4808_52_ff, NULL, 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
 { op_4810_52_ff, NULL, 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4818_52_ff, NULL, 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
 { op_4820_52_ff, NULL, 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
@@ -69251,7 +69257,7 @@ const struct cputbl op_smalltbl_53[] = {
 { op_4cfa_52_ff, NULL, 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
 { op_4cfb_52_ff, NULL, 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
 { op_4e40_50_ff, NULL, 0x4e40, 2, { 0, 0 }, 0 }, /* TRAP */
-{ op_4e50_51_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ op_4e50_52_ff, NULL, 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
 { op_4e58_50_ff, NULL, 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
 { op_4e60_52_ff, NULL, 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
 { op_4e68_50_ff, NULL, 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */

diff --git a/cputbl.h b/cputbl.h
index eba23c6d5c31a51885c684c7cb9022496722d007..5c1b753cad3720a20c5aa73ebbe69a80bb725ce0 100644 (file)
--- a/cputbl.h
+++ b/cputbl.h
@@ -3973,6 +3973,8 @@ extern cpuop_func op_0efc_2_nf;
 extern cpuop_func op_0efc_2_ff;
 extern cpuop_func op_4800_2_nf;
 extern cpuop_func op_4800_2_ff;
+extern cpuop_func op_4808_2_nf;
+extern cpuop_func op_4808_2_ff;
 extern cpuop_func op_4810_2_nf;
 extern cpuop_func op_4810_2_ff;
 extern cpuop_func op_4818_2_nf;
@@ -4043,6 +4045,8 @@ extern cpuop_func op_4cfa_2_nf;
 extern cpuop_func op_4cfa_2_ff;
 extern cpuop_func op_4cfb_2_nf;
 extern cpuop_func op_4cfb_2_ff;
+extern cpuop_func op_4e50_2_nf;
+extern cpuop_func op_4e50_2_ff;
 extern cpuop_func op_4e60_2_nf;
 extern cpuop_func op_4e60_2_ff;
 extern cpuop_func op_4e71_2_nf;
@@ -59219,6 +59223,8 @@ extern cpuop_func op_0efc_42_nf;
 extern cpuop_func op_0efc_42_ff;
 extern cpuop_func op_4800_42_nf;
 extern cpuop_func op_4800_42_ff;
+extern cpuop_func op_4808_42_nf;
+extern cpuop_func op_4808_42_ff;
 extern cpuop_func op_4810_42_nf;
 extern cpuop_func op_4810_42_ff;
 extern cpuop_func op_4818_42_nf;
@@ -59289,6 +59295,8 @@ extern cpuop_func op_4cfa_42_nf;
 extern cpuop_func op_4cfa_42_ff;
 extern cpuop_func op_4cfb_42_nf;
 extern cpuop_func op_4cfb_42_ff;
+extern cpuop_func op_4e50_42_nf;
+extern cpuop_func op_4e50_42_ff;
 extern cpuop_func op_4e60_42_nf;
 extern cpuop_func op_4e60_42_ff;
 extern cpuop_func op_4e71_42_nf;
@@ -67495,6 +67503,8 @@ extern cpuop_func op_0efc_52_nf;
 extern cpuop_func op_0efc_52_ff;
 extern cpuop_func op_4800_52_nf;
 extern cpuop_func op_4800_52_ff;
+extern cpuop_func op_4808_52_nf;
+extern cpuop_func op_4808_52_ff;
 extern cpuop_func op_4810_52_nf;
 extern cpuop_func op_4810_52_ff;
 extern cpuop_func op_4818_52_nf;
@@ -67565,6 +67575,8 @@ extern cpuop_func op_4cfa_52_nf;
 extern cpuop_func op_4cfa_52_ff;
 extern cpuop_func op_4cfb_52_nf;
 extern cpuop_func op_4cfb_52_ff;
+extern cpuop_func op_4e50_52_nf;
+extern cpuop_func op_4e50_52_ff;
 extern cpuop_func op_4e60_52_nf;
 extern cpuop_func op_4e60_52_ff;
 extern cpuop_func op_4e71_52_nf;

diff --git a/gencpu.cpp b/gencpu.cpp
index 363ad3080574e0c7b30406fa1154c181ef67fa6e..71893bc4e28db637270f59801bbb648589407f6a 100644 (file)
--- a/gencpu.cpp
+++ b/gencpu.cpp
@@ -7305,8 +7305,11 @@ static void gen_opcode (unsigned int opcode)
                        genastore("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
                        out("m68k_areg(regs, 7) += offs;\n");
                        fill_prefetch_next_t();
-                       if (!next_level_060_to_040())
-                               next_level_020_to_010();
+                       if (!next_level_060_to_040()) {
+                               if (!next_level_040_to_030()) {
+                                       next_level_020_to_010();
+                               }
+                       }
                }
                break;
        case i_UNLK: