false, 0, NULL,
{ 0xc1, 1, 0x00, 0x00, 0x07, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
},
+ {
+ _T("pacificoverdrive"), _T("Overdrive"), _T("Pacific Peripherals/IVS"),
+ NULL, overdrive_init, NULL, overdrive_add_scsi_unit, ROMTYPE_OVERDRIVE, 0, 0, BOARD_AUTOCONFIG_Z2, true,
+ NULL, 0,
+ true, EXPANSIONTYPE_SCSI,
+ 0, 0, 0, false, NULL,
+ false, 0, NULL,
+ { 0xd1, 16, 0x00, 0x00, 0x08, 0x40, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }
+ },
{
_T("fastlane"), _T("Fastlane"), _T("Phase 5"),
NULL, ncr_fastlane_autoconfig_init, NULL, fastlane_add_scsi_unit, ROMTYPE_FASTLANE, 0, 0, BOARD_AUTOCONFIG_Z3, false,
#define ROMTYPE_SBISA 0x00100075
#define ROMTYPE_X86MOUSE 0x00100076
#define ROMTYPE_ACCESSX 0x00100077
+#define ROMTYPE_OVERDRIVE 0x00100078
#define ROMTYPE_NOT 0x00800000
#define ROMTYPE_QUAD 0x01000000
bool fasttrak_init(struct autoconfig_info *aci);
void fasttrak_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+bool overdrive_init(struct autoconfig_info *aci);
+void overdrive_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+
uae_u8 idescsi_scsi_get(uaecptr addr);
void idescsi_scsi_put(uaecptr addr, uae_u8 v);
0x039a14a7, 0x1a710b94, 0xcc1bd217, 0xb0c310af, 0x4b0f6d0a, 0x1125b05a, NULL, NULL },
{ _T("AccessX 500 v2.1 (descrambled)"), 2, 1, 2, 1, _T("ACCESSX\0"), 32768, 243, 0, 0, ROMTYPE_ACCESSX, 0, 0, NULL,
0x415a5cae, 0x15c8c15f, 0x3700e867, 0xd1dbe2ee, 0xcbb7c7cd, 0x245555fa, NULL, NULL },
+ { _T("Pacific Peripherals Overdrive v1.5"), 1, 5, 1, 5, _T("OVERDRIVE\0"), 8192, 246, 0, 0, ROMTYPE_OVERDRIVE, 0, 0, NULL,
+ 0x086e2716b, 0x075b50cb,0x166e00ac,0x4016ef7f,0x02532e86,0xe73b7711, NULL, NULL },
+ { _T("Pacific Peripherals Overdrive v2.0"), 2, 0, 2, 0, _T("OVERDRIVE\0"), 8192, 247, 0, 0, ROMTYPE_OVERDRIVE, 0, 0, NULL,
+ 0xebe42aa6, 0xdff761c2,0x429d0d26,0x2151d831,0x12746f83,0x3b8d36f0, NULL, NULL },
{ _T("CyberStorm MK I 68040"), 0, 0, 0, 0, _T("CSMKI\0"), 32768, 95, 0, 0, ROMTYPE_CB_CSMK1, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk1_040.rom") },
#define OMTI_PROFEX 39
#define NCR5380_FASTTRAK 40
#define NCR5380_12GAUGE 41
-#define NCR_LAST 42
+#define NCR5380_OVERDRIVE 42
+#define NCR_LAST 43
extern int log_scsiemu;
}
}
+static void overdrive_do_dma(struct soft_scsi *ncr)
+{
+ struct raw_scsi *rs = &ncr->rscsi;
+ while ((rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT || rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) && ncr->dmac_length > 0) {
+ if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) {
+ x_put_byte(ncr->dmac_address, ncr5380_bget(ncr, 8));
+ ncr->dmac_address++;
+ ncr->dmac_length--;
+ } else if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT) {
+ ncr5380_bput(ncr, 8, x_get_byte(ncr->dmac_address));
+ ncr->dmac_address++;
+ ncr->dmac_length--;
+ }
+ }
+}
+
static void dma_check(struct soft_scsi *ncr)
{
}
+ if (ncr->type == NCR5380_OVERDRIVE) {
+
+ overdrive_do_dma(ncr);
+
+ }
+
ncr->dmac_active = 0;
}
}
return (addr >> 4) & 7;
}
+static int overdrive_reg(struct soft_scsi *ncr, uaecptr addr)
+{
+ if (addr & 0x8000)
+ return -1;
+ if ((addr & 0x7000) == 0x4000)
+ return 0x100 + (addr & 0x3f);
+ if (addr & 1)
+ return -1;
+ if ((addr & 0x7000) == 0x2000)
+ return (addr >> 1) & 7;
+ if ((addr & 0x7000) == 0x6000)
+ return 8;
+ return -1;
+}
+
static uae_u8 read_684xx_dma(struct soft_scsi *ncr, uaecptr addr)
{
uae_u8 val = 0;
break;
case 7:
ncr->dmac_active = (val & 0x80) != 0;
+ dma_check(ncr);
break;
case 10: // MTCR
ncr->dmac_length &= 0x000000ff;
reg = twelvegauge_reg(ncr, addr);
if (reg >= 0) {
v = ncr5380_bget(ncr, reg);
- } else {
+ } else {
v = ncr->rom[addr & 0x7fff];
}
+ } else if (ncr->type == NCR5380_OVERDRIVE) {
+
+ reg = overdrive_reg(ncr, addr);
+ if (reg >= 0) {
+ if (reg >= 0x100)
+ v = read_684xx_dma(ncr, reg);
+ else
+ v = ncr5380_bget(ncr, reg);
+ } else {
+ v = ncr->rom[addr & 0x3fff];
+ }
+
}
#if NCR5380_DEBUG > 1
reg = twelvegauge_reg(ncr, addr);
if (reg >= 0)
ncr5380_bput(ncr, reg, val);
+
+ } else if (ncr->type == NCR5380_OVERDRIVE) {
+
+ reg = overdrive_reg(ncr, addr);
+ if (reg >= 0) {
+ if (reg >= 0x100)
+ write_684xx_dma(ncr, reg, val);
+ else
+ ncr5380_bput(ncr, reg, val);
+ }
}
#if NCR5380_DEBUG > 1
generic_soft_scsi_add(ch, ci, rc, NCR5380_FASTTRAK, 65536, 65536, ROMTYPE_FASTTRAK);
}
+bool overdrive_init(struct autoconfig_info *aci)
+{
+ const struct expansionromtype *ert = get_device_expansion_rom(ROMTYPE_OVERDRIVE);
+ if (!aci->doinit) {
+ aci->autoconfigp = ert->autoconfig;
+ return true;
+ }
+
+ struct soft_scsi *scsi = getscsi(aci->rc);
+ if (!scsi)
+ return false;
+
+ load_rom_rc(aci->rc, ROMTYPE_OVERDRIVE, 8192, 0, scsi->rom, 32768, LOADROM_EVENONLY_ODDONE);
+ for (int i = 0; i < 16; i++) {
+ uae_u8 b = ert->autoconfig[i];
+ if (aci->rc->autoboot_disabled) {
+ if (i == 0)
+ b = 0xc1;
+ if (i == 10)
+ b = 0;
+ }
+ ew(scsi, i * 4, b);
+ }
+ aci->addrbank = scsi->bank;
+ return true;
+}
+
+void overdrive_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
+{
+ generic_soft_scsi_add(ch, ci, rc, NCR5380_OVERDRIVE, 65536, 32768, ROMTYPE_OVERDRIVE);
+}
+
// x86 bridge scsi rancho rt1000
void x86_rt1000_bput(int portnum, uae_u8 v)
{