#include "disasm.h"
#include "ini.h"
#include "fpp.h"
-#include "mmu_common.h"
#include "options.h"
int movem_index2[256];
int movem_next[256];
int bus_error_offset;
+int cpu_bus_error;
struct mmufixup mmufixup[2];
cpuop_func *cpufunctbl[65536];
static int feature_full_extension_format = 0;
static int feature_test_rounds = 2;
static int feature_flag_mode = 0;
+static TCHAR *feature_instruction_size = NULL;
static uae_u32 feature_addressing_modes[2];
static int ad8r[2], pc8r[2];
static int multi_mode;
return 0;
}
+static bool is_nowrite_address(uaecptr addr, int size)
+{
+ return addr + size >= safe_memory_start && addr < safe_memory_end;
+}
+
static void validate_addr(uaecptr addr, int size)
{
if (valid_address(addr, size, 0))
if (safe_memory_start == 0xffffffff && safe_memory_end == 0xffffffff)
return;
if (addr >= safe_memory_start && addr < safe_memory_end) {
- test_exception = 2;
- test_exception_3_w = write;
- test_exception_addr = addr;
- test_exception_3_fc = fc;
- THROW(2);
+ cpu_bus_error = 1;
}
}
return op_illg_1(opcode);
}
+void exception2_read(uae_u32 opcode, uaecptr addr, int fc)
+{
+ test_exception = 2;
+ test_exception_3_w = 0;
+ test_exception_addr = addr;
+ test_exception_opcode = opcode;
+ test_exception_3_fc = fc;
+ doexcstack();
+}
+
+void exception2_write(uae_u32 opcode, uaecptr addr, int fc)
+{
+ test_exception = 2;
+ test_exception_3_w = 1;
+ test_exception_addr = addr;
+ test_exception_opcode = opcode;
+ test_exception_3_fc = fc;
+ doexcstack();
+}
+
+
void exception3_read(uae_u32 opcode, uae_u32 addr, int fc)
{
test_exception = 3;
}
case PC16:
{
- uae_u32 pct = opcode_memory_start + 2;
+ uae_u32 pct = pc + 2 - 2;
if (target <= pct + 0x7ffe && target >= pct - 0x8000) {
put_word_test(pc, target - pct);
*eap = target;
case PC8r:
{
for (int r = 0; r < 16; r++) {
- uae_u32 aval = opcode_memory_start + 2;
+ uae_u32 aval = pc + 2 - 2;
int rn = ((ea_exact_cnt >> 1) + r) & 15;
for (int i = 0; i < 2; i++) {
if ((ea_exact_cnt & 1) == 0 || i == 1) {
test_memory_accessed = 0;
testing_active = 1;
testing_active_opcode = opc;
+ cpu_bus_error = 0;
int cnt = feature_loop_mode * 2;
if (multi_mode)
uaecptr a7 = regs.regs[15];
int s = regs.s;
- TRY (ex) {
- (*cpufunctbl[opc])(opc);
- } CATCH(ex) {
- // got bus error
- Exception(2);
- } ENDTRY
+ (*cpufunctbl[opc])(opc);
// Supervisor mode and A7 was modified: skip this test round.
if (s && regs.regs[15] != a7) {
// parse exception and store fields that are unique
// SR and PC was already saved with non-exception data
if (cpu_lvl == 0) {
- if (test_exception == 3) {
+ if (test_exception == 2 || test_exception == 3) {
// status
*p++ = sf[1];
// opcode (which is not necessarily current opcode!)
continue;
} else {
// branch target = generate exception
- put_word_test(srcaddr, 0x4afc);
+ if (!is_nowrite_address(srcaddr, 2)) {
+ put_word_test(srcaddr, 0x4afc);
+ }
branch_target = srcaddr;
dst = store_mem(dst, 1);
memcpy(&ahist2, &ahist, sizeof(struct accesshistory) *MAX_ACCESSHIST);
_tcscpy(modetxt, mode);
my_trim(modetxt);
TCHAR *s = _tcschr(modetxt, '.');
- if (s) {
- *s = 0;
- TCHAR c = _totlower(s[1]);
- if (c == 'b')
+ if (s || feature_instruction_size != NULL) {
+ TCHAR c = 0;
+ if (s) {
+ *s = 0;
+ TCHAR c = _totlower(s[1]);
+ }
+ if (!c && feature_instruction_size) {
+ c = feature_instruction_size[0];
+ }
+ if (c == 'b' || c == 'B')
sizes = 6;
- if (c == 'w')
+ if (c == 'w' || c == 'W')
sizes = 4;
- if (c == 'l')
+ if (c == 'l' || c == 'L')
sizes = 0;
- if (c == 'u')
+ if (c == 'u' || c == 'U')
sizes = 8;
- if (c == 's')
+ if (c == 's' || c == 'S')
sizes = 1;
- if (c == 'x')
+ if (c == 'x' || c == 'X')
sizes = 2;
- if (c == 'p')
+ if (c == 'p' || c == 'P')
sizes = 3;
- if (c == 'd')
+ if (c == 'd' || c == 'D')
sizes = 5;
}
int __cdecl main(int argc, char *argv[])
{
const struct cputbl *tbl = NULL;
- TCHAR path[1000];
+ TCHAR path[1000], *vs;
int v;
struct ini_data *ini = ini_load(_T("cputestgen.ini"), false);
feature_exception3_instruction = 0;
ini_getval(ini, INISECTION, _T("feature_exception3_instruction"), &feature_exception3_instruction);
- v = -1;
- ini_getval(ini, INISECTION, _T("feature_target_src_ea"), &v);
- feature_target_ea[0] = v;
- v = -1;
- ini_getval(ini, INISECTION, _T("feature_target_dst_ea"), &v);
- feature_target_ea[1] = v;
+ feature_target_ea[0] = 0xffffffff;
+ if (ini_getval(ini, INISECTION, _T("feature_target_src_ea"), &v))
+ feature_target_ea[0] = v;
+ feature_target_ea[1] = 0xffffffff;
+ if (ini_getval(ini, INISECTION, _T("feature_target_dst_ea"), &v))
+ feature_target_ea[1] = v;
+
if (feature_target_ea[0] != 0xffffffff || feature_target_ea[1] != 0xffffffff) {
if (feature_target_ea[0] & 1) {
feature_exception3_data = 3;
feature_test_rounds = 2;
ini_getval(ini, INISECTION, _T("test_rounds"), &feature_test_rounds);
+ feature_instruction_size = NULL;
+ ini_getstring(ini, INISECTION, _T("feature_instruction_size"), &feature_instruction_size);
+
+ ini_getval(ini, INISECTION, _T("feature_instruction_size"), &feature_test_rounds);
+
v = 0;
ini_getval(ini, INISECTION, _T("test_memory_start"), &v);
if (!v) {
static uae_u32 addressing_mask = 0x00ffffff;
static uae_u32 interrupt_mask;
-#define SIZE_STORED_ADDRESS 20
+#define SIZE_STORED_ADDRESS_OFFSET 8
+#define SIZE_STORED_ADDRESS 16
static uae_u8 srcaddr[SIZE_STORED_ADDRESS];
static uae_u8 dstaddr[SIZE_STORED_ADDRESS];
static uae_u8 stackaddr[SIZE_STORED_ADDRESS];
exit(0);
}
}
- if (safe_memory_start == (uae_u8*)0xffffffff && safe_memory_end == (uae_u8*)0xffffffff) {
- *sizep = fread(p, 1, size, f);
- } else if (safe_memory_end < p || safe_memory_start >= p + size) {
+ if (safe_memory_end < p || safe_memory_start >= p + size) {
*sizep = fread(p, 1, size, f);
} else {
- *sizep = size;
- uae_u8 *pp = p;
- while (size > 0) {
- int size2 = size > sizeof(tmpbuffer) ? sizeof(tmpbuffer) : size;
- if (p + size2 > safe_memory_start && p < safe_memory_end) {
- if (fread(tmpbuffer, 1, size2, f) != size2) {
- printf("Couldn't read file '%s' %ld\n", fname, size2);
- exit(0);
- }
- uae_u8 *sp = tmpbuffer;
- for (int i = 0; i < size2; i++) {
- if (pp < safe_memory_start || pp >= safe_memory_end) {
- *pp = *sp;
- }
- pp++;
- sp++;
- }
- } else {
- if (fread(p, 1, size2, f) != size2) {
- printf("Couldn't read file '%s'\n", fname);
- exit(0);
- }
- p += size2;
- }
+ if (size > 0 && p < safe_memory_start) {
+ int size2 = safe_memory_start - p;
+ if (size2 > size)
+ size2 = size;
+ if (fread(p, 1, size2, f) != size2)
+ goto end;
+ p += size2;
+ size -= size2;
+ }
+ if (size > 0 && p >= safe_memory_start && p < safe_memory_end) {
+ int size2 = safe_memory_end - p;
+ if (size2 > size)
+ size2 = size;
+ fseek(f, size2, SEEK_CUR);
+ p += size2;
size -= size2;
}
+ if (size > 0) {
+ if (fread(p, 1, size, f) != size)
+ goto end;
+ }
size = *sizep;
}
if (*sizep != size) {
+end:
printf("Couldn't read file '%s'\n", fname);
exit(0);
}
static void addinfo_bytes(char *name, uae_u8 *src, uae_u32 address, int offset, int len)
{
- sprintf(outbp, "%s: %08lx ", name, address);
+ sprintf(outbp, "%s %08lx ", name, address);
address += offset;
outbp += strlen(outbp);
int cnt = 0;
}
*outbp = 0;
if (code[0] == 0x4e73 || code[0] == 0x4e74 || code[0] == 0x4e75) {
- addinfo_bytes("SA", stackaddr, stackaddr_ptr, -SIZE_STORED_ADDRESS / 2, SIZE_STORED_ADDRESS);
- addinfo_bytes(" ", (uae_u8 *)stackaddr_ptr - SIZE_STORED_ADDRESS / 2, stackaddr_ptr, -SIZE_STORED_ADDRESS / 2, SIZE_STORED_ADDRESS);
+ addinfo_bytes("P", stackaddr, stackaddr_ptr, -SIZE_STORED_ADDRESS_OFFSET, SIZE_STORED_ADDRESS);
+ addinfo_bytes(" ", (uae_u8 *)stackaddr_ptr - SIZE_STORED_ADDRESS_OFFSET, stackaddr_ptr, -SIZE_STORED_ADDRESS_OFFSET, SIZE_STORED_ADDRESS);
}
if (regs.srcaddr != 0xffffffff) {
uae_u8 *a = srcaddr;
- uae_u8 *b = (uae_u8 *)regs.srcaddr - SIZE_STORED_ADDRESS / 2;
- addinfo_bytes("SA", a, regs.srcaddr, -SIZE_STORED_ADDRESS / 2, SIZE_STORED_ADDRESS);
+ uae_u8 *b = (uae_u8 *)regs.srcaddr - SIZE_STORED_ADDRESS_OFFSET;
+ addinfo_bytes("S", a, regs.srcaddr, -SIZE_STORED_ADDRESS_OFFSET, SIZE_STORED_ADDRESS);
if (addr_diff(a, b, SIZE_STORED_ADDRESS)) {
- addinfo_bytes(" ", b, regs.srcaddr, -SIZE_STORED_ADDRESS / 2, SIZE_STORED_ADDRESS);
+ addinfo_bytes(" ", b, regs.srcaddr, -SIZE_STORED_ADDRESS_OFFSET, SIZE_STORED_ADDRESS);
}
}
if (regs.dstaddr != 0xffffffff) {
uae_u8 *a = dstaddr;
- uae_u8 *b = (uae_u8*)regs.dstaddr - SIZE_STORED_ADDRESS / 2;
- addinfo_bytes("DA", a, regs.dstaddr, -SIZE_STORED_ADDRESS / 2, SIZE_STORED_ADDRESS);
+ uae_u8 *b = (uae_u8*)regs.dstaddr - SIZE_STORED_ADDRESS_OFFSET;
+ addinfo_bytes("D", a, regs.dstaddr, -SIZE_STORED_ADDRESS_OFFSET, SIZE_STORED_ADDRESS);
if (addr_diff(a, b, SIZE_STORED_ADDRESS)) {
- addinfo_bytes(" ", b, regs.dstaddr, -SIZE_STORED_ADDRESS / 2, SIZE_STORED_ADDRESS);
+ addinfo_bytes(" ", b, regs.dstaddr, -SIZE_STORED_ADDRESS_OFFSET, SIZE_STORED_ADDRESS);
}
}
-
-#if 0
-int Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer);
-void Disasm_SetCPUType(int CPU, int FPU);
- Disasm_SetCPUType(0, 0);
- char buf1[80], buf2[80], buf3[80], buf4[80];
- Disass68k((long)opcode_memory, buf1, buf2, buf3, buf4);
- sprintf(outbp, "%s %s\n", buf2, buf3);
- outbp += strlen(outbp);
-#endif
}
struct srbit
exc = last_exception;
if (excdatalen != 0xff) {
if (cpu_lvl == 0) {
- if (excnum == 3) {
+ if (excnum == 2 || excnum == 3) {
// status (with undocumented opcode part)
uae_u8 opcode0 = p[1];
uae_u8 opcode1 = p[2];
{
if (s == 0xffffffff)
return;
- for (int i = -SIZE_STORED_ADDRESS / 2; i < SIZE_STORED_ADDRESS / 2; i++) {
- uae_u32 ss = s + i;
+ for (int i = 0; i < SIZE_STORED_ADDRESS; i++) {
+ uae_u32 ss = s + (i - SIZE_STORED_ADDRESS_OFFSET);
if (is_valid_test_addr(ss)) {
*d++ = *((uae_u8 *)ss);
} else {
cpu_lvl = get_cpu_model();
-#endif
-
if (cpu_lvl == 5) {
-#ifdef M68K
// Overwrite MOVEC to/from MSP
// with NOPs if 68060
extern void *msp_address1;
*((uae_u32*)&msp_address2) = 0x4e714e71;
*((uae_u32*)&msp_address3) = 0x4e714e71;
*((uae_u32*)&msp_address4) = 0x4e714e71;
-#endif
}
+#endif
+
if (argc < 2) {
printf("cputest <all/mnemonic> (<start mnemonic>) (continue)\n");
printf("mnemonic = test single mnemonic\n");
static int n_braces, limit_braces;
static int m68k_pc_offset, m68k_pc_offset_old;
static int m68k_pc_total;
+static int exception_pc_offset;
static int branch_inst;
static int insn_n_cycles, insn_n_cycles020;
static int ir2irc;
start_brace ();
}
+static char bus_error_text[200];
+
+static void do_instruction_buserror(void)
+{
+ if (bus_error_text[0]) {
+ printf("\tif(cpu_bus_error) {\n");
+ printf("%s", bus_error_text);
+ printf("\t\tgoto %s;\n", endlabelstr);
+ need_endlabel = 1;
+ printf("\t}\n");
+ bus_error_text[0] = 0;
+ }
+}
+
+static void check_bus_error_ins(int offset)
+{
+ sprintf(bus_error_text, "\t\texception2_read(opcode, m68k_getpci() + %d, 2);\n", offset);
+}
+
+static void check_prefetch_bus_error(int offset)
+{
+ check_bus_error_ins(offset);
+ do_instruction_buserror();
+}
+
static void gen_nextilong2 (const char *type, const char *name, int flags, int movem)
{
int r = m68k_pc_offset;
}
static void gen_nextilong (const char *type, const char *name, int flags)
{
+ bus_error_text[0] = 0;
gen_nextilong2 (type, name, flags, 0);
}
int r = m68k_pc_offset;
m68k_pc_offset += 2;
+ bus_error_text[0] = 0;
if (using_ce020) {
if (flags & GF_NOREFILL)
sprintf(buffer, "%s (%d)", prefetch_word, r);
} else {
sprintf (buffer, "%s (%d)", prefetch_word, r + 2);
count_read++;
+ check_bus_error_ins(r + 2);
}
} else {
if (using_prefetch) {
} else {
sprintf (buffer, "%s (%d)", prefetch_word, r + 2);
count_read++;
+ check_bus_error_ins(r + 2);
insn_n_cycles += 4;
}
} else {
sprintf (buffer, "%s (%d)", prefetch_word, r);
+ check_bus_error_ins(r);
insn_n_cycles += 4;
}
}
int r = m68k_pc_offset;
m68k_pc_offset += 2;
+ bus_error_text[0] = 0;
if (using_ce020 || using_prefetch_020) {
if (flags & GF_NOREFILL)
sprintf(buffer, "(uae_u8)%s (%d)", prefetch_word, r);
} else {
sprintf (buffer, "(uae_u8)%s (%d)", prefetch_word, r + 2);
count_read++;
+ check_bus_error_ins(r + 2);
}
} else {
insn_n_cycles += 4;
strcpy (buffer, "(uae_u8)regs.irc");
} else {
sprintf (buffer, "(uae_u8)%s (%d)", prefetch_word, r + 2);
- insn_n_cycles += 4;
count_read++;
+ check_bus_error_ins(r + 2);
+ insn_n_cycles += 4;
}
} else {
sprintf (buffer, "%s (%d)", srcbi, r);
+ check_bus_error_ins(r);
insn_n_cycles += 4;
}
}
if (!using_prefetch)
return;
printf ("\t%s (%d);\n", prefetch_word, m68k_pc_offset + 2);
+ check_prefetch_bus_error(m68k_pc_offset + 2);
did_prefetch = 1;
ir2irc = 0;
count_read++;
{
if (using_prefetch) {
printf ("\t%s (%d);\n", prefetch_word, o);
+ check_prefetch_bus_error(o);
did_prefetch = 1;
ir2irc = 0;
count_read++;
if (!using_prefetch)
return;
printf ("\t%s (0);\n", prefetch_word);
+ check_prefetch_bus_error(0);
did_prefetch = 1;
ir2irc = 0;
count_read++;
if (!using_prefetch)
return;
printf ("\t%s (%d);\n", srcwi, o);
+ check_prefetch_bus_error(o);
count_read++;
insn_n_cycles += 4;
}
}
}
+static char const *bus_error_reg;
+static int bus_error_reg_add;
+
+static void check_bus_error(const char *name, int offset, int write, int fc)
+{
+ // check possible bus error (if 68000/010 and enabled)
+ if (!using_bus_error)
+ return;
+ if (!using_prefetch && !using_ce)
+ return;
+ printf("\tif(cpu_bus_error) {\n");
+
+ if (fc == 2) {
+
+ printf("\t\texception2_read(opcode, m68k_getpci() + %d, 2);\n", offset);
+
+ } else {
+
+ if (exception_pc_offset)
+ incpc("%d", exception_pc_offset);
+
+ switch (bus_error_reg_add)
+ {
+ case 1:
+ printf("\t\tm68k_areg(regs, %s) += areg_byteinc[%s] + %d;\n", bus_error_reg, bus_error_reg, offset);
+ break;
+ case 2:
+ printf("\t\tm68k_areg(regs, %s) += 2 + %d;\n", bus_error_reg, offset);
+ break;
+ case 3:
+ if (g_instr->mnemo == i_CMPM) {
+ // CMPM.L (an)+,(an)+: increased by 2
+ printf("\t\tm68k_areg(regs, %s) += 2 + %d;\n", bus_error_reg, offset);
+ } else {
+ // not increased if long first word causes bus error
+ ;
+ }
+ break;
+ case 4:
+ if ((g_instr->mnemo == i_ADDX || g_instr->mnemo == i_SUBX) && g_instr->size == sz_long) {
+ // ADDX.L/SUBX.L -(an),-(an): not decreased
+ ;
+ } else {
+ printf("\t\tm68k_areg (regs, %s) = %sa;\n", bus_error_reg, name);
+ }
+ break;
+ }
+
+ printf("\t\texception2_%s(opcode, %sa + %d, %d);\n",
+ write ? "write" : "read", name, offset,
+ (!write && (g_instr->smode == PC16 || g_instr->smode == PC8r) ? 2 : fc));
+ }
+
+ // if (exception_pc_offset)
+ // printf("\tbus_error_offset = %d;\n", exception_pc_offset);
+
+ printf("\t\tgoto %s;\n", endlabelstr);
+ printf("\t}\n");
+ need_endlabel = 1;
+}
+
static void gen_set_fault_pc (bool multi, bool not68030)
{
int m68k_pc_total_old = m68k_pc_total;
default:
term ();
}
+ do_instruction_buserror();
maybeaddop_ce020 (flags);
syncmovepc (getv, flags);
return;
term ();
}
+ do_instruction_buserror();
+
syncmovepc (getv, flags);
maybeaddop_ce020 (flags);
/* We get here for all non-reg non-immediate addressing modes to
* actually fetch the value. */
- int exception_pc_offset = 0;
+ exception_pc_offset = 0;
if (getv == 2) {
// store
if (pc_68000_offset) {
start_brace ();
}
- if ((using_prefetch || using_ce) && using_bus_error && getv != 0) {
- if (exception_pc_offset)
- printf("\tbus_error_offset = %d;\n", exception_pc_offset);
- }
-
if (flags & GF_PREFETCH)
fill_prefetch_next ();
else if (flags & GF_IR2IRC)
irc2ir (true);
+ bus_error_reg_add = 0;
+ bus_error_reg = reg;
+ if (!movem) {
+ if (mode == Aipi) {
+ switch (size)
+ {
+ case sz_byte:
+ bus_error_reg_add = 1;
+ break;
+ case sz_word:
+ bus_error_reg_add = 2;
+ break;
+ case sz_long:
+ bus_error_reg_add = 3;
+ break;
+ }
+ } else if (mode == Apdi) {
+ bus_error_reg_add = 4;
+ }
+ }
+
if (getv == 1) {
const char *srcbx = !(flags & GF_FC) ? srcb : "sfc_nommu_get_byte";
const char *srcwx = !(flags & GF_FC) ? srcw : "sfc_nommu_get_word";
}
} else if (using_ce || using_prefetch) {
switch (size) {
- case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcbx, name); count_read++; break;
- case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcwx, name); count_read++; break;
- case sz_long: {
+ case sz_byte:
+ {
+ insn_n_cycles += 4; printf("\tuae_s8 %s = %s (%sa);\n", name, srcbx, name);
+ count_read++;
+ check_bus_error(name, 0, 0, 1);
+ break;
+ }
+ case sz_word:
+ {
+ insn_n_cycles += 4; printf("\tuae_s16 %s = %s (%sa);\n", name, srcwx, name);
+ count_read++;
+ check_bus_error(name, 0, 0, 1);
+ break;
+ }
+ case sz_long:
+ {
insn_n_cycles += 8;
- if ((flags & GF_REVERSE) && mode == Apdi)
- printf("\tuae_s32 %s = %s (%sa + 2); %s |= %s (%sa) << 16;\n", name, srcwx, name, name, srcw, name);
- else
- printf("\tuae_s32 %s = %s (%sa) << 16; %s |= %s (%sa + 2);\n", name, srcwx, name, name, srcw, name);
+ if ((flags & GF_REVERSE) && mode == Apdi) {
+ printf("\tuae_s32 %s = %s (%sa + 2);\n", name, srcwx, name);
+ check_bus_error(name, 0, 0, 1);
+ printf("\t%s |= % s(% sa) << 16; \n", name, srcw, name);
+ check_bus_error(name, 0, 0, 1);
+ } else {
+ printf("\tuae_s32 %s = %s (%sa) << 16;\n", name, srcwx, name);
+ check_bus_error(name, 0, 0, 1);
+ printf("\t%s |= % s(% sa + 2); \n", name, srcw, name);
+ check_bus_error(name, 2, 0, 1);
+ }
count_read += 2;
break;
}
}
}
+ bus_error_reg_add = 0;
+
/* We now might have to fix up the register for pre-dec or post-inc
* addressing modes. */
if (!movem)
check_ipl_again();
printf ("\tx_put_byte (%sa, %s);\n", to, from);
count_write++;
+ check_bus_error(to, 0, 1, 1);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
check_ipl_again();
printf ("\tx_put_word (%sa, %s);\n", to, from);
count_write++;
+ check_bus_error(to, 0, 1, 1);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
if (store_dir) {
printf ("\t%s (%sa + 2, %s);\n", dstwx, to, from);
+ check_bus_error(to, 2, 1, 1);
check_ipl_again();
printf ("%s (%sa, %s >> 16);\n", dstwx, to, from);
+ check_bus_error(to, 0, 1, 1);
} else {
printf ("\t%s (%sa, %s >> 16);\n", dstwx, to, from);
+ check_bus_error(to, 0, 1, 1);
check_ipl_again();
printf ("\t%s (%sa + 2, %s);\n", dstwx, to, from);
+ check_bus_error(to, 2, 1, 1);
}
count_write += 2;
break;
insn_n_cycles += 4;
printf ("\t%s (%sa, %s);\n", dstbx, to, from);
count_write++;
+ check_bus_error(to, 0, 1, 1);
break;
case sz_word:
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
printf ("\t%s (%sa, %s);\n", dstwx, to, from);
+ check_bus_error(to, 0, 1, 1);
count_write++;
break;
case sz_long:
insn_n_cycles += 8;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
- if (store_dir)
- printf ("\t%s (%sa + 2, %s); %s (%sa, %s >> 16);\n", dstwx, to, from, dstwx, to, from);
- else
- printf ("\t%s (%sa, %s >> 16); %s (%sa + 2, %s);\n", dstwx, to, from, dstwx, to, from);
+ if (store_dir) {
+ printf("\t%s(%sa + 2, %s);\n", dstwx, to, from);
+ check_bus_error(to, 2, 1, 1);
+ printf("\t%s(%sa, %s >> 16); \n", dstwx, to, from);
+ check_bus_error(to, 0, 1, 1);
+ } else {
+ printf("\t%s (%sa, %s >> 16);\n", dstwx, to, from);
+ check_bus_error(to, 0, 1, 1);
+ printf("\t%s(%sa + 2, %s); \n", dstwx, to, from);
+ check_bus_error(to, 2, 1, 1);
+ }
count_write += 2;
break;
default:
* weird things... */
case i_MVPRM: // MOVEP R->M
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
- printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
+ printf ("\tuaecptr mempa = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
if (curi->size == sz_word) {
- printf ("\t%s (memp, src >> 8);\n\t%s (memp + 2, src);\n", dstb, dstb);
+ printf("\t%s(mempa, src >> 8);\n", dstb);
+ check_bus_error("memp", 0, 1, 1);
+ printf("\t%s(mempa + 2, src); \n", dstb);
+ check_bus_error("memp", 2, 1, 1);
count_write += 2;
} else {
- printf ("\t%s (memp, src >> 24);\n\t%s (memp + 2, src >> 16);\n", dstb, dstb);
- printf ("\t%s (memp + 4, src >> 8);\n\t%s (memp + 6, src);\n", dstb, dstb);
+ printf("\t%s(mempa, src >> 24);\n", dstb);
+ check_bus_error("memp", 0, 1, 1);
+ printf("\t%s(mempa + 2, src >> 16);\n", dstb);
+ check_bus_error("memp", 2, 1, 1);
+ printf("\t%s(mempa + 4, src >> 8);\n", dstb);
+ check_bus_error("memp", 4, 1, 1);
+ printf("\t%s(mempa + 6, src); \n", dstb);
+ check_bus_error("memp", 6, 1, 1);
count_write += 4;
}
fill_prefetch_next ();
break;
case i_MVPMR: // MOVEP M->R
- printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
+ printf ("\tuaecptr mempa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
if (curi->size == sz_word) {
- printf ("\tuae_u16 val = (%s (memp) & 0xff) << 8;\n", srcb);
- printf ("\t val |= (%s (memp + 2) & 0xff);\n", srcb);
+ printf ("\tuae_u16 val = (%s (mempa) & 0xff) << 8;\n", srcb);
+ check_bus_error("memp", 0, 0, 1);
+ printf ("\t val |= (%s (mempa + 2) & 0xff);\n", srcb);
+ check_bus_error("memp", 2, 0, 1);
count_read += 2;
} else {
- printf ("\tuae_u32 val = (%s (memp) & 0xff) << 24;\n", srcb);
- printf ("\t val |= (%s (memp + 2) & 0xff) << 16;\n", srcb);
- printf ("\t val |= (%s (memp + 4) & 0xff) << 8;\n", srcb);
- printf ("\t val |= (%s (memp + 6) & 0xff);\n", srcb);
+ printf ("\tuae_u32 val = (%s (mempa) & 0xff) << 24;\n", srcb);
+ check_bus_error("memp", 0, 0, 1);
+ printf ("\t val |= (%s (mempa + 2) & 0xff) << 16;\n", srcb);
+ check_bus_error("memp", 2, 0, 1);
+ printf ("\t val |= (%s (mempa + 4) & 0xff) << 8;\n", srcb);
+ check_bus_error("memp", 4, 0, 1);
+ printf ("\t val |= (%s (mempa + 6) & 0xff);\n", srcb);
+ printf ("\t val |= (%s (mempa + 6) & 0xff);\n", srcb);
+ check_bus_error("memp", 6, 0, 1);
count_read += 4;
}
fill_prefetch_next ();
} else if (using_ce020 == 2) {
add_head_cycs (1);
printf ("\tm68k_do_rts_ce030 ();\n");
- } else if (using_ce) {
- printf ("\tm68k_do_rts_ce ();\n");
- } else if (using_prefetch || using_prefetch_020) {
+ } else if (using_ce || using_prefetch || (using_test && cpu_level <= 1)) {
+ printf("\tuaecptr newpc, dsta = m68k_areg(regs, 7);\n");
+ printf("\tnewpc = %s(dsta) << 16;\n", srcw);
+ check_bus_error("dst", 0, 0, 1);
+ printf("\tnewpc |= %s(dsta + 2);\n", srcw);
+ check_bus_error("dst", 2, 0, 1);
+ printf("\tm68k_areg(regs, 7) += 4;\n");
+ setpc("newpc");
+ } else if (using_prefetch_020 || (using_test && cpu_level >= 2)) {
printf ("\tm68k_do_rtsi ();\n");
} else {
printf ("\tm68k_do_rts ();\n");
clear_m68k_offset();
fill_prefetch_1 (0);
if (using_ce || using_prefetch) {
- printf ("\t%s (m68k_areg (regs, 7), nextpc >> 16);\n", dstw);
- printf ("\t%s (m68k_areg (regs, 7) + 2, nextpc);\n", dstw);
+ printf("\tuaecptr dsta = m68k_areg(regs, 7);\n");
+ printf("\t%s(dsta, nextpc >> 16);\n", dstw);
+ check_bus_error("dst", 0, 1, 1);
+ printf("\t%s(dsta + 2, nextpc);\n", dstw);
+ check_bus_error("dst", 2, 1, 1);
} else {
- printf ("\t%s (m68k_areg (regs, 7), nextpc);\n", dstl);
+ printf ("\t%s(m68k_areg(regs, 7), nextpc);\n", dstl);
}
if (using_debugmem) {
printf("\tif (debugmem_trace)\n");
printf ("\tm68k_do_bsr_ce030 (nextpc, s);\n");
} else if (using_ce) {
printf ("\tm68k_do_bsr_ce (nextpc, s);\n");
- } else if (using_prefetch || using_prefetch_020 || using_test) {
+ } else if (using_prefetch || (using_test && cpu_level <= 1)) {
+ printf("\tm68k_areg(regs, 7) -= 4;\n");
+ printf("\tuaecptr dsta = m68k_areg(regs, 7);\n");
+ printf("\t%s(dsta, nextpc >> 16);\n", dstw);
+ check_bus_error("dst", 0, 1, 1);
+ printf("\t%s(dsta + 2, nextpc);\n", dstw);
+ check_bus_error("dst", 2, 1, 1);
+ incpc("s");
+ } else if (using_prefetch_020 || (using_test && cpu_level >= 2)) {
printf ("\tm68k_do_bsri (nextpc, s);\n");
} else {
printf ("\tm68k_do_bsr (nextpc, s);\n");
}
using_exception_3 = 1;
+ using_bus_error = 1;
using_prefetch = 0;
using_prefetch_020 = 0;
using_ce = 0;