if (alloc && !bitplane_dma_access(hpos, coffset) && !cycle_line_pipe[offset]) {
cycle_line_pipe[offset] = CYCLE_PIPE_NONE | CYCLE_PIPE_COPPER;
blitter_pipe[offset] = CYCLE_PIPE_COPPER;
+#ifdef DEBUGGER
+ record_dma_event2(DMA_EVENT2_COPPERUSE, offset, vpos);
+#endif
}
coffset++;
}
{
// COPJMP when previous instruction is mid-cycle
cop_state.state = COP_read1;
+ record_dma_event2(DMA_EVENT2_COPPERUSE, hpos, vpos);
alloc_cycle(hpos, CYCLE_COPPER);
}
break;
dr->ipl = regs.ipl_pin;
}
+void record_dma_event2(uae_u32 evt2, int hpos, int vpos)
+{
+ struct dma_rec *dr;
+
+ if (!dma_record[0])
+ return;
+ if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
+ return;
+ dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
+ dr->evt2 |= evt2;
+ dr->ipl = regs.ipl_pin;
+}
+
void record_dma_event_data(uae_u32 evt, int hpos, int vpos, uae_u32 data)
{
struct dma_rec *dr;
if (dr->evt2 & DMA_EVENT2_IPLSAMPLE) {
l3[cl2++] = '^';
}
+ if (dr->evt2 & DMA_EVENT2_COPPERUSE) {
+ l3[cl2++] = 'C';
+ }
}
if (l5) {
#define DMA_EVENT_CPUINS 0x80000000
#define DMA_EVENT2_IPL 0x00000001
#define DMA_EVENT2_IPLSAMPLE 0x00000002
+#define DMA_EVENT2_COPPERUSE 0x00000004
#define DMARECORD_REFRESH 1
#define DMARECORD_CPU 2
extern void record_dma_replace(int hpos, int vpos, int type, int extra);
extern void record_dma_reset(int);
extern void record_dma_event(uae_u32 evt, int hpos, int vpos);
+extern void record_dma_event2(uae_u32 evt, int hpos, int vpos);
extern void record_dma_event_data(uae_u32 evt, int hpos, int vpos, uae_u32 data);
extern void record_dma_clear(int hpos, int vpos);
extern bool record_dma_check(int hpos, int vpos);