static const TCHAR *ciatype[] = { _T("default"), _T("391078-01"), 0 };
static const TCHAR *debugfeatures[] = { _T("segtracker"), _T("fsdebug"), 0 };
static const TCHAR *hvcsync[] = { _T("hvcsync"), _T("csync"), _T("hvsync"), 0 };
+static const TCHAR* eclocksync[] = { _T("default"), _T("68000"), _T("Gayle"), _T("68000_opt"), 0 };
struct hdcontrollerconfig
{
cfgfile_dwrite(f, _T("keyboard_handshake"), _T("%d"), currprefs.cs_kbhandshake);
cfgfile_dwrite(f, _T("chipset_hacks"), _T("0x%x"), p->cs_hacks);
cfgfile_dwrite(f, _T("eclockphase"), _T("%d"), p->cs_eclockphase);
+ cfgfile_dwrite_str(f, _T("eclocksync"), eclocksync[p->cs_eclocksync]);
if (is_board_enabled(p, ROMTYPE_CD32CART, 0)) {
cfgfile_dwrite_bool(f, _T("cd32fmv"), true);
|| cfgfile_strval(option, value, _T("unmapped_address_space"), &p->cs_unmapped_space, unmapped, 0)
|| cfgfile_strval(option, value, _T("ciaa_type"), &p->cs_ciatype[0], ciatype, 0)
|| cfgfile_strval(option, value, _T("ciab_type"), &p->cs_ciatype[1], ciatype, 0)
- || cfgfile_strboolval (option, value, _T("comp_flushmode"), &p->comp_hardflush, flushmode, 0))
+ || cfgfile_strboolval (option, value, _T("comp_flushmode"), &p->comp_hardflush, flushmode, 0)
+ || cfgfile_strval(option, value, _T("eclocksync"), &p->cs_eclocksync, eclocksync, 0))
return 1;
if (cfgfile_strval(option, value, _T("uaeboard"), &p->uaeboard, uaeboard_off, 1)) {
p->cs_color_burst = false;
p->cs_romisslow = false;
p->cs_toshibagary = false;
+ p->cs_eclocksync = 0;
p->cs_ciatype[0] = p->cs_ciatype[1] = 0;
switch (p->cs_compatible)
p->cs_ciaoverlay = 0;
p->cs_resetwarning = 0;
p->cs_unmapped_space = 1;
+ p->cs_eclocksync = 2;
if (has_expansion_with_rtc(p, 0x200000))
p->cs_rtc = 1;
break;
p->cs_resetwarning = 0;
p->cs_ciatodbug = true;
p->cs_ciatype[0] = p->cs_ciatype[1] = 1;
+ p->cs_eclocksync = 2;
if (has_expansion_with_rtc(p, 0x100000))
p->cs_rtc = 1;
break;
p->cs_pcmcia = 1;
p->cs_ksmirror_a8 = 1;
p->cs_ciaoverlay = 0;
+ p->cs_eclocksync = 2;
if (has_expansion_with_rtc(p, 0x200000))
p->cs_rtc = 1;
break;
p->cs_ksmirror_e0 = 0;
p->cs_z3autoconfig = true;
p->cs_unmapped_space = 1;
+ p->cs_eclocksync = 2;
break;
case CP_A4000T: // A4000T
p->cs_rtc = 2;
p->cs_ksmirror_e0 = 0;
p->cs_z3autoconfig = true;
p->cs_unmapped_space = 1;
+ p->cs_eclocksync = 2;
break;
case CP_CASABLANCA:
break;
#include "sampler.h"
#include "dongle.h"
#include "inputrecord.h"
-#include "autoconf.h"
#include "uae/ppc.h"
#include "rommgr.h"
#include "scsi.h"
*/
-#define E_CLOCK_SYNC 2
-#define E_CLOCK_1 4
-#define E_CLOCK_2 6
+#define E_CLOCK_SYNC_N 2
+#define E_CLOCK_START_N 4
+#define E_CLOCK_END_N 6
+#define E_CLOCK_TOD_N -2
-#define E_CLOCK_LENGTH (E_CLOCK_1 + E_CLOCK_2)
+#define E_CLOCK_SYNC_N2 4
+#define E_CLOCK_START_N2 6
+#define E_CLOCK_END_N2 6
+#define E_CLOCK_TOD_N2 0
+
+#define E_CLOCK_SYNC_X 4
+#define E_CLOCK_START_X 2
+#define E_CLOCK_END_X 6
+#define E_CLOCK_TOD_X 0
+
+static int e_clock_sync = E_CLOCK_SYNC_N;
+static int e_clock_start = E_CLOCK_START_N;
+static int e_clock_end = E_CLOCK_END_N;
+static int e_clock_tod = E_CLOCK_TOD_N;
+
+#define E_CLOCK_LENGTH 10
#define E_CYCLE_UNIT (CYCLE_UNIT / 2)
-#define DIV10 ((E_CLOCK_LENGTH) * E_CYCLE_UNIT) /* Yes, a bad identifier. */
+#define DIV10 (E_CLOCK_LENGTH * E_CYCLE_UNIT) /* Yes, a bad identifier. */
struct CIATimer
{
- uae_u16 timer;
- uae_u16 latch;
+ uae_u32 timer;
+ uae_u32 latch;
uae_u32 passed;
uae_u16 inputpipe;
uae_u32 loaddelay;
return currprefs.m68k_speed >= 0 && currprefs.cpu_compatible;
}
-int blop;
+int blop, blop2;
void cia_adjust_eclock_phase(int diff)
{
internaleclockphase += 20;
}
internaleclockphase %= 20;
+ write_log("CIA E-clock phase %d\n", internaleclockphase);
+}
+
+static void set_eclockphase(void)
+{
+ if (currprefs.cs_eclocksync == 3) {
+ e_clock_sync = E_CLOCK_SYNC_X;
+ e_clock_start = E_CLOCK_START_X;
+ e_clock_end = E_CLOCK_END_X;
+ e_clock_tod = E_CLOCK_TOD_X;
+ } else if (currprefs.cs_eclocksync == 2) {
+ e_clock_sync = E_CLOCK_SYNC_N2;
+ e_clock_start = E_CLOCK_START_N2;
+ e_clock_end = E_CLOCK_END_N2;
+ e_clock_tod = E_CLOCK_TOD_N2;
+ } else {
+ e_clock_sync = E_CLOCK_SYNC_N;
+ e_clock_start = E_CLOCK_START_N;
+ e_clock_end = E_CLOCK_END_N;
+ e_clock_tod = E_CLOCK_TOD_N;
+ }
}
static evt_t get_e_cycles(void)
cia_adjust_eclock_phase(1);
blop = 0;
}
+ if (blop2) {
+ if (currprefs.cs_eclocksync == 0) {
+ currprefs.cs_eclocksync = 1;
+ }
+ currprefs.cs_eclocksync += 1;
+ if (currprefs.cs_eclocksync >= 4) {
+ currprefs.cs_eclocksync = 1;
+ }
+ changed_prefs.cs_eclocksync = currprefs.cs_eclocksync;
+ set_eclockphase();
+ write_log("CIA elock timing mode %d\n", currprefs.cs_eclocksync);
+ blop2 = 0;
+ }
evt_t c = get_cycles();
c += currprefs.cs_eclockphase * E_CYCLE_UNIT;
c->icr2 = 0;
c->icr_change = false;
-
ovfl[0] = 0;
ovfl[1] = 0;
sp = 0;
CIA_calctimers();
}
+static int get_cia_sync_cycles(void)
+{
+ evt_t c = get_e_cycles();
+ int div10 = c % DIV10;
+ int add = 0;
+ int synccycle = e_clock_sync * E_CYCLE_UNIT;
+ if (div10 < synccycle) {
+ add += synccycle - div10;
+ }
+ else if (div10 > synccycle) {
+ add += DIV10 - div10;
+ add += synccycle;
+ }
+ // sync + 4 first cycles of E-clock
+ add += e_clock_start * E_CYCLE_UNIT;
+ return add;
+}
+
static void CIA_synced_interrupt(uae_u32 v)
{
CIA_update();
CIA_calctimers();
}
-#define CIA_IRQ_PHASE (6 * E_CYCLE_UNIT)
-
static void CIA_sync_interrupt(int num, uae_u8 icr)
{
struct CIA *c = &cia[num];
c->icr1 |= icr;
return;
}
- c->icr_change = true;
- evt_t evt = get_e_cycles();
- int delay = 0;
- int div10 = evt % DIV10;
-#if 0
- if (div10 > CIA_IRQ_PHASE) {
- delay = DIV10 - div10;
- } else if (div10 < CIA_IRQ_PHASE) {
- delay = CIA_IRQ_PHASE - div10;
- }
-#else
- if (div10 > 0) {
- delay += DIV10 - div10;
- }
-#endif
+ int delay = get_cia_sync_cycles();
event2_newevent_xx(-1, DIV10 + delay, num, CIA_synced_interrupt);
} else {
c->icr1 |= icr;
- c->icr_change = true;
CIA_check_ICR();
}
}
static int tod_inc_delay(int hoffset)
{
int hoff = hoffset + 1; // 1 = HSYNC/VSYNC Agnus pin output is delayed by 1 CCK
- evt_t c = get_e_cycles() + 2 * E_CYCLE_UNIT + hoff * CYCLE_UNIT;
+ evt_t c = get_e_cycles() + 6 * E_CYCLE_UNIT + hoff * CYCLE_UNIT;
int offset = hoff;
offset += TOD_INC_DELAY;
int unit = (E_CLOCK_LENGTH * 4) / 2; // 4 E-clocks
int div10 = (c / CYCLE_UNIT) % unit;
offset += unit - div10;
+ offset += e_clock_tod;
return offset;
}
CIA_calctimers();
DISK_select_set(cia[1].prb);
}
+ set_eclockphase();
map_overlay(0);
check_led();
#ifdef SERIAL_PORT
ABFLAG_IO | ABFLAG_CIA, S_READ, S_WRITE, NULL, 0x3f01, 0xbfc000
};
-static int get_cia_sync_cycles(void)
-{
- evt_t c = get_e_cycles();
- int div10 = c % DIV10;
- int add = 0;
- int synccycle = E_CLOCK_SYNC * E_CYCLE_UNIT;
- if (div10 < synccycle) {
- add += synccycle - div10;
- } else if (div10 > synccycle) {
- add += DIV10 - div10;
- add += synccycle;
- }
- // sync + 4 first cycles of E-clock
- add += E_CLOCK_1 * E_CYCLE_UNIT;
- return add;
-}
-
static void cia_wait_pre(int cianummask)
{
if (currprefs.cachesize || currprefs.cpu_thread)
if (currprefs.cpu_thread)
return;
if (currprefs.cachesize) {
- do_cycles(8 * E_CYCLE_UNIT);
+ do_cycles(12 * E_CYCLE_UNIT);
} else {
// Last 6 cycles of E-clock
- x_do_cycles_post(E_CLOCK_2 * E_CYCLE_UNIT, value);
+ x_do_cycles_post(e_clock_end * E_CYCLE_UNIT, value);
#if CIA_IRQ_PROCESS_DELAY
if (currprefs.cpu_memory_cycle_exact) {
cia_interrupt_disabled &= ~cianummask;
}
}
- int hdiff = (v & 0xff) - current_hpos();
- cia_adjust_eclock_phase(hdiff);
+ int hpos = current_hpos();
+ int hnew = v & 0xff;
+ int hdiff = hnew - hpos;
+ if (copper_access && (hdiff & 1)) {
+ write_log("VHPOSW write with odd horizontal change. Possible copper confusion possible.\n");
+ }
+ modify_eventcounter(-(hdiff - 2));
v >>= 8;
vpos &= 0xff00;
uae_u16 old = intreq;
setclr(&intreq, v);
- //write_log("%04x -> %04x %08x\n", old, intreq, M68K_GETPC);
+ //write_log("%04x %04x -> %04x %08x\n", v, old, intreq, M68K_GETPC);
if ((old & 0x0800) && !(intreq & 0x0800)) {
serial_rbf_clear();
currprefs.cs_romisslow = changed_prefs.cs_romisslow;
currprefs.cs_toshibagary = changed_prefs.cs_toshibagary;
currprefs.cs_unmapped_space = changed_prefs.cs_unmapped_space;
+ currprefs.cs_eclockphase = changed_prefs.cs_eclockphase;
+ currprefs.cs_eclocksync = changed_prefs.cs_eclocksync;
currprefs.cs_ciatype[0] = changed_prefs.cs_ciatype[0];
currprefs.cs_ciatype[1] = changed_prefs.cs_ciatype[1];
#include "xwin.h"
#include "x86.h"
#include "audio.h"
+#include "cia.h"
static const int pissoff_nojit_value = 256 * CYCLE_UNIT;
events_fast();
}
-void events_schedule (void)
+void events_schedule(void)
{
int i;
return false;
}
-void do_cycles_slow (int cycles_to_add)
+void do_cycles_slow(int cycles_to_add)
{
#ifdef WITH_X86
#if 0
}
}
}
- events_schedule ();
-
+ events_schedule();
}
currcycle += cycles_to_add;
}
-void MISC_handler (void)
+void MISC_handler(void)
{
static bool dorecheck;
bool recheck;
if (eventtab2[i].evtime == ct) {
eventtab2[i].active = false;
event2_count--;
- eventtab2[i].handler (eventtab2[i].data);
+ eventtab2[i].handler(eventtab2[i].data);
if (dorecheck || eventtab2[i].active) {
recheck = true;
dorecheck = false;
eventtab[ev_misc].active = true;
eventtab[ev_misc].oldcycles = ct;
eventtab[ev_misc].evtime = ct + mintime;
- events_schedule ();
+ events_schedule();
}
recursive--;
}
evt_t et;
static int next = ev2_misc;
- et = t + get_cycles ();
+ et = t + get_cycles();
if (no < 0) {
no = next;
for (;;) {
eventtab2[no].evtime = et;
eventtab2[no].handler = func;
eventtab2[no].data = data;
- MISC_handler ();
+ MISC_handler();
}
void event2_newevent_x_replace(evt_t t, uae_u32 data, evfunc2 func)
}
-int current_hpos (void)
+int current_hpos(void)
{
int hp = current_hpos_safe();
if (hp < 0 || hp > 256) {
return hp;
}
+// emulate VPOSHW writes changing cycle counter
+void modify_eventcounter(int diff)
+{
+
+ int hpos = current_hpos();
+
+ if (hpos + diff < 0) {
+ return;
+ }
+ if (hpos + diff >= maxhpos) {
+ return;
+ }
+
+ int cdiff = diff * CYCLE_UNIT;
+ if (cdiff < 0) {
+ if (currcycle >= cdiff) {
+ currcycle -= cdiff;
+ } else {
+ cdiff = -(int)currcycle;
+ currcycle = 0;
+ }
+ } else {
+ currcycle += cdiff;
+ }
+
+ int hp1 = current_hpos();
+
+ cia_adjust_eclock_phase(diff);
+
+ // adjust all existing timers
+ for (int i = 0; i < ev_max; i++) {
+ if (i != ev_hsync && i != ev_hsynch) {
+ eventtab[i].evtime += cdiff;
+ eventtab[i].oldcycles += cdiff;
+ }
+ }
+
+ for (int i = 0; i < ev2_max; i++) {
+ eventtab2[i].evtime += cdiff;
+ }
+
+ int hp2 = current_hpos();
+
+ events_schedule();
+}
extern void events_schedule(void);
extern void do_cycles_slow(int cycles_to_add);
extern void events_reset_syncline(void);
+extern void modify_eventcounter(int diff);
extern bool is_cycle_ce(uaecptr);
STATIC_INLINE int current_hpos_safe(void)
{
- int hp = (int)((get_cycles () - eventtab[ev_hsync].oldcycles)) / CYCLE_UNIT;
+ int hp = (int)((get_cycles() - eventtab[ev_hsync].oldcycles)) / CYCLE_UNIT;
return hp;
}
int cs_kbhandshake;
int cs_hvcsync;
int cs_eclockphase;
+ int cs_eclocksync;
struct boardromconfig expansionboard[MAX_EXPANSION_BOARDS];
#define IDC_CS_UNMAPPED 1858
#define IDC_CHS_CYLINDERS 1859
#define IDC_CS_HVCSYNC 1859
+#define IDC_CS_CIASYNC 1859
#define IDC_CHS_HEADS 1860
#define IDC_CONFIGCATEGORY 1860
#define IDC_CHS_SECTORS 1861
CONTROL "CIA 391078-01 [] CIA revision that can't read IO pin status in output mode",IDC_CS_CIA,
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,184,125,12
RTEXT "Unmapped address space:",IDC_STATIC,15,215,101,9
- COMBOBOX IDC_CS_UNMAPPED,125,212,113,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ COMBOBOX IDC_CS_UNMAPPED,125,212,71,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
GROUPBOX "Internal SCSI Hardware",IDC_STATIC,0,232,395,30
CONTROL "A3000 WD33C93 SCSI",IDC_CS_DMAC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,84,247,108,11
CONTROL "A4000T NCR53C710 SCSI",IDC_CS_DMAC2,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,200,247,125,11
CONTROL "Denise/Lisa revision:",IDC_CS_DENISE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,200,299,107,11
EDITTEXT IDC_CS_AGNUSREV,311,284,45,13,ES_AUTOHSCROLL
EDITTEXT IDC_CS_DENISEREV,311,298,45,13,ES_AUTOHSCROLL
+ COMBOBOX IDC_CS_CIASYNC,313,212,71,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ RTEXT "CIA E-Clock Sync",IDC_STATIC,206,215,101,9
END
IDD_AVIOUTPUT DIALOGEX 0, 0, 396, 316
STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD
FONT 8, "MS Sans Serif", 0, 0, 0x1
BEGIN
- GROUPBOX "Emulated Hardware",IDC_QUICKSTART_CONFIG,1,25,393,54
- RTEXT "Model:",IDC_STATIC,5,39,68,10,SS_CENTERIMAGE
- COMBOBOX IDC_QUICKSTART_MODEL,77,37,263,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
- CONTROL "NTSC [] North American and Japanese display standard, 60Hz refresh rate. Other countries use PAL (50Hz. display refresh rate)",IDC_NTSC,
- "Button",BS_AUTOCHECKBOX | WS_TABSTOP,347,39,35,12
- RTEXT "Configuration:",IDC_STATIC,5,58,68,10,SS_CENTERIMAGE
- COMBOBOX IDC_QUICKSTART_CONFIGURATION,77,56,310,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
- GROUPBOX "Compatibility vs Required CPU Power ",IDC_QUICKSTART_COMPA,1,83,393,36
- RTEXT "Best compatibility",IDC_STATIC,20,98,98,10,SS_CENTERIMAGE
- CONTROL "",IDC_QUICKSTART_COMPATIBILITY,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,145,93,115,21
- LTEXT "Low compatibility",IDC_STATIC,279,99,92,10,SS_CENTERIMAGE
- GROUPBOX "Host Configuration",IDC_QUICKSTART_HOST,1,123,393,35
- RTEXT "Configuration:",IDC_STATIC,5,136,68,10,SS_CENTERIMAGE
- COMBOBOX IDC_QUICKSTART_HOSTCONFIG,77,134,310,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
- GROUPBOX "Emulated Drives",IDC_QUICKSTART_DF,1,163,393,93
- CONTROL "Floppy drive DF0:",IDC_DF0QENABLE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,176,71,15
PUSHBUTTON "Select image file",IDC_DF0QQ,85,176,88,15
+ CONTROL "Floppy drive DF0:",IDC_DF0QENABLE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,176,71,15
+ COMBOBOX IDC_DF0TYPE,179,177,66,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
RTEXT "Write-protected",IDC_DF0WPTEXTQ,244,179,69,10,SS_CENTERIMAGE
CONTROL "",IDC_DF0WPQ,"Button",BS_AUTOCHECKBOX | BS_MULTILINE | WS_TABSTOP,318,177,10,15
PUSHBUTTON "?",IDC_INFO0Q,334,176,19,15
COMBOBOX IDC_DF0TEXTQ,9,195,379,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
CONTROL "Floppy drive DF1:",IDC_DF1QENABLE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,214,71,15
PUSHBUTTON "Select image file",IDC_DF1QQ,85,214,88,15
+ COMBOBOX IDC_DF1TYPE,179,215,68,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
RTEXT "Write-protected",IDC_DF1WPTEXTQ,243,217,69,10,SS_CENTERIMAGE
COMBOBOX IDC_CD0Q_TYPE,253,215,74,50,CBS_DROPDOWNLIST | NOT WS_VISIBLE | WS_VSCROLL | WS_TABSTOP
CONTROL "",IDC_DF1WPQ,"Button",BS_AUTOCHECKBOX | BS_MULTILINE | WS_TABSTOP,316,213,10,15
PUSHBUTTON "Set configuration",IDC_QUICKSTART_SETCONFIG,9,266,88,15,NOT WS_VISIBLE
GROUPBOX "Mode",IDC_STATIC,250,258,144,28,BS_LEFT
CONTROL "Start in Quickstart mode",IDC_QUICKSTARTMODE,"Button",BS_AUTOCHECKBOX | BS_LEFT | WS_TABSTOP,259,269,131,12
- COMBOBOX IDC_DF0TYPE,179,177,66,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
- COMBOBOX IDC_DF1TYPE,179,215,68,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ GROUPBOX "Emulated Hardware",IDC_QUICKSTART_CONFIG,1,25,393,54
+ RTEXT "Model:",IDC_STATIC,5,39,68,10,SS_CENTERIMAGE
+ COMBOBOX IDC_QUICKSTART_MODEL,77,37,263,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ CONTROL "NTSC [] North American and Japanese display standard, 60Hz refresh rate. Other countries use PAL (50Hz. display refresh rate)",IDC_NTSC,
+ "Button",BS_AUTOCHECKBOX | WS_TABSTOP,347,39,35,12
+ RTEXT "Configuration:",IDC_STATIC,5,58,68,10,SS_CENTERIMAGE
+ COMBOBOX IDC_QUICKSTART_CONFIGURATION,77,56,310,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ GROUPBOX "Compatibility vs Required CPU Power ",IDC_QUICKSTART_COMPA,1,83,393,36
+ RTEXT "Best compatibility",IDC_STATIC,20,98,98,10,SS_CENTERIMAGE
+ CONTROL "",IDC_QUICKSTART_COMPATIBILITY,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,145,93,115,21
+ LTEXT "Low compatibility",IDC_STATIC,279,99,92,10,SS_CENTERIMAGE
+ GROUPBOX "Host Configuration",IDC_QUICKSTART_HOST,1,123,393,35
+ RTEXT "Configuration:",IDC_STATIC,5,136,68,10,SS_CENTERIMAGE
+ COMBOBOX IDC_QUICKSTART_HOSTCONFIG,77,134,310,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ GROUPBOX "Emulated Drives",IDC_QUICKSTART_DF,1,163,393,93
END
IDD_FRONTEND DIALOGEX 0, 0, 420, 242
CheckDlgButton(hDlg, IDC_CS_ROMISSLOW, workprefs.cs_romisslow);
CheckDlgButton(hDlg, IDC_CS_CIA, workprefs.cs_ciatype[0]);
xSendDlgItemMessage(hDlg, IDC_CS_UNMAPPED, CB_SETCURSEL, workprefs.cs_unmapped_space, 0);
+ xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_SETCURSEL, workprefs.cs_eclocksync, 0);
txt[0] = 0;
_stprintf (txt, _T("%d"), workprefs.cs_rtc_adjust);
SetDlgItemText(hDlg, IDC_CS_RTCADJUST, txt);
if (val != CB_ERR)
workprefs.cs_unmapped_space = val;
+ val = xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_GETCURSEL, 0, 0L);
+ if (val != CB_ERR)
+ workprefs.cs_eclocksync = val;
+
cfgfile_compatibility_romtype(&workprefs);
if (workprefs.cs_rtc) {
ew(hDlg, IDC_CS_TOSHIBAGARY, e);
ew(hDlg, IDC_CS_ROMISSLOW, e);
ew(hDlg, IDC_CS_UNMAPPED, e);
+ ew(hDlg, IDC_CS_CIASYNC, e);
ew(hDlg, IDC_CS_CIA, e);
}
pages[CHIPSET2_ID] = hDlg;
currentpage = CHIPSET2_ID;
cs_compatible = workprefs.cs_compatible;
+ xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_RESETCONTENT, 0, 0L);
+ xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_ADDSTRING, 0, (LPARAM)_T("Autoselect"));
+ xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_ADDSTRING, 0, (LPARAM)_T("68000"));
+ xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_ADDSTRING, 0, (LPARAM)_T("Gayle"));
+ xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_ADDSTRING, 0, (LPARAM)_T("68000 Alternate"));
xSendDlgItemMessage(hDlg, IDC_CS_UNMAPPED, CB_RESETCONTENT, 0, 0L);
WIN32GUI_LoadUIString(IDS_UNMAPPED_ADDRESS, tmp, sizeof tmp / sizeof(TCHAR));
TCHAR *p1 = tmp;
projects / francis / winuae.git / commitdiff