write_return_cycles(0);
out("}\n");
}
- out("regs.sr = sr;\n");
check_ipl_always();
- out("MakeFromSR();\n");
+ if (cpu_level <= 1) {
+ out("checkint();\n");
+ out("regs.sr = sr;\n");
+ out("MakeFromSR_STOP();\n");
+ } else {
+ out("regs.sr = sr;\n");
+ out("checkint();\n");
+ out("MakeFromSR_STOP();\n");
+ }
out("do_cycles_stop(4);\n");
out("m68k_setstopped();\n");
// STOP does not prefetch anything
extern void REGPARAM3 MakeSR (void) REGPARAM;
extern void REGPARAM3 MakeFromSR(void) REGPARAM;
extern void REGPARAM3 MakeFromSR_T0(void) REGPARAM;
+extern void REGPARAM3 MakeFromSR_STOP(void) REGPARAM;
extern void REGPARAM3 MakeFromSR_intmask(uae_u16 oldsr, uae_u16 newsr) REGPARAM;
extern void REGPARAM3 Exception (int) REGPARAM;
extern void REGPARAM3 Exception_cpu(int) REGPARAM;
extern void IRQ_forced(int, int);
extern void prepare_interrupt (uae_u32);
extern void doint(void);
+extern void checkint(void);
extern void intlev_load(void);
extern void dump_counts (void);
extern int m68k_move2c (int, uae_u32 *);
}
// make sure interrupt is checked immediately after current instruction
-static void doint_imm(void)
+void checkint(void)
{
doint();
if (!currprefs.cachesize && !(regs.spcflags & SPCFLAG_INT) && (regs.spcflags & SPCFLAG_DOINT))
regs.t1 = (regs.sr >> 15) & 1;
regs.t0 = (regs.sr >> 14) & 1;
regs.s = (regs.sr >> 13) & 1;
- regs.m = (regs.sr >> 12) & 1;
+ regs.m = (regs.sr >> 12) & 1;
regs.intmask = (regs.sr >> 8) & 7;
if (currprefs.cpu_model >= 68020) {
}
#endif
- doint_imm();
+ if (t0trace >= 0) {
+ checkint();
+ }
+
if (regs.t1 || regs.t0) {
set_special (SPCFLAG_TRACE);
} else {
{
MakeFromSR_x(0);
}
+void REGPARAM2 MakeFromSR_STOP(void)
+{
+ MakeFromSR_x(-1);
+}
void REGPARAM2 MakeFromSR_intmask(uae_u16 oldsr, uae_u16 newsr)
{