static int ciavsyncmode;
static int diw_hstrt, diw_hstop;
static int diw_hcounter;
+static uae_u16 refptr;
#define HSYNCTIME (maxhpos * CYCLE_UNIT)
static int toscr_res, toscr_res2p;
static int toscr_nr_planes, toscr_nr_planes2, toscr_nr_planes_agnus, toscr_nr_planes_shifter;
static int fetchwidth;
-static int toscr_delay[2], toscr_delay_adjusted[2];
+static int toscr_delay[2], toscr_delay_adjusted[2], toscr_delay_sh[2];
static int delay_cycles, delay_lastcycle[2];
static bool bplcon1_written;
{
int delay1 = (bplcon1 & 0x0f) | ((bplcon1 & 0x0c00) >> 6);
int delay2 = ((bplcon1 >> 4) & 0x0f) | (((bplcon1 >> 4) & 0x0c00) >> 6);
- int shdelay1 = (bplcon1 >> 12) & 3;
- int shdelay2 = (bplcon1 >> 8) & 3;
+ int shdelay1 = (bplcon1 >> 8) & 3;
+ int shdelay2 = (bplcon1 >> 12) & 3;
int delaymask = fetchmode_mask >> toscr_res;
toscr_delay[0] = (delay1 & delaymask) << toscr_res;
toscr_delay[1] = (delay2 & delaymask) << toscr_res;
toscr_delay[1] |= shdelay2 >> (RES_MAX - toscr_res);
+ // AGA subpixel scrolling in lores/hires modes
+ toscr_delay_sh[0] = (shdelay1 & 3) >> toscr_res;
+ toscr_delay_sh[1] = (shdelay2 & 3) >> toscr_res;
+
#if SPEEDUP
/* SPEEDUP code still needs this hack */
int delayoffset = fetchmode_size - (((bpl_hstart - (HARD_DDF_START_REAL + DDF_OFFSET)) & fetchstart_mask) << 1);
thisline_decision.plfleft = hpos;
}
-static int fetch_warn (int nr, int hpos)
+static uae_s16 fetch_warn (int nr, int hpos)
{
- static int warned = 30;
+ static int warned1 = 30, warned2 = 30;
int add = fetchmode_bytes;
if (hpos == maxhpos - 1) {
- if (warned >= 0)
+ if (warned1 >= 0) {
write_log (_T("WARNING: BPL fetch conflicts with strobe refresh slot!\n"));
- add = (scanlinecount & 255) * fetchmode_bytes;
+ warned1--;
+ }
+ add = refptr & ~(0x0101);
} else {
- if (warned >= 0)
+ if (warned2 >= 0) {
+ warned2--;
write_log (_T("WARNING: BPL fetch at hpos 0x%02X!\n"), hpos);
+ }
+ add = refptr & ~(0x0101);
}
bitplane_line_crossing = hpos;
- warned--;
#if 0
line_cyclebased = vpos;
corrupt_offset = (vpos ^ (timeframes << 12)) & 0xff00;
bplpt[i] = (bplpt[i] & 0xffff0000) | v;
}
#endif
- return add;
+ return (uae_s16)add;
}
static void fetch (int nr, int fm, int hpos)
return vp;
}
+static void REFPTR(uae_u16 v)
+{
+ refptr = v;
+}
+
static int test_copper_dangerous (unsigned int address)
{
int addr = address & 0x01fe;
hsync_counter++;
+ refptr += 0x0200 * 4;
+
if (islinetoggle ())
lol ^= 1;
else
diwhigh_written = 0;
hdiwstate = DIW_waiting_start; // this does not reset at vblank
+ refptr = 0xffff;
FMODE (0, 0);
CLXCON (0);
CLXCON2 (0);
case 0x022: DSKPTL (value); break;
case 0x024: DSKLEN (value, hpos); break;
case 0x026: /* DSKDAT (value). Writing to DMA write registers won't do anything */; break;
-
+ case 0x028: REFPTR (value); break;
case 0x02A: VPOSW (value); break;
case 0x02C: VHPOSW (value); break;
case 0x02E: COPCON (value); break;
dskpt = RL; /* 020-022 DSKPT */
dsklen = RW; /* 024 DSKLEN */
RW; /* 026 DSKDAT */
- RW; /* 028 REFPTR */
+ refptr = RW; /* 028 REFPTR */
i = RW; lof_store = lof_current = (i & 0x8000) ? 1 : 0; lol = (i & 0x0080) ? 1 : 0; /* 02A VPOSW */
RW; /* 02C VHPOSW */
COPCON (RW); /* 02E COPCON */
SL (dskpt); /* 020-023 DSKPT */
SW (dsklen); /* 024 DSKLEN */
SW (0); /* 026 DSKDAT */
- SW (0); /* 028 REFPTR */
+ SW (refptr); /* 028 REFPTR */
SW ((lof_store ? 0x8001 : 0) | (lol ? 0x0080 : 0));/* 02A VPOSW */
SW (0); /* 02C VHPOSW */
SW (copcon); /* 02E COPCON */