return offset;
}
-static void check_bus_error(const char *name, int offset, int write, int size, const char *writevar, int fc)
+static void check_bus_error(const char *name, int offset, int write, int size, const char *writevar, int fc, int pcoffset)
{
int mnemo = g_instr->mnemo;
bus_error_cycles = 0;
}
- if (exception_pc_offset || exception_pc_offset_extra) {
- incpc("%d", exception_pc_offset + exception_pc_offset_extra);
+ if (pcoffset < 0) {
+ incpc("%d", m68k_pc_offset + 2);
+ } else if (exception_pc_offset || exception_pc_offset_extra || pcoffset) {
+ incpc("%d", exception_pc_offset + exception_pc_offset_extra + pcoffset);
}
if (g_instr->mnemo == i_MOVE && write) {
case sz_byte:
out("uae_s8 %s = %s(%sa);\n", name, srcbx, name);
count_readw++;
- check_bus_error(name, 0, 0, 0, NULL, 1);
+ check_bus_error(name, 0, 0, 0, NULL, 1, 0);
break;
case sz_word:
out("uae_s16 %s = %s(%sa);\n", name, srcwx, name);
count_readw++;
- check_bus_error(name, 0, 0, 1, NULL, 1);
+ check_bus_error(name, 0, 0, 1, NULL, 1, 0);
break;
case sz_long:
out("uae_s32 %s = %s(%sa);\n", name, srclx, name);
count_readl++;
- check_bus_error(name, 0, 0, 2, NULL, 1);
+ check_bus_error(name, 0, 0, 2, NULL, 1, 0);
break;
default: term();
}
{
out("uae_s8 %s = %s(%sa);\n", name, srcbx, name);
count_readw++;
- check_bus_error(name, 0, 0, 0, NULL, 1);
+ check_bus_error(name, 0, 0, 0, NULL, 1, 0);
break;
}
case sz_word:
{
out("uae_s16 %s = %s(%sa);\n", name, srcwx, name);
count_readw++;
- check_bus_error(name, 0, 0, 1, NULL, 1);
+ check_bus_error(name, 0, 0, 1, NULL, 1, 0);
break;
}
case sz_long:
if ((flags & GF_REVERSE) && mode == Apdi) {
out("uae_s32 %s = %s(%sa + 2);\n", name, srcwx, name);
count_readw++;
- check_bus_error(name, 0, 0, 1, NULL, 1);
+ check_bus_error(name, 0, 0, 1, NULL, 1, 0);
out("%s |= %s(%sa) << 16; \n", name, srcwx, name);
count_readw++;
- check_bus_error(name, -2, 0, 1, NULL, 1);
+ check_bus_error(name, -2, 0, 1, NULL, 1, 0);
} else {
out("uae_s32 %s = %s(%sa) << 16;\n", name, srcwx, name);
count_readw++;
- check_bus_error(name, 0, 0, 1, NULL, 1);
+ check_bus_error(name, 0, 0, 1, NULL, 1, 0);
out("%s |= %s(%sa + 2); \n", name, srcwx, name);
count_readw++;
- check_bus_error(name, 2, 0, 1, NULL, 1);
+ check_bus_error(name, 2, 0, 1, NULL, 1, 0);
}
break;
}
case sz_byte:
out("uae_s8 %s = %s(%sa);\n", name, srcbx, name);
count_readw++;
- check_bus_error(name, 0, 0, 0, NULL, 1);
+ check_bus_error(name, 0, 0, 0, NULL, 1, 0);
break;
case sz_word:
out("uae_s16 %s = %s(%sa);\n", name, srcwx, name);
count_readw++;
- check_bus_error(name, 0, 0, 1, NULL, 1);
+ check_bus_error(name, 0, 0, 1, NULL, 1, 0);
break;
case sz_long:
out("uae_s32 %s = %s(%sa);\n", name, srclx, name);
count_readl++;
- check_bus_error(name, 0, 0, 2, NULL, 1);
+ check_bus_error(name, 0, 0, 2, NULL, 1, 0);
break;
default: term();
}
case sz_byte:
out("%s(%sa, %s);\n", dstbx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 0, from, 1);
+ check_bus_error(to, 0, 1, 0, from, 1, 0);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term();
out("%s(%sa, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 1, from, 1);
+ check_bus_error(to, 0, 1, 1, from, 1, 0);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term();
out("%s(%sa, %s);\n", dstlx, to, from);
count_writel++;
- check_bus_error(to, 0, 1, 2, from, 1);
+ check_bus_error(to, 0, 1, 2, from, 1, 0);
break;
default:
term();
set_last_access();
out("%s(%sa, %s);\n", dstbx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 0, from, 1);
+ check_bus_error(to, 0, 1, 0, from, 1, 0);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
set_last_access();
out("%s(%sa, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 1, from, 1);
+ check_bus_error(to, 0, 1, 1, from, 1, 0);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
if (store_dir) {
out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 2, 1, 1, from, 1);
+ check_bus_error(to, 2, 1, 1, from, 1, 0);
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_writew++;
- check_bus_error(to, 0, 1, 1, tmp, 1);
+ check_bus_error(to, 0, 1, 1, tmp, 1, 0);
} else {
out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_writew++;
- check_bus_error(to, 0, 1, 1, tmp, 1);
+ check_bus_error(to, 0, 1, 1, tmp, 1, 0);
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
set_last_access();
out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 2, 1, 1, from, 1);
+ check_bus_error(to, 2, 1, 1, from, 1, 0);
}
break;
default:
set_last_access();
out("%s(%sa, %s);\n", dstbx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 0, from, 1);
+ check_bus_error(to, 0, 1, 0, from, 1, 0);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
set_last_access();
out("%s(%sa, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 1, from, 1);
+ check_bus_error(to, 0, 1, 1, from, 1, 0);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
if (store_dir) {
out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 2, 1, 1, from, 1);
+ check_bus_error(to, 2, 1, 1, from, 1, 0);
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
out("%s(%sa, %s >> 16); \n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_writew++;
- check_bus_error(to, 0, 1, 1, tmp, 1);
+ check_bus_error(to, 0, 1, 1, tmp, 1, 0);
} else {
out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_writew++;
- check_bus_error(to, 0, 1, 1, tmp, 1);
+ check_bus_error(to, 0, 1, 1, tmp, 1, 0);
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
set_last_access();
out("%s(%sa + 2, %s); \n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 2, 1, 1, from, 1);
+ check_bus_error(to, 2, 1, 1, from, 1, 0);
}
break;
default:
case sz_byte:
out("%s(%sa, %s);\n", dstbx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 0, from, 1);
+ check_bus_error(to, 0, 1, 0, from, 1, 0);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term();
out("%s(%sa, %s);\n", dstwx, to, from);
count_writew++;
- check_bus_error(to, 0, 1, 1, from, 1);
+ check_bus_error(to, 0, 1, 1, from, 1, 0);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
}
out("%s(%sa, %s);\n", dstlx, to, from);
count_writel++;
- check_bus_error(to, 0, 1, 2, from, 1);
+ check_bus_error(to, 0, 1, 2, from, 1, 0);
break;
default:
term();
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
- check_bus_error("src", 0, 0, table68k[opcode].size, NULL, 1);
+ check_bus_error("src", 0, 0, table68k[opcode].size, NULL, 1, 0);
out("srca += %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("}\n");
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
- check_bus_error("src", 0, 0, table68k[opcode].size, NULL, 1);
+ check_bus_error("src", 0, 0, table68k[opcode].size, NULL, 1, 0);
out("srca += %d;\n", size);
out("amask = movem_next[amask];\n");
out("}\n");
if (cpu_level <= 3) {
out("%s(srca);\n", srcw); // and final extra word fetch that goes nowhere..
count_readw++;
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, 0);
}
if (!next_level_040_to_030())
next_level_020_to_010();
out("uae_u16 mask = %s;\n", gen_nextiword (0));
check_prefetch_buserror(m68k_pc_offset);
out("uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
- if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
+ if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r) {
addcycles000(2);
+ }
genamode(NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, -1, GF_AA | GF_MOVE);
movem_ex3(0);
if (table68k[opcode].size == sz_long) {
out("while (dmask) {\n");
out("uae_u32 v = (%s(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);\n", srcw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, -1);
if (cpu_level == 0) {
// 68010 does not do partial updates
out("m68k_dreg(regs, movem_index1[dmask]) = v;\n");
out("v &= 0xffff0000;\n");
out("v |= %s(srca + 2); \n", srcw);
addcycles000_nonce(4);
- check_bus_error("src", 2, 0, 1, NULL, 1);
+ check_bus_error("src", 2, 0, 1, NULL, 1, -1);
out("m68k_dreg(regs, movem_index1[dmask]) = v;\n");
out("srca += %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("while (amask) {\n");
out("uae_u32 v = (%s(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);\n", srcw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, -1);
if (cpu_level == 0) {
out("m68k_areg(regs, movem_index1[amask]) = v;\n");
}
out("v &= 0xffff0000;\n");
out("v |= %s(srca + 2);\n", srcw);
addcycles000_nonce(4);
- check_bus_error("src", 2, 0, 1, NULL, 1);
+ check_bus_error("src", 2, 0, 1, NULL, 1, -1);
out("m68k_areg(regs, movem_index1[amask]) = v;\n");
out("srca += %d;\n", size);
out("amask = movem_next[amask];\n");
out("while (dmask) {\n");
out("uae_u32 v = (uae_s32)(uae_s16)%s(srca);\n", srcw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, -1);
out("m68k_dreg(regs, movem_index1[dmask]) = v;\n");
out("srca += %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("while (amask) {\n");
out("uae_u32 v = (uae_s32)(uae_s16)%s(srca);\n", srcw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, -1);
out("m68k_areg(regs, movem_index1[amask]) = v;\n");
out("srca += %d;\n", size);
out("amask = movem_next[amask];\n");
}
out("%s(srca);\n", srcw); // and final extra word fetch that goes nowhere..
count_readw++;
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, -1);
if (table68k[opcode].dmode == Aipi)
out("m68k_areg(regs, dstreg) = srca;\n");
count_ncycles++;
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
- check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask])", 1);
+ check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask])", 1, 0);
out("} else {\n");
out("%s, m68k_areg(regs, movem_index2[amask]) - %d);\n", putcode, size);
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
if (size == 4) {
- check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask]) - 4", 1);
+ check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask]) - 4", 1, 0);
} else {
- check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask]) - 2", 1);
+ check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask]) - 2", 1, 0);
}
out("}\n");
out("amask = movem_next[amask];\n");
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
- check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_dreg(regs, movem_index2[dmask])", 1);
+ check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_dreg(regs, movem_index2[dmask])", 1, 0);
out("dmask = movem_next[dmask];\n");
out("}\n");
out("m68k_areg(regs, dstreg) = srca;\n");
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
- check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_dreg(regs, movem_index1[dmask])", 1);
+ check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_dreg(regs, movem_index1[dmask])", 1, 0);
out("srca += %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("}\n");
if (cpu_level <= 3) {
addcycles000_nonce(cpu_level <= 1 ? size * 2 : 4);
}
- check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index1[amask])", 1);
+ check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index1[amask])", 1, 0);
out("srca += %d;\n", size);
out("amask = movem_next[amask];\n");
out("}\n");
out("while (amask) {\n");
out("%s(srca - 2, m68k_areg(regs, movem_index2[amask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", -2, 1, 1, "m68k_areg(regs, movem_index2[amask])", 1);
+ check_bus_error("src", -2, 1, 1, "m68k_areg(regs, movem_index2[amask])", 1, 0);
out("%s(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", -4, 1, 1, "m68k_areg(regs, movem_index2[amask]) >> 16", 1);
+ check_bus_error("src", -4, 1, 1, "m68k_areg(regs, movem_index2[amask]) >> 16", 1, 0);
out("srca -= %d;\n", size);
out("amask = movem_next[amask];\n");
out("}\n");
out("while (dmask) {\n");
out("%s(srca - 2, m68k_dreg(regs, movem_index2[dmask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", -2, 1, 1, "m68k_dreg(regs, movem_index2[dmask])", 1);
+ check_bus_error("src", -2, 1, 1, "m68k_dreg(regs, movem_index2[dmask])", 1, 0);
out("%s(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", -4, 1, 1, "m68k_dreg(regs, movem_index2[dmask]) >> 16", 1);
+ check_bus_error("src", -4, 1, 1, "m68k_dreg(regs, movem_index2[dmask]) >> 16", 1, 0);
out("srca -= %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("}\n");
out("while (dmask) {\n");
out("%s(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index1[dmask]) >> 16", 1);
+ check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index1[dmask]) >> 16", 1, 0);
out("%s(srca + 2, m68k_dreg(regs, movem_index1[dmask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 2, 1, 1, "m68k_dreg(regs, movem_index1[dmask])", 1);
+ check_bus_error("src", 2, 1, 1, "m68k_dreg(regs, movem_index1[dmask])", 1, 0);
out("srca += %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("}\n");
out("while (amask) {\n");
out("%s(srca, m68k_areg(regs, movem_index1[amask]) >> 16);\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index1[amask]) >> 16", 1);
+ check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index1[amask]) >> 16", 1, 0);
out("%s(srca + 2, m68k_areg(regs, movem_index1[amask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 2, 1, 1, "m68k_areg(regs, movem_index1[amask])", 1);
+ check_bus_error("src", 2, 1, 1, "m68k_areg(regs, movem_index1[amask])", 1, 0);
out("srca += %d;\n", size);
out("amask = movem_next[amask];\n");
out("}\n");
out("srca -= %d;\n", size);
out("%s(srca, m68k_areg(regs, movem_index2[amask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index2[amask])", 1);
+ check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index2[amask])", 1, 0);
out("amask = movem_next[amask];\n");
out("}\n");
out("while (dmask) {\n");
out("srca -= %d;\n", size);
out("%s(srca, m68k_dreg(regs, movem_index2[dmask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index2[dmask])", 1);
+ check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index2[dmask])", 1, 0);
out("dmask = movem_next[dmask];\n");
out("}\n");
out("m68k_areg(regs, dstreg) = srca;\n");
out("while (dmask) {\n");
out("%s(srca, m68k_dreg(regs, movem_index1[dmask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index1[dmask])", 1);
+ check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index1[dmask])", 1, 0);
out("srca += %d;\n", size);
out("dmask = movem_next[dmask];\n");
out("}\n");
out("while (amask) {\n");
out("%s(srca, m68k_areg(regs, movem_index1[amask]));\n", dstw);
addcycles000_nonce(4);
- check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index1[amask])", 1);
+ check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index1[amask])", 1, 0);
out("srca += %d;\n", size);
out("amask = movem_next[amask];\n");
out("}\n");
branch_inst = 0;
set_fpulimit = 0;
bus_error_cycles = 0;
+ exception_pc_offset = 0;
+ exception_pc_offset_extra = 0;
ir2irc = 0;
mmufixupcnt = 0;
bus_error_code2[0] = 0;
opcode_nextcopy = 0;
last_access_offset = -1;
- exception_pc_offset_extra = 0;
loopmode = 0;
// 68010 loop mode available if
}
break;
case i_SBCD:
+ exception_pc_offset_extra = 2;
if (!isreg (curi->smode))
addcycles000(2);
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
}
break;
case i_ABCD:
+ exception_pc_offset_extra = 2;
if (!isreg (curi->smode))
addcycles000(2);
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
if (curi->size == sz_word) {
out("%s(mempa, src >> 8);\n", dstb);
count_writew++;
- check_bus_error("memp", 0, 1, 0, "src >> 8", 1 | 0x10000);
+ check_bus_error("memp", 0, 1, 0, "src >> 8", 1 | 0x10000, 2);
out("%s(mempa + 2, src); \n", dstb);
count_writew++;
- check_bus_error("memp", 2, 1, 0, "src", 1);
+ check_bus_error("memp", 2, 1, 0, "src", 1, 2);
} else {
out("%s(mempa, src >> 24);\n", dstb);
count_writew++;
- check_bus_error("memp", 0, 1, 0, "src >> 24", 1 | 0x10000);
+ check_bus_error("memp", 0, 1, 0, "src >> 24", 1 | 0x10000, 0);
out("%s(mempa + 2, src >> 16);\n", dstb);
count_writew++;
- check_bus_error("memp", 2, 1, 0, "src >> 16", 1);
+ check_bus_error("memp", 2, 1, 0, "src >> 16", 1, 0);
out("%s(mempa + 4, src >> 8);\n", dstb);
count_writew++;
- check_bus_error("memp", 4, 1, 0, "src >> 8", 1 | 0x10000);
+ check_bus_error("memp", 4, 1, 0, "src >> 8", 1 | 0x10000, 0);
out("%s(mempa + 6, src); \n", dstb);
count_writew++;
- check_bus_error("memp", 6, 1, 0, "src", 1);
+ check_bus_error("memp", 6, 1, 0, "src", 1, 0);
}
fill_prefetch_next_t();
next_level_000();
if (curi->size == sz_word) {
out("uae_u16 val = (%s(mempa) & 0xff) << 8;\n", srcb);
count_readw++;
- check_bus_error("memp", 0, 0, 0, NULL, 1 | 0x10000);
+ check_bus_error("memp", 0, 0, 0, NULL, 1 | 0x10000, 2);
out("val |= (%s(mempa + 2) & 0xff);\n", srcb);
count_readw++;
- check_bus_error("memp", 2, 0, 0, NULL, 1);
+ check_bus_error("memp", 2, 0, 0, NULL, 1, 2);
} else {
out("uae_u32 val = (%s(mempa) & 0xff) << 24;\n", srcb);
count_readw++;
- check_bus_error("memp", 0, 0, 0, NULL, 1 | 0x10000);
+ check_bus_error("memp", 0, 0, 0, NULL, 1 | 0x10000, 2);
out("val |= (%s(mempa + 2) & 0xff) << 16;\n", srcb);
count_readw++;
- check_bus_error("memp", 2, 0, 0, NULL, 1);
+ check_bus_error("memp", 2, 0, 0, NULL, 1, 2);
// upper word gets updated after two bytes (makes only difference if bus error is possible)
if (cpu_level <= 1) {
out("val |= (%s(mempa + 4) & 0xff) << 8;\n", srcb);
count_readw++;
- check_bus_error("memp", 4, 0, 0, NULL, 1 | 0x10000);
+ check_bus_error("memp", 4, 0, 0, NULL, 1 | 0x10000, 2);
out("val |= (%s(mempa + 6) & 0xff);\n", srcb);
count_readw++;
- check_bus_error("memp", 6, 0, 0, NULL, 1);
+ check_bus_error("memp", 6, 0, 0, NULL, 1, 2);
}
genastore("val", curi->dmode, "dstreg", curi->size, "dst");
fill_prefetch_next_t();
exception_pc_offset_extra = -2;
}
genamode(curi, curi->smode, "srcreg", sz_word, "src", cpu_level == 0 ? 2 : 3, 0, cpu_level == 1 ? GF_NOFETCH : 0);
- exception_pc_offset_extra = 0;
out("MakeSR();\n");
if (isreg (curi->smode)) {
if (cpu_level == 0 && curi->size == sz_word) {
if (cpu_level == 0 && curi->size == sz_word) {
out("%s(srca);\n", srcw);
count_writew++;
- check_bus_error("src", 0, 0, 1, NULL, 1);
+ check_bus_error("src", 0, 0, 1, NULL, 1, 0);
}
fill_prefetch_next_after(1, NULL);
}
+ exception_pc_offset_extra = 0;
if (!isreg(curi->smode) && cpu_level == 1 && using_exception_3 && (using_prefetch || using_ce)) {
out("if(srca & 1) {\n");
out("exception3_write(opcode, srca, 1, regs.sr & 0x%x, 1);\n", curi->size == sz_byte ? 0x00ff : 0xffff);
out("uaecptr a = m68k_areg(regs, 7);\n");
out("uae_u16 sr = %s(a);\n", srcw);
count_readw++;
- check_bus_error("", 0, 0, 1, NULL, 1);
+ check_bus_error("", 0, 0, 1, NULL, 1, 0);
out("m68k_areg(regs, 7) += 6;\n");
out("uae_u32 pc = %s(a + 2) << 16;\n", srcw);
count_readw++;
- check_bus_error("", 2, 0, 1, NULL, 1);
+ check_bus_error("", 2, 0, 1, NULL, 1, 0);
out("pc |= %s(a + 2 + 2); \n", srcw);
count_readw++;
- check_bus_error("", 4, 0, 1, NULL, 1);
+ check_bus_error("", 4, 0, 1, NULL, 1, 0);
out("uae_u16 oldt1 = regs.t1;\n");
out("regs.sr = sr;\n");
out("uaecptr a = m68k_areg(regs, 7);\n");
out("uae_u16 sr = %s(a);\n", srcw);
count_readw++;
- check_bus_error("", 0, 0, 1, NULL, 1);
+ check_bus_error("", 0, 0, 1, NULL, 1, 0);
out("uae_u16 format = %s(a + 2 + 4);\n", srcw);
count_readw++;
- check_bus_error("", 6, 0, 1, NULL, 1);
+ check_bus_error("", 6, 0, 1, NULL, 1, 0);
out("uae_u32 pc = %s(a + 2) << 16;\n", srcw);
count_readw++;
- check_bus_error("", 2, 0, 1, NULL, 1);
+ check_bus_error("", 2, 0, 1, NULL, 1, 0);
out("int frame = format >> 12;\n");
out("int offset = 8;\n");
out("pc |= %s(a + 2 + 2); \n", srcw);
count_readw++;
- check_bus_error("", 4, 0, 1, NULL, 1);
+ check_bus_error("", 4, 0, 1, NULL, 1, 0);
out("regs.sr = sr;\n");
makefromsr();
out("if (pc & 1) {\n");
out("uaecptr newpc, dsta = m68k_areg(regs, 7);\n");
out("newpc = %s(dsta) << 16;\n", srcw);
count_readw++;
- check_bus_error("dst", 0, 0, 1, NULL, 1);
+ check_bus_error("dst", 0, 0, 1, NULL, 1, 0);
out("newpc |= %s(dsta + 2);\n", srcw);
count_readw++;
- check_bus_error("dst", 2, 0, 1, NULL, 1);
+ check_bus_error("dst", 2, 0, 1, NULL, 1, 0);
out("m68k_areg(regs, 7) += 4;\n");
setpc("newpc");
} else if (using_prefetch_020 || (using_test && cpu_level >= 2)) {
out("uaecptr dsta = m68k_areg(regs, 7);\n");
out("%s(dsta, nextpc >> 16);\n", dstw);
count_writew++;
- check_bus_error("dst", 0, 1, 1, "nextpc >> 16", 1);
+ check_bus_error("dst", 0, 1, 1, "nextpc >> 16", 1, 0);
out("%s(dsta + 2, nextpc);\n", dstw);
count_writew++;
- check_bus_error("dst", 2, 1, 1, "nextpc", 1);
+ check_bus_error("dst", 2, 1, 1, "nextpc", 1, 0);
} else {
if (cpu_level < 4)
out("%s(m68k_areg(regs, 7), nextpc);\n", dstl);
out("m68k_areg(regs, 7) -= 4;\n");
out("uaecptr dsta = m68k_areg(regs, 7);\n");
out("%s(dsta, nextpc >> 16);\n", dstw);
- check_bus_error("dst", 0, 1, 1, "nextpc >> 16", 1);
+ check_bus_error("dst", 0, 1, 1, "nextpc >> 16", 1, 0);
count_writew++;
out("%s(dsta + 2, nextpc);\n", dstw);
- check_bus_error("dst", 2, 1, 1, "nextpc", 1);
+ check_bus_error("dst", 2, 1, 1, "nextpc", 1, 0);
count_writew++;
incpc("s");
} else if (using_prefetch_020 || (using_test && cpu_level >= 2)) {
} else {
genamode(curi, curi->smode, "srcreg", curi->size, "src", 2, 0, GF_LRMW | GF_NOFETCH);
out("uae_u8 src = %s(srca);\n", srcb);
- check_bus_error("src", 0, 0, 0, "src", 1);
+ check_bus_error("src", 0, 0, 0, "src", 1, 0);
}
genflags(flag_logical, curi->size, "src", "", "");
if (!isreg(curi->smode)) {