#define CARD_FLAG_CHILD 8
#define CARD_FLAG_UAEROM 16
-// More information in first revision HRM Appendix_G
-#define BOARD_PROTOAUTOCONFIG 1
-
-#define BOARD_AUTOCONFIG_Z2 2
-#define BOARD_AUTOCONFIG_Z3 3
-#define BOARD_NONAUTOCONFIG_BEFORE 4
-#define BOARD_NONAUTOCONFIG_AFTER_Z2 5
-#define BOARD_NONAUTOCONFIG_AFTER_Z3 6
-#define BOARD_IGNORE 7
-
#define KS12_BOOT_HACK 1
#define EXP_DEBUG 0
{
return v == BOARD_NONAUTOCONFIG_AFTER_Z2 ||
v == BOARD_NONAUTOCONFIG_AFTER_Z3 ||
- v == BOARD_NONAUTOCONFIG_BEFORE;
+ v == BOARD_NONAUTOCONFIG_BEFORE ||
+ v == BOARD_PCI;
}
static bool ks12orolder(void)
return;
}
int devnum = (cd->flags >> 16) & 255;
- if (!_tcsicmp(cd->name, _T("Z2Fast"))) {
- p->fastmem[devnum].device_order = order;
- return;
- }
- if (!_tcsicmp(cd->name, _T("Z3Fast"))) {
- p->z3fastmem[devnum].device_order = order;
- return;
+ if (devnum < MAX_RAM_BOARDS) {
+ if (!_tcsicmp(cd->name, _T("Z2Fast"))) {
+ p->fastmem[devnum].device_order = order;
+ return;
+ }
+ if (!_tcsicmp(cd->name, _T("Z3Fast"))) {
+ p->z3fastmem[devnum].device_order = order;
+ return;
+ }
}
- if (!_tcsicmp(cd->name, _T("Z3RTG")) || !_tcsicmp(cd->name, _T("Z2RTG"))) {
- p->rtgboards[devnum].device_order = order;
- return;
+ if (devnum < MAX_RTG_BOARDS) {
+ if (!_tcsicmp(cd->name, _T("Z3RTG")) || !_tcsicmp(cd->name, _T("Z2RTG"))) {
+ p->rtgboards[devnum].device_order = order;
+ return;
+ }
}
-
}
static int get_order(struct uae_prefs *p, struct card_data *cd)
}
if (cd->zorro <= 0)
return -1;
- if (cd->zorro >= 4)
+ if (cd->zorro == BOARD_PCI)
+ return EXPANSION_ORDER_MAX - 1;
+ if (cd->zorro >= BOARD_NONAUTOCONFIG_BEFORE)
return -2;
if (cd->rc && cd->rc->back)
return cd->rc->back->device_order;
int devnum = (cd->flags >> 16) & 255;
- if (!_tcsicmp(cd->name, _T("Z2Fast")))
- return p->fastmem[devnum].device_order;
- if (!_tcsicmp(cd->name, _T("Z3Fast")))
- return p->z3fastmem[devnum].device_order;
- if (!_tcsicmp(cd->name, _T("Z3RTG")) || !_tcsicmp(cd->name, _T("Z2RTG")))
- return p->rtgboards[devnum].device_order;
+ if (devnum < MAX_RAM_BOARDS) {
+ if (!_tcsicmp(cd->name, _T("Z2Fast")))
+ return p->fastmem[devnum].device_order;
+ if (!_tcsicmp(cd->name, _T("Z3Fast")))
+ return p->z3fastmem[devnum].device_order;
+ }
+ if (devnum < MAX_RTG_BOARDS) {
+ if (!_tcsicmp(cd->name, _T("Z3RTG")) || !_tcsicmp(cd->name, _T("Z2RTG")))
+ return p->rtgboards[devnum].device_order;
+ }
if (!_tcsicmp(cd->name, _T("MegaChipRAM")))
return -1;
return EXPANSION_ORDER_MAX - 1;
static void expansion_autoconfig_sort(struct uae_prefs *p)
{
- const int zs[] = { BOARD_NONAUTOCONFIG_BEFORE, 0, BOARD_PROTOAUTOCONFIG, BOARD_AUTOCONFIG_Z2, BOARD_NONAUTOCONFIG_AFTER_Z2, BOARD_AUTOCONFIG_Z3, BOARD_NONAUTOCONFIG_AFTER_Z3, -1 };
+ const int zs[] = { BOARD_NONAUTOCONFIG_BEFORE, BOARD_PCI, 0, BOARD_PROTOAUTOCONFIG, BOARD_AUTOCONFIG_Z2, BOARD_NONAUTOCONFIG_AFTER_Z2, BOARD_AUTOCONFIG_Z3, BOARD_NONAUTOCONFIG_AFTER_Z3, -1 };
bool inuse[MAX_EXPANSION_BOARD_SPACE];
struct card_data *tcards[MAX_EXPANSION_BOARD_SPACE];
int new_cardno = 0;
for (int i = 0; i < MAX_RTG_BOARDS; i++) {
struct rtgboardconfig *rbc = &p->rtgboards[i];
int type = gfxboard_get_configtype(rbc);
- if (rbc->rtgmem_size && rbc->rtgmem_type >= GFXBOARD_HARDWARE && type == BOARD_NONAUTOCONFIG_BEFORE) {
+ if (rbc->rtgmem_size && rbc->rtgmem_type >= GFXBOARD_HARDWARE && (type == BOARD_NONAUTOCONFIG_BEFORE || type == BOARD_PCI)) {
cards_set[cardno].flags = 4 | (i << 16);
cards_set[cardno].name = _T("MainBoardRTG");
- cards_set[cardno].zorro = BOARD_NONAUTOCONFIG_BEFORE;
+ cards_set[cardno].zorro = type;
cards_set[cardno++].initnum = gfxboard_init_memory;
}
}
// add possible non-autoconfig boards
add_cpu_expansions(p, BOARD_NONAUTOCONFIG_BEFORE, NULL);
add_expansions(p, BOARD_NONAUTOCONFIG_BEFORE, NULL, 0);
+ add_expansions(p, BOARD_PCI, NULL, 0);
fastmem_num = 0;
add_expansions(p, BOARD_PROTOAUTOCONFIG, &fastmem_num, 0);
},
#endif
{
- _T("a1000wom512k"), _T("A1000 512k WOM"), _T("J�rg Huth"),
+ _T("a1000wom512k"), _T("A1000 512k WOM"), _T("Jörg Huth"),
NULL, NULL, NULL, NULL, ROMTYPE_512KWOM | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
NULL, 0,
false, EXPANSIONTYPE_INTERNAL
},
{
_T("es1370"), _T("ES1370 PCI"), _T("Ensoniq"),
- NULL, pci_expansion_init, NULL, NULL, ROMTYPE_ES1370 | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
+ NULL, pci_expansion_init, NULL, NULL, ROMTYPE_ES1370 | ROMTYPE_NOT, 0, 0, BOARD_PCI, true,
NULL, 0,
false, EXPANSIONTYPE_SOUND
},
{
_T("fm801"), _T("FM801 PCI"), _T("Fortemedia"),
- NULL, pci_expansion_init, NULL, NULL, ROMTYPE_FM801 | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
+ NULL, pci_expansion_init, NULL, NULL, ROMTYPE_FM801 | ROMTYPE_NOT, 0, 0, BOARD_PCI, true,
NULL, 0,
false, EXPANSIONTYPE_SOUND
},
},
{
_T("ne2000_pci"), _T("RTL8029 PCI (NE2000 compatible)"), NULL,
- NULL, pci_expansion_init, NULL, NULL, ROMTYPE_NE2KPCI | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
+ NULL, pci_expansion_init, NULL, NULL, ROMTYPE_NE2KPCI | ROMTYPE_NOT, 0, 0, BOARD_PCI, true,
NULL, 0,
false, EXPANSIONTYPE_NET,
0, 0, 0, false, NULL,
#include "qemuvga/qemuuaeglue.h"
#include "qemuvga/vga.h"
#include "draco.h"
-
+#include "autoconf.h"
extern void put_io_pcem(uaecptr, uae_u32, int);
extern uae_u32 get_io_pcem(uaecptr, int);
GFXBOARD_ID_A2410,
_T("A2410 [Zorro II]"), _T("Commodore"), _T("A2410"),
1030, 0, 0, 0,
- 0x00000000, 0x00200000, 0x00200000, 0x10000, 0, 0, 2, false, false,
+ 0x00000000, 0x00200000, 0x00200000, 0x10000, 0, 2, 2, false, false,
0, 0xc1, &a2410_func
},
{
GFXBOARD_ID_PERMEDIA2_PCI,
_T("BlizzardVision/CyberVision PPC (Permedia2) [PCI]"), _T("3DLabs"), _T("PERMEDIA2_PCI"),
0, 0, 0, 0,
- 0x00000000, 0x00800000, 0x00800000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00800000, 0x00800000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &permedia2_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_ALTAIS_Z3,
_T("Altais [DracoBus]"), _T("MacroSystem"), _T("Altais"),
18260, 19, 0, 0,
- 0x00000000, 0x00400000, 0x00400000, 0x00400000, 0, 4, 3, false, false,
+ 0x00000000, 0x00400000, 0x00400000, 0x00400000, 0, BOARD_NONAUTOCONFIG_BEFORE, 3, false, false,
0, 0, NULL, &ncr_retina_z3_device, 0, GFXBOARD_BUSTYPE_DRACO
},
{
GFXBOARD_ID_EGS_110_24,
_T("EGS 110/24 [GVP local bus]"), _T("GVP"), _T("EGS_110_24"),
2193, 0, 0, 0,
- 0x00000000, 0x00400000, 0x00800000, 0x00800000, 0, 4, 2, false, false,
+ 0x00000000, 0x00400000, 0x00800000, 0x00800000, 0, BOARD_NONAUTOCONFIG_BEFORE, 2, false, false,
0, 0, NULL, &inmos_egs_110_24_device
},
{
GFXBOARD_ID_VOODOO3_PCI,
_T("Voodoo 3 3000 [PCI]"), _T("3dfx"), _T("V3_3000"),
0, 0, 0, 0,
- 0x00000000, 0x01000000, 0x01000000, 0x01000000, 0, 0, -1, false, false,
+ 0x00000000, 0x01000000, 0x01000000, 0x01000000, 0, BOARD_PCI, -1, false, false,
ROMTYPE_VOODOO3,
0, NULL, &voodoo_3_3000_device, 0, GFXBOARD_BUSTYPE_PCI
},
GFXBOARD_ID_S3VIRGE_PCI,
_T("Virge [PCI]"), _T("S3"), _T("S3VIRGE_PCI"),
0, 0, 0, 0,
- 0x00000000, 0x00400000, 0x00400000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00400000, 0x00400000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &s3_virge_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_S3TRIO64_PCI,
_T("Trio64 [PCI]"), _T("S3"), _T("S3TRIO64_PCI"),
0, 0, 0, 0,
- 0x00000000, 0x00200000, 0x00400000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00200000, 0x00400000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &s3_trio64_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_MATROX_MILLENNIUM_PCI,
_T("Matrox Millennium [PCI]"), _T("Matrox"), _T("Matrox_Millennium"),
0, 0, 0, 0,
- 0x00000000, 0x00200000, 0x00400000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00200000, 0x00400000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &millennium_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_MATROX_MILLENNIUM_II_PCI,
_T("Matrox Millennium II [PCI]"), _T("Matrox"), _T("Matrox_Millennium_II"),
0, 0, 0, 0,
- 0x00000000, 0x00200000, 0x01000000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00200000, 0x01000000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &millennium_ii_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_MATROX_MYSTIQUE_PCI,
_T("Matrox Mystique [PCI]"), _T("Matrox"), _T("Matrox_Mystique"),
0, 0, 0, 0,
- 0x00000000, 0x00200000, 0x00800000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00200000, 0x00800000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &mystique_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_MATROX_MYSTIQUE220_PCI,
_T("Matrox Mystique 220 [PCI]"), _T("Matrox"), _T("Matrox_Mystique220"),
0, 0, 0, 0,
- 0x00000000, 0x00200000, 0x00800000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00200000, 0x00800000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &mystique_220_device, 0, GFXBOARD_BUSTYPE_PCI
},
#if 0
GFXBOARD_ID_GD5446_PCI,
_T("GD5446 [PCI]"), _T("Cirrus Logic"), _T("GD5446_PCI"),
0, 0, 0, 0,
- 0x00000000, 0x00400000, 0x00400000, 0x10000000, 0, 0, -1, false, false,
+ 0x00000000, 0x00400000, 0x00400000, 0x10000000, 0, BOARD_PCI, -1, false, false,
0, 0, NULL, &gd5446_device, 0, GFXBOARD_BUSTYPE_PCI
},
#endif
};
extern const struct memoryboardtype memoryboards[];
+// More information in first revision HRM Appendix_G
+#define BOARD_PROTOAUTOCONFIG 1
+#define BOARD_AUTOCONFIG_Z2 2
+#define BOARD_AUTOCONFIG_Z3 3
+#define BOARD_NONAUTOCONFIG_BEFORE 4
+#define BOARD_NONAUTOCONFIG_AFTER_Z2 5
+#define BOARD_NONAUTOCONFIG_AFTER_Z3 6
+#define BOARD_PCI 7
+#define BOARD_IGNORE 8
#endif /* UAE_AUTOCONF_H */
}
ew(hDlg, IDC_SCSIROMFILE, true);
ew(hDlg, IDC_SCSIROMCHOOSER, true);
- hide(hDlg, IDC_SCSIROMFILEAUTOBOOT, 0);
+ hide(hDlg, IDC_SCSIROMFILEAUTOBOOT, !ert->autoboot_jumper);
if (romtype & ROMTYPE_NOT) {
hide(hDlg, IDC_SCSIROMCHOOSER, 1);
hide(hDlg, IDC_SCSIROMFILE, 1);
static struct pci_bridge *pci_bridge_get_zorro(struct romconfig *rc)
{
+ static int lastbridge;
for (int i = 0; i < PCI_BRIDGE_MAX; i++) {
- if (bridges[i] && bridges[i]->rc == rc) {
+ int idx = (i + lastbridge) % PCI_BRIDGE_MAX;
+ if (bridges[idx] && bridges[idx]->rc == rc) {
+ lastbridge = i;
return bridges[i];
}
}
struct pci_bridge *pci_bridge_get(void)
{
- // FIXME!
+ static int lastbridge;
for (int i = 0; i < PCI_BRIDGE_MAX; i++) {
- if (bridges[i])
- return bridges[i];
+ int idx = (i + lastbridge) % PCI_BRIDGE_MAX;
+ if (bridges[idx]) {
+ lastbridge = i;
+ return bridges[idx];
+ }
}
return NULL;
}
pci_bridge_wput_2(addr + 2, b >> 0);
}
-
-addrbank pci_config_bank = {
+static addrbank pci_config_bank = {
pci_config_lget, pci_config_wget, pci_config_bget,
pci_config_lput, pci_config_wput, pci_config_bput,
default_xlate, default_check, NULL, NULL, _T("PCI CONFIG"),
pci_config_lget, pci_config_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
-addrbank pci_io_bank = {
+static addrbank pci_io_bank = {
pci_io_lget, pci_io_wget, pci_io_bget,
pci_io_lput, pci_io_wput, pci_io_bput,
default_xlate, default_check, NULL, NULL, _T("PCI IO"),
pci_io_lget, pci_io_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
-addrbank pci_mem_bank = {
+static addrbank pci_mem_bank = {
pci_mem_lget, pci_mem_wget, pci_mem_bget,
pci_mem_lput, pci_mem_wput, pci_mem_bput,
default_xlate, default_check, NULL, NULL, _T("PCI MEMORY"),
pci_mem_lget, pci_mem_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
-addrbank pci_bridge_bank = {
+static addrbank pci_bridge_bank = {
pci_bridge_lget, pci_bridge_wget, pci_bridge_bget,
pci_bridge_lput, pci_bridge_wput, pci_bridge_bput,
default_xlate, default_check, NULL, NULL, _T("PCI BRIDGE"),
pci_bridge_lget, pci_bridge_wget,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
-addrbank pci_bridge_bank_2 = {
+static addrbank pci_bridge_bank_2 = {
pci_bridge_lget_2, pci_bridge_wget_2, pci_bridge_bget_2,
pci_bridge_lput_2, pci_bridge_wput_2, pci_bridge_bput_2,
default_xlate, default_check, NULL, NULL, _T("PCI BRIDGE #2"),