#define RX_STP 0x0200
#define RX_ENP 0x0100
+DECLARE_MEMORY_FUNCTIONS(a2065);
+
static uae_u16 gword2 (uae_u8 *p)
{
return (p[0] << 8) | p[1];
a2065_wput (addr + 2, l);
}
-DECLARE_MEMORY_FUNCTIONS(a2065);
+uae_u8 *REGPARAM2 a2065_xlate(uaecptr addr)
+{
+ if ((addr & 65535) >= RAM_OFFSET)
+ return &boardram[addr & RAM_MASK];
+ return default_xlate(addr);
+}
+
+int REGPARAM2 a2065_check(uaecptr a, uae_u32 b)
+{
+ a &= 65535;
+ return a >= RAM_OFFSET && a + b < 65536;
+}
static addrbank a2065_bank = {
a2065_lget, a2065_wget, a2065_bget,
a2065_lput, a2065_wput, a2065_bput,
- default_xlate, default_check, NULL, NULL, _T("A2065 Z2 Ethernet"),
+ a2065_xlate, a2065_check, NULL, NULL, _T("A2065 Z2 Ethernet"),
a2065_lgeti, a2065_wgeti, ABFLAG_IO
};
dblpf_ind1[i] = i >= 128 ? i & 0x7F : (plane1 == 0 ? plane2 : plane1);
dblpf_ind2[i] = i >= 128 ? i & 0x7F : (plane2 == 0 ? plane1 : plane2);
+ // Hack for OCS/ECS-only dualplayfield chipset bug.
+ // If PF2P2 is invalid (>5), playfield color becomes transparent but
+ // playfield still hides playfield under it! (if plfpri is set)
+ if (i & 64) {
+ dblpf_ind2[i] = 0;
+ dblpf_ind1[i] = 0;
+ }
+
sprite_offs[i] = (i & 15) ? 0 : 2;
clxtab[i] = ((((i & 3) && (i & 12)) << 9)
}
#endif
-/* emulate OCS/ECS only undocumented "SWIV" hardware feature */
static void weird_bitplane_fix (int start, int end)
{
- int i;
int sh = lores_shift;
uae_u8 *p = pixdata.apixels + pixels_offset;
- for (i = start >> sh; i < end >> sh; i++) {
- if (p[i] > 16)
- p[i] = 16;
+ start >>= sh;
+ end >>= sh;
+ if (bplplanecnt == 5 && !bpldualpf) {
+ /* emulate OCS/ECS only undocumented "SWIV" hardware feature */
+ for (int i = start; i < end; i++) {
+ if (p[i] & 16)
+ p[i] = 16;
+ }
+ } else if (bpldualpf && bpldualpfpri) {
+ /* in dualplayfield mode this feature is even more strange.. */
+ for (int i = start; i < end; i++) {
+ if (p[i] & (2 | 8 | 32))
+ p[i] |= 0x40;
+ }
+ } else if (bpldualpf && !bpldualpfpri) {
+ for (int i = start; i < end; i++) {
+ p[i] &= ~(2 | 8 | 32);
+ }
}
}
// playfield
if (nextpos_in_range > lastpos && lastpos >= playfield_start && lastpos < playfield_end) {
int t = nextpos_in_range <= playfield_end ? nextpos_in_range : playfield_end;
- if (plf2pri > 5 && bplplanecnt == 5 && !(currprefs.chipset_mask & CSMASK_AGA))
+ if (plf2pri > 5 && !(currprefs.chipset_mask & CSMASK_AGA))
weird_bitplane_fix (lastpos, t);
if (bplxor && may_require_hard_way && worker_pfield != pfield_do_linetoscr_bordersprite_aga)
playfield_hard_way(worker_pfield, lastpos, t);
static void show_rom_list (void)
{
TCHAR *p;
- TCHAR unavail[MAX_DPATH], avail[MAX_DPATH];
TCHAR *p1, *p2;
int *rp;
+ bool first = true;
int romtable[] = {
5, 4, -1, -1, // A500 1.2
6, 32, -1, -1, // A500 1.3
16, 46, 31, 13, 12, -1, -1, // A4000
17, -1, -1, // A4000T
18, -1, 19, -1, -1, // CD32
- 18, -1, 19, -1, 74, 23, -1, -1, // CD32 FMV
20, 21, 22, -1, 6, 32, -1, -1, // CDTV
- 49, 50, 75, 51, 76, 77, -1, 5, 4, -1, -1, // ARCADIA
- 46, 16, 17, 31, 13, 12, -1, -1, // highend, any 3.x A4000
+ 49, 50, 75, 51, 76, 77, -1, 5, 4, -1, -2, // ARCADIA
+
53, 54, 55, 56, -1, -1, // A590/A2091
57, 58, -1, -1, // A4091
+ 18, -1, 19, -1, 74, 23, -1, -1, // CD32 FMV
+ 91, -1, -2, // Picasso IV
+
+ 89, -1, -1, // 1230-IV
+ 89, -1, 94, -1, -1, // 1230-IV SCSI
+ 90, -1, -1, // 1260
+ 90, -1, 94, -1, -1, // 1260 SCSI
+ 92, -1, -1, // 2060
+ 93, -1, -1, // Warp Engine
+ 95, 101, -1, -1, // CS MK I
+ 96, -1, -1, // CS MK II
+ 97, -1, -1, // CS MK III
+ 99, 100, -1, -1, // BPPC
+ 98, -1 ,-2, // CSPPC
+
+ 69, 67, 70, -1, -1, // nordic power
+ 65, 68, -1, -1, // x-power
+ 62, 60, -1, -1, // action cartridge
+ 52, 25, -1, -1, // ar 1
+ 26, 27, 28, -1, -1, // ar 2
+ 29, 30, -1, -1, // ar 3
+
0, 0, 0
};
- WIN32GUI_LoadUIString (IDS_ROM_AVAILABLE, avail, sizeof (avail) / sizeof (TCHAR));
- WIN32GUI_LoadUIString (IDS_ROM_UNAVAILABLE, unavail, sizeof (avail) / sizeof (TCHAR));
- _tcscat (avail, _T("\n"));
- _tcscat (unavail, _T("\n"));
- p1 = _T("A500 Boot ROM 1.2\0A500 Boot ROM 1.3\0A500+\0A600\0A1000\0A1200\0A3000\0A4000\0A4000T\0CD32\0CD32 FMV\0CDTV\0Arcadia Multi Select\0High end WinUAE\0A590/A2091 SCSI Boot ROM\0A4091 SCSI Boot ROM\0\0");
+ p1 = _T("A500 Boot ROM 1.2\0A500 Boot ROM 1.3\0A500+\0A600\0A1000\0A1200\0A3000\0A4000\0A4000T\0")
+ _T("CD32\0CDTV\0Arcadia Multi Select\0")
+
+ _T("A590/A2091 SCSI\0A4091 SCSI\0")
+ _T("CD32 Full Motion Video\0")
+ _T("Picasso IV\0")
+
+ _T("Blizzard 1230-IV\0Blizzard 1260\0")
+ _T("Blizzard 1230-IV/SCSI\0Blizzard 1260/SCSI\0")
+ _T("Blizzard 2060\0Warp Engine\0")
+ _T("CyberStorm MK I\0CyberStorm MK II\0CyberStorm MK III\0")
+ _T("Blizzard PPC\0CyberStorm PPC\0")
+
+ _T("Nordic Power\0X-Power Professional 500\0Action Cartridge Super IV Professional\0")
+ _T("Action Replay MK I\0Action Replay MK II\0Action Replay MK III\0")
+ _T("Action Replay 1200\0")
+
+ _T("\0");
p = xmalloc (TCHAR, 100000);
if (!p)
while(rp[0]) {
int ok = 1;
p2 = p1 + _tcslen (p1) + 1;
- _tcscat (p, _T(" "));
- _tcscat (p, p1); _tcscat (p, _T(": "));
- while (*rp != -1) {
+ while (*rp >= 0) {
if (ok) {
ok = 0;
if (listrom (rp))
ok = 1;
}
- while(*rp++ != -1);
+ while(*rp++ >= 0);
+ }
+ if (ok) {
+ if (!first)
+ _tcscat (p, _T(", "));
+ first = false;
+ _tcscat (p, p1);
+ }
+ if (*rp == -2) {
+ _tcscat(p, _T("\n\n"));
+ first = true;
}
rp++;
- if (ok)
- _tcscat (p, avail);
- else
- _tcscat (p, unavail);
p1 = p2;
}