From: Toni Wilen Date: Sun, 24 Oct 2010 09:23:09 +0000 (+0300) Subject: 2310b2 X-Git-Tag: 2310~12 X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=27f1e4f4ea298d40db1536b1f7c9985ef277cc60;p=francis%2Fwinuae.git 2310b2 --- diff --git a/cia.cpp b/cia.cpp index a2b16359..3bebe9c6 100644 --- a/cia.cpp +++ b/cia.cpp @@ -156,9 +156,6 @@ static int CIA_update_check (void) div10 = ccount % DIV10; - if (!ciaclocks) - return 0; - /* CIA A timers */ if ((ciaacra & 0x21) == 0x01) { assert ((ciaata + 1) >= ciaclocks); diff --git a/custom.cpp b/custom.cpp index 5c771eb4..b6c60245 100644 --- a/custom.cpp +++ b/custom.cpp @@ -6603,8 +6603,6 @@ uae_u8 *restore_custom (uae_u8 *src) CLXCON (RW); /* 098 CLXCON */ intena = intena_internal = RW; /* 09A INTENA */ intreq = RW; /* 09C INTREQ */ - if (!currprefs.cs_dipagnus) - intreq |= 0x20; intreq_internal = intreq; adkcon = RW; /* 09E ADKCON */ for (i = 0; i < 8; i++) @@ -7259,7 +7257,7 @@ uae_u32 wait_cpu_cycle_read_ce020 (uaecptr addr, int mode) struct dma_rec *dr; hpos = dma_cycle (); - x_do_cycles (CYCLE_UNIT); + x_do_cycles_pre (CYCLE_UNIT); #ifdef DEBUGGER if (debug_dma) { @@ -7326,7 +7324,7 @@ void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v) int hpos; hpos = dma_cycle (); - x_do_cycles (CYCLE_UNIT); + x_do_cycles_pre (CYCLE_UNIT); #ifdef DEBUGGER if (debug_dma) { diff --git a/include/cpu_prefetch.h b/include/cpu_prefetch.h index b35d2df1..c35c035e 100644 --- a/include/cpu_prefetch.h +++ b/include/cpu_prefetch.h @@ -14,32 +14,31 @@ STATIC_INLINE uae_u32 get_long_prefetch (int o) #ifdef CPUEMU_20 - STATIC_INLINE void do_cycles_ce020 (int clocks) { - do_cycles_ce (clocks * cpucycleunit); + x_do_cycles (clocks * cpucycleunit); } -STATIC_INLINE void do_cycles_ce020_mem (int clocks) +STATIC_INLINE void do_cycles_ce020_mem (int clocks, uae_u32 val) { regs.ce020memcycles -= clocks * cpucycleunit; - do_cycles_ce (clocks * cpucycleunit); + x_do_cycles_post (clocks * cpucycleunit, val); } STATIC_INLINE void checkcycles_ce020 (void) { if (regs.ce020memcycles > 0) - do_cycles_ce (regs.ce020memcycles); + x_do_cycles_pre (regs.ce020memcycles); regs.ce020memcycles = 0; } STATIC_INLINE uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr) { + uae_u32 v; checkcycles_ce020 (); switch (ce_banktype[addr >> 16]) { case CE_MEMBANK_CHIP: if ((addr & 3) != 0) { - uae_u32 v; v = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16; v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) << 0; return v; @@ -47,26 +46,28 @@ STATIC_INLINE uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr) return wait_cpu_cycle_read_ce020 (addr, -1); } case CE_MEMBANK_FAST: + v = get_long (addr); if ((addr & 3) != 0) - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); else - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return v; case CE_MEMBANK_FAST16BIT: - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); - break; + v = get_long (addr); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); + return v; } return get_long (addr); } STATIC_INLINE uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr) { + uae_u32 v; checkcycles_ce020 (); switch (ce_banktype[addr >> 16]) { case CE_MEMBANK_CHIP: if ((addr & 3) != 0) { - uae_u32 v; v = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16; v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) << 0; return v; @@ -74,26 +75,28 @@ STATIC_INLINE uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr) return wait_cpu_cycle_read_ce020 (addr, -1); } case CE_MEMBANK_FAST: + v = get_longi (addr); if ((addr & 3) != 0) - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); else - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return v; case CE_MEMBANK_FAST16BIT: - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); - break; + v = get_longi (addr); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); + return v; } return get_longi (addr); } STATIC_INLINE uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr) { + uae_u32 v; checkcycles_ce020 (); switch (ce_banktype[addr >> 16]) { case CE_MEMBANK_CHIP: if ((addr & 3) == 3) { - uae_u16 v; v = wait_cpu_cycle_read_ce020 (addr + 0, 0) << 8; v |= wait_cpu_cycle_read_ce020 (addr + 1, 0) << 0; return v; @@ -102,17 +105,19 @@ STATIC_INLINE uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr) } case CE_MEMBANK_FAST: case CE_MEMBANK_FAST16BIT: + v = get_word (addr); if ((addr & 3) == 3) - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); else - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return v; } return get_word (addr); } STATIC_INLINE uae_u32 mem_access_delay_wordi_read_ce020 (uaecptr addr) { + uae_u32 v; checkcycles_ce020 (); switch (ce_banktype[addr >> 16]) { @@ -120,14 +125,16 @@ STATIC_INLINE uae_u32 mem_access_delay_wordi_read_ce020 (uaecptr addr) return wait_cpu_cycle_read_ce020 (addr, 1); case CE_MEMBANK_FAST: case CE_MEMBANK_FAST16BIT: - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + v = get_wordi (addr); + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return v; } return get_wordi (addr); } STATIC_INLINE uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr) { + uae_u32 v; checkcycles_ce020 (); switch (ce_banktype[addr >> 16]) { @@ -135,8 +142,9 @@ STATIC_INLINE uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr) return wait_cpu_cycle_read_ce020 (addr, 0); case CE_MEMBANK_FAST: case CE_MEMBANK_FAST16BIT: - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + v = get_byte (addr); + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return v; } return get_byte (addr); @@ -152,8 +160,9 @@ STATIC_INLINE void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v) return; case CE_MEMBANK_FAST: case CE_MEMBANK_FAST16BIT: - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + put_byte (addr, v); + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return; } put_byte (addr, v); } @@ -174,11 +183,12 @@ STATIC_INLINE void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v) break; case CE_MEMBANK_FAST: case CE_MEMBANK_FAST16BIT: + put_word (addr, v); if ((addr & 3) == 3) - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); else - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return; } put_word (addr, v); } @@ -198,14 +208,16 @@ STATIC_INLINE void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v) return; break; case CE_MEMBANK_FAST: + put_long (addr, v); if ((addr & 3) != 0) - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); else - do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE); - break; + do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v); + return; case CE_MEMBANK_FAST16BIT: - do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE); - break; + put_long (addr, v); + do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v); + return; } put_long (addr, v); } @@ -262,12 +274,12 @@ STATIC_INLINE uae_u32 next_ilong_020ce (void) STATIC_INLINE void m68k_do_bsr_ce020 (uaecptr oldpc, uae_s32 offset) { m68k_areg (regs, 7) -= 4; - put_long_ce020 (m68k_areg (regs, 7), oldpc); + x_put_long (m68k_areg (regs, 7), oldpc); m68k_incpc (offset); } STATIC_INLINE void m68k_do_rts_ce020 (void) { - m68k_setpc (get_long_ce020 (m68k_areg (regs, 7))); + m68k_setpc (x_get_long (m68k_areg (regs, 7))); m68k_areg (regs, 7) += 4; } diff --git a/include/newcpu.h b/include/newcpu.h index 1336063c..9a0f523d 100644 --- a/include/newcpu.h +++ b/include/newcpu.h @@ -84,6 +84,8 @@ typedef double fptype; #endif #endif +#define MAX68020CYCLES 4 + #define CPU_PIPELINE_MAX 3 #define CPU000_MEM_CYCLE 4 #define CPU000_CLOCK_MULT 2 @@ -172,6 +174,7 @@ struct regstruct uae_u32 cacheholdingdata020; uae_u32 cacheholdingaddr020; int ce020memcycles; + int ce020tmpcycles; }; extern struct regstruct regs; @@ -190,6 +193,15 @@ struct cputracestruct uae_u32 usp, isp, pc; uae_u16 ir, irc, sr, opcode; int intmask, stopped, state; + + uae_u32 msp, vbr; + uae_u32 cacr, caar; + uae_u16 prefetch020[CPU_PIPELINE_MAX]; + uae_u32 prefetch020addr; + uae_u32 cacheholdingdata020; + uae_u32 cacheholdingaddr020; + struct cache020 caches020[CACHELINES020]; + int memoryoffset; int cyclecounter, cyclecounter_pre, cyclecounter_post; int readcounter, writecounter; diff --git a/inputrecord.cpp b/inputrecord.cpp index 09aa1625..9c7e4d67 100644 --- a/inputrecord.cpp +++ b/inputrecord.cpp @@ -228,7 +228,8 @@ static int inprec_pstart (uae_u8 type) write_log (L"\n"); } cycleoffset = cycles - cycles2; - gui_message (L"INPREC OFFSET=%d\n", cycleoffset / CYCLE_UNIT); + gui_message (L"INPREC OFFSET=%d\n", (int)cycleoffset / CYCLE_UNIT); + activate_debugger (); } lastcycle = cycles; inprec_plast = p; diff --git a/newcpu.cpp b/newcpu.cpp index 08bd4882..10c4acc1 100644 --- a/newcpu.cpp +++ b/newcpu.cpp @@ -796,7 +796,7 @@ static void set_x_funcs (void) bool can_cpu_tracer (void) { - return (currprefs.cpu_model == 68000) && currprefs.cpu_cycle_exact; + return (currprefs.cpu_model == 68000 || currprefs.cpu_model == 68020) && currprefs.cpu_cycle_exact; } bool is_cpu_tracer (void) @@ -2050,10 +2050,19 @@ kludge_me_do: } #endif +static uae_u32 exception_pc (int nr) +{ + // zero divide, chk, trapcc/trapv, trace, trap# + if (nr == 5 || nr == 6 || nr == 7 || nr == 9 || (nr >= 32 && nr <= 47)) + return m68k_getpc (); + return regs.instruction_pc; +} + static void Exception_mmu (int nr) { uae_u32 newpc; int sv = regs.s; + int pc = exception_pc (nr); int i; exception_debug (nr); @@ -2154,7 +2163,7 @@ static void Exception_mmu (int nr) } m68k_areg (regs, 7) -= 4; - put_long_mmu (m68k_areg (regs, 7), regs.instruction_pc); + put_long_mmu (m68k_areg (regs, 7), pc); m68k_areg (regs, 7) -= 2; put_word_mmu (m68k_areg (regs, 7), regs.sr); kludge_me_do: @@ -2196,7 +2205,7 @@ static void Exception_normal (int nr) mmu_set_super (regs.s != 0); } if (currprefs.cpu_model > 68000) { - currpc = regs.instruction_pc; + currpc = exception_pc (nr); if (nr == 2 || nr == 3) { int i; if (currprefs.cpu_model >= 68040) { @@ -2921,6 +2930,8 @@ void m68k_reset (int hardreset) if (kickstart_rom) regs.pcr |= 2; /* disable FPU */ } + regs.ce020tmpcycles = MAX68020CYCLES; + regs.ce020memcycles = 0; fill_prefetch_quick (); } @@ -3470,7 +3481,7 @@ static void m68k_run_1 (void) struct regstruct *r = ®s; for (;;) { - uae_u32 opcode = r->ir; + uae_u16 opcode = r->ir; count_instr (opcode); @@ -3541,7 +3552,7 @@ static void m68k_run_1_ce (void) set_cpu_tracer (false); for (;;) { - uae_u32 opcode = r->ir; + uae_u16 opcode = r->ir; #if DEBUG_CD32CDTVIO out_cd32io (m68k_getpc ()); #endif @@ -3714,7 +3725,7 @@ static void opcodedebug (uae_u32 pc, uae_u16 opcode, bool full) /* Aranym MMU 68040 */ static void m68k_run_mmu040 (void) { - uae_u32 opcode; + uae_u16 opcode; uaecptr pc; retry: TRY (prb) { @@ -3801,12 +3812,20 @@ retry: } /* "cycle exact" 68020/030 */ -#define MAX68020CYCLES 4 + +STATIC_INLINE void docodece020 (uae_u32 opcode) +{ + (*cpufunctbl[opcode])(opcode); + if (regs.ce020memcycles > 0) { + regs.ce020tmpcycles = CYCLE_UNIT * MAX68020CYCLES; + x_do_cycles (regs.ce020memcycles); + regs.ce020memcycles = 0; + } +} static void m68k_run_2ce (void) { struct regstruct *r = ®s; - int tmpcycles = MAX68020CYCLES; if (cpu_tracer < 0) { memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32)); @@ -3817,11 +3836,22 @@ static void m68k_run_2ce (void) r->isp = cputrace.isp; r->intmask = cputrace.intmask; r->stopped = cputrace.stopped; + + r->msp = cputrace.msp; + r->vbr = cputrace.vbr; + r->caar = cputrace.caar; + r->cacr = cputrace.cacr; + r->cacheholdingdata020 = cputrace.cacheholdingdata020; + r->cacheholdingaddr020 = cputrace.cacheholdingaddr020; + r->prefetch020addr = cputrace.prefetch020addr; + memcpy (&r->prefetch020, &cputrace.prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u16)); + memcpy (&caches020, &cputrace.caches020, sizeof caches020); + m68k_setpc (cputrace.pc); if (cputrace.state > 1) Exception (cputrace.state); else if (cputrace.state == 1) - (*cpufunctbl[cputrace.opcode])(cputrace.opcode); + docodece020 (cputrace.opcode); if (regs.stopped) set_special (SPCFLAG_STOP); set_cpu_tracer (false); @@ -3829,11 +3859,10 @@ static void m68k_run_2ce (void) } set_cpu_tracer (false); - ipl_fetch (); for (;;) { r->instruction_pc = m68k_getpc (); - uae_u32 opcode = x_prefetch (0); + uae_u16 opcode = x_prefetch (0); if (cpu_tracer) { memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32)); @@ -3847,6 +3876,17 @@ static void m68k_run_2ce (void) cputrace.stopped = r->stopped; cputrace.state = 1; cputrace.pc = m68k_getpc (); + + cputrace.msp = r->msp; + cputrace.vbr = r->vbr; + cputrace.caar = r->caar; + cputrace.cacr = r->cacr; + cputrace.cacheholdingdata020 = r->cacheholdingdata020; + cputrace.cacheholdingaddr020 = r->cacheholdingaddr020; + cputrace.prefetch020addr = r->prefetch020addr; + memcpy (&cputrace.prefetch020, &r->prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u16)); + memcpy (&cputrace.caches020, &caches020, sizeof caches020); + cputrace.memoryoffset = 0; cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0; cputrace.readcounter = cputrace.writecounter = 0; @@ -3859,21 +3899,18 @@ static void m68k_run_2ce (void) inprec_playdebug_cpu (1); } - (*cpufunctbl[opcode])(opcode); - if (r->ce020memcycles > 0) { - tmpcycles = CYCLE_UNIT * MAX68020CYCLES; - do_cycles_ce (r->ce020memcycles); - r->ce020memcycles = 0; - } + docodece020 (opcode); + cont: if (r->spcflags || time_for_interrupt ()) { if (do_specialties (0)) return; } - tmpcycles -= cpucycleunit; - if (tmpcycles <= 0) { - do_cycles_ce (1 * CYCLE_UNIT); - tmpcycles = CYCLE_UNIT * MAX68020CYCLES;; + + regs.ce020tmpcycles -= cpucycleunit; + if (regs.ce020tmpcycles <= 0) { + x_do_cycles (1 * CYCLE_UNIT); + regs.ce020tmpcycles = CYCLE_UNIT * MAX68020CYCLES;; } regs.ipl = regs.ipl_pin; } @@ -3888,7 +3925,7 @@ static void m68k_run_2p (void) prefetch_pc = m68k_getpc (); prefetch = x_get_long (prefetch_pc); for (;;) { - uae_u32 opcode; + uae_u16 opcode; uae_u32 pc = m68k_getpc (); #if DEBUG_CD32CDTVIO @@ -3902,7 +3939,7 @@ static void m68k_run_2p (void) regs.instruction_pc = pc; } else if (pc == prefetch_pc + 2) { regs.instruction_pc = pc + 2; - opcode = prefetch & 0xffff; + opcode = prefetch; } else { regs.instruction_pc = pc; opcode = x_get_word (pc); @@ -3930,7 +3967,7 @@ static void m68k_run_2 (void) struct regstruct *r = ®s; for (;;) { - uae_u32 opcode = get_iword (0); + uae_u16 opcode = get_iword (0); count_instr (opcode); #if 0 if (!used[opcode]) { @@ -3953,7 +3990,7 @@ static void m68k_run_2 (void) static void m68k_run_mmu (void) { for (;;) { - uae_u32 opcode = get_iword (0); + uae_u16 opcode = get_iword (0); do_cycles (cpu_cycles); mmu_backup_regs = regs; cpu_cycles = (*cpufunctbl[opcode])(opcode); @@ -4126,7 +4163,7 @@ void m68k_go (int may_quit) #if 0 static void m68k_verify (uaecptr addr, uaecptr *nextpc) { - uae_u32 opcode, val; + uae_u16 opcode, val; struct instr *dp; opcode = get_iword_1 (0); @@ -4688,6 +4725,10 @@ uae_u8 *restore_cpu (uae_u8 *src) dcaches030[i].tag = restore_u32 (); } } + if (model >= 68020) { + regs.ce020memcycles = restore_u32 (); + regs.ce020tmpcycles = restore_u32 (); + } } write_log (L"CPU: %d%s%03d, PC=%08X\n", @@ -4923,6 +4964,10 @@ uae_u8 *save_cpu (int *len, uae_u8 *dstptr) save_u32 (dcaches030[i].tag); } } + if (currprefs.cpu_model >= 68020) { + save_u32 (regs.ce020memcycles); + save_u32 (regs.ce020tmpcycles); + } *len = dst - dstbak; return dstbak; } diff --git a/od-win32/serial_win32.cpp b/od-win32/serial_win32.cpp index 712f7ed2..744fa0ac 100644 --- a/od-win32/serial_win32.cpp +++ b/od-win32/serial_win32.cpp @@ -40,7 +40,7 @@ static int dtr; static int serial_period_hsyncs, serial_period_hsync_counter; static int ninebit; int serdev; -int seriallog; +int seriallog = 1; int serial_enet; void serial_open (void); @@ -104,6 +104,8 @@ static TCHAR dochar (int v) v &= 0xff; if (v >= 32 && v < 127) return v; + if (v == 10) + return 10; return '.'; } diff --git a/od-win32/win32.h b/od-win32/win32.h index 606ae212..64725fda 100644 --- a/od-win32/win32.h +++ b/od-win32/win32.h @@ -18,8 +18,8 @@ #define WINUAEPUBLICBETA 1 #define LANG_DLL 1 -#define WINUAEBETA L"1" -#define WINUAEDATE MAKEBD(2010, 10, 23) +#define WINUAEBETA L"2" +#define WINUAEDATE MAKEBD(2010, 10, 24) #define WINUAEEXTRA L"" #define WINUAEREV L"" diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt index 77c0c21b..a13187e7 100644 --- a/od-win32/winuaechangelog.txt +++ b/od-win32/winuaechangelog.txt @@ -1,4 +1,9 @@ +- CIA timing issue in some situations (b1) +- some 68020+ exceptions had wrong return address (b1) +- do not attempt to save log window position if it is minimized +- do not set vblank bit during state restore, old code that broke interrupt delaying and rerecorder timing + Beta 1 !!!!!! NOTE: Re-recorder discussion will be opened later in another thread. All posts related to new input recorder diff --git a/od-win32/writelog.cpp b/od-win32/writelog.cpp index dd20d17d..6a8c00f4 100644 --- a/od-win32/writelog.cpp +++ b/od-win32/writelog.cpp @@ -194,7 +194,7 @@ void close_console (void) close_debug_window (); } else if (consoleopen < 0) { HWND hwnd = myGetConsoleWindow (); - if (hwnd) { + if (hwnd && !IsIconic (hwnd)) { RECT r; if (GetWindowRect (hwnd, &r)) { r.bottom -= r.top;