From: Toni Wilen Date: Thu, 30 Apr 2026 15:57:37 +0000 (+0300) Subject: 6100b5 X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=2c7f8581a106d880a31d43b439e6a2962c9a8e32;p=francis%2Fwinuae.git 6100b5 --- diff --git a/od-win32/win32.h b/od-win32/win32.h index bda4bcb3..c1393083 100644 --- a/od-win32/win32.h +++ b/od-win32/win32.h @@ -20,12 +20,12 @@ #define LANG_DLL_FULL_VERSION_MATCH 1 #if WINUAEPUBLICBETA -#define WINUAEBETA _T("4") +#define WINUAEBETA _T("5") #else #define WINUAEBETA _T("") #endif -#define WINUAEDATE MAKEBD(2026, 4, 26) +#define WINUAEDATE MAKEBD(2026, 4, 30) //#define WINUAEEXTRA _T("AmiKit Preview") //#define WINUAEEXTRA _T("Amiga Forever Edition") diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt index 1560cace..9efc780f 100644 --- a/od-win32/winuaechangelog.txt +++ b/od-win32/winuaechangelog.txt @@ -1,4 +1,12 @@ +Beta 5: + +- Emulated A1200 and A4000 mainboard (CD32 fix is inside Akiko) Alice blitter busy bug fix circuitry that causes graphics glitches in FMODE=0 and 7 lores planes AGA mode and blitter nasty off. If blitter finished but final D write is still pending, CPU can steal multiple cycles from the blitter and can have more than enough time to update blitter registers for next blit before blitter finally gets free cycle to write final D. This fixes graphics glitches for example in Charlie J Cool, Zool 2 AGA and more. +- b4 CPU stealing blitter cycle change reverted, it was wrong, correct fix is above fix. +- Last 2-3 lines were not visible in normal PAL/NTSC modes. + +This should fix "68020 CE has something wrong (no easy test case so far), it was supposed to be same as previously but it isn't.". This was extremely nasty and can affect 6.0 (6.0 differently than 6.1) up to 610b4. Blitter emulation was rewritten to match Alice schematics accurately in v6 but it missed very important bit: blitter in non-nasty mode has a bug which is fixed by extra logic on mainboard (TTL chip on A1200, PAL in A4000, CD32 fixed in Akiko) which I missed completely until now. Previoius blitter emulation was not accurate enough to not trigger this condition. Note that OCS/ECS also have same "bug" but it can't trigger (at least not continuously) because Agnus bitplane DMA can't steal as many cycles back to back and still have single free cycle every 7 cycles which CPU would always steal from the blitter. + Beta 4: - When config was changed on the fly (This includes loading statefile after emulation has been started), FMODE AGA-only register could have reset back to previous zero value after few seconds. (Probably introduced in 5.x)