From: Toni Wilen <twilen@winuae.net>
Date: Sat, 26 Sep 2020 15:05:04 +0000 (+0300)
Subject: It seems SCSI chip always resets phase state after MSGACC command.
X-Git-Tag: 4900~304
X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=786c89d8f807777a0d75c601d1f97014bffbdca9;p=francis%2Fwinuae.git

It seems SCSI chip always resets phase state after MSGACC command.
---

diff --git a/ncr9x_scsi.cpp b/ncr9x_scsi.cpp
index 25ffcfd6..85d13b67 100644
--- a/ncr9x_scsi.cpp
+++ b/ncr9x_scsi.cpp
@@ -954,9 +954,11 @@ static void ncr9x_io_bput3(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val, i
 			esp_dma_enable(ncr->devobject.lsistate, ncr->dma_on);
 			ncr->states[0] = val;
 			ncr->dma_cnt = 0;
+#if NCR_DEBUG
 			if (ncr->dma_on) {
 				write_log(_T("Trifecta DMA %08x %c\n"), ncr->dma_ptr, (val & 1) ? 'R' : 'W');
 			}
+#endif
 		} else if (addr == 0x402) {
 			ncr->dma_ptr &= 0xffff00;
 			ncr->dma_ptr |= val;
diff --git a/qemuvga/esp.cpp b/qemuvga/esp.cpp
index 3ffc970a..e73bc91d 100644
--- a/qemuvga/esp.cpp
+++ b/qemuvga/esp.cpp
@@ -71,7 +71,10 @@ static void esp_raise_irq(ESPState *s)
 {
     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
         s->rregs[ESP_RSTAT] |= STAT_INT;
-		esp_raise_ext_irq(s);
+#if ESPLOG
+        write_log("irq->1\n");
+#endif
+        esp_raise_ext_irq(s);
     }
 }
 
@@ -79,7 +82,10 @@ static void esp_lower_irq(ESPState *s)
 {
     if (s->rregs[ESP_RSTAT] & STAT_INT) {
         s->rregs[ESP_RSTAT] &= ~STAT_INT;
-		esp_lower_ext_irq(s);
+#if ESPLOG
+        write_log("irq->0\n");
+#endif
+        esp_lower_ext_irq(s);
     }
 }
 
@@ -87,6 +93,9 @@ static void fas408_raise_irq(ESPState *s)
 {
 	if (!(s->rregs[ESP_REGS + NCR_PSTAT] & NCRPSTAT_SIRQ)) {
 		s->rregs[ESP_REGS + NCR_PSTAT] |= NCRPSTAT_SIRQ;
+#if ESPLOG
+        write_log("irq408->1\n");
+#endif
 		esp_raise_ext_irq(s);
 	}
 }
@@ -95,7 +104,10 @@ static void fas408_lower_irq(ESPState *s)
 {
 	if (s->rregs[ESP_REGS + NCR_PSTAT] & NCRPSTAT_SIRQ) {
 		s->rregs[ESP_REGS + NCR_PSTAT] &= ~NCRPSTAT_SIRQ;
-		esp_lower_ext_irq(s);
+#if ESPLOG
+        write_log("irq408->0\n");
+#endif
+        esp_lower_ext_irq(s);
 	}
 }
 
@@ -855,11 +867,8 @@ void esp_reg_write(void *opaque, uint32_t saddr, uint64_t val)
             s->rregs[ESP_RINTR] = INTR_DC;
             s->rregs[ESP_RSEQ] = 0;
             //s->rregs[ESP_RFLAGS] = 0;
-			// Features enable
-			if (!(s->wregs[ESP_CFG2] & 0x40)) {
-				// Masoboshi driver expects phase=0!
-				s->rregs[ESP_RSTAT] &= ~7;
-			}
+			// Masoboshi and Trifecta drivers expects phase=0
+			s->rregs[ESP_RSTAT] &= ~7;
             esp_raise_irq(s);
             break;
         case CMD_PAD: