From: Dimitris Panokostas <midwan@gmail.com>
Date: Mon, 18 May 2026 22:14:35 +0000 (+0200)
Subject: Port Amiberry ARM64 and x86-64 JIT fixes
X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=8be91380a309223af27ec552cf360899c886fe79;p=francis%2Fwinuae.git

Port Amiberry ARM64 and x86-64 JIT fixes
---

diff --git a/include/memory.h b/include/memory.h
index 9b4a3c6e..13568469 100644
--- a/include/memory.h
+++ b/include/memory.h
@@ -17,6 +17,7 @@ extern void a1000_reset(void);
 extern int special_mem;
 extern int special_mem_default;
 extern int jit_n_addr_unsafe;
+extern int jit_n_addr_bank_unsafe;
 #endif
 
 #define S_READ 1
diff --git a/include/sysdeps.h b/include/sysdeps.h
index e7e49be1..714c280e 100644
--- a/include/sysdeps.h
+++ b/include/sysdeps.h
@@ -41,6 +41,7 @@ using namespace std;
 #endif
 
 #if defined(__aarch64__) || defined(_M_ARM64) || defined(_M_ARM64EC) 
+#define CPU_AARCH64 1
 #define CPU_arm 1
 #define ARM_ASSEMBLY 1
 #define CPU_64_BIT 1
diff --git a/jit/arm/aarch64.h b/jit/arm/aarch64.h
new file mode 100644
index 00000000..2917d00c
--- /dev/null
+++ b/jit/arm/aarch64.h
@@ -0,0 +1,2126 @@
+/* Universal Disassembler Function Library
+ * https://gitlab.com/bztsrc/udisasm
+ *
+ *            ----- GENERATED FILE, DO NOT EDIT! -----
+ *
+ * Copyright (C) 2017 bzt (bztsrc@gitlab)
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * @brief Disassembler source generated from aarch64.txt
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define disasm_arch "aarch64"
+enum { disasm_arg_NONE,disasm_arg_ofs,disasm_arg_ofe, disasm_arg_Xt, disasm_arg_labelij1, disasm_arg_RtS, disasm_arg_RnS, disasm_arg_i, disasm_arg_j12_opt, disasm_arg_Rn, disasm_arg_ib, disasm_arg_Rt, disasm_arg_j16_opt, disasm_arg_j, disasm_arg_Rm, disasm_arg_c, disasm_arg_labeli4, disasm_arg_i_opt, disasm_arg_pstate, disasm_arg_sh, disasm_arg_a0, disasm_arg_a1, disasm_arg_a2, disasm_arg_dc0, disasm_arg_dc1, disasm_arg_ZVA, disasm_arg_dc2, disasm_arg_ic, disasm_arg_Xt_opt, disasm_arg_tl0, disasm_arg_tl1, disasm_arg_tl2, disasm_arg_sysreg, disasm_arg_Cn, disasm_arg_Cm, disasm_arg_Xn, disasm_arg_b, disasm_arg_VtT, disasm_arg_Vt2T, disasm_arg_Vt3T, disasm_arg_Vt4T, disasm_arg_offs, disasm_arg_XnS, disasm_arg_offe, disasm_arg_Qi, disasm_arg_Xm, disasm_arg_Qi3, disasm_arg_Qi2, disasm_arg_Qi1, disasm_arg_VtB, disasm_arg_VtH, disasm_arg_VtS, disasm_arg_VtD, disasm_arg_i1, disasm_arg_i2, disasm_arg_i4, disasm_arg_i8, disasm_arg_Vt3B, disasm_arg_Vt3H, disasm_arg_Vt3S, disasm_arg_Vt3D, disasm_arg_i3, disasm_arg_i6, disasm_arg_i12, disasm_arg_i24, disasm_arg_Vt2B, disasm_arg_Vt2H, disasm_arg_Vt2S, disasm_arg_Vt2D, disasm_arg_i16, disasm_arg_Vt4B, disasm_arg_Vt4H, disasm_arg_Vt4S, disasm_arg_Vt4D, disasm_arg_i32, disasm_arg_z, disasm_arg_z3, disasm_arg_z2, disasm_arg_z4, disasm_arg_Rd, disasm_arg_Rd1, disasm_arg_Rt1, disasm_arg_Wd, disasm_arg_Wt, disasm_arg_FPt, disasm_arg_prf_op, disasm_arg_is4_opt, disasm_arg_FPm, disasm_arg_iz4_opt, disasm_arg_im4_opt, disasm_arg_nRt, disasm_arg_FPst, disasm_arg_j_opt, disasm_arg_Rom, disasm_arg_amountj, disasm_arg_amountz, disasm_arg_amountjs, disasm_arg_amountj2, disasm_arg_amountj3, disasm_arg_shiftj_opt, disasm_arg_Rsom, disasm_arg_exts, disasm_arg_Wn, disasm_arg_Wm, disasm_arg_Xd, disasm_arg_Vt16b, disasm_arg_Vn16b, disasm_arg_Qt, disasm_arg_Sn, disasm_arg_Vm4s, disasm_arg_Vt4s, disasm_arg_Vn4s, disasm_arg_Qn, disasm_arg_St, disasm_arg_FPjt, disasm_arg_Vnj, disasm_arg_FPidx, disasm_arg_Vtjq, disasm_arg_Ht, disasm_arg_Hn, disasm_arg_Hm, disasm_arg_FPn, disasm_arg_VtH1, disasm_arg_VnH1, disasm_arg_VmH1, disasm_arg_Vtzq, disasm_arg_Vnzq, disasm_arg_Vmzq, disasm_arg_simd0, disasm_arg_FPz2t, disasm_arg_FPz2n, disasm_arg_FPz2m, disasm_arg_VnT, disasm_arg_VmT, disasm_arg_FPz3t, disasm_arg_FPz3n, disasm_arg_FPz4n, disasm_arg_VnT3, disasm_arg_Vn2d, disasm_arg_Vn2h, disasm_arg_Vnz, disasm_arg_FPz4t, disasm_arg_Vtz, disasm_arg_FPz3m, disasm_arg_Dt, disasm_arg_Dn, disasm_arg_shrshift, disasm_arg_Vtj2, disasm_arg_Vnj2, disasm_arg_shlshift, disasm_arg_FPnj, disasm_arg_VnTa, disasm_arg_FPjt2, disasm_arg_FPjn2, disasm_arg_Vtz3, disasm_arg_VmTs, disasm_arg_VmHs, disasm_arg_VmTs2, disasm_arg_Vn116b, disasm_arg_Vn216b, disasm_arg_Vn316b, disasm_arg_Vn416b, disasm_arg_Vtj, disasm_arg_R2n, disasm_arg_FPidxk, disasm_arg_Vtzq2, disasm_arg_VnT2, disasm_arg_Vnz3, disasm_arg_Vnzq2, disasm_arg_shift8, disasm_arg_VtT3, disasm_arg_VmT3, disasm_arg_VtT4, disasm_arg_imm8, disasm_arg_amountk_opt, disasm_arg_amountk2_opt, disasm_arg_imm64, disasm_arg_Vt2d, disasm_arg_F16, disasm_arg_F32, disasm_arg_F64, disasm_arg_VmTs4b, disasm_arg_Vm2d, disasm_arg_Vm16b, disasm_arg_Vd16b, disasm_arg_Vd4s, disasm_arg_FPz5t, disasm_arg_fbits, disasm_arg_FPz5n, disasm_arg_Vn1d, disasm_arg_Vt1d, disasm_arg_FPk5t, disasm_arg_FPz5m, disasm_arg_jz, disasm_arg_FPz5d };
+
+/*** private functions ***/
+const char *disasm_str(char*s,int n) {if(!s)return "?";while(n){s++;if(!*s){s++;n--;}}return *s?s:"?";}
+const char *disasm_sysreg(uint8_t p,uint8_t k,uint8_t n,uint8_t m,uint8_t j) {char *t=NULL;switch(p){case 2: switch(k) {case 0: switch(n) {case 0: switch(m) {case 0: t="?\0?\0OSDTRRX_EL1\0"; break;case 2: t="MDCCINT_EL1\0?\0MDSCR_EL1\0"; break;case 3: t="?\0?\0OSDTRTX_EL1\0"; break;case 6: t="?\0?\0OSECCR_EL1\0"; break;default: { n=j; j=m; switch(n) {case 4: t="DBGBVR0_EL1\0DBGBVR1_EL1\0DBGBVR2_EL1\0DBGBVR3_EL1\0DBGBVR4_EL1\0DBGBVR5_EL1\0DBGBVR6_EL1\0DBGBVR7_EL1\0"; break;case 5: t="DBGBCR0_EL1\0DBGBCR1_EL1\0DBGBCR2_EL1\0DBGBCR3_EL1\0DBGBCR4_EL1\0DBGBCR5_EL1\0DBGBCR6_EL1\0DBGBCR7_EL1\0"; break;case 6: t="DBGWVR0_EL1\0DBGWVR1_EL1\0DBGWVR2_EL1\0DBGWVR3_EL1\0DBGWVR4_EL1\0DBGWVR5_EL1\0DBGWVR6_EL1\0DBGWVR7_EL1\0"; break;case 7: t="DBGWCR0_EL1\0DBGWCR1_EL1\0DBGWCR2_EL1\0DBGWCR3_EL1\0DBGWCR4_EL1\0DBGWCR5_EL1\0DBGWCR6_EL1\0DBGWCR7_EL1\0"; break;} break; }} break;case 1: if(m==0) t="MDRAR_EL1\0?\0?\0?\0OSLAR_EL1\0"; else if(j==4) { j=m; t="OSLSR_EL1\0?\0OSDLR_EL1\0DBGPRCR_EL1\0"; }break;case 7: if(j==6) { j=m; t="?\0?\0?\0?\0?\0?\0?\0?\0DBGCLAIMSET_EL1\0DBGCLAIMCLR_EL1\0?\0?\0?\0?\0DBGAUTHSTATUS_EL1\0"; }break;} break;case 3: if(n==0&&j==0) { j=m; t="?\0MDCCSR_EL0\0?\0?\0DBGDTR_EL0\0DBGDTRRX_EL0\0"; } break;case 4: if(n==0&&m==7) t="DBGVCR32_EL2\0"; break;} break;case 3: switch(k) {case 0: switch(n) {case 0: if(m==0) t="MIDR_EL1\0?\0?\0?\0?\0MPIDR_EL1\0REVIDR_EL1\0?\0ID_PFR0_EL1\0ID_PFR1_EL1\0ID_DFR0_EL1\0ID_AFR0_EL1\0ID_MMFR0_EL1\0ID_MMFR1_EL1\0ID_MMFR2_EL1\0ID_MMFR3_EL1\0ID_ISAR0_EL1\0ID_ISAR1_EL1\0ID_ISAR2_EL1\0ID_ISAR2_EL1\0ID_ISAR3_EL1\0ID_ISAR4_EL1\0ID_ISAR5_EL1\0ID_MMFR4_EL1\0?\0MVFR0_EL1\0MVFR1_EL1\0MVFR2_EL1\0?\0?\0?\0?\0?\0ID_A64PFR0_EL1\0ID_A64PFR1_EL1\0?\0?\0ID_A64ZFR0_EL1\0?\0?\0?\0ID_A64DFR0_EL1\0ID_A64DFR1_EL1\0?\0?\0ID_A64AFR0_EL1\0ID_A64AFR1_EL1\0?\0?\0ID_A64ISAR0_EL1\0ID_A64ISAR1_EL1\0?\0?\0?\0?\0?\0?\0ID_A64MMFR0_EL1\0ID_A64MMFR1_EL1\0ID_A64MMFR2_EL1\0"; break;case 1: switch(m) {case 0: t="SCTLR_EL1\0ACTLR_EL1\0CPACR_EL1\0"; break;case 2: t="ZCR_EL1\0"; break;} break;case 2: if(m==0) t="TTBR0_EL1\0TTBR1_EL1\0TCR_EL1\0"; break;case 4: switch(m) {case 0: t="SPSR_EL1\0ELR_EL1\0"; break;case 1: t="SP_EL0\0"; break;case 2: t="SPSel\0?\0CurrentEL\0PAN\0UAO\0"; break;case 6: t="ICC_PMR_EL1\0"; break;} break;case 5: switch(m) {case 1: t="AFSR0_EL1\0AFSR1_EL1\0"; break;case 2: t="ESR_EL1"; break;case 3: t="ERRIDR_EL1\0ERRSELR_EL1\0"; break;case 4: t="ERXFR_EL1\0ERXCTLR_EL1\0ERXSTATUS_EL1\0ERXADDR_EL1\0"; break;case 5: t="ERXMISC0_EL1\0ERXMISC1_EL1\0"; break;} break;case 6: if(m==0) t="FAR_EL1\0"; break;case 7: if(m==4) t="PAR_EL1\0"; break;case 9: switch(m) {case 9: t="PMSCR_EL1\0?\0PMSICR_EL1\0PMSIRR_EL1\0PMSFCR_EL1\0PMSEVFR_EL1\0PMSLATFR_EL1\0PMSIDR_EL1\0PMSIDR_EL1\0"; break;case 10: t="PMBLIMITR_EL1\0PMBPTR_EL1\0?\0PMBSR_EL1\0?\0?\0?\0PMBIDR_EL1\0"; break;case 14: t="?\0PMINTENSET_EL1\0PMINTENCLR_EL1\0"; break;} break;case 10: if(m==4) t="LORSA_EL1\0LOREA_EL1\0LORN_EL1\0LORC_EL1\0?\0?\0?\0LORID_EL1\0"; else if(m!=4&&j==0) { j=m; t="?\0?\0MAIR_EL1\0AMAIR_EL1\0"; }break;case 12: switch(m) {case 0: t="VBAR_EL1\0RVBAR_EL1\0RMR_EL1\0"; break;case 1: t="ISR_EL1\0DISR_EL1\0"; break;case 8: t="ICC_IAR0_EL1\0ICC_EOIR0_EL1\0ICC_HPPIR0_EL1\0ICC_BPR0_EL1\0ICC_AP0R0_EL1\0ICC_AP0R1_EL1\0ICC_AP0R2_EL1\0ICC_AP0R3_EL1\0"; break;case 9: t="ICC_AP1R0_EL1\0ICC_AP1R1_EL1\0ICC_AP1R2_EL1\0ICC_AP1R3_EL1\0"; break;case 11: t="?\0ICC_DIR_EL1\0?\0ICC_RPR_EL1\0?\0ICC_SGI1R_EL1\0ICC_ASGI1R_EL1\0ICC_SGI0R_EL1\0"; break;case 12: t="ICC_IAR1_EL1\0ICC_EOIR1_EL1\0ICC_HPPIR1_EL1\0ICC_BPR1_EL1\0ICC_CTLR_EL1\0ICC_SRE_EL1\0ICC_IGRPEN0_EL1\0ICC_IGRPEN1_EL1\0"; break;} break;case 13: if(m==0) t="?\0CONTEXTIDR_EL1\0?\0?\0TPIDR_EL1\0"; break;case 14: if(m==1) t="CNTKCTL_EL1\0"; break;} break;case 1: if(n==0&&m==0) t="CCSIDR_EL1\0CLIDR_EL1\0?\0?\0?\0?\0?\0AIDR_EL1\0"; break;case 2: if(n==0&&m==0) t="CSSELR_EL1\0"; break;case 3: switch(n) {case 0: if(m==0) t="?\0CTR_EL0\0?\0?\0?\0?\0?\0DCZID_EL0\0"; break;case 4: switch(m) {case 2: t="NZCV\0DAIF\0"; break;case 4: t="FPCR\0FPSR\0"; break;case 5: t="DSPSR_EL0\0DLR_EL0\0"; break;} break;case 9: switch(m) {case 12: t="PMCR_EL0\0PMCNTENSET_EL0\0PMCNTENCLR_EL0\0PMOVSCLR_EL0\0PMSWINC_EL0\0PMSELR_EL0\0PMCEID0_EL0\0PMCEID1_EL0\0"; break;case 13: t="PMCCNTR_EL0\0PMXEVTYPER_EL0\0PMXEVCNTR_EL0\0"; break;case 14: t="PMUSERENR_EL0\0?\0?\0PMOVSSET_EL0\0"; break;} break;
+case 13: if(m==0) t="?\0?\0TPIDR_EL0\0TPIDRRO_EL0\0"; break;case 14: switch(m) {case 0: t="CNTFRQ_EL0\0CNTPCT_EL0\0CNTVCT_EL0\0"; break;case 2: t="CNTP_TVAL_EL0\0CNTP_CTL_EL0\0CNTP_CVAL_EL0\0"; break;case 3: t="CNTV_TVAL_EL0\0CNTV_CTL_EL0\0CNTV_CVAL_EL0\0"; break;} break;} break;case 4: switch(n) {case 0: if(m==0) t="VPIDR_EL2\0?\0?\0?\0?\0VMPIDR_EL2\0"; break;case 1: switch(m) {case 0: t="SCTLR_EL2\0ACTLR_EL2\0"; break;case 1: t="HCR_EL2\0MDCR_EL2\0CPTR_EL2\0HSTR_EL2\0?\0?\0?\0HACR_EL2\0"; break;case 2: t="ZCR_EL2\0"; break;} break;case 2: switch(m) {case 0: t="TTBR0_EL2\0?\0TCR_EL2\0"; break;case 1: t="VTTBR0_EL2\0?\0VTCR_EL2\0"; break;} break;case 3: if(m==0) t="DACR32_EL2\0"; break;case 4: switch(m) {case 0: t="SPSR_EL2\0ELR_EL2\0"; break;case 1: t="SP_EL1\0"; break;case 3: t="SPSR_irq\0SPSR_abt\0SPSR_und\0SPSR_fiq\0"; break;} break;case 5: switch(m) {case 0: t="?\0IFSR32_EL2\0"; break;case 1: t="AFSR0_EL2\0AFSR1_EL2\0"; break;case 2: t="ESR_EL2\0?\0?\0VSESR_EL2\0"; break;case 3: t="FPEXC32_EL2\0"; break;} break;case 6: if(m==0) t="FAR_EL2\0?\0?\0?\0HPFAR_EL2\0"; break;case 9: if(m==9) t="PMSCR_EL2\0"; break;case 10: switch(m) {case 2: t="MAIR_EL2\0"; break;case 3: t="AMAIR_EL2\0"; break;} break;case 12: switch(m) {case 0: t="VBAR_EL2\0RVBAR_EL2\0RMR_EL2\0"; break;case 1: t="?\0VDISR_EL2\0"; break;case 8: t="ICH_AP0R0_EL2\0ICH_AP0R1_EL2\0ICH_AP0R2_EL2\0ICH_AP0R3_EL2\0"; break;case 9: t="ICH_AP1R0_EL2\0ICH_AP1R1_EL2\0ICH_AP1R2_EL2\0ICH_AP1R3_EL2\0ICC_SRE_EL2\0"; break;case 11: t="ICH_HCR_EL2\0ICH_VTR_EL2\0ICH_MISR_EL2\0ICH_EISR_EL2\0?\0ICH_ELRSR_EL2\0?\0ICH_VMCR_EL2\0"; break;case 12: t="ICH_LR0_EL2\0ICH_LR1_EL2\0ICH_LR2_EL2\0ICH_LR3_EL2\0ICH_LR4_EL2\0ICH_LR5_EL2\0ICH_LR6_EL2\0ICH_LR7_EL2\0"; break;case 13: t="ICH_LR8_EL2\0ICH_LR9_EL2\0ICH_LR10_EL2\0ICH_LR11_EL2\0ICH_LR12_EL2\0ICH_LR13_EL2\0ICH_LR14_EL2\0ICH_LR15_EL2\0"; break;} break;case 13: if(m==0) t="?\0CONTEXTIDR_EL2\0TPIDR_EL2\0"; break;case 14: switch(m) {case 0: t="?\0?\0?\0CNTVOFF_EL2\0"; break;case 1: t="CNTHCTL_EL2\0"; break;case 2: t="CNTHP_TVAL_EL2\0CNTHP_CTL_EL2\0CNTHP_CVAL_EL2\0"; break;case 3: t="CNTHV_TVAL_EL2\0CNTHV_CTL_EL2\0CNTHV_CVAL_EL2\0"; break;} break;} break;case 5: if(n==4&&m==0) t="SPSR_EL12\0ELR_EL12\0"; break;case 6: if(n==4&&m==1) t="SP_EL2\0"; break;case 7: if(n==14&&m==2) t="CNTPS_TVAL_EL1\0CNTPS_CTL_EL1\0CNTPS_CVAL_EL1\0"; break;} break;}return t?disasm_str(t,j):NULL;}
+uint64_t disasm_dbm(int k, int j, int i) {int e=(k<<6)|(~j&0x3F),l=6;uint64_t m,r;while(l>=0 && !(e&(1<<l))){l--;}if(l<1)return -1;e=1<<l;l=e-1;j&=l;i&=l;if(j==l)return -1;m=~0UL>>(64-(j+1));m=(m>>i)|(m<<(e-i));r=m;i=e;while(i<64){r|=(m<<i);i+=e;}return r;}
+
+/*** public API ***/
+uint64_t disasm(uint64_t addr, char *str)
+{
+    uint32_t i=0;
+    uint16_t op=0, om=0, j=0;
+    uint8_t t=0, s=0, n=0, k=0, m=0, c=0, p=0, a=0, d=0, b=0, q=0, z=0, o=0;
+    uint32_t ic32, ic32_20, ic32_15, ic32_16, ic32_5, ic32_8, ic32_22, ic32_13, ic32_14, ic32_9, ic32_10, ic32_21, ic32_4, ic32_12, ic32_24, ic32_11, ic32_18, ic32_27, ic32_28, ic32_29, ic32_25, ic32_26, ic32_23, ic32_30, ic32_19, ic32_31;
+    uint64_t iaddr=addr;
+    char *names=NULL,*olds=str;
+    char *pstate="?\0?\0?\0uao\0pan\0spsel\0daifs\0daifc\0";
+    char *conds="eq\0ne\0cs\0cc\0mi\0pl\0vs\0vc\0hi\0ls\0ge\0lt\0gt\0le\0al\0nv\0";
+    char *share="?\0oshld\0oshst\0osh\0?\0nshld\0nshst\0nsh\0?\0ishld\0ishst\0ish\0?\0ld\0st\0sy\0";
+    char *at_op0="s1e1r\0s1e1w\0s1e0r\0s1e0w\0";
+    char *at_op1="s1e1rp\0s1e1wp\0";
+    char *at_op2="s1e2r\0s1e2w\0?\0?\0s12e1r\0s12e1w\0s12e0r\0s12e0w\0s1e3r\0s1e3w\0";
+    char *dc_op0="?\0ivac\0isw\0";
+    char *dc_op1="csw\0cisw\0";
+    char *dc_op2="cvac\0cvau\0civac\0";
+    char *ic_op="ialluis\0iallu\0?\0ivau\0";
+    char *tlbi_op0="vmalle1is\0vae1is\0aside1is\0vaae1is\0?\0vale1is\0?\0vaale1is\0vmalle1\0vae1\0aside1\0vaae1\0?\0vale1\0?\0vaale1\0alle2is\0vae2is\0?\0?\0alle1is\0vale2is\0vmalls12e1is\0alle2\0vae2\0?\0?\0alle1\0vale2\0vmalls12e1\0";
+    char *tlbi_op1="ipas2e1is\0ipas2le1is\0ipas2e1\0ipas2el1\0";
+    char *tlbi_op2="alle3is\0vae3is\0?\0vale3is\0alle3\0vae3\0?\0vale3\0";
+    char *quantum="8b\016b\04h\08h\02s\04s\01d\02d\01q\02q\0";
+    char *prf_typ="pld\0pli\0pst\0";
+    char *prf_pol="keep\0strm\0";
+    char *extend32="uxtb\0uxth\0lsl\0uxtx\0sxtb\0sxth\0sxtw\0sxtx\0";
+    char *extend64="uxtb\0uxth\0uxtw\0lsl\0sxtb\0sxth\0sxtw\0sxtx\0";
+    char *shift="lsl\0lsr\0asr\0ror\0";
+    uint8_t args[9]={0,0,0,0,0,0,0,0,0};
+
+    ic32=*((uint32_t*)addr);
+    ic32_20=ic32>>20; ic32_15=ic32>>15; ic32_16=ic32>>16; ic32_5=ic32>>5; ic32_8=ic32>>8; ic32_22=ic32>>22; ic32_13=ic32>>13; ic32_14=ic32>>14; ic32_9=ic32>>9; ic32_10=ic32>>10; ic32_21=ic32>>21; ic32_4=ic32>>4; ic32_12=ic32>>12; ic32_24=ic32>>24; ic32_11=ic32>>11; ic32_18=ic32>>18; ic32_27=ic32>>27; ic32_28=ic32>>28; ic32_29=ic32>>29; ic32_25=ic32>>25; ic32_26=ic32>>26; ic32_23=ic32>>23; ic32_30=ic32>>30; ic32_19=ic32>>19; ic32_31=ic32>>31;
+
+    /* handle multiple NOPs at once */
+    if(ic32==0xd503201f) {
+        while(*((uint32_t*)addr)==ic32) { op++; addr+=4; }
+        if(str!=NULL) str+=sprintf(str,"  %d x nop",op);
+        *str=0;
+        return addr;
+    }
+
+    /* decode instruction */
+    if(((ic32_8)&0xff007c)==0x8007c) {
+        names="stxrb\0stlxrb\0?\0?\0?\0?\0?\0?\0?\0?\0casb\0caslb\0?\0?\0casab\0casalb\0";
+        op=((ic32_20)&0xe)|((ic32_15)&0x1); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wd; args[1]=disasm_arg_Wt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffbffc)==0xe2168) {
+        names="fcvtn\0";
+        z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_Vtzq2; args[1]=disasm_arg_Vnz3;
+    } else
+    if(((ic32_8)&0xffbffc)==0xe21e8) {
+        names="fcvtl\0";
+        z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_Vtz3; args[1]=disasm_arg_Vnzq2;
+    } else
+    if(((ic32_8)&0xff3ffc)==0xe2128) {
+        names="xtn\0";
+        z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT2;
+    } else
+    if(((ic32_8)&0xff3ffc)==0xe2138) {
+        names="shll\0";
+        z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_shift8;
+    } else
+    if(((ic32_8)&0xff209c)==0xe2090) {
+        names="sqdmlal\0sqdmlsl\0sqdmull\0";
+        op=((ic32_13)&0x3); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xffc0b4)==0xf4020) {
+        names="smlal\0smlsl\0";
+        op=((ic32_14)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;q=0;
+        args[0]=disasm_arg_Vtz3; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc0f4)==0xf40a0) {
+        names="smull\0";
+        j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;q=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc0b4)==0xf8020) {
+        names="smlal\0smlsl\0";
+        op=((ic32_14)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;q=0;
+        args[0]=disasm_arg_Vtz3; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc0f4)==0xf80a0) {
+        names="smull\0";
+        j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;q=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xfffffc)==0x1e6240) {
+        names="fcvt\0";
+        n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_St; args[1]=disasm_arg_Dn;
+    } else
+    if(((ic32_8)&0xff3e7c)==0x1e2240) {
+        names="fcvt\0";
+        z=((ic32_22)&0x3); k=((ic32_15)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPk5t; args[1]=disasm_arg_FPz5n;
+    } else
+    if(((ic32_8)&0xff387c)==0x1e2040) {
+        names="fmov\0fabs\0fneg\0fsqrt\0?\0?\0?\0?\0frintn\0frintp\0frintm\0frintz\0frinta\0?\0frintx\0frinti\0";
+        op=((ic32_15)&0xf); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_FPz5n;
+    } else
+    if((ic32&0xff20fc0f)==0x1e202000) {
+        names="fcmp\0fcmpe\0";
+        op=((ic32_4)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f);
+        args[0]=disasm_arg_FPz5n; args[1]=disasm_arg_FPz5m;
+    } else
+    if((ic32&0xff20fc0f)==0x1e202008) {
+        names="fcmp\0fcmpe\0";
+        op=((ic32_4)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f);
+        args[0]=disasm_arg_FPz5n; args[1]=disasm_arg_simd0;
+    } else
+    if((ic32&0xff201fe0)==0x1e201000) {
+        names="fmov\0";
+        z=((ic32_22)&0x3); j=((ic32_13)&0xff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_jz;
+    } else
+    if(((ic32_8)&0xff200c)==0x1e2004) {
+        names="ffcmp\0ffcmpe\0";
+        op=((ic32_4)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); c=((ic32_12)&0xf); n=((ic32_5)&0x1f); j=((ic32)&0xf);
+        args[0]=disasm_arg_FPz5n; args[1]=disasm_arg_FPz5m; args[2]=disasm_arg_j; args[3]=disasm_arg_c;
+    } else
+    if(((ic32_8)&0xff200c)==0x1e2008) {
+        names="fmul\0fdiv\0fadd\0fsub\0fmax\0fmin\0fmaxnm\0fminmn\0fnmul\0";
+        op=((ic32_12)&0xf); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_FPz5n; args[2]=disasm_arg_FPz5m;
+    } else
+    if(((ic32_8)&0xff200c)==0x1e200c) {
+        names="fcsel\0";
+        z=((ic32_22)&0x3); m=((ic32_16)&0x1f); c=((ic32_12)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_FPz5n; args[2]=disasm_arg_FPz5m; args[3]=disasm_arg_c;
+    } else
+    if(((ic32_24)&0xff)==0x1f) {
+        names="fmadd\0fmsub\0fnmadd\0fnmsub\0";
+        op=((ic32_20)&0x2)|((ic32_15)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); d=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_FPz5n; args[2]=disasm_arg_FPz5m; args[3]=disasm_arg_FPz5t; args[4]=disasm_arg_FPz5n; args[5]=disasm_arg_FPz5d;
+    } else
+    if(((ic32_8)&0xfff8fc)==0x2f00e4) {
+        names="movi\0";
+        j=((ic32_11)&0xe0)|((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Dt; args[1]=disasm_arg_imm64;
+    } else
+    if(((ic32_8)&0xff200c)==0x382000) {
+        names="ldaddb\0ldclrb\0ldeorb\0ldsetb\0ldsmaxb\0ldsminb\0ldumaxb\0lduminb\0swpb\0?\0?\0?\0?\0?\0?\0?\0ldaddlb\0ldclrlb\0ldeorlb\0ldsetlb\0ldsmaxlb\0ldsminlb\0ldumaxlb\0lduminlb\0swplb\0?\0?\0?\0?\0?\0?\0?\0ldaddab\0ldclrab\0ldeorab\0ldsetab\0ldsmaxab\0ldsminab\0ldumaxab\0lduminab\0swpab\0?\0?\0?\0?\0?\0?\0?\0ldaddalb\0ldclralb\0ldeoralb\0ldsetalb\0ldsmaxalb\0ldsminalb\0ldumaxalb\0lduminalb\0swpalb\0";
+        op=((ic32_18)&0x30)|((ic32_12)&0xf); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wd; args[1]=disasm_arg_Wt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xdf3f9c)==0xe2108) {
+        names="?\0xtn\0sqxtn\0?\0?\0sqxtun\0uqxtn\0fcvtxn\0";
+        op=((ic32_27)&0x4)|((ic32_13)&0x3); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT3;
+    } else
+    if(((ic32_8)&0xdf20dc)==0xe2010) {
+        names="saddw\0ssubw\0uaddw\0usubw\0";
+        op=((ic32_28)&0x2)|((ic32_13)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_VtT3; args[1]=disasm_arg_VnT3; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xdf20dc)==0xe2040) {
+        names="addhn\0subhn\0raddhn\0rsubhn\0";
+        op=((ic32_28)&0x2)|((ic32_13)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT3; args[2]=disasm_arg_VmT3;
+    } else
+    if(((ic32_8)&0xdf20fc)==0xe20e0) {
+        names="pmull\0umull\0";
+        op=((ic32_29)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_VtT4; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xdf200c)==0xe2000) {
+        names="saddl\0saddw\0ssubl\0ssubw\0addhn\0sabal\0subhn\0sabdl\0smlal\0sqdmlal\0smlsl\0sqdmlsl\0?\0sqdmull\0pmull\0?\0uaddl\0uaddw\0usubl\0usubw\0raddhn\0uabal\0rsubhn\0uabdl\0umlal\0?\0umlsl\0?\0?\0?\0umull\0";
+        op=((ic32_25)&0x10)|((ic32_12)&0xf); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_VtT3; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xdfc024)==0xf4020) {
+        names="smlal\0sqdmlal\0smlsl\0sqdmlsl\0smull\0sqdmull\0?\0?\0umlal\0?\0umlsl\0?\0umull\0";
+        op=((ic32_26)&0x8)|((ic32_13)&0x6)|((ic32_12)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;q=0;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xdf80e4)==0xf0084) {
+        names="?\0rshrn\0sqshrn\0sqrshrn\0sqshrun\0sqrshrun\0uqshrn\0uqrshrn\0";
+        op=((ic32_27)&0x4)|((ic32_11)&0x3); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_VnTa; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xdf80fc)==0xf00a4) {
+        names="sshll\0usshll\0";
+        op=((ic32_29)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=0;
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_VnTa; args[2]=disasm_arg_shlshift;
+    } else
+    if(((ic32_8)&0xdfc024)==0xf8020) {
+        names="smlal\0sqdmlal\0smlsl\0sqdmlsl\0smull\0sqdmull\0?\0?\0umlal\0?\0umlsl\0?\0umull\0";
+        op=((ic32_26)&0x8)|((ic32_13)&0x6)|((ic32_12)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;q=0;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xff007c)==0x48007c) {
+        names="stxrh\0stlxrh\0?\0?\0?\0?\0?\0?\0?\0?\0cash\0caslh\0?\0?\0casah\0casalh\0";
+        op=((ic32_20)&0xe)|((ic32_15)&0x1); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wd; args[1]=disasm_arg_Wt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x4e001c) {
+        names="ins\0";
+        j=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj; args[1]=disasm_arg_offs; args[2]=disasm_arg_FPidx; args[3]=disasm_arg_offe; args[4]=disasm_arg_R2n;
+    } else
+    if(((ic32_8)&0xffffcc)==0x4e2848) {
+        names="aese\0aesd\0aesmc\0aesimc\0";
+        op=((ic32_12)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt16b; args[1]=disasm_arg_Vn16b;
+    } else
+    if(((ic32_8)&0xffbffc)==0x4e2168) {
+        names="fcvtn2\0";
+        z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_Vtzq2; args[1]=disasm_arg_Vnz3;
+    } else
+    if(((ic32_8)&0xffbffc)==0x4e21e8) {
+        names="fcvtl2\0";
+        z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_Vtz3; args[1]=disasm_arg_Vnzq2;
+    } else
+    if(((ic32_8)&0xff3ffc)==0x4e2128) {
+        names="xtn2\0";
+        z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT2;
+    } else
+    if(((ic32_8)&0xff3ffc)==0x4e2138) {
+        names="shll2\0";
+        z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_shift8;
+    } else
+    if(((ic32_8)&0xff209c)==0x4e2090) {
+        names="sqdmlal2\0sqdmlsl2\0sqdmull2\0";
+        op=((ic32_13)&0x3); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xffc0b4)==0x4f4020) {
+        names="smlal2\0smlsl2\0";
+        op=((ic32_14)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;q=1;
+        args[0]=disasm_arg_Vtz3; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc0f4)==0x4f40a0) {
+        names="smull2\0";
+        j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;q=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc0b4)==0x4f8020) {
+        names="smlal2\0smlsl2\0";
+        op=((ic32_14)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;q=1;
+        args[0]=disasm_arg_Vtz3; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc0f4)==0x4f80a0) {
+        names="smull2\0";
+        j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;q=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if((ic32&0xff000010)==0x54000000) {
+        names="b.%s\0";
+        i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); c=((ic32)&0xf);
+        args[0]=disasm_arg_labeli4;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x5e0004) {
+        names="dup\0";
+        j=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPjt; args[1]=disasm_arg_Vnj; args[2]=disasm_arg_offs; args[3]=disasm_arg_FPidx; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x5e0030) {
+        names="sha1su0\0";
+        m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s; args[2]=disasm_arg_Vm4s;
+    } else
+    if(((ic32_8)&0xffe0cc)==0x5e0000) {
+        names="sha1c\0sha1p\0sha1m\0sha1su0\0";
+        op=((ic32_12)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Qt; args[1]=disasm_arg_Sn; args[2]=disasm_arg_Vm4s;
+    } else
+    if(((ic32_8)&0xffe0ec)==0x5e0040) {
+        names="sha256h\0sha256h2\0";
+        op=((ic32_12)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Qt; args[1]=disasm_arg_Qn; args[2]=disasm_arg_Vm4s;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x5e0060) {
+        names="sha256su1\0";
+        m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s; args[2]=disasm_arg_Vm4s;
+    } else
+    if(((ic32_8)&0xfffffc)==0x5e2808) {
+        names="sha1h\0";
+        n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_St; args[1]=disasm_arg_Sn;
+    } else
+    if(((ic32_8)&0xfffffc)==0x5e2818) {
+        names="sha1su1\0";
+        n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s;
+    } else
+    if(((ic32_8)&0xfffffc)==0x5e2828) {
+        names="sha256su0\0";
+        n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x5e401c) {
+        names="fmulx\0";
+        m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_Hm;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x5e4024) {
+        names="fcmeq\0";
+        m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_Hm;
+    } else
+    if(((ic32_8)&0xffa0fc)==0x5e20dc) {
+        names="fmulx\0";
+        z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_FPm;
+    } else
+    if(((ic32_8)&0xffa0fc)==0x5e20e4) {
+        names="fcmeq\0";
+        z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_FPm;
+    } else
+    if(((ic32_8)&0xff7fcc)==0x5e30c8) {
+        names="fmaxnmp\0faddp\0?\0fmaxp\0fminnmp\0?\0?\0fminp\0";
+        op=((ic32_21)&0x4)|((ic32_12)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Vn2h;
+    } else
+    if(((ic32_8)&0xff60fc)==0x5e403c) {
+        names="frecps\0frsqrts\0";
+        op=((ic32_23)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_Hm;
+    } else
+    if(((ic32_8)&0xff3ffc)==0x5e31b8) {
+        names="addp\0";
+        z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz3t; args[1]=disasm_arg_Vn2d;
+    } else
+    if(((ic32_8)&0xff20fc)==0x5e20fc) {
+        names="frecps\0frsqrts\0";
+        op=((ic32_23)&0x1); z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_FPm;
+    } else
+    if(((ic32_8)&0xff209c)==0x5e2090) {
+        names="sqdmlal\0sqdmlsl\0sqdmull\0";
+        op=((ic32_13)&0x3); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz2n; args[2]=disasm_arg_FPz2m;
+    } else
+    if(((ic32_8)&0xffc0e4)==0x5f40c0) {
+        names="sqdmulh\0sqrdmulh\0";
+        op=((ic32_12)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz4n; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc034)==0x5f4030) {
+        names="sqdmlal\0sqdmlsl\0sqdmull\0";
+        op=((ic32_14)&0x3); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz3n; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xff80dc)==0x5f0054) {
+        names="shl\0sqshl\0";
+        op=((ic32_13)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Dt; args[1]=disasm_arg_Dn; args[2]=disasm_arg_shlshift;
+    } else
+    if(((ic32_8)&0xffc0e4)==0x5f80c0) {
+        names="sqdmulh\0sqrdmulh\0";
+        op=((ic32_12)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz4n; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffc034)==0x5f8030) {
+        names="sqdmlal\0sqdmlsl\0sqdmull\0";
+        op=((ic32_14)&0x3); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz3n; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_16)&0xffc0)==0x68c0) {
+        names="ldpsw\0";
+        i=((ic32_21)&1?(0xffffffff<<7):0)|((ic32_15)&0x7f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_Xm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_im4_opt;
+    } else
+    if(((ic32_16)&0xff40)==0x6940) {
+        names="ldpsw\0";
+        p=((ic32_23)&0x1); i=((ic32_21)&1?(0xffffffff<<7):0)|((ic32_15)&0x7f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_Xm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_im4_opt; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffe084)==0x6e0004) {
+        names="ins\0";
+        j=((ic32_16)&0x1f); k=((ic32_11)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj; args[1]=disasm_arg_offs; args[2]=disasm_arg_FPidx; args[3]=disasm_arg_offe; args[4]=disasm_arg_Vnj; args[5]=disasm_arg_offs; args[6]=disasm_arg_FPidxk; args[7]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xff3fcc)==0x6e30c8) {
+        names="fmaxnmv\0?\0?\0fmaxv\0fminnmv\0?\0?\0fminv\0";
+        op=((ic32_21)&0x4)|((ic32_12)&0x3); z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_Vn4s;
+    } else
+    if(((ic32_8)&0xfff8fc)==0x6f00e4) {
+        names="movi\0";
+        j=((ic32_11)&0xe0)|((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2d; args[1]=disasm_arg_imm64;
+    } else
+    if(((ic32_8)&0xfff8fc)==0x6f00f4) {
+        names="fmov\0";
+        j=((ic32_11)&0xe0)|((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2d; args[1]=disasm_arg_F64;
+    } else
+    if(((ic32_8)&0xff200c)==0x782000) {
+        names="ldaddh\0ldclrh\0ldeorh\0ldseth\0ldsmaxh\0ldsminh\0ldumaxh\0lduminh\0swph\0?\0?\0?\0?\0?\0?\0?\0ldaddlh\0ldclrlh\0ldeorlh\0ldsetlh\0ldsmaxlh\0ldsminlh\0ldumaxlh\0lduminlh\0swplh\0?\0?\0?\0?\0?\0?\0?\0ldaddah\0ldclrah\0ldeorah\0ldsetah\0ldsmaxah\0ldsminah\0ldumaxah\0lduminah\0swpah\0?\0?\0?\0?\0?\0?\0?\0ldaddalh\0ldclralh\0ldeoralh\0ldsetalh\0ldsmaxalh\0ldsminalh\0ldumaxalh\0lduminalh\0swpalh\0";
+        op=((ic32_18)&0x30)|((ic32_12)&0xf); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wd; args[1]=disasm_arg_Wt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffdffc)==0x7e10c8) {
+        names="fmaxnmp\0";
+        z=((ic32_21)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_Vnz;
+    } else
+    if(((ic32_8)&0xffe0f4)==0x7e4024) {
+        names="fcmge\0facge\0";
+        op=((ic32_11)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_Hm;
+    } else
+    if(((ic32_8)&0xffa0f4)==0x7e20e4) {
+        names="fcmge\0facge\0";
+        op=((ic32_11)&0x1); z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_FPm;
+    } else
+    if(((ic32_8)&0xffe0fc)==0x7ec014) {
+        names="fabd\0";
+        m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_Hm;
+    } else
+    if(((ic32_8)&0xffe0f4)==0x7ec024) {
+        names="fcmgt\0facgt\0";
+        op=((ic32_11)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_Hm;
+    } else
+    if(((ic32_8)&0xffa0fc)==0x7ea0d4) {
+        names="fabd\0";
+        z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_FPm;
+    } else
+    if(((ic32_8)&0xffa0f4)==0x7ea0e4) {
+        names="fcmgt\0facgt\0";
+        op=((ic32_11)&0x1); z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_FPm;
+    } else
+    if(((ic32_8)&0xff20f4)==0x7e0084) {
+        names="sqrdmlah\0sqrdmlsh\0";
+        op=((ic32_11)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz2t; args[1]=disasm_arg_FPz2n; args[2]=disasm_arg_FPz2m;
+    } else
+    if(((ic32_8)&0xff3fcc)==0x7e30c8) {
+        names="?\0faddp\0?\0fmaxp\0fminnmp\0?\0?\0fminp\0";
+        op=((ic32_21)&0x4)|((ic32_12)&0x3); z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_Vnz;
+    } else
+    if(((ic32_8)&0xffc0d4)==0x7f40d0) {
+        names="sqrdmlah\0sqrdmlsh\0";
+        op=((ic32_13)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz3n; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xff80fc)==0x7f0064) {
+        names="sqshlu\0";
+        j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Dt; args[1]=disasm_arg_Dn; args[2]=disasm_arg_shlshift;
+    } else
+    if(((ic32_8)&0xff80fc)==0x7f0074) {
+        names="uqshl\0";
+        j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPjt2; args[1]=disasm_arg_FPjn2; args[2]=disasm_arg_shlshift;
+    } else
+    if(((ic32_8)&0xffc0d4)==0x7f80d0) {
+        names="sqrdmlah\0sqrdmlsh\0";
+        op=((ic32_13)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_FPz3n; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xdf3f9c)==0x4e2108) {
+        names="?\0xtn2\0sqxtn2\0?\0?\0sqxtun2\0uqxtn2\0fcvtxn2\0";
+        op=((ic32_27)&0x4)|((ic32_13)&0x3); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT3;
+    } else
+    if(((ic32_8)&0xdf20dc)==0x4e2010) {
+        names="saddw2\0ssubw2\0uaddw2\0usubw2\0";
+        op=((ic32_28)&0x2)|((ic32_13)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_VtT3; args[1]=disasm_arg_VnT3; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xdf20dc)==0x4e2040) {
+        names="addhn2\0subhn2\0raddhn2\0rsubhn2\0";
+        op=((ic32_28)&0x2)|((ic32_13)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT3; args[2]=disasm_arg_VmT3;
+    } else
+    if(((ic32_8)&0xdf20fc)==0x4e20e0) {
+        names="pmull2\0umull2\0";
+        op=((ic32_29)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_VtT4; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xdf200c)==0x4e2000) {
+        names="saddl2\0saddw2\0ssubl2\0ssubw2\0addhn2\0sabal2\0subhn2\0sabdl2\0smlal2\0sqdmlal2\0smlsl2\0sqdmlsl2\0?\0sqdmull2\0pmull2\0?\0uaddl2\0uaddw2\0usubl2\0usubw2\0raddhn2\0uabal2\0rsubhn2\0uabdl2\0umlal2\0?\0umlsl2\0?\0?\0?\0umull2\0";
+        op=((ic32_25)&0x10)|((ic32_12)&0xf); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_VtT3; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xdfc024)==0x4f4020) {
+        names="smlal2\0sqdmlal2\0smlsl2\0sqdmlsl2\0smull2\0sqdmull2\0?\0?\0umlal2\0?\0umlsl2\0?\0umull2\0";
+        op=((ic32_26)&0x8)|((ic32_13)&0x6)|((ic32_12)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;q=1;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xdf80e4)==0x4f0084) {
+        names="?\0rshrn2\0sqshrn2\0sqrshrn2\0sqshrun2\0sqrshrun2\0uqshrn2\0uqrshrn2\0";
+        op=((ic32_27)&0x4)|((ic32_11)&0x3); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_VnTa; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xdf80fc)==0x4f00a4) {
+        names="sshll2\0usshll2\0";
+        op=((ic32_29)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        q=1;
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_VnTa; args[2]=disasm_arg_shlshift;
+    } else
+    if(((ic32_8)&0xdfc024)==0x4f8020) {
+        names="smlal2\0sqdmlal2\0smlsl2\0sqdmlsl2\0smull2\0sqdmull2\0?\0?\0umlal2\0?\0umlsl2\0?\0umull2\0";
+        op=((ic32_26)&0x8)|((ic32_13)&0x6)|((ic32_12)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;q=1;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xdfffcc)==0x5ef8c8) {
+        names="fcmgt\0fcmeq\0fcmlt\0?\0fcmge\0fcmle\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_simd0;
+    } else
+    if(((ic32_8)&0xdfbfcc)==0x5ea0c8) {
+        names="fcmgt\0fcmeq\0fcmlt\0?\0fcmge\0fcmle\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_simd0;
+    } else
+    if(((ic32_8)&0xdf7f8c)==0x5e7988) {
+        names="?\0?\0fcvtns\0fcvtms\0fcvtas\0scvtf\0?\0?\0?\0?\0fcvtps\0fcvtzs\0?\0frecpe\0?\0frecpx\0?\0?\0fcvtnu\0fcvtmu\0fcvtau\0ucvtf\0?\0?\0?\0?\0fcvtpu\0fcvtzu\0?\0frsqrte\0";
+        op=((ic32_25)&0x10)|((ic32_20)&0x8)|((ic32_12)&0x7); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn;
+    } else
+    if(((ic32_8)&0xdf3fcc)==0x5e2088) {
+        names="cmgt\0cmeq\0cmlt\0abs\0cmge\0cmle\0?\0neg\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz3t; args[1]=disasm_arg_FPz3n; args[2]=disasm_arg_simd0;
+    } else
+    if(((ic32_8)&0xdf3f3c)==0x5e2038) {
+        names="suqadd\0sqabs\0abs\0?\0usqadd\0sqneg\0neg\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz3t; args[1]=disasm_arg_FPz3n;
+    } else
+    if(((ic32_8)&0xdf3f9c)==0x5e2108) {
+        names="?\0?\0sqxtn\0?\0?\0sqxtun\0uqxtn\0fcvtxn\0";
+        op=((ic32_27)&0x4)|((ic32_13)&0x3); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz3t; args[1]=disasm_arg_FPz4n;
+    } else
+    if(((ic32_8)&0xdf3f8c)==0x5e2188) {
+        names="?\0?\0fcvtns\0fcvtms\0fcvtas\0scvtf\0?\0?\0?\0?\0fcvtps\0fcvtzs\0?\0frecpe\0?\0frecpx\0?\0?\0fcvtnu\0fcvtmu\0fcvtau\0ucvtf\0?\0?\0?\0?\0fcvtpu\0fcvtzu\0?\0frsqrte\0";
+        op=((ic32_25)&0x10)|((ic32_20)&0x8)|((ic32_12)&0x7); z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn;
+    } else
+    if(((ic32_8)&0xdf2004)==0x5e2004) {
+        names="?\0sqadd\0?\0?\0?\0sqsub\0cmgt\0cmge\0sshl\0sqshl\0srshl\0sqrshl\0?\0?\0?\0?\0add\0cmtst\0?\0?\0?\0?\0sqdmulh\0?\0?\0?\0?\0?\0?\0?\0?\0?\0?\0uqadd\0?\0?\0?\0uqsub\0cmhi\0cmhs\0ushl\0uqshl\0urshl\0uqrshl\0?\0?\0?\0?\0sub\0cmeq\0?\0?\0?\0?\0sqrdmulh\0";
+        op=((ic32_24)&0x20)|((ic32_11)&0x1f); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz3t; args[1]=disasm_arg_FPz3n; args[2]=disasm_arg_FPz3m;
+    } else
+    if(((ic32_8)&0xdfc034)==0x5f0010) {
+        names="fmla\0fmls\0fmul\0?\0?\0?\0fmulx\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); j=((ic32_9)&0x4)|((ic32_20)&0x3); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Hn; args[2]=disasm_arg_VmHs;
+    } else
+    if(((ic32_8)&0xdf808c)==0x5f0004) {
+        names="sshr\0ssra\0srshr\0srsra\0?\0shl\0?\0sqshl\0ushr\0usra\0urshr\0ursra\0sri\0sli\0sqshlu\0uqshl\0";
+        op=((ic32_26)&0x8)|((ic32_12)&0x7); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Dt; args[1]=disasm_arg_Dn; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xdf80e4)==0x5f0084) {
+        names="?\0?\0sqshrn\0sqrshrn\0sqshrun\0sqrshrun\0uqshrn\0uqrshrn\0";
+        op=((ic32_27)&0x4)|((ic32_11)&0x3); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPjt; args[1]=disasm_arg_FPnj; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xdf80fc)==0x5f00e4) {
+        names="scvtf\0ucvtf\0";
+        op=((ic32_29)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPjt2; args[1]=disasm_arg_FPjn2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xdf80fc)==0x5f00fc) {
+        names="fcvtzs\0fcvtzu\0";
+        op=((ic32_29)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPjt; args[1]=disasm_arg_FPjn2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xdfc034)==0x5f8010) {
+        names="fmla\0fmls\0fmul\0sqrdmulh\0?\0?\0fmulx\0sqrdmlah\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); j=((ic32_10)&0x2)|((ic32_21)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_VmTs2;
+    } else
+    if(((ic32_8)&0xdfe034)==0x5fc010) {
+        names="fmla\0fmls\0fmul\0?\0?\0?\0fmulx\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); j=((ic32_11)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPn; args[2]=disasm_arg_VmTs2;
+    } else
+    if(((ic32_8)&0xbfa07c)==0x8207c) {
+        names="casp\0caspl\0caspa\0caspal\0";
+        op=((ic32_21)&0x2)|((ic32_15)&0x1); s=((ic32_30)&0x1); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rd; args[1]=disasm_arg_Rd1; args[2]=disasm_arg_Rt; args[3]=disasm_arg_Rt1; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbf3f7c)==0x81f7c) {
+        names="?\0?\0ldxrb\0ldaxrb\0stllrb\0stlrb\0ldlarb\0ldarb\0?\0?\0ldxrh\0ldaxrh\0stllrh\0stlrh\0ldlarh\0ldarh\0";
+        op=((ic32_27)&0x8)|((ic32_21)&0x6)|((ic32_15)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfd0)==0xc0000) {
+        names="st4\0st1\0ld4\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_Vt4T; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbff0)==0xc0070) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfd0)==0xc0040) {
+        names="st3\0st1\0ld3\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfd0)==0xc0080) {
+        names="st2\0st1\0ld2\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfd0)==0xc9f00) {
+        names="st4\0st1\0ld4\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_Vt4T; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe; args[7]=disasm_arg_Qi;
+    } else
+    if(((ic32_8)&0xbfbff0)==0xc9f70) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Qi1;
+    } else
+    if(((ic32_8)&0xbfbfd0)==0xc9f40) {
+        names="st3\0st1\0ld3\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe; args[6]=disasm_arg_Qi3;
+    } else
+    if(((ic32_8)&0xbfbfd0)==0xc9f80) {
+        names="st2\0st1\0ld2\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_Qi2;
+    } else
+    if(((ic32_8)&0xbfa0d0)==0xc8000) {
+        names="st4\0st1\0ld4\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_Vt4T; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe; args[7]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0f0)==0xc8070) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0d0)==0xc8040) {
+        names="st3\0st1\0ld3\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe; args[6]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0d0)==0xc8080) {
+        names="st2\0st1\0ld2\0ld1\0";
+        op=((ic32_21)&0x2)|((ic32_13)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbffff0)==0xd40c0) {
+        names="ld1r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbffff0)==0xd40e0) {
+        names="ld3r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbffff0)==0xd60c0) {
+        names="ld2r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbffff0)==0xd60e0) {
+        names="ld4r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_Vt4T; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd0000) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtB; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd0020) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd0040) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd0060) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xd0084) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtD; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xd0080) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtS; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xd00a4) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xd00a0) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd2000) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd2020) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd2040) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd2060) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xd2084) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xd2080) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xd20a4) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xd20a0) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbffff0)==0xddfc0) {
+        names="ld1r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_z;
+    } else
+    if(((ic32_8)&0xbffff0)==0xddfe0) {
+        names="ld3r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe; args[6]=disasm_arg_z3;
+    } else
+    if(((ic32_8)&0xbfe0f0)==0xdc0c0) {
+        names="ld1r\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfe0f0)==0xdc0e0) {
+        names="ld3r\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe; args[6]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbffff0)==0xdffc0) {
+        names="ld2r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_z2;
+    } else
+    if(((ic32_8)&0xbffff0)==0xdffe0) {
+        names="ld4r\0";
+        q=((ic32_30)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_Vt4T; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe; args[7]=disasm_arg_z4;
+    } else
+    if(((ic32_8)&0xbfe0f0)==0xde0c0) {
+        names="ld2r\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfe0f0)==0xde0e0) {
+        names="ld4r\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vt2T; args[2]=disasm_arg_Vt3T; args[3]=disasm_arg_Vt4T; args[4]=disasm_arg_offs; args[5]=disasm_arg_XnS; args[6]=disasm_arg_offe; args[7]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd9f00) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtB; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i1;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd9f20) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i3;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd9f40) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i2;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xd9f60) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i6;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xd9f84) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtD; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i8;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xd9f80) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtS; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i4;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xd9fa4) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i24;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xd9fa0) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i12;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xd8000) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtB; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xd8020) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xd8040) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xd8060) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0fc)==0xd8084) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtD; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0ec)==0xd8080) {
+        names="st1\0ld1\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtS; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0fc)==0xd80a4) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0ec)==0xd80a0) {
+        names="st3\0ld3\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt3S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xdbf00) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i2;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xdbf20) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i4;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xdbf40) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i4;
+    } else
+    if(((ic32_8)&0xbfbfe0)==0xdbf60) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i8;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xdbf84) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i16;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xdbf80) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i8;
+    } else
+    if(((ic32_8)&0xbfbffc)==0xdbfa4) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i32;
+    } else
+    if(((ic32_8)&0xbfbfec)==0xdbfa0) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i16;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xda000) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xda020) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4B; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xda040) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0e0)==0xda060) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); z=((ic32_10)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4H; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0fc)==0xda084) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0ec)==0xda080) {
+        names="st2\0ld2\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0fc)==0xda0a4) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4D; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfa0ec)==0xda0a0) {
+        names="st4\0ld4\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); s=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4S; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xbfe0fc)==0xe0004) {
+        names="dup\0";
+        q=((ic32_30)&0x1); j=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtjq; args[1]=disasm_arg_Vnj; args[2]=disasm_arg_offs; args[3]=disasm_arg_FPidx; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfe0ec)==0xe0000) {
+        names="tbl\0tbx\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vn116b; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xbfe0ec)==0xe0020) {
+        names="tbl\0tbx\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vn216b; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xbfe0ec)==0xe002c) {
+        names="smov\0umov\0";
+        op=((ic32_12)&0x1); s=((ic32_30)&0x1); j=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Vnj; args[2]=disasm_arg_offs; args[3]=disasm_arg_FPidx; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfe0ec)==0xe0040) {
+        names="tbl\0tbx\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vn316b; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xbfe0ec)==0xe0060) {
+        names="tbl\0tbx\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vn416b; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xbfe0fc)==0xe401c) {
+        names="fmulx\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmH1;
+    } else
+    if(((ic32_8)&0xbfe0fc)==0xe4024) {
+        names="fcmeq\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmH1;
+    } else
+    if(((ic32_8)&0xbfffec)==0xe7988) {
+        names="frintn\0frintm\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbffffc)==0xe79f8) {
+        names="fabs\0";
+        q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbfa0fc)==0xe201c) {
+        names="fmulx\0";
+        q=((ic32_30)&0x1); z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_Vnzq; args[2]=disasm_arg_Vmzq;
+    } else
+    if(((ic32_8)&0xbfffec)==0xef988) {
+        names="frintp\0frintz\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbf7fcc)==0xe30c8) {
+        names="fmaxnmv\0?\0?\0fmaxv\0fminnmv\0?\0?\0fminv\0";
+        op=((ic32_21)&0x4)|((ic32_12)&0x3); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_Ht; args[1]=disasm_arg_Vnzq2;
+    } else
+    if(((ic32_8)&0xbf60fc)==0xe403c) {
+        names="frecps\0frsqrts\0";
+        op=((ic32_23)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmH1;
+    } else
+    if(((ic32_8)&0xbf0080)==0xe0000) {
+        names="?\0?\0?\0?\0?\0?\0uzp1\0?\0?\0?\0trn1\0?\0?\0?\0zip1\0?\0?\0?\0?\0?\0?\0?\0uzp2\0?\0?\0?\0trn2\0?\0?\0?\0zip2\0?\0?\0shadd\0?\0sqadd\0?\0srhadd\0?\0?\0?\0?\0?\0sqsub\0?\0cmgt\0?\0cmge\0?\0sshl\0?\0sqshl\0?\0srshl\0?\0sqrshl\0?\0smax\0?\0smin\0?\0sabd\0?\0saba\0";
+        op=((ic32_16)&0x20)|((ic32_10)&0x1f); q=((ic32_30)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xbff8fc)==0xf00e4) {
+        names="movi\0";
+        q=((ic32_30)&0x1); j=((ic32_11)&0xe0)|((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_imm8;
+    } else
+    if(((ic32_8)&0xbff8fc)==0xf00f4) {
+        names="fmov\0";
+        q=((ic32_30)&0x1); j=((ic32_11)&0xe0)|((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_F32;
+    } else
+    if(((ic32_8)&0xbff8fc)==0xf00fc) {
+        names="fmov\0";
+        q=((ic32_30)&0x1); j=((ic32_11)&0xe0)|((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_F16;
+    } else
+    if(((ic32_8)&0xbfc0a4)==0xf4080) {
+        names="mul\0?\0sqdmulh\0sqrdmulh\0";
+        op=((ic32_13)&0x2)|((ic32_12)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); q=((ic32_30)&0x1); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xbf80cc)==0xf0004) {
+        names="sshr\0ssra\0srshr\0srsra\0";
+        op=((ic32_12)&0x3); q=((ic32_30)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_Vnj2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xbf80fc)==0xf00e4) {
+        names="scvtf\0";
+        q=((ic32_30)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_Vnj2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xbf80fc)==0xf00fc) {
+        names="fcvtzs\0";
+        q=((ic32_30)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_Vnj2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xbfc0a4)==0xf8080) {
+        names="mul\0fmul\0sqdmulh\0sqrdmulh\0";
+        op=((ic32_13)&0x2)|((ic32_12)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_24)&0xbf)==0x18) {
+        names="ldr\0";
+        s=((ic32_30)&0x1); i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_labeli4;
+    } else
+    if(((ic32_8)&0xbfe0fc)==0x1e000c) {
+        names="dup\0";
+        q=((ic32_30)&0x1); j=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        s=q;
+        args[0]=disasm_arg_Vtjq; args[1]=disasm_arg_Rn;
+    } else
+    if(((ic32_8)&0xbfe084)==0x2e0000) {
+        names="ext\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); i=((ic32_14)&1?(0xffffffff<<4):0)|((ic32_11)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT; args[3]=disasm_arg_i;
+    } else
+    if(((ic32_8)&0xbfe0f4)==0x2e4024) {
+        names="fcmge\0facge\0";
+        op=((ic32_11)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmH1;
+    } else
+    if(((ic32_8)&0xbffffc)==0x2e7998) {
+        names="frintx\0";
+        q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbfbffc)==0x2e2058) {
+        names="not\0rbit\0";
+        op=((ic32_22)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbfe0fc)==0x2ec014) {
+        names="fabd\0";
+        q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmH1;
+    } else
+    if(((ic32_8)&0xbfe0f4)==0x2ec024) {
+        names="fcmgt\0facgt\0";
+        op=((ic32_11)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmH1;
+    } else
+    if(((ic32_8)&0xbffffc)==0x2ef8f8) {
+        names="fneg\0";
+        q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbfffec)==0x2ef988) {
+        names="frinta\0frinti\0";
+        op=((ic32_12)&0x1); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbffffc)==0x2ef9f8) {
+        names="fsqrt\0";
+        q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0xbf2004)==0x2e2004) {
+        names="uhadd\0uqadd\0urhadd\0?\0uhsub\0uqsub\0cmhi\0cmhs\0ushl\0uqshl\0urshl\0uqrshl\0umax\0umin\0uabd\0uaba\0sub\0cmeq\0mls\0pmul\0umaxp\0uminp\0cqrdmulh\0";
+        op=((ic32_11)&0x1f); q=((ic32_30)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0xbfc0d4)==0x2f40d0) {
+        names="sqrdmlah\0sqrdmlsh\0";
+        op=((ic32_13)&0x1); j=((ic32_9)&0x4)|((ic32_20)&0x3); q=((ic32_30)&0x1); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xbf80fc)==0x2f00fc) {
+        names="fcvtzu\0";
+        q=((ic32_30)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_Vnj2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xbf800c)==0x2f0004) {
+        names="ushr\0usra\0urshr\0ursra\0sri\0sli\0sqshlu\0uqshl\0?\0?\0?\0?\0?\0?\0ucvtf\0";
+        op=((ic32_12)&0xf); q=((ic32_30)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_Vnj2; args[2]=disasm_arg_shrshift;
+    } else
+    if(((ic32_8)&0xbfc0d4)==0x2f80d0) {
+        names="sqrdmlah\0sqrdmlsh\0";
+        op=((ic32_13)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_Vtz; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xbf00b4)==0x2f0000) {
+        names="mla\0mls\0";
+        op=((ic32_14)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); q=((ic32_30)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xbfa00c)==0x380004) {
+        names="strb\0ldrb\0strh\0ldrh\0";
+        op=((ic32_29)&0x2)|((ic32_22)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i_opt;
+    } else
+    if(((ic32_8)&0xbfa004)==0x380004) {
+        names="strb\0ldrb\0strh\0ldrh\0";
+        op=((ic32_29)&0x2)|((ic32_22)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); p=((ic32_11)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa00c)==0x382008) {
+        names="strb\0ldrb\0strh\0ldrh\0";
+        op=((ic32_29)&0x2)|((ic32_22)&0x1); m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_Rom; args[4]=disasm_arg_amountj; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa00c)==0x388004) {
+        names="ldrsb\0ldrsh\0";
+        op=((ic32_30)&0x1); s=((ic32_22)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_nRt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i_opt;
+    } else
+    if(((ic32_8)&0xbfa004)==0x388000) {
+        names="ldursb\0?\0ldursh\0ldtrsh\0";
+        op=((ic32_29)&0x2)|((ic32_11)&0x1); s=((ic32_22)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_nRt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa004)==0x388004) {
+        names="ldrsb\0ldrsh\0";
+        op=((ic32_30)&0x1); s=((ic32_22)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); p=((ic32_11)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_nRt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa00c)==0x38a008) {
+        names="ldrsb\0ldrsh\0";
+        op=((ic32_30)&0x1); s=((ic32_22)&0x1); m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_nRt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_Rom; args[4]=disasm_arg_amountj; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbf2004)==0x380000) {
+        names="sturb\0sttrb\0ldurb\0ldtrb\0?\0ldtrsb\0?\0ldtrsb\0sturh\0sttrh\0ldurh\0ldtrh\0";
+        op=((ic32_27)&0x8)|((ic32_21)&0x6)|((ic32_11)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xbf80)==0x3900) {
+        names="strb\0ldrb\0strh\0ldrh\0";
+        op=((ic32_29)&0x2)|((ic32_22)&0x1); j=((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_j_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xbf80)==0x3980) {
+        names="ldrsb\0ldrsh\0";
+        op=((ic32_30)&0x1); s=((ic32_22)&0x1); j=((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_nRt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_j_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0x9fffcc)==0xef8c8) {
+        names="fcmgt\0fcmeq\0fcmlt\0?\0fcmge\0fcmle\0?\0fneg\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_simd0;
+    } else
+    if(((ic32_8)&0x9fbfcc)==0xea0c8) {
+        names="fcmgt\0fcmeq\0fcmlt\0?\0fcmge\0fcmle\0?\0fneg\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); q=((ic32_30)&0x1); z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_Vnzq; args[2]=disasm_arg_simd0;
+    } else
+    if(((ic32_8)&0x9f60c4)==0xe4004) {
+        names="fmaxnm\0fmla\0fadd\0fmulx\0fcmeq\0?\0fmax\0frecps\0fminnm\0fmls\0fsub\0?\0?\0?\0fmin\0frsqrts\0fmaxnmp\0?\0faddp\0fmul\0fcmge\0facge\0fmaxp\0fdiv\0fminnmp\0?\0fabd\0?\0fcmgt\0facgt\0fminp\0";
+        op=((ic32_25)&0x10)|((ic32_20)&0x8)|((ic32_11)&0x7); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0x9f7f8c)==0xe7988) {
+        names="frintn\0frintm\0fcvtns\0fcvtms\0fcvtas\0scvtf\0?\0fabs\0frintp\0frintz\0fcvtps\0fcvtzs\0?\0frecpe\0?\0frecpx\0?\0frintx\0fcvtnu\0fcvtmu\0fcvtau\0ucvtf\0?\0?\0frinta\0frinti\0fcvtpu\0fcvtzu\0?\0frsqrte\0?\0fsqrt\0";
+        op=((ic32_25)&0x10)|((ic32_20)&0x8)|((ic32_12)&0x7); q=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1;
+    } else
+    if(((ic32_8)&0x9f20fc)==0xe0094) {
+        names="sdot\0udot\0";
+        op=((ic32_29)&0x1); q=((ic32_30)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_Vnzq; args[2]=disasm_arg_Vmzq;
+    } else
+    if(((ic32_8)&0x9f3fbc)==0xe2028) {
+        names="saddlp\0sadalp\0uaddlp\0uadalp\0";
+        op=((ic32_28)&0x2)|((ic32_14)&0x1); q=((ic32_30)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtzq2; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0x9f3fcc)==0xe2088) {
+        names="cmgt\0cmeq\0cmlt\0abs\0cmge\0cmle\0?\0neg\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); q=((ic32_30)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_simd0;
+    } else
+    if(((ic32_8)&0x9f3f0c)==0xe2008) {
+        names="rev64\0rev16\0saddlp\0suqadd\0cls\0cnt\0sadalp\0sqabs\0cmgt\0cmeq\0cmlt\0abs\0?\0?\0?\0?\0rev32\0?\0uaddlp\0usqadd\0clz\0?\0uadalp\0sqneg\0cmge\0cmle\0?\0neg\0";
+        op=((ic32_25)&0x10)|((ic32_12)&0xf); q=((ic32_30)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0x9f3e8c)==0xe2088) {
+        names="?\0?\0?\0?\0?\0?\0?\0?\0frintn\0frintm\0fcvtns\0fcvtms\0fcvtas\0scvtf\0?\0fabs\0?\0?\0?\0?\0fcmgt\0fcmeq\0fcmlt\0?\0frintp\0frintz\0fcvtps\0fcvtzs\0urecpe\0frecpe\0?\0frecpx\0?\0?\0?\0?\0?\0?\0?\0?\0?\0frintx\0fcvtnu\0fcvtmu\0fcvtau\0ucvtf\0?\0?\0?\0?\0?\0?\0fcmge\0fcmle\0?\0fneg\0frinta\0frinti\0fcvtpu\0fcvtzu\0?\0frsqrte\0?\0fsqrt\0";
+        op=((ic32_24)&0x20)|((ic32_19)&0x10)|((ic32_13)&0x8)|((ic32_12)&0x7); q=((ic32_30)&0x1); z=((ic32_22)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_Vnzq;
+    } else
+    if(((ic32_8)&0x9f3ffc)==0xe3038) {
+        names="saddlv\0uaddlv\0";
+        op=((ic32_29)&0x1); q=((ic32_30)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz4t; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0x9f3eec)==0xe30a8) {
+        names="smaxv\0?\0sminv\0addv\0umaxv\0?\0uminv\0";
+        op=((ic32_27)&0x4)|((ic32_15)&0x2)|((ic32_12)&0x1); q=((ic32_30)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz3t; args[1]=disasm_arg_VnT;
+    } else
+    if(((ic32_8)&0x9f20fc)==0xe201c) {
+        names="and\0bic\0orr\0orn\0eor\0bsl\0bit\0bif\0";
+        op=((ic32_27)&0x4)|((ic32_22)&0x3); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0x9f20c4)==0xe20c4) {
+        names="fmaxnm\0fmla\0fadd\0?\0fcmeq\0?\0fmax\0frecps\0fminnm\0fmls\0fsub\0?\0?\0?\0fmin\0frsqrts\0fmaxnmp\0?\0faddp\0fmul\0fcmge\0facge\0fmaxp\0fdiv\0fminnmp\0?\0fabd\0?\0fcmgt\0facgt\0fminp\0";
+        op=((ic32_25)&0x10)|((ic32_20)&0x8)|((ic32_11)&0x7); q=((ic32_30)&0x1); z=((ic32_22)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_Vnzq; args[2]=disasm_arg_Vmzq;
+    } else
+    if(((ic32_8)&0x9f00c4)==0xe0084) {
+        names="?\0?\0sdot\0?\0?\0?\0?\0?\0add\0cmtst\0mla\0mul\0smaxp\0sminp\0sqdmulh\0addp\0sqrdmlah\0sqrdmlsh\0udot\0?\0?\0?\0?\0?\0sub\0cmeq\0mls\0pmul\0umaxp\0uminp\0cqrdmulh\0";
+        op=((ic32_25)&0x10)|((ic32_18)&0x8)|((ic32_11)&0x7); q=((ic32_30)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmT;
+    } else
+    if(((ic32_8)&0x9ff88c)==0xf0004) {
+        names="movi\0orr\0mvni\0bic\0";
+        op=((ic32_28)&0x2)|((ic32_12)&0x1); q=((ic32_30)&0x1); j=((ic32_11)&0xe0)|((ic32_5)&0x1f); k=((ic32_13)&0x3); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_imm8; args[2]=disasm_arg_amountk_opt;
+    } else
+    if(((ic32_8)&0x9ff8cc)==0xf0084) {
+        names="movi\0orr\0mvni\0bic\0";
+        op=((ic32_28)&0x2)|((ic32_12)&0x1); q=((ic32_30)&0x1); j=((ic32_11)&0xe0)|((ic32_5)&0x1f); k=((ic32_13)&0x1); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_imm8; args[2]=disasm_arg_amountk_opt;
+    } else
+    if(((ic32_8)&0x9ff8ec)==0xf00c4) {
+        names="movi\0mvni\0";
+        op=((ic32_29)&0x1); q=((ic32_30)&0x1); j=((ic32_11)&0xe0)|((ic32_5)&0x1f); k=((ic32_12)&0x1); t=((ic32)&0x1f);
+        z=2;
+        args[0]=disasm_arg_VtT; args[1]=disasm_arg_imm8; args[2]=disasm_arg_amountk2_opt;
+    } else
+    if(((ic32_8)&0x9fc034)==0xf0010) {
+        names="fmla\0fmls\0fmul\0?\0?\0?\0fmulx\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); j=((ic32_9)&0x4)|((ic32_20)&0x3); q=((ic32_30)&0x1); m=((ic32_16)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_VtH1; args[1]=disasm_arg_VnH1; args[2]=disasm_arg_VmHs;
+    } else
+    if(((ic32_8)&0x9f80cc)==0xf0044) {
+        names="?\0shl\0?\0sqshl\0sri\0sli\0sqshlu\0uqshl\0";
+        op=((ic32_27)&0x4)|((ic32_12)&0x3); q=((ic32_30)&0x1); j=((ic32_16)&0x7f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vtj2; args[1]=disasm_arg_Vnj2; args[2]=disasm_arg_shlshift;
+    } else
+    if(((ic32_8)&0x9fc0f4)==0xf80e0) {
+        names="sdot\0udot\0";
+        op=((ic32_29)&0x1); j=((ic32_10)&0x2)|((ic32_21)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_VnT; args[2]=disasm_arg_VmTs4b;
+    } else
+    if(((ic32_8)&0x9fc034)==0xf8010) {
+        names="fmla\0fmls\0fmul\0sqrdmulh\0?\0?\0fmulx\0sqrdmlah\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); j=((ic32_10)&0x2)|((ic32_21)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_Vnzq; args[2]=disasm_arg_VmTs2;
+    } else
+    if(((ic32_8)&0x9fe034)==0xfc010) {
+        names="fmla\0fmls\0fmul\0?\0?\0?\0fmulx\0";
+        op=((ic32_27)&0x4)|((ic32_14)&0x3); j=((ic32_11)&0x1); q=((ic32_30)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=1;
+        args[0]=disasm_arg_Vtzq; args[1]=disasm_arg_Vnzq; args[2]=disasm_arg_VmTs2;
+    } else
+    if(((ic32_8)&0xffe07c)==0x88007c) {
+        names="stxr\0stlxr\0";
+        op=((ic32_15)&0x1); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wd; args[1]=disasm_arg_Wt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_24)&0xff)==0x98) {
+        names="ldrsw\0";
+        i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_labeli4;
+    } else
+    if(((ic32_8)&0xff607c)==0x9b207c) {
+        names="smull\0smnegl\0umull\0umnegl\0";
+        op=((ic32_22)&0x2)|((ic32_15)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_Wn; args[2]=disasm_arg_Wm;
+    } else
+    if(((ic32_16)&0xff60)==0x9b20) {
+        names="smaddl\0smsubl\0umaddl\0umsubl\0";
+        op=((ic32_22)&0x2)|((ic32_15)&0x1); m=((ic32_16)&0x1f); d=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_Wn; args[2]=disasm_arg_Wm; args[3]=disasm_arg_Xd;
+    } else
+    if(((ic32_8)&0xff60fc)==0x9b407c) {
+        names="smulh\0umulh\0";
+        op=((ic32_23)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_Xn; args[2]=disasm_arg_Xm;
+    } else
+    if(((ic32_8)&0xffe00c)==0xb88004) {
+        names="ldrsw\0";
+        i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i_opt;
+    } else
+    if(((ic32_8)&0xffe004)==0xb88004) {
+        names="ldrsw\0";
+        i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); p=((ic32_11)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffe00c)==0xb8a008) {
+        names="ldrsw\0";
+        m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_Rom; args[4]=disasm_arg_amountj2; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xffc0)==0xb980) {
+        names="ldrsw\0";
+        j=((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_j_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffc080)==0xce0000) {
+        names="eor3\0bcax\0";
+        op=((ic32_21)&0x1); m=((ic32_16)&0x1f); d=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt16b; args[1]=disasm_arg_Vn16b; args[2]=disasm_arg_Vm16b; args[3]=disasm_arg_Vd16b;
+    } else
+    if(((ic32_8)&0xffe080)==0xce4000) {
+        names="sm3ss1\0";
+        m=((ic32_16)&0x1f); d=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s; args[2]=disasm_arg_Vm4s; args[3]=disasm_arg_Vd4s;
+    } else
+    if(((ic32_8)&0xffe0c0)==0xce4080) {
+        names="sm3tt1a\0sm3tt1b\0sm3tt2a\0sm3tt2b\0";
+        op=((ic32_10)&0x3); m=((ic32_16)&0x1f); j=((ic32_12)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        z=0;
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s; args[2]=disasm_arg_VmTs;
+    } else
+    if(((ic32_8)&0xffe0f8)==0xce6080) {
+        names="sha512h\0sha512h2\0";
+        op=((ic32_10)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Qt; args[1]=disasm_arg_Qn; args[2]=disasm_arg_Vm2d;
+    } else
+    if(((ic32_8)&0xffe0f8)==0xce6088) {
+        names="sha512su1\0rax1\0";
+        op=((ic32_10)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2d; args[1]=disasm_arg_Vn2d; args[2]=disasm_arg_Vm2d;
+    } else
+    if(((ic32_8)&0xffe0f0)==0xce60c0) {
+        names="sm3partw1\0sm3partw2\0sm4ekey\0";
+        op=((ic32_10)&0x3); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s; args[2]=disasm_arg_Vm4s;
+    } else
+    if(((ic32_8)&0xfffffc)==0xcec080) {
+        names="sha512su0\0";
+        n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt2d; args[1]=disasm_arg_Vn2d;
+    } else
+    if(((ic32_8)&0xfffffc)==0xcec084) {
+        names="sm4e\0";
+        n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt4s; args[1]=disasm_arg_Vn4s;
+    } else
+    if(((ic32_16)&0xffc0)==0xd400) {
+        names="?\0svc\0hvc\0smc\0brk\0";
+        op=((ic32_19)&0x4)|((ic32)&0x3); i=((ic32_20)&1?(0xffffffff<<16):0)|((ic32_5)&0xffff);
+        args[0]=disasm_arg_i;
+    } else
+    if((ic32&0xffe00003)==0xd4400000) {
+        names="hlt\0";
+    } else
+    if(((ic32_16)&0xffe0)==0xd4a0) {
+        names="?\0dcsp1\0dcps2\0dcps3\0";
+        op=((ic32)&0x3); i=((ic32_20)&1?(0xffffffff<<16):0)|((ic32_5)&0xffff);
+        args[0]=disasm_arg_i_opt;
+    } else
+    if((ic32&0xfffffd1f)==0xd503201f) {
+        names="nop\0yield\0wfe\0wfi\0sev\0sevl\0?\0?\0esb\0psc\0";
+        op=((ic32>>6)&0x8)|((ic32_5)&0x7);
+    } else
+    if((ic32&0xfffff0ff)==0xd503305f) {
+        names="clrex\0";
+        i=((ic32_11)&1?(0xffffffff<<4):0)|((ic32_8)&0xf);
+        args[0]=disasm_arg_i_opt;
+    } else
+    if((ic32&0xfffff09f)==0xd503309f) {
+        names="dsb\0dmb\0?\0isb\0";
+        op=((ic32_5)&0x3); j=((ic32_8)&0xf);
+        args[0]=disasm_arg_sh;
+    } else
+    if((ic32&0xfff8f01f)==0xd500401f) {
+        names="msr\0";
+        i=((ic32_11)&1?(0xffffffff<<4):0)|((ic32_8)&0xf); p=((ic32_5)&0x7);
+        args[0]=disasm_arg_pstate; args[1]=disasm_arg_i;
+    } else
+    if((ic32&0xffffff80)==0xd5087600) {
+        names="dc\0";
+        d=((ic32_5)&0x3); t=((ic32)&0x1f);
+        args[0]=disasm_arg_dc0; args[1]=disasm_arg_Xt;
+    } else
+    if((ic32&0xffffff80)==0xd5087800) {
+        names="at\0";
+        a=((ic32_5)&0x3); t=((ic32)&0x1f);
+        args[0]=disasm_arg_a0; args[1]=disasm_arg_Xt;
+    } else
+    if(((ic32_8)&0xffffff)==0xd50879) {
+        names="at\0";
+        a=((ic32_5)&0x7); t=((ic32)&0x1f);
+        args[0]=disasm_arg_a1; args[1]=disasm_arg_Xt;
+    } else
+    if((ic32&0xfffffbe0)==0xd5087a40) {
+        names="dc\0";
+        d=((ic32_10)&0x1); t=((ic32)&0x1f);
+        args[0]=disasm_arg_dc1; args[1]=disasm_arg_Xt;
+    } else
+    if((ic32&0xffffffe0)==0xd50b7420) {
+        names="dc\0";
+        t=((ic32)&0x1f);
+        args[0]=disasm_arg_ZVA; args[1]=disasm_arg_Xt;
+    } else
+    if((ic32&0xfffffae0)==0xd50b7a20) {
+        names="dc\0";
+        d=((ic32_9)&0x2)|((ic32_8)&0x1); t=((ic32)&0x1f);
+        args[0]=disasm_arg_dc2; args[1]=disasm_arg_Xt;
+    } else
+    if((ic32&0xfffcfbc0)==0xd5087100) {
+        names="ic\0";
+        c=((ic32_15)&0x2)|((ic32_10)&0x1); t=((ic32)&0x1f);
+        args[0]=disasm_arg_ic; args[1]=disasm_arg_Xt_opt;
+    } else
+    if((ic32&0xfffffb60)==0xd50c8020) {
+        names="tlbi\0";
+        n=((ic32_9)&0x2)|((ic32>>7)&0x1); t=((ic32)&0x1f);
+        args[0]=disasm_arg_tl1; args[1]=disasm_arg_Xt_opt;
+    } else
+    if((ic32&0xfffffb40)==0xd50e8300) {
+        names="tlbi\0";
+        n=((ic32_8)&0x4)|((ic32>>6)&0x2)|((ic32_5)&0x1); t=((ic32)&0x1f);
+        args[0]=disasm_arg_tl2; args[1]=disasm_arg_Xt_opt;
+    } else
+    if(((ic32_8)&0xfffdff)==0xd50c78) {
+        names="at\0";
+        a=((ic32_14)&0x8)|((ic32_5)&0x7); t=((ic32)&0x1f);
+        args[0]=disasm_arg_a2; args[1]=disasm_arg_Xt;
+    } else
+    if(((ic32_8)&0xfffbfb)==0xd50883) {
+        names="tlbi\0";
+        n=((ic32_14)&0x10)|((ic32>>7)&0x8)|((ic32_5)&0x7); t=((ic32)&0x1f);
+        args[0]=disasm_arg_tl0; args[1]=disasm_arg_Xt_opt;
+    } else
+    if(((ic32_16)&0xffe0)==0xd500) {
+        names="msr\0";
+        p=((ic32_19)&0x3); k=((ic32_16)&0x7); n=((ic32_12)&0xf); m=((ic32_8)&0xf); j=((ic32_5)&0x7); t=((ic32)&0x1f);
+        args[0]=disasm_arg_sysreg; args[1]=disasm_arg_Xt;
+    } else
+    if(((ic32_16)&0xfff8)==0xd528) {
+        names="sysl\0";
+        i=((ic32_18)&1?(0xffffffff<<3):0)|((ic32_16)&0x7); n=((ic32_12)&0xf); m=((ic32_8)&0xf); j=((ic32_5)&0x7); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_i; args[2]=disasm_arg_Cn; args[3]=disasm_arg_Cm; args[4]=disasm_arg_j;
+    } else
+    if(((ic32_16)&0xffe0)==0xd520) {
+        names="mrs\0";
+        p=((ic32_19)&0x3); k=((ic32_16)&0x7); n=((ic32_12)&0xf); m=((ic32_8)&0xf); j=((ic32_5)&0x7); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_sysreg;
+    } else
+    if((ic32&0xff9ffc1f)==0xd61f0000) {
+        names="br\0blr\0ret\0";
+        op=((ic32_21)&0x3); n=((ic32_5)&0x1f);
+        args[0]=disasm_arg_Xn;
+    } else
+    if((ic32&0xffdfffff)==0xd69f03e0) {
+        names="eret\0drps\0";
+        op=((ic32_21)&0x1);
+    } else
+    if(((ic32_24)&0xff)==0xd8) {
+        names="prfm\0";
+        i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_prf_op; args[1]=disasm_arg_labeli4;
+    } else
+    if(((ic32_8)&0xffe00c)==0xf88000) {
+        names="prfum\0";
+        i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_prf_op; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xffe00c)==0xf8a008) {
+        names="prfm\0";
+        m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_prf_op; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_Rom; args[4]=disasm_arg_amountj3; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xffc0)==0xf980) {
+        names="prfm\0";
+        j=((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_prf_op; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_j_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xbfe0)==0x8820) {
+        names="stxp\0stlxp\0";
+        op=((ic32_15)&0x1); s=((ic32_30)&0x1); d=((ic32_16)&0x1f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Wd; args[1]=disasm_arg_Rt; args[2]=disasm_arg_Rm; args[3]=disasm_arg_offs; args[4]=disasm_arg_XnS; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xbfff)==0x887f) {
+        names="ldxp\0ldaxp\0";
+        op=((ic32_15)&0x1); s=((ic32_30)&0x1); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa07c)==0x88207c) {
+        names="cas\0casl\0casa\0casal\0";
+        op=((ic32_21)&0x2)|((ic32_15)&0x1); s=((ic32_30)&0x1); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rd; args[1]=disasm_arg_Rt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbf3f7c)==0x881f7c) {
+        names="?\0?\0ldxr\0ldaxr\0stllr\0stlr\0ldlar\0ldar\0";
+        op=((ic32_21)&0x6)|((ic32_15)&0x1); s=((ic32_30)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa00c)==0xb80004) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); s=((ic32_30)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i_opt;
+    } else
+    if(((ic32_8)&0xbfa004)==0xb80000) {
+        names="stur\0sttr\0ldur\0ldtr\0";
+        op=((ic32_21)&0x2)|((ic32_11)&0x1); s=((ic32_30)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa004)==0xb80004) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); s=((ic32_30)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); p=((ic32_11)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbfa00c)==0xb82008) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); s=((ic32_30)&0x1); m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_Rom; args[4]=disasm_arg_amountjs; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0xbf200c)==0xb82000) {
+        names="ldadd\0ldclr\0ldeor\0ldset\0ldsmax\0ldsmin\0ldumax\0ldumin\0swp\0?\0?\0?\0?\0?\0?\0?\0ldaddl\0ldclrl\0ldeorl\0ldsetl\0ldsmaxl\0ldsminl\0ldumaxl\0lduminl\0swpl\0?\0?\0?\0?\0?\0?\0?\0ldadda\0ldclra\0ldeora\0ldseta\0ldsmaxa\0ldsmina\0ldumaxa\0ldumina\0swpa\0?\0?\0?\0?\0?\0?\0?\0ldaddal\0ldclral\0ldeoral\0ldsetal\0ldsmaxal\0ldsminal\0ldumaxal\0lduminal\0swpal\0";
+        op=((ic32_18)&0x30)|((ic32_12)&0xf); s=((ic32_30)&0x1); d=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rd; args[1]=disasm_arg_Rt; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0xbf80)==0xb900) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); s=((ic32_30)&0x1); j=((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_j_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0x7fa0)==0x1380) {
+        names="extr\0";
+        s=((ic32_31)&0x1); m=((ic32_16)&0x1f); i=((ic32_15)&1?(0xffffffff<<6):0)|((ic32_10)&0x3f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm; args[3]=disasm_arg_i;
+    } else
+    if(((ic32_24)&0x7c)==0x14) {
+        names="b\0bl\0";
+        op=((ic32_31)&0x1); i=((ic32_25)&1?(0xffffffff<<26):0)|((ic32)&0x3ffffff);
+        args[0]=disasm_arg_labeli4;
+    } else
+    if(((ic32_8)&0x7fe0fc)==0x1a0000) {
+        names="adc\0";
+        s=((ic32_31)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm;
+    } else
+    if(((ic32_8)&0x7fe080)==0x1ac000) {
+        names="?\0?\0udiv\0sdiv\0?\0?\0?\0?\0lslv\0lsrv\0asrv\0rorv\0?\0?\0?\0?\0crc32b\0crc32h\0crc32w\0crc32x\0crc32cb\0crc32ch\0crc32cw\0crc32cx\0";
+        op=((ic32_10)&0x1f); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm;
+    } else
+    if(((ic32_8)&0x7fe07c)==0x1b007c) {
+        names="mul\0mneg\0";
+        op=((ic32_15)&0x1); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm;
+    } else
+    if(((ic32_16)&0x7fe0)==0x1b00) {
+        names="madd\0msub\0";
+        op=((ic32_15)&0x1); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); d=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm; args[3]=disasm_arg_Rd;
+    } else
+    if(((ic32_8)&0x7ffffc)==0x1eae00) {
+        names="fmov\0";
+        s=((ic32_31)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Vn1d;
+    } else
+    if(((ic32_8)&0x7ffffc)==0x1eaf00) {
+        names="fmov\0";
+        s=((ic32_31)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Vt1d; args[1]=disasm_arg_Rn;
+    } else
+    if(((ic32_16)&0x7f3e)==0x1e02) {
+        names="scvtf\0ucvtf\0";
+        op=((ic32_16)&0x1); s=((ic32_31)&0x1); z=((ic32_22)&0x3); j=((ic32_10)&0x3f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_Rn; args[2]=disasm_arg_fbits;
+    } else
+    if(((ic32_16)&0x7f3e)==0x1e18) {
+        names="fcvtzs\0fcvtzu\0";
+        op=((ic32_16)&0x1); s=((ic32_31)&0x1); z=((ic32_22)&0x3); j=((ic32_10)&0x3f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_FPz5n; args[2]=disasm_arg_fbits;
+    } else
+    if(((ic32_8)&0x7f3afc)==0x1e2200) {
+        names="scvtf\0ucvtf\0fmov\0fmov\0";
+        op=((ic32>>17)&0x2)|((ic32_16)&0x1); s=((ic32_31)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPz5t; args[1]=disasm_arg_Rn;
+    } else
+    if(((ic32_8)&0x7f30fc)==0x1e2000) {
+        names="fcvtns\0fcvtnu\0scvtf\0ucvtf\0fcvtas\0fcvtau\0fmov\0fmov\0fcvtns\0fcvtnu\0";
+        op=((ic32_16)&0xf); s=((ic32_31)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_FPz5n;
+    } else
+    if(((ic32_8)&0x7f3efc)==0x1e3000) {
+        names="fcvtms\0fcvtmu\0";
+        op=((ic32_16)&0x1); s=((ic32_31)&0x1); z=((ic32_22)&0x3); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_FPz5n;
+    } else
+    if(((ic32_16)&0x7f80)==0x2880) {
+        names="stp\0ldp\0";
+        op=((ic32_22)&0x1); s=((ic32_31)&0x1); i=((ic32_21)&1?(0xffffffff<<7):0)|((ic32_15)&0x7f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_is4_opt;
+    } else
+    if(((ic32_24)&0x7e)==0x28) {
+        names="stnp\0ldnp\0stp\0ldp\0";
+        op=((ic32_23)&0x2)|((ic32_22)&0x1); s=((ic32_31)&0x1); p=((ic32_23)&0x1); i=((ic32_21)&1?(0xffffffff<<7):0)|((ic32_15)&0x7f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_is4_opt; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_24)&0x7e)==0x34) {
+        names="cbz\0cbnz\0";
+        op=((ic32_24)&0x1); s=((ic32_31)&0x1); i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_labeli4;
+    } else
+    if(((ic32_24)&0x7e)==0x36) {
+        names="tbz\0tbnz\0";
+        op=((ic32_24)&0x1); b=((ic32_26)&0x20)|((ic32_19)&0x1f); i=((ic32_18)&1?(0xffffffff<<14):0)|((ic32_5)&0x3fff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_b; args[2]=disasm_arg_labeli4;
+    } else
+    if(((ic32_8)&0x7fe004)==0x388000) {
+        names="?\0ldtrsb\0ldursw\0ldtrsw\0";
+        op=((ic32_30)&0x2)|((ic32_11)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if((ic32&0x7fe0ffe0)==0x5a0003e0) {
+        names="ngc\0";
+        s=((ic32_31)&0x1); m=((ic32_16)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rm;
+    } else
+    if(((ic32_8)&0x7ffff8)==0x5ac008) {
+        names="rev\0";
+        s=((ic32_31)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn;
+    } else
+    if(((ic32_8)&0x7fffe8)==0x5ac000) {
+        names="rbit\0rev16\0clz\0cls\0";
+        op=((ic32_11)&0x2)|((ic32_10)&0x1); s=((ic32_31)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn;
+    } else
+    if(((ic32_8)&0x3fe008)==0x1a8000) {
+        names="csel\0csinc\0csinv\0csneg\0";
+        op=((ic32_29)&0x2)|((ic32_10)&0x1); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); c=((ic32_12)&0xf); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm; args[3]=disasm_arg_c;
+    } else
+    if(((ic32_24)&0x3f)==0x1c) {
+        names="ldr\0";
+        z=((ic32_30)&0x3); i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_labeli4;
+    } else
+    if((ic32&0x3fe0001f)==0x2b20001f) {
+        names="cmn\0cmp\0";
+        op=((ic32_30)&0x1); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_10)&0x7); n=((ic32_5)&0x1f);
+        args[0]=disasm_arg_RnS; args[1]=disasm_arg_Rsom; args[2]=disasm_arg_exts;
+    } else
+    if(((ic32_16)&0x3f80)==0x2c80) {
+        names="stp\0ldp\0";
+        op=((ic32_22)&0x1); z=((ic32_30)&0x3); i=((ic32_21)&1?(0xffffffff<<7):0)|((ic32_15)&0x7f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_offe; args[5]=disasm_arg_iz4_opt;
+    } else
+    if(((ic32_24)&0x3e)==0x2c) {
+        names="stnp\0ldnp\0stp\0ldp\0";
+        op=((ic32_23)&0x2)|((ic32_22)&0x1); z=((ic32_30)&0x3); p=((ic32_23)&0x1); i=((ic32_21)&1?(0xffffffff<<7):0)|((ic32_15)&0x7f); m=((ic32_10)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPt; args[1]=disasm_arg_FPm; args[2]=disasm_arg_offs; args[3]=disasm_arg_XnS; args[4]=disasm_arg_iz4_opt; args[5]=disasm_arg_offe;
+    } else
+    if((ic32&0x3fe00c10)==0x3a400000) {
+        names="ccmn\0ccmp\0";
+        op=((ic32_30)&0x1); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); c=((ic32_12)&0xf); n=((ic32_5)&0x1f); j=((ic32)&0xf);
+        args[0]=disasm_arg_Rn; args[1]=disasm_arg_Rm; args[2]=disasm_arg_j; args[3]=disasm_arg_c;
+    } else
+    if((ic32&0x3fe00c10)==0x3a400800) {
+        names="ccmn\0ccmp\0";
+        op=((ic32_30)&0x1); s=((ic32_31)&0x1); b=((ic32_16)&0x1f); c=((ic32_12)&0xf); n=((ic32_5)&0x1f); j=((ic32)&0xf);
+        args[0]=disasm_arg_Rn; args[1]=disasm_arg_b; args[2]=disasm_arg_j; args[3]=disasm_arg_c;
+    } else
+    if(((ic32_8)&0x3f200c)==0x3c0000) {
+        names="stur\0ldur\0";
+        op=((ic32_22)&0x1); z=((ic32_30)&0x3); s=((ic32_23)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPst; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0x3f200c)==0x3c0004) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); z=((ic32_30)&0x3); s=((ic32_23)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPst; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_offe; args[4]=disasm_arg_i_opt;
+    } else
+    if(((ic32_8)&0x3f2004)==0x3c0004) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); z=((ic32_30)&0x3); s=((ic32_23)&0x1); i=((ic32_20)&1?(0xffffffff<<9):0)|((ic32_12)&0x1ff); p=((ic32_11)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPst; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_i_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_8)&0x3f200c)==0x3c2008) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); z=((ic32_30)&0x3); s=((ic32_23)&0x1); m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_12)&0x1); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPst; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_Rom; args[4]=disasm_arg_amountz; args[5]=disasm_arg_offe;
+    } else
+    if(((ic32_24)&0x3f)==0x3d) {
+        names="str\0ldr\0";
+        op=((ic32_22)&0x1); z=((ic32_30)&0x3); s=((ic32_23)&0x1); j=((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_FPst; args[1]=disasm_arg_offs; args[2]=disasm_arg_XnS; args[3]=disasm_arg_j_opt; args[4]=disasm_arg_offe;
+    } else
+    if(((ic32_16)&0x1fe0)==0xb20) {
+        names="add\0adds\0sub\0subs\0";
+        op=((ic32_29)&0x3); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); o=((ic32_13)&0x7); j=((ic32_10)&0x7); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_RtS; args[1]=disasm_arg_RnS; args[2]=disasm_arg_Rsom; args[3]=disasm_arg_exts;
+    } else
+    if(((ic32_24)&0x1e)==0xa) {
+        names="and\0bic\0add\0?\0orr\0orn\0adds\0?\0eor\0eon\0sub\0?\0ands\0bics\0subs\0";
+        op=((ic32_27)&0xc)|((ic32_23)&0x2)|((ic32_21)&0x1); s=((ic32_31)&0x1); z=((ic32_22)&0x3); m=((ic32_16)&0x1f); j=((ic32_10)&0x3f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm; args[3]=disasm_arg_shiftj_opt;
+    } else
+    if(((ic32_24)&0x1f)==0x10) {
+        names="adr\0adrp\0";
+        op=((ic32_31)&0x1); j=((ic32_29)&0x3); i=((ic32_23)&1?(0xffffffff<<19):0)|((ic32_5)&0x7ffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Xt; args[1]=disasm_arg_labelij1;
+    } else
+    if(((ic32_24)&0x1f)==0x11) {
+        names="add\0adds\0sub\0subs\0";
+        op=((ic32_29)&0x3); s=((ic32_31)&0x1); j=((ic32_22)&0x3); i=((ic32_21)&1?(0xffffffff<<12):0)|((ic32_10)&0xfff); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_RtS; args[1]=disasm_arg_RnS; args[2]=disasm_arg_i; args[3]=disasm_arg_j12_opt;
+    } else
+    if(((ic32_16)&0x1f80)==0x1200) {
+        names="and\0orr\0eor\0ands\0";
+        op=((ic32_29)&0x3); s=((ic32_31)&0x1); k=((ic32_22)&0x1); i=((ic32_21)&1?(0xffffffff<<6):0)|((ic32_16)&0x3f); j=((ic32_10)&0x3f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_RtS; args[1]=disasm_arg_Rn; args[2]=disasm_arg_ib;
+    } else
+    if(((ic32_16)&0x1f80)==0x1280) {
+        names="movn\0?\0movz\0movk\0";
+        op=((ic32_29)&0x3); s=((ic32_31)&0x1); j=((ic32_21)&0x3); i=((ic32_20)&1?(0xffffffff<<16):0)|((ic32_5)&0xffff); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_i; args[2]=disasm_arg_j16_opt;
+    } else
+    if(((ic32_16)&0x1f80)==0x1300) {
+        names="sbfm\0bfm\0ubfm\0";
+        op=((ic32_29)&0x3); s=((ic32_31)&0x1); i=((ic32_21)&1?(0xffffffff<<6):0)|((ic32_16)&0x3f); j=((ic32_10)&0x3f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_i; args[3]=disasm_arg_j;
+    } else
+    if(((ic32_8)&0x1fe0fc)==0x1a0000) {
+        names="adc\0adcs\0sbc\0sbcs\0";
+        op=((ic32_29)&0x3); s=((ic32_31)&0x1); m=((ic32_16)&0x1f); n=((ic32_5)&0x1f); t=((ic32)&0x1f);
+        args[0]=disasm_arg_Rt; args[1]=disasm_arg_Rn; args[2]=disasm_arg_Rm;
+    } else
+        names=NULL;
+    if(str!=NULL && names==NULL) {
+      sprintf(str,"0x%08x",ic32);
+    }
+
+    if(str!=NULL && names!=NULL) {
+        str+=sprintf(str,disasm_str(names,op),disasm_str(conds,c));
+        if(str-olds<10)om=10-(str-olds);else om=1;for(op=0;op<om;op++) *str++=' ';
+        for(op=0;op<sizeof(args) && args[op]!=disasm_arg_NONE;op++) {
+            if(op&&args[op-1]!=disasm_arg_offs&&args[op]!=disasm_arg_offe) { *str++=','; *str++=' '; }
+            switch(args[op]) {
+                case disasm_arg_Xt: str+=sprintf(str,t==31?"xzr":"x%d", t); break;
+                case disasm_arg_labelij1: str+=sprintf(str,"0x%x", (int)iaddr+(i<<2)+j); break;
+                case disasm_arg_RtS: str+=sprintf(str,t==31?"%csp":"%c%d", (s?'x':'w'), t); break;
+                case disasm_arg_RnS: str+=sprintf(str,n==31?"%csp":"%c%d", (s?'x':'w'), n); break;
+                case disasm_arg_i: str+=sprintf(str,"#0x%x", i); break;
+                case disasm_arg_j12_opt: str+=sprintf(str,!j?"":"lsl #%d", j*12); break;
+                case disasm_arg_Rn: str+=sprintf(str,n==31?"%czr":"%c%d", (s?'x':'w'), n); break;
+                case disasm_arg_ib: str+=sprintf(str,"#0x%lx", disasm_dbm(k,j,i)); break;
+                case disasm_arg_Rt: str+=sprintf(str,t==31?"%czr":"%c%d", (s?'x':'w'), t); break;
+                case disasm_arg_j16_opt: str+=sprintf(str,!j?"":"lsl #%d", j*16); break;
+                case disasm_arg_j: str+=sprintf(str,"#0x%x", j); break;
+                case disasm_arg_Rm: str+=sprintf(str,m==31?"%czr":"%c%d", (s?'x':'w'), m); break;
+                case disasm_arg_c: str+=sprintf(str,"%s", disasm_str(conds,c)); break;
+                case disasm_arg_labeli4: str+=sprintf(str,"0x%x", (int)iaddr+(i<<2)); break;
+                case disasm_arg_i_opt: str+=sprintf(str,!i?"":"#0x%x", i); break;
+                case disasm_arg_pstate: str+=sprintf(str,"%s", disasm_str(pstate,p)); break;
+                case disasm_arg_sh: str+=sprintf(str,"%s", disasm_str(share,j)); break;
+                case disasm_arg_a0: str+=sprintf(str,"%s", disasm_str(at_op0,a)); break;
+                case disasm_arg_a1: str+=sprintf(str,"%s", disasm_str(at_op1,a)); break;
+                case disasm_arg_a2: str+=sprintf(str,"%s", disasm_str(at_op2,a)); break;
+                case disasm_arg_dc0: str+=sprintf(str,"%s", disasm_str(dc_op0,d)); break;
+                case disasm_arg_dc1: str+=sprintf(str,"%s", disasm_str(dc_op1,d)); break;
+                case disasm_arg_ZVA: str+=sprintf(str,"ZVA"); break;
+                case disasm_arg_dc2: str+=sprintf(str,"%s", disasm_str(dc_op2,d)); break;
+                case disasm_arg_ic: str+=sprintf(str,"%s", disasm_str(ic_op,c)); break;
+                case disasm_arg_Xt_opt: str+=sprintf(str,t==31?"":"x%d", t); break;
+                case disasm_arg_tl0: str+=sprintf(str,"%s", disasm_str(tlbi_op0,n)); break;
+                case disasm_arg_tl1: str+=sprintf(str,"%s", disasm_str(tlbi_op1,n)); break;
+                case disasm_arg_tl2: str+=sprintf(str,"%s", disasm_str(tlbi_op2,n)); break;
+                case disasm_arg_sysreg: str+=sprintf(str,disasm_sysreg(p,k,n,m,j)?disasm_sysreg(p,k,n,m,j):"S%d_%d_%d_%d_%d", p,k,n,m,j); break;
+                case disasm_arg_Cn: str+=sprintf(str,"C%d", n); break;
+                case disasm_arg_Cm: str+=sprintf(str,"C%d", m); break;
+                case disasm_arg_Xn: str+=sprintf(str,n==31?"xzr":"x%d", n); break;
+                case disasm_arg_b: str+=sprintf(str,"#0x%x", b); break;
+                case disasm_arg_VtT: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,(z<<1)|q)); break;
+                case disasm_arg_Vt2T: str+=sprintf(str,"V%d.%s", (t+1)&0x1f, disasm_str(quantum,(z<<1)|q)); break;
+                case disasm_arg_Vt3T: str+=sprintf(str,"V%d.%s", (t+2)&0x1f, disasm_str(quantum,(z<<1)|q)); break;
+                case disasm_arg_Vt4T: str+=sprintf(str,"V%d.%s", (t+3)&0x1f, disasm_str(quantum,(z<<1)|q)); break;
+                case disasm_arg_offs: str+=sprintf(str,"["); break;
+                case disasm_arg_XnS: str+=sprintf(str,n==31?"xsp":"x%d", n); break;
+                case disasm_arg_offe: str+=sprintf(str,"]%s", p?"!":""); break;
+                case disasm_arg_Qi: str+=sprintf(str,"#%d", q?64:32); break;
+                case disasm_arg_Xm: str+=sprintf(str,m==31?"xzr":"x%d", m); break;
+                case disasm_arg_Qi3: str+=sprintf(str,"#%d", q?48:24); break;
+                case disasm_arg_Qi2: str+=sprintf(str,"#%d", q?32:16); break;
+                case disasm_arg_Qi1: str+=sprintf(str,"#%d", q?16:8); break;
+                case disasm_arg_VtB: str+=sprintf(str,"V%d.b[%d]", t, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_VtH: str+=sprintf(str,"V%d.h[%d]", t, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_VtS: str+=sprintf(str,"V%d.s[%d]", t, (q<<1)|s); break;
+                case disasm_arg_VtD: str+=sprintf(str,"V%d.d[%d]", t, q); break;
+                case disasm_arg_i1: str+=sprintf(str,"1"); break;
+                case disasm_arg_i2: str+=sprintf(str,"2"); break;
+                case disasm_arg_i4: str+=sprintf(str,"4"); break;
+                case disasm_arg_i8: str+=sprintf(str,"8"); break;
+                case disasm_arg_Vt3B: str+=sprintf(str,"V%d.b V%d.b V%d.b[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_Vt3H: str+=sprintf(str,"V%d.h V%d.h V%d.h[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_Vt3S: str+=sprintf(str,"V%d.s V%d.s V%d.s[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (q<<1)|s); break;
+                case disasm_arg_Vt3D: str+=sprintf(str,"V%d.d V%d.d V%d.d[%d]", t, (t+1)&0x1f, (t+2)&0x1f, q); break;
+                case disasm_arg_i3: str+=sprintf(str,"3"); break;
+                case disasm_arg_i6: str+=sprintf(str,"6"); break;
+                case disasm_arg_i12: str+=sprintf(str,"12"); break;
+                case disasm_arg_i24: str+=sprintf(str,"24"); break;
+                case disasm_arg_Vt2B: str+=sprintf(str,"V%d.b V%d.b[%d]", t, (t+1)&0x1f, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_Vt2H: str+=sprintf(str,"V%d.h V%d.h[%d]", t, (t+1)&0x1f, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_Vt2S: str+=sprintf(str,"V%d.s V%d.s[%d]", t, (t+1)&0x1f, (q<<1)|s); break;
+                case disasm_arg_Vt2D: str+=sprintf(str,"V%d.d V%d.d[%d]", t, (t+1)&0x1f, q); break;
+                case disasm_arg_i16: str+=sprintf(str,"16"); break;
+                case disasm_arg_Vt4B: str+=sprintf(str,"V%d.b V%d.b V%d.b V%d.b[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (t+3)&0x1f, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_Vt4H: str+=sprintf(str,"V%d.h V%d.h V%d.h V%d.h[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (t+3)&0x1f, (q<<3)|(s<<2)|z); break;
+                case disasm_arg_Vt4S: str+=sprintf(str,"V%d.s V%d.s V%d.s V%d.s[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (t+3)&0x1f, (q<<1)|s); break;
+                case disasm_arg_Vt4D: str+=sprintf(str,"V%d.d V%d.d V%d.d V%d.d[%d]", t, (t+1)&0x1f, (t+2)&0x1f, (t+3)&0x1f, q); break;
+                case disasm_arg_i32: str+=sprintf(str,"32"); break;
+                case disasm_arg_z: str+=sprintf(str,"#%d", 1<<z); break;
+                case disasm_arg_z3: str+=sprintf(str,"#%d", 3<<z); break;
+                case disasm_arg_z2: str+=sprintf(str,"#%d", 2<<z); break;
+                case disasm_arg_z4: str+=sprintf(str,"#%d", 4<<z); break;
+                case disasm_arg_Rd: str+=sprintf(str,d==31?"%czr":"%c%d", (s?'x':'w'), d); break;
+                case disasm_arg_Rd1: str+=sprintf(str,d+1==31?"%czr":"%c%d", (s?'x':'w'), (d+1)&0x1f); break;
+                case disasm_arg_Rt1: str+=sprintf(str,t+1==31?"%czr":"%c%d", (s?'x':'w'), (t+1)&0x1f); break;
+                case disasm_arg_Wd: str+=sprintf(str,d==31?"wzr":"w%d", d); break;
+                case disasm_arg_Wt: str+=sprintf(str,t==31?"wzr":"w%d", t); break;
+                case disasm_arg_FPt: str+=sprintf(str,"%c%d", z==2?'q':(z==1?'d':'s'), t); break;
+                case disasm_arg_prf_op: str+=sprintf(str,"%s L%d %s", disasm_str(prf_typ,(t>>3)&3), ((t>>1)&3)+1, disasm_str(prf_pol,t&1)); break;
+                case disasm_arg_is4_opt: str+=sprintf(str,!i?"":"#0x%x", i<<(2+s)); break;
+                case disasm_arg_FPm: str+=sprintf(str,"%c%d", z==2?'q':(z==1?'d':'s'), m); break;
+                case disasm_arg_iz4_opt: str+=sprintf(str,!i?"":"#0x%x", i<<(2+z)); break;
+                case disasm_arg_im4_opt: str+=sprintf(str,!i?"":"#0x%x", i<<2); break;
+                case disasm_arg_nRt: str+=sprintf(str,t==31?"%czr":"%c%d", (s?'w':'x'), t); break;
+                case disasm_arg_FPst: str+=sprintf(str,"%c%d", s==1?'q':(z==3?'d':(z==2?'s':(z==1?'h':'b'))), t); break;
+                case disasm_arg_j_opt: str+=sprintf(str,!j?"":"#0x%x", j); break;
+                case disasm_arg_Rom: str+=sprintf(str,m==31?"%czr":"%c%d", (o&1?'x':'w'), m); break;
+                case disasm_arg_amountj: str+=sprintf(str,"%s #%d", disasm_str(extend64,o), j); break;
+                case disasm_arg_amountz: str+=sprintf(str,"%s #%d", disasm_str(extend64,o), j?(s?4:z):0); break;
+                case disasm_arg_amountjs: str+=sprintf(str,"%s #%d", disasm_str(extend64,o), j?(s?3:2):0); break;
+                case disasm_arg_amountj2: str+=sprintf(str,"%s #%d", disasm_str(extend64,o), j?2:0); break;
+                case disasm_arg_amountj3: str+=sprintf(str,"%s #%d", disasm_str(extend64,o), j?3:0); break;
+                case disasm_arg_shiftj_opt: str+=sprintf(str, !j?"":"%s #%d", disasm_str(shift,z), j); break;
+                case disasm_arg_Rsom: str+=sprintf(str,m==31?"%czr":"%c%d", (s&&(o&3)==3?'x':'w'), m); break;
+                case disasm_arg_exts: str+=sprintf(str,"%s #%d", s?disasm_str(extend64,o):disasm_str(extend32,o), j); break;
+                case disasm_arg_Wn: str+=sprintf(str,n==31?"wzr":"w%d", n); break;
+                case disasm_arg_Wm: str+=sprintf(str,m==31?"wzr":"w%d", m); break;
+                case disasm_arg_Xd: str+=sprintf(str,d==31?"xzr":"x%d", d); break;
+                case disasm_arg_Vt16b: str+=sprintf(str,"V%d.16b", t); break;
+                case disasm_arg_Vn16b: str+=sprintf(str,"V%d.16b", n); break;
+                case disasm_arg_Qt: str+=sprintf(str,"q%d", t); break;
+                case disasm_arg_Sn: str+=sprintf(str,"s%d", n); break;
+                case disasm_arg_Vm4s: str+=sprintf(str,"V%d.4s", m); break;
+                case disasm_arg_Vt4s: str+=sprintf(str,"V%d.4s", t); break;
+                case disasm_arg_Vn4s: str+=sprintf(str,"V%d.4s", n); break;
+                case disasm_arg_Qn: str+=sprintf(str,"q%d", n); break;
+                case disasm_arg_St: str+=sprintf(str,"s%d", t); break;
+                case disasm_arg_FPjt: str+=sprintf(str,"%c%d", j&1?'b':((j&3)==2?'h':((j&7)==4?'s':'d')), t); break;
+                case disasm_arg_Vnj: str+=sprintf(str,"V%d.%c", n, j&1?'b':((j&3)==2?'h':((j&7)==4?'s':'d'))); break;
+                case disasm_arg_FPidx: str+=sprintf(str,"%d", j>>(j&1?1:((j&3)==2?2:((j&7)==4?3:4))), t); break;
+                case disasm_arg_Vtjq: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,(j&1?0:((j&3)==2?2:(j&7)==4?4:6))+q)); break;
+                case disasm_arg_Ht: str+=sprintf(str,"h%d", t); break;
+                case disasm_arg_Hn: str+=sprintf(str,"h%d", n); break;
+                case disasm_arg_Hm: str+=sprintf(str,"h%d", m); break;
+                case disasm_arg_FPn: str+=sprintf(str,"%c%d", z==2?'q':(z==1?'d':'s'), n); break;
+                case disasm_arg_VtH1: str+=sprintf(str,"V%d.%dh", t, q?8:4); break;
+                case disasm_arg_VnH1: str+=sprintf(str,"V%d.%dh", n, q?8:4); break;
+                case disasm_arg_VmH1: str+=sprintf(str,"V%d.%dh", m, q?8:4); break;
+                case disasm_arg_Vtzq: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,4+(z*2)+q)); break;
+                case disasm_arg_Vnzq: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,4+(z*2)+q)); break;
+                case disasm_arg_Vmzq: str+=sprintf(str,"V%d.%s", m, disasm_str(quantum,4+(z*2)+q)); break;
+                case disasm_arg_simd0: str+=sprintf(str,"#0.0"); break;
+                case disasm_arg_FPz2t: str+=sprintf(str,"%c%d", z==1?'h':'s', t); break;
+                case disasm_arg_FPz2n: str+=sprintf(str,"%c%d", z==1?'h':'s', n); break;
+                case disasm_arg_FPz2m: str+=sprintf(str,"%c%d", z==1?'h':'s', m); break;
+                case disasm_arg_VnT: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,(z<<1)|q)); break;
+                case disasm_arg_VmT: str+=sprintf(str,"V%d.%s", m, disasm_str(quantum,(z<<1)|q)); break;
+                case disasm_arg_FPz3t: str+=sprintf(str,"%c%d", z==3?'d':(z==2?'s':(z==1?'h':'b')), t); break;
+                case disasm_arg_FPz3n: str+=sprintf(str,"%c%d", z==3?'d':(z==2?'s':(z==1?'h':'b')), n); break;
+                case disasm_arg_FPz4n: str+=sprintf(str,"%c%d", z==2?'d':(z==1?'s':'h'), n); break;
+                case disasm_arg_VnT3: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,(z<<1)+3)); break;
+                case disasm_arg_Vn2d: str+=sprintf(str,"V%d.2d", n); break;
+                case disasm_arg_Vn2h: str+=sprintf(str,"V%d.2h", n); break;
+                case disasm_arg_Vnz: str+=sprintf(str,"V%d.2%c", n, z?'d':'s'); break;
+                case disasm_arg_FPz4t: str+=sprintf(str,"%c%d", z==2?'d':(z==1?'s':'h'), t); break;
+                case disasm_arg_Vtz: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,4+(z*2))); break;
+                case disasm_arg_FPz3m: str+=sprintf(str,"%c%d", z==3?'d':(z==2?'s':(z==1?'h':'b')), m); break;
+                case disasm_arg_Dt: str+=sprintf(str,"d%d", t); break;
+                case disasm_arg_Dn: str+=sprintf(str,"d%d", n); break;
+                case disasm_arg_shrshift: str+=sprintf(str,"#%d", ((j>>3)==1?16:((j>>4)==1?32:((j>>5)==1?64:128)))-j); break;
+                case disasm_arg_Vtj2: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,((j>>3)==1?0:((j>>4)==1?2:((j>>5)==1?4:6)))|q)); break;
+                case disasm_arg_Vnj2: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,((j>>3)==1?0:((j>>4)==1?2:((j>>5)==1?4:6)))|q)); break;
+                case disasm_arg_shlshift: str+=sprintf(str,"#%d", j-((j>>3)==1?8:((j>>4)==1?16:((j>>5)==1?32:64)))); break;
+                case disasm_arg_FPnj: str+=sprintf(str,"%c%d", (j>>3)==1?'h':((j>>4)==1?'s':'d'), n); break;
+                case disasm_arg_VnTa: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,((j>>3)==1?3:((j>>4)==1?4:7)))); break;
+                case disasm_arg_FPjt2: str+=sprintf(str,"%c%d", (j>>3)==1?'b':((j>>4)==1?'h':((j>>5)==1?'s':'d')), t); break;
+                case disasm_arg_FPjn2: str+=sprintf(str,"%c%d", (j>>3)==1?'b':((j>>4)==1?'h':((j>>5)==1?'s':'d')), n); break;
+                case disasm_arg_Vtz3: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,(z<<1)+6)); break;
+                case disasm_arg_VmTs: str+=sprintf(str,"V%d.%c[%d]", m, z==1?'h':'s', j); break;
+                case disasm_arg_VmHs: str+=sprintf(str,"V%d.h[%d]", m, j); break;
+                case disasm_arg_VmTs2: str+=sprintf(str,"V%d.%c[%d]", m, z==1?'d':'s', j); break;
+                case disasm_arg_Vn116b: str+=sprintf(str,"{ V%d.16b }", n); break;
+                case disasm_arg_Vn216b: str+=sprintf(str,"{ V%d.16b, V%d.16b }", n, (n+1)&0x1f); break;
+                case disasm_arg_Vn316b: str+=sprintf(str,"{ V%d.16b, V%d.16b, V%d.16b }", n, (n+1)&0x1f, (n+2)&0x1f); break;
+                case disasm_arg_Vn416b: str+=sprintf(str,"{ V%d.16b, V%d.16b, V%d.16b, V%d.16b }", n, (n+1)&0x1f, (n+2)&0x1f, (n+3)&0x1f); break;
+                case disasm_arg_Vtj: str+=sprintf(str,"V%d.%c", t, j&1?'b':((j&3)==2?'h':((j&7)==4?'s':'d'))); break;
+                case disasm_arg_R2n: str+=sprintf(str,n==31?"%czr":"%c%d", ((j&15)==8?'x':'w'), n); break;
+                case disasm_arg_FPidxk: str+=sprintf(str,"%d", k>>(k&1?1:((k&3)==2?2:((k&7)==4?3:4))), t); break;
+                case disasm_arg_Vtzq2: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,2+(z*2)+q)); break;
+                case disasm_arg_VnT2: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,z+3)); break;
+                case disasm_arg_Vnz3: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,(z<<1)+6)); break;
+                case disasm_arg_Vnzq2: str+=sprintf(str,"V%d.%s", n, disasm_str(quantum,2+(z*2)+q)); break;
+                case disasm_arg_shift8: str+=sprintf(str,"#%d", 1<<(z+3)); break;
+                case disasm_arg_VtT3: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,(z<<1)+3)); break;
+                case disasm_arg_VmT3: str+=sprintf(str,"V%d.%s", m, disasm_str(quantum,(z<<1)+3)); break;
+                case disasm_arg_VtT4: str+=sprintf(str,"V%d.%s", t, disasm_str(quantum,z?8:3)); break;
+                case disasm_arg_imm8: str+=sprintf(str,"#%x", j); break;
+                case disasm_arg_amountk_opt: str+=sprintf(str,!k?"":"lsl #%d", 1<<(k*3)); break;
+                case disasm_arg_amountk2_opt: str+=sprintf(str,!k?"":"msl #%d", 1<<(k*3)); break;
+                case disasm_arg_imm64: str+=sprintf(str,"#0x%02x%02x%02x%02x%02x%02x%02x%02x", j&128?255:0,j&64?255:0,j&32?255:0,j&16?255:0,j&8?255:0,j&4?255:0,j&2?255:0,j&1?255:0); break;
+                case disasm_arg_Vt2d: str+=sprintf(str,"V%d.2d", t); break;
+                case disasm_arg_F16: str+=sprintf(str,"#0x02x%02x", (j&128)|(j&64?0:64)|(j&64?32:0)|(j&64?16:0)|((j>>2)&0xF), (j&3)<<6); break;
+                case disasm_arg_F32: str+=sprintf(str,"#0x02x%02x0000", (j&128)|(j&64?0:64)|(j&64?32:0)|(j&64?16:0)|(j&64?8:0)|(j&64?4:0)|(j&64?2:0)|(j&32?1:0), (j&0x1f)<<3); break;
+                case disasm_arg_F64: str+=sprintf(str,"#0x02x%02x%06x", (j&128)|(j&64?0:64)|(j&64?32:0)|(j&64?16:0)|(j&64?8:0)|(j&64?4:0)|(j&64?2:0)|(j&64?1:0), (j&64?128:0)|(j&64?64:0)|(j&0x3f), 0); break;
+                case disasm_arg_VmTs4b: str+=sprintf(str,"V%d.4b[%d]", m, j); break;
+                case disasm_arg_Vm2d: str+=sprintf(str,"V%d.2d", m); break;
+                case disasm_arg_Vm16b: str+=sprintf(str,"V%d.16b", m); break;
+                case disasm_arg_Vd16b: str+=sprintf(str,"V%d.16b", d); break;
+                case disasm_arg_Vd4s: str+=sprintf(str,"V%d.4s", d); break;
+                case disasm_arg_FPz5t: str+=sprintf(str,"%c%d", z==1?'d':(z==0?'s':'h'), t); break;
+                case disasm_arg_fbits: str+=sprintf(str,"#%d", 64-j); break;
+                case disasm_arg_FPz5n: str+=sprintf(str,"%c%d", z==1?'d':(z==0?'s':'h'), n); break;
+                case disasm_arg_Vn1d: str+=sprintf(str,"V%d.1d[n]", n); break;
+                case disasm_arg_Vt1d: str+=sprintf(str,"V%d.1d[1]", t); break;
+                case disasm_arg_FPk5t: str+=sprintf(str,"%c%d", k==1?'d':(k==0?'s':'h'), t); break;
+                case disasm_arg_FPz5m: str+=sprintf(str,"%c%d", z==1?'d':(z==0?'s':'h'), m); break;
+                case disasm_arg_jz: str+=sprintf(str,z==3?"#0x02x%02x":(z==0?"#0x02x%02x0000":"#0x02x%02x%06x"), z==3?(j&128)|(j&64?0:64)|(j&64?32:0)|(j&64?16:0)|((j>>2)&0xF):(j&128)|(j&64?0:64)|(j&64?32:0)|(j&64?16:0)|(j&64?8:0)|(j&64?4:0)|(j&64?2:0)|(j&(z==0?32:64)?1:0),z==3?(j&3)<<6:(z==0?(j&0x1f)<<3:(j&64?128:0)|(j&64?64:0)|(j&0x3f)), 0); break;
+                case disasm_arg_FPz5d: str+=sprintf(str,"%c%d", z==1?'d':(z==0?'s':'h'), d); break;
+                default: break;
+            }
+            if(*(str-2)==',')str-=2;
+        }
+        *str=0;
+    }
+    return addr+4;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/jit/arm/codegen_arm.cpp b/jit/arm/codegen_arm.cpp
new file mode 100644
index 00000000..14944304
--- /dev/null
+++ b/jit/arm/codegen_arm.cpp
@@ -0,0 +1,1207 @@
+/*
+ * compiler/codegen_arm.cpp - ARM code generator
+ *
+ * Copyright (c) 2013 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ * Copyright (c) 2019 TomB
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ * This file is part of the ARAnyM project which builds a new and powerful
+ * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
+ *
+ * JIT compiler m68k -> ARM
+ *
+ * Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ * Adaptation for Basilisk II and improvements, copyright 2000-2004 Gwenole Beauchesne
+ * Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include "flags_arm.h"
+
+// Declare the built-in __clear_cache function.
+extern void __clear_cache (char*, char*);
+
+/*************************************************************************
+ * Some basic information about the the target CPU                       *
+ *************************************************************************/
+
+#define R0_INDEX 0
+#define R1_INDEX 1
+#define R2_INDEX 2
+#define R3_INDEX 3
+#define R4_INDEX 4
+#define R5_INDEX 5
+#define R6_INDEX 6
+#define R7_INDEX 7
+#define R8_INDEX  8
+#define R9_INDEX  9
+#define R10_INDEX 10
+#define R11_INDEX 11
+#define R12_INDEX 12
+#define R13_INDEX 13
+#define R14_INDEX 14
+#define R15_INDEX 15
+
+#define RSP_INDEX 13
+#define RLR_INDEX 14
+#define RPC_INDEX 15
+
+/* The register in which subroutines return an integer return value */
+#define REG_RESULT R0_INDEX
+
+/* The registers subroutines take their first and second argument in */
+#define REG_PAR1 R0_INDEX
+#define REG_PAR2 R1_INDEX
+
+#define REG_WORK1 R2_INDEX
+#define REG_WORK2 R3_INDEX
+#define REG_WORK3 R12_INDEX
+
+//#define REG_DATAPTR R10_INDEX
+
+#define REG_PC_TMP R1_INDEX /* Another register that is not the above */
+
+#define R_MEMSTART 10
+#define R_REGSTRUCT 11
+uae_s8 always_used[]={2,3,R_MEMSTART,R_REGSTRUCT,12,-1}; // r2, r3 and r12 are work register in emitted code
+
+uae_u8 call_saved[]={0,0,0,0, 1,1,1,1, 1,1,1,1, 0,1,1,1};
+
+/* This *should* be the same as call_saved. But:
+   - We might not really know which registers are saved, and which aren't,
+	 so we need to preserve some, but don't want to rely on everyone else
+	 also saving those registers
+   - Special registers (such like the stack pointer) should not be "preserved"
+	 by pushing, even though they are "saved" across function calls
+*/
+/* Without save and restore R12, we sometimes get seg faults when entering gui...
+   Don't understand why. */
+static const uae_u8 need_to_preserve[]={0,0,0,0, 1,1,1,1, 1,1,1,1, 1,0,0,0};
+static const uae_u32 PRESERVE_MASK = ((1<<R4_INDEX)|(1<<R5_INDEX)|(1<<R6_INDEX)|(1<<R7_INDEX)|(1<<R8_INDEX)|(1<<R9_INDEX)
+		|(1<<R10_INDEX)|(1<<R11_INDEX)|(1<<R12_INDEX));
+
+#include "codegen_arm.h"
+
+#define FIX_INVERTED_CARRY              \
+  if(flags_carry_inverted) {            \
+	  MRS_CPSR(REG_WORK1);                \
+	  EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);  \
+	  MSR_CPSRf_r(REG_WORK1);             \
+	flags_carry_inverted = false;       \
+  }
+
+
+STATIC_INLINE void SIGNED8_IMM_2_REG(W4 r, IM8 v) {
+	if (v & 0x80) {
+		MVN_ri8(r, (uae_u8) ~v);
+	} else {
+		MOV_ri8(r, (uae_u8) v);
+	}
+}
+
+STATIC_INLINE void UNSIGNED16_IMM_2_REG(W4 r, IM16 v) {
+#ifdef ARMV6T2
+  MOVW_ri16(r, v);
+#else
+	MOV_ri8(r, (uae_u8) v);
+	ORR_rri8RORi(r, r, (uae_u8)(v >> 8), 24);
+#endif
+}
+
+STATIC_INLINE void SIGNED16_IMM_2_REG(W4 r, IM16 v) {
+#ifdef ARMV6T2
+  MOVW_ri16(r, v);
+  SXTH_rr(r, r);
+#else
+  uae_s32 offs = data_long_offs((uae_s32)(uae_s16) v);
+  LDR_rRI(r, RPC_INDEX, offs);
+#endif
+}
+
+STATIC_INLINE void UNSIGNED8_REG_2_REG(W4 d, RR4 s) {
+	UXTB_rr(d, s);
+}
+
+STATIC_INLINE void SIGNED8_REG_2_REG(W4 d, RR4 s) {
+	SXTB_rr(d, s);
+}
+
+STATIC_INLINE void UNSIGNED16_REG_2_REG(W4 d, RR4 s) {
+	UXTH_rr(d, s);
+}
+
+STATIC_INLINE void SIGNED16_REG_2_REG(W4 d, RR4 s) {
+	SXTH_rr(d, s);
+}
+
+STATIC_INLINE void LOAD_U16(int r, uae_u32 val)
+{
+#ifdef ARMV6T2
+  MOVW_ri16(r, val);
+#else
+  uae_s32 offs = data_long_offs(val);
+  LDR_rRI(r, RPC_INDEX, offs);
+#endif
+}
+
+STATIC_INLINE void LOAD_U32(int r, uae_u32 val)
+{
+#ifdef ARMV6T2
+  MOVW_ri16(r, val);
+  if(val >> 16)
+	MOVT_ri16(r, val >> 16);
+#else
+  uae_s32 offs = data_long_offs(val);
+  LDR_rRI(r, RPC_INDEX, offs);
+#endif
+}
+
+STATIC_INLINE void raw_push_regs_to_preserve(void) {
+	PUSH_REGS(PRESERVE_MASK);
+}
+
+STATIC_INLINE void raw_pop_preserved_regs(void) {
+	POP_REGS(PRESERVE_MASK);
+}
+
+STATIC_INLINE void raw_flags_to_reg(int r)
+{
+  uintptr idx = (uintptr) &(regflags.nzcv) - (uintptr) &regs;
+	MRS_CPSR(r);
+	if(flags_carry_inverted) {
+	  EOR_rri(r, r, ARM_C_FLAG);
+	  MSR_CPSRf_r(r);
+	  flags_carry_inverted = false;
+	}
+	STR_rRI(r, R_REGSTRUCT, idx);
+
+  live.state[FLAGTMP].status = INMEM;
+  live.state[FLAGTMP].realreg = -1;
+  /* We just "evicted" FLAGTMP. */
+  live.nat[r].nholds = 0;
+}
+
+STATIC_INLINE void raw_reg_to_flags(int r)
+{
+	MSR_CPSRf_r(r);
+}
+
+
+//
+// compuemu_support used raw calls
+//
+LOWFUNC(WRITE,RMW,2,compemu_raw_inc_opcount,(IM16 op))
+{
+  uintptr idx = (uintptr) &(regs.raw_cputbl_count) - (uintptr) &regs;
+  LDR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+#ifdef ARMV6T2
+  MOVW_ri16(REG_WORK3, op);
+#else
+  uae_s32 offs = data_long_offs(op);
+  LDR_rRI(REG_WORK3, RPC_INDEX, offs);
+#endif
+  LDR_rRR_LSLi(REG_WORK1, REG_WORK2, REG_WORK3, 2);
+  ADD_rri(REG_WORK1, REG_WORK1, 1);
+  STR_rRR_LSLi(REG_WORK1, REG_WORK2, REG_WORK3, 2);
+}
+LENDFUNC(WRITE,RMW,1,compemu_raw_inc_opcount,(IM16 op))
+
+LOWFUNC(WRITE,READ,1,compemu_raw_cmp_pc,(IMPTR s))
+{
+  /* s is always >= NATMEM_OFFSET and < NATMEM_OFFSET + max. Amiga mem */
+  clobber_flags();
+
+  uintptr idx = (uintptr) &(regs.pc_p) - (uintptr) &regs;
+  LDR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+
+  LOAD_U32(REG_WORK2, s);
+	CMP_rr(REG_WORK1, REG_WORK2);
+}
+LENDFUNC(WRITE,READ,1,compemu_raw_cmp_pc,(IMPTR s))
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_set_pc_i,(IMPTR s))
+{
+  LOAD_U32(REG_WORK2, s);
+  uintptr idx = (uintptr) &(regs.pc_p) - (uintptr) &regs;
+  STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_set_pc_i,(IMPTR s))
+
+LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IM32 s))
+{
+  /* d points always to memory in regs struct */
+  LOAD_U32(REG_WORK2, s);
+  uintptr idx = d - (uintptr) &regs;
+  STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+}
+LENDFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IM32 s))
+
+LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(MEMW d, RR4 s))
+{
+  /* d points always to memory in regs struct */
+  uintptr idx = d - (uintptr) &regs;
+  STR_rRI(s, R_REGSTRUCT, idx);
+}
+LENDFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(MEMW d, RR4 s))
+
+LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IM32 s))
+{
+  LOAD_U32(d, s);
+}
+LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IM32 s))
+
+LOWFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s))
+{
+  if(s >= (uintptr) &regs && s < ((uintptr) &regs) + sizeof(struct regstruct)) {
+	uintptr idx = s - (uintptr) &regs;
+	LDR_rRI(d, R_REGSTRUCT, idx);
+  } else {
+	LOAD_U32(REG_WORK1, s);
+	  LDR_rR(d, REG_WORK1);
+  }
+}
+LENDFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s))
+
+LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s))
+{
+	MOV_rr(d, s);
+}
+LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s))
+
+LOWFUNC(WRITE,RMW,1,compemu_raw_dec_m,(MEMRW d))
+{
+  clobber_flags();
+
+  LOAD_U32(REG_WORK1, d);
+  LDR_rR(REG_WORK2, REG_WORK1);
+  SUBS_rri(REG_WORK2, REG_WORK2, 1);
+  STR_rR(REG_WORK2, REG_WORK1);
+}
+LENDFUNC(WRITE,RMW,1,compemu_raw_dec_m,(MEMRW ds))
+
+STATIC_INLINE void compemu_raw_call(uintptr t)
+{
+  LOAD_U32(REG_WORK1, t);
+
+	PUSH(RLR_INDEX);
+	BLX_r(REG_WORK1);
+	POP(RLR_INDEX);
+}
+
+STATIC_INLINE void compemu_raw_call_r(RR4 r)
+{
+	PUSH(RLR_INDEX);
+	BLX_r(r);
+	POP(RLR_INDEX);
+}
+
+STATIC_INLINE void compemu_raw_jcc_l_oponly(int cc)
+{
+  FIX_INVERTED_CARRY
+
+	switch (cc) {
+		case NATIVE_CC_HI: // HI
+			BEQ_i(0);										// beq no jump
+			BCC_i(0);										// bcc jump
+			break;
+
+		case NATIVE_CC_LS: // LS
+			BEQ_i(0);										// beq jump
+			BCC_i(0);										// bcc no jump
+			// jump
+			B_i(0);
+			// no jump
+			break;
+
+		case NATIVE_CC_F_OGT: // Jump if valid and greater than
+			BVS_i(0);		// do not jump if NaN
+			BGT_i(0);		// jump if greater than
+			break;
+
+		case NATIVE_CC_F_OGE: // Jump if valid and greater or equal
+			BVS_i(0);		// do not jump if NaN
+			BCS_i(0);		// jump if carry set
+			break;
+
+		case NATIVE_CC_F_OLT: // Jump if vaild and less than
+			BVS_i(0);		// do not jump if NaN
+			BCC_i(0);		// jump if carry cleared
+			break;
+
+		case NATIVE_CC_F_OLE: // Jump if valid and less or equal
+			BVS_i(0);		// do not jump if NaN
+			BLE_i(0);		// jump if less or equal
+			break;
+
+		case NATIVE_CC_F_OGL: // Jump if valid and greator or less
+			BVS_i(0);		// do not jump if NaN
+			BNE_i(0);		// jump if not equal
+			break;
+
+		case NATIVE_CC_F_OR: // Jump if valid
+			BVC_i(0);
+			break;
+
+		case NATIVE_CC_F_UN: // Jump if NAN
+			BVS_i(0);
+			break;
+
+		case NATIVE_CC_F_UEQ: // Jump if NAN or equal
+			BVS_i(0); 	// jump if NaN
+			BNE_i(0);		// do not jump if greater or less
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_UGT: // Jump if NAN or greater than
+			BVS_i(0); 	// jump if NaN
+			BLS_i(0);		// do not jump if lower or same
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_UGE: // Jump if NAN or greater or equal
+			BVS_i(0); 	// jump if NaN
+			BMI_i(0);		// do not jump if lower
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_ULT: // Jump if NAN or less than
+			BVS_i(0); 	// jump if NaN
+			BGE_i(0);		// do not jump if greater or equal
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_ULE: // Jump if NAN or less or equal
+			BVS_i(0); 	// jump if NaN
+			BGT_i(0);		// do not jump if greater
+			// jump
+			B_i(0);
+			break;
+
+		default:
+		CC_B_i(cc, 0);
+			break;
+	}
+  // emit of target into last branch will be done by caller
+}
+
+STATIC_INLINE void compemu_raw_handle_except(IM32 cycles)
+{
+	uae_u32* branchadd;
+
+  clobber_flags();
+
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  LDR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+	TST_rr(REG_WORK1, REG_WORK1);
+	branchadd = (uae_u32*)get_target();
+	BEQ_i(0);		// no exception, jump to next instruction
+
+  LOAD_U32(REG_PAR1, cycles);
+  uae_u32* branchadd2 = (uae_u32*)get_target();
+  B_i(0); // <exec_nostats>
+  write_jmp_target(branchadd2, (uintptr)popall_execute_exception);
+
+	// Write target of next instruction
+	write_jmp_target(branchadd, (uintptr)get_target());
+}
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_execute_normal,(MEMR s))
+{
+  LOAD_U32(REG_WORK1, s);
+  LDR_rR(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0); // <exec_nostats>
+  write_jmp_target(branchadd, (uintptr)popall_execute_normal_setpc);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_execute_normal,(MEMR s))
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_check_checksum,(MEMR s))
+{
+  LOAD_U32(REG_WORK1, s);
+  LDR_rR(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0); // <exec_nostats>
+  write_jmp_target(branchadd, (uintptr)popall_check_checksum_setpc);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_check_checksum,(MEMR s))
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_exec_nostats,(IMPTR s))
+{
+  LOAD_U32(REG_WORK1, s);
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0); // <exec_nostats>
+  write_jmp_target(branchadd, (uintptr)popall_exec_nostats_setpc);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_exec_nostats,(IMPTR s))
+
+STATIC_INLINE void compemu_raw_maybe_recompile(void)
+{
+  uae_u32* branchadd = (uae_u32*)get_target();
+  BLT_i(0);
+  write_jmp_target(branchadd, (uintptr)popall_recompile_block);
+}
+
+STATIC_INLINE void compemu_raw_jmp(uintptr t)
+{
+	if(t >= (uintptr)popallspace && t < (uintptr)(popallspace + POPALLSPACE_SIZE + MAX_JIT_CACHE * 1024)) {
+		uae_u32* loc = (uae_u32*)get_target();
+		B_i(0);
+		write_jmp_target(loc, t);
+	} else {
+	LDR_rRI(RPC_INDEX, RPC_INDEX, -4);
+	  emit_long(t);
+	}
+}
+
+STATIC_INLINE void compemu_raw_jmp_pc_tag(void)
+{
+  uintptr idx = (uintptr)&regs.pc_p - (uintptr)&regs;
+  LDRH_rRI(REG_WORK1, R_REGSTRUCT, idx);
+	idx = (uintptr)&regs.cache_tags - (uintptr)&regs;
+	LDR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+	LDR_rRR_LSLi(RPC_INDEX, REG_WORK2, REG_WORK1, 2);
+}
+
+STATIC_INLINE void compemu_raw_maybe_cachemiss(void)
+{
+  uae_u32* branchadd = (uae_u32*)get_target();
+  BNE_i(0);
+  write_jmp_target(branchadd, (uintptr)popall_cache_miss);
+}
+
+STATIC_INLINE void compemu_raw_maybe_do_nothing(IM32 cycles)
+{
+  clobber_flags();
+
+  uintptr idx = (uintptr)&regs.spcflags - (uintptr)&regs;
+  LDR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_s8 *branchadd = (uae_s8 *)get_target();
+  BEQ_i(0); // <end>
+
+  idx = (uintptr)&countdown - (uintptr) &regs;
+  LDR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+  if(CHECK32(cycles)) {
+	SUB_rri(REG_WORK2, REG_WORK2, cycles);
+  } else {
+	LOAD_U32(REG_WORK1, cycles);
+	  SUB_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  }
+  STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+
+  uae_u32* branchadd2 = (uae_u32*)get_target();
+  B_i(0);
+  write_jmp_target(branchadd2, (uintptr)popall_do_nothing);
+
+  // <end>
+  write_jmp_target((uae_u32*)branchadd, (uintptr)get_target());
+}
+
+STATIC_INLINE void compemu_raw_branch(IM32 d)
+{
+	B_i((d >> 2) - 1);
+}
+
+
+// Optimize access to struct regstruct with and memory with fixed registers
+
+LOWFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMPTR s))
+{
+  LOAD_U32(R_REGSTRUCT, s);
+	uintptr offsmem = (uintptr)&NATMEM_OFFSET - (uintptr) &regs;
+  LDR_rRI(R_MEMSTART, R_REGSTRUCT, offsmem);
+}
+LENDFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMPTR s))
+
+// Handle end of compiled block
+LOWFUNC(NONE,NONE,2,compemu_raw_endblock_pc_inreg,(RR4 rr_pc, IM32 cycles))
+{
+  clobber_flags();
+
+  // countdown -= scaled_cycles(totcycles);
+  uintptr offs = (uintptr)&countdown - (uintptr)&regs;
+	LDR_rRI(REG_WORK1, R_REGSTRUCT, offs);
+  if(CHECK32(cycles)) {
+	  SUBS_rri(REG_WORK1, REG_WORK1, cycles);
+	} else {
+	LOAD_U32(REG_WORK2, cycles);
+	SUBS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+  }
+	STR_rRI(REG_WORK1, R_REGSTRUCT, offs);
+
+  uae_u32* branchadd = (uae_u32*)get_target();
+	CC_B_i(NATIVE_CC_MI, 0);
+  write_jmp_target(branchadd, (uintptr)popall_do_nothing);
+#ifdef ARMV6T2
+	BFC_rii(rr_pc, 16, 31); // apply TAGMASK
+#else
+	BIC_rri(rr_pc, rr_pc, 0x00ff0000);
+	BIC_rri(rr_pc, rr_pc, 0xff000000);
+#endif
+	offs = (uintptr)(&regs.cache_tags) - (uintptr)&regs;
+	LDR_rRI(REG_WORK1, R_REGSTRUCT, offs);
+	LDR_rRR_LSLi(RPC_INDEX, REG_WORK1, rr_pc, 2);
+}
+LENDFUNC(NONE,NONE,2,compemu_raw_endblock_pc_inreg,(RR4 rr_pc, IM32 cycles))
+
+STATIC_INLINE uae_u32* compemu_raw_endblock_pc_isconst(IM32 cycles, IMPTR v)
+{
+  /* v is always >= NATMEM_OFFSET and < NATMEM_OFFSET + max. Amiga mem */
+	uae_u32* tba;
+  clobber_flags();
+
+  // countdown -= scaled_cycles(totcycles);
+  uintptr offs = (uintptr)&countdown - (uintptr)&regs;
+	LDR_rRI(REG_WORK1, R_REGSTRUCT, offs);
+  if(CHECK32(cycles)) {
+	  SUBS_rri(REG_WORK1, REG_WORK1, cycles);
+	} else {
+	LOAD_U32(REG_WORK2, cycles);
+	SUBS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+  }
+	STR_rRI(REG_WORK1, R_REGSTRUCT, offs);
+
+	tba = (uae_u32*)get_target();
+  CC_B_i(NATIVE_CC_MI^1, 0); // <target set by caller>
+
+  LDR_rRI(REG_WORK1, RPC_INDEX, 4); // <v>
+  offs = (uintptr)&regs.pc_p - (uintptr)&regs;
+  STR_rRI(REG_WORK1, R_REGSTRUCT, offs);
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0);
+  write_jmp_target(branchadd, (uintptr)popall_do_nothing);
+
+	emit_long(v);
+
+	return tba;
+}
+
+/*************************************************************************
+* FPU stuff                                                             *
+*************************************************************************/
+
+#ifdef USE_JIT_FPU
+
+LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
+{
+	VMOV64_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
+
+LOWFUNC(NONE,WRITE,2,compemu_raw_fmov_mr_drop,(MEMW mem, FR s))
+{
+  if(mem >= (uintptr) &regs && mem < (uintptr) &regs + 1020 && ((mem - (uintptr) &regs) & 0x3) == 0) {
+	VSTR64_dRi(s, R_REGSTRUCT, (mem - (uintptr) &regs));
+  } else {
+	LOAD_U32(REG_WORK3, mem);
+	if((mem & 0x3) == 0)
+	  VSTR64_dRi(s, REG_WORK3, 0);
+	else {
+	  VMOV64_rrd(REG_WORK1, REG_WORK2, s);
+#ifdef ALLOW_UNALIGNED_LDRD
+	  STRD_rRI(REG_WORK1, REG_WORK3, 0);
+#else
+          STR_rRI(REG_WORK1, REG_WORK3, 0);
+          STR_rRI(REG_WORK2, REG_WORK3, 4);
+#endif
+	}
+  }
+}
+LENDFUNC(NONE,WRITE,2,compemu_raw_fmov_mr_drop,(MEMW mem, FR s))
+
+LOWFUNC(NONE,READ,2,compemu_raw_fmov_rm,(FW d, MEMR mem))
+{
+  if(mem >= (uintptr) &regs && mem < (uintptr) &regs + 1020 && ((mem - (uintptr) &regs) & 0x3) == 0) {
+	VLDR64_dRi(d, R_REGSTRUCT, (mem - (uintptr) &regs));
+  } else {
+	LOAD_U32(REG_WORK3, mem);
+	if((mem & 0x3) == 0)
+	  VLDR64_dRi(d, REG_WORK3, 0);
+	else {
+#ifdef ALLOW_UNALIGNED_LDRD
+		LDRD_rRI(REG_WORK1, REG_WORK3, 0);
+#else
+                LDR_rRI(REG_WORK1, REG_WORK3, 0);
+                LDR_rRI(REG_WORK2, REG_WORK3, 4);
+#endif
+		VMOV64_drr(d, REG_WORK1, REG_WORK2);
+	}
+  }
+}
+LENDFUNC(NONE,READ,2,compemu_raw_fmov_rm,(FW d, MEMW mem))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_l_rr,(FW d, RR4 s))
+{
+  VMOVi_from_ARM_dr(SCRATCH_F64_1, s, 0);
+  VCVTIto64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_l_rr,(FW d, RR4 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_s_rr,(FW d, RR4 s))
+{
+  VMOV32_sr(SCRATCH_F32_1, s);
+  VCVT32to64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_s_rr,(FW d, RR4 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_w_rr,(FW d, RR2 s))
+{
+  SIGNED16_REG_2_REG(REG_WORK1, s);
+  VMOVi_from_ARM_dr(SCRATCH_F64_1, REG_WORK1, 0);
+  VCVTIto64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_w_rr,(FW d, RR2 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_b_rr,(FW d, RR1 s))
+{
+  SIGNED8_REG_2_REG(REG_WORK1, s);
+  VMOVi_from_ARM_dr(SCRATCH_F64_1, REG_WORK1, 0);
+  VCVTIto64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_b_rr,(FW d, RR1 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+{
+  VMOV64_drr(d, s1, s2);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_to_l_rr,(W4 d, FR s))
+{
+  VCVTR64toI_sd(SCRATCH_F32_1, s);
+  VMOV32_rs(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_to_l_rr,(W4 d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_to_s_rr,(W4 d, FR s))
+{
+  VCVT64to32_sd(SCRATCH_F32_1, s);
+  VMOV32_rs(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_to_s_rr,(W4 d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s, int targetIsReg))
+{
+  VCVTR64toI_sd(SCRATCH_F32_1, s);
+  VMOV32_rs(REG_WORK1, SCRATCH_F32_1);
+  if(targetIsReg) {
+		SSAT_rir(REG_WORK1, 15, REG_WORK1);
+	  PKHTB_rrr(d, d, REG_WORK1);
+  } else {
+		SSAT_rir(d, 15, REG_WORK1);
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s, int targetIsReg))
+
+LOWFUNC(NONE,NONE,3,raw_fmov_to_b_rr,(W4 d, FR s, int targetIsReg))
+{
+  VCVTR64toI_sd(SCRATCH_F32_1, s);
+  VMOV32_rs(REG_WORK1, SCRATCH_F32_1);
+  if(targetIsReg) {
+	  SSAT_rir(REG_WORK1, 7, REG_WORK1);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+  } else {
+	  SSAT_rir(d, 7, REG_WORK1);
+	}
+}
+LENDFUNC(NONE,NONE,3,raw_fmov_to_b_rr,(W4 d, FR s, int targetIsReg))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_0,(FW r))
+{
+	VMOV_I64_dimmI(r, 0x00);		// load imm #0 into reg
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_0,(FW r))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_1,(FW r))
+{
+  VMOV_F64_dimmF(r, 0x70); // load imm #1 into reg
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_1,(FW r))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_10,(FW r))
+{
+  VMOV_F64_dimmF(r, 0x24); // load imm #10 into reg
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_10,(FW r))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_100,(FW r))
+{
+  VMOV_F64_dimmF(r, 0x24); // load imm #10 into reg
+  VMUL64_ddd(r, r, r);
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_10,(FW r))
+
+LOWFUNC(NONE,READ,2,raw_fmov_d_rm,(FW r, MEMR m))
+{
+  LOAD_U32(REG_WORK3, m);
+  if((m & 0x3) == 0)
+	VLDR64_dRi(r, REG_WORK3, 0);
+  else {
+#ifdef ALLOW_UNALIGNED_LDRD
+	LDRD_rRI(REG_WORK1, REG_WORK3, 0);
+#else
+        LDR_rRI(REG_WORK1, REG_WORK3, 0);
+        LDR_rRI(REG_WORK2, REG_WORK3, 4);
+#endif
+	VMOV64_drr(r, REG_WORK1, REG_WORK2);
+  }
+}
+LENDFUNC(NONE,READ,2,raw_fmov_d_rm,(FW r, MEMR m))
+
+LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
+{
+  LOAD_U32(REG_WORK1, m);
+  VLDR32_sRi(SCRATCH_F32_1, REG_WORK1, 0);
+  VCVT32to64_ds(r, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
+
+LOWFUNC(NONE,NONE,3,raw_fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+{
+  VMOV64_rrd(d1, d2, s);
+}
+LENDFUNC(NONE,NONE,3,raw_fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+{
+	VSQRT64_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+{
+	VABS64_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+{
+	VNEG64_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+{
+	VDIV64_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+{
+	VADD64_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+{
+	VMUL64_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+{
+	VSUB64_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+{
+	VCVTR64toI_sd(SCRATCH_F32_1, s);
+	VCVTIto64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frndintz_rr,(FW d, FR s))
+{
+	VCVT64toI_sd(SCRATCH_F32_1, s);
+	VCVTIto64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_frndintz_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmod_rr,(FRW d, FR s))
+{
+	VDIV64_ddd(SCRATCH_F64_2, d, s);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_2);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_1);
+	VMUL64_ddd(SCRATCH_F64_1, SCRATCH_F64_2, s);
+	VSUB64_ddd(d, d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmod_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsgldiv_rr,(FRW d, FR s))
+{
+	VCVT64to32_sd(SCRATCH_F32_1, d);
+	VCVT64to32_sd(SCRATCH_F32_2, s);
+	VDIV32_sss(SCRATCH_F32_1, SCRATCH_F32_1, SCRATCH_F32_2);
+	VCVT32to64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fsgldiv_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,1,raw_fcuts_r,(FRW r))
+{
+	VCVT64to32_sd(SCRATCH_F32_1, r);
+	VCVT32to64_ds(r, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,1,raw_fcuts_r,(FRW r))
+
+LOWFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+{
+	VMRS_r(REG_WORK1);
+	BIC_rri(REG_WORK2, REG_WORK1, 0x00c00000);
+	VMSR_r(REG_WORK2);
+
+	VDIV64_ddd(SCRATCH_F64_2, d, s);
+	VCVTR64toI_sd(SCRATCH_F32_1, SCRATCH_F64_2);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_1);
+	VMUL64_ddd(SCRATCH_F64_1, SCRATCH_F64_2, s);
+	VSUB64_ddd(d, d, SCRATCH_F64_1);
+
+	VMRS_r(REG_WORK2);
+	UBFX_rrii(REG_WORK1, REG_WORK1, 22, 2);
+	BFI_rrii(REG_WORK2, REG_WORK1, 22, 23);
+	VMSR_r(REG_WORK2);
+}
+LENDFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsglmul_rr,(FRW d, FR s))
+{
+	VCVT64to32_sd(SCRATCH_F32_1, d);
+	VCVT64to32_sd(SCRATCH_F32_2, s);
+	VMUL32_sss(SCRATCH_F32_1, SCRATCH_F32_1, SCRATCH_F32_2);
+	VCVT32to64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fsglmul_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmovs_rr,(FW d, FR s))
+{
+	VCVT64to32_sd(SCRATCH_F32_1, s);
+	VCVT32to64_ds(d, SCRATCH_F32_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmovs_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,3,raw_ffunc_rr,(double (*func)(double), FW d, FR s))
+{
+	VMOV64_dd(0, s);
+
+  LOAD_U32(REG_WORK1, (uintptr)func);
+
+	PUSH(RLR_INDEX);
+	BLX_r(REG_WORK1);
+	POP(RLR_INDEX);
+
+	VMOV64_dd(d, 0);
+}
+LENDFUNC(NONE,NONE,3,raw_ffunc_rr,(double (*func)(double), FW d, FR s))
+
+LOWFUNC(NONE,NONE,3,raw_fpowx_rr,(uae_u32 x, FW d, FR s))
+{
+	double (*func)(double,double) = pow;
+
+	if(x == 2) {
+		VMOV_F64_dimmF(0, 0x00); // load imm #2 into first reg
+	} else {
+		VMOV_F64_dimmF(0, 0x24); // load imm #10 into first reg
+	}
+
+	VMOV64_dd(1, s);
+
+  LOAD_U32(REG_WORK1, (uintptr)func);
+
+	PUSH(RLR_INDEX);
+	BLX_r(REG_WORK1);
+	POP(RLR_INDEX);
+
+	VMOV64_dd(d, 0);
+}
+LENDFUNC(NONE,NONE,3,raw_fpowx_rr,(uae_u32 x, FW d, FR s))
+
+LOWFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
+{
+  VMOVi_to_ARM_rd(REG_WORK1, s, 1);    				// get high part of double
+  VCMP64_d0(s);
+  VMRS_CPSR();
+  uae_u32* branchadd_iszero = (uae_u32*)get_target();
+  BEQ_i(0);          // iszero
+
+  UBFX_rrii(REG_WORK2, REG_WORK1, 20, 11);  	// get exponent
+	MOVW_ri16(REG_WORK3, 2047);
+	CMP_rr(REG_WORK2, REG_WORK3);
+
+  uae_u32* branchadd_isnan = (uae_u32*)get_target();
+	BEQ_i(0); 				// isnan
+
+  MOVW_ri16(REG_WORK3, 15360);              	// diff of bias between double and long double
+  ADD_rrr(REG_WORK2, REG_WORK2, REG_WORK3); 	// exponent done
+  AND_rri(REG_WORK1, REG_WORK1, 0x80000000);        // extract sign
+  ORR_rrrLSLi(REG_WORK2, REG_WORK1, REG_WORK2, 16); // merge sign and exponent
+
+	ADD_rrr(REG_WORK3, adr, R_MEMSTART);
+
+  REV_rr(REG_WORK2, REG_WORK2);
+  STRH_rR(REG_WORK2, REG_WORK3);             	// write exponent
+
+  VSHL64_ddi(SCRATCH_F64_1, s, 11);           // shift mantissa to correct position
+  VREV64_8_dd(SCRATCH_F64_1, SCRATCH_F64_1);
+  VMOV64_rrd(REG_WORK1, REG_WORK2, SCRATCH_F64_1);
+  ORR_rri(REG_WORK1, REG_WORK1, 0x80);  			// insert explicit 1
+#ifdef ALLOW_UNALIGNED_LDRD
+  STRD_rRI(REG_WORK1, REG_WORK3, 4);
+#else
+  STR_rRI(REG_WORK1, REG_WORK3, 4);
+  STR_rRI(REG_WORK2, REG_WORK3, 8);
+#endif
+  uae_u32* branchadd_end = (uae_u32*)get_target();
+  B_i(0);            // end_of_op
+
+// isnan
+  write_jmp_target(branchadd_isnan, (uintptr)get_target());
+  MOVW_ri16(REG_WORK1, 0x7fff);
+  LSL_rri(REG_WORK1, REG_WORK1, 16);
+  MVN_ri(REG_WORK2, 0);
+
+// iszero
+  write_jmp_target(branchadd_iszero, (uintptr)get_target());
+  CC_AND_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, 0x80000000); // extract sign
+  CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	ADD_rrr(REG_WORK3, adr, R_MEMSTART);
+
+  REV_rr(REG_WORK1, REG_WORK1);
+#ifdef ALLOW_UNALIGNED_LDRD
+  STRD_rR(REG_WORK1, REG_WORK3);
+#else
+  STR_rR(REG_WORK1, REG_WORK3);
+  STR_rRI(REG_WORK2, REG_WORK3, 4);
+#endif
+  STR_rRI(REG_WORK2, REG_WORK3, 8);
+
+// end_of_op
+  write_jmp_target(branchadd_end, (uintptr)get_target());
+}
+LENDFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
+
+LOWFUNC(NONE,READ,2,raw_fp_to_exten_rm,(FW d, RR4 adr))
+{
+	ADD_rrr(REG_WORK3, adr, R_MEMSTART);
+
+#ifdef ALLOW_UNALIGNED_LDRD
+	LDRD_rRI(REG_WORK1, REG_WORK3, 4);
+#else
+	LDR_rRI(REG_WORK1, REG_WORK3, 4);
+	LDR_rRI(REG_WORK2, REG_WORK3, 8);
+#endif
+	BIC_rri(REG_WORK1, REG_WORK1, 0x80); 	// clear explicit 1
+	VMOV64_drr(d, REG_WORK1, REG_WORK2);
+  VREV64_8_dd(d, d);
+
+  LDRH_rR(REG_WORK1, REG_WORK3);
+  REV16_rr(REG_WORK1, REG_WORK1);				// exponent now in lower half
+
+	MOVW_ri16(REG_WORK2, 0x7fff);
+	ANDS_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+	uae_u32* branchadd_notzero = (uae_u32*)get_target();
+	BNE_i(0);				// not_zero
+	VCMP64_d0(d);
+	VMRS_CPSR();
+	uae_u32* branchadd_notzero2 = (uae_u32*)get_target();
+	BNE_i(0);				// not zero
+
+// zero
+	VMOV_I64_dimmI(d, 0x00);
+	TST_ri(REG_WORK1, 0x8000);								// check sign
+	uae_u32* branchadd_end = (uae_u32*)get_target();
+	BEQ_i(0);			// end_of_op
+	MOV_ri(REG_WORK1, 0x80000000);
+	MOV_ri(REG_WORK2, 0);
+	VMOV64_drr(d, REG_WORK2, REG_WORK1);
+	uae_u32* branchadd_end2 = (uae_u32*)get_target();
+	B_i(0);					// end_of_op
+
+// not_zero
+  write_jmp_target(branchadd_notzero, (uintptr)get_target());
+  write_jmp_target(branchadd_notzero2, (uintptr)get_target());
+	MOVW_ri16(REG_WORK3, 15360);              // diff of bias between double and long double
+	SUB_rrr(REG_WORK2, REG_WORK2, REG_WORK3);	// exponent done, ToDo: check for carry -> result gets Inf in double
+	UBFX_rrii(REG_WORK1, REG_WORK1, 15, 1);		// extract sign
+	BFI_rrii(REG_WORK2, REG_WORK1, 11, 11);		// insert sign
+	VSHR64_ddi(d, d, 11);											// shift mantissa to correct position
+	LSL_rri(REG_WORK2, REG_WORK2, 20);
+	VMOV_I64_dimmI(SCRATCH_F64_1, 0x00);
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, REG_WORK2, 1);
+	VORR_ddd(d, d, SCRATCH_F64_1);
+// end_of_op
+  write_jmp_target(branchadd_end, (uintptr)get_target());
+  write_jmp_target(branchadd_end2, (uintptr)get_target());
+}
+LENDFUNC(NONE,READ,2,raw_fp_to_exten_rm,(FW d, RR4 adr))
+
+LOWFUNC(NONE,WRITE,2,raw_fp_from_double_mr,(RR4 adr, FR s))
+{
+	ADD_rrr(REG_WORK3, adr, R_MEMSTART);
+	VREV64_8_dd(SCRATCH_F64_1, s);
+  VMOV64_rrd(REG_WORK1, REG_WORK2, SCRATCH_F64_1);
+#ifdef ALLOW_UNALIGNED_LDRD
+  STRD_rRI(REG_WORK1, REG_WORK3, 0);
+#else
+  STR_rRI(REG_WORK1, REG_WORK3, 0);
+  STR_rRI(REG_WORK2, REG_WORK3, 4);
+#endif
+}
+LENDFUNC(NONE,WRITE,2,raw_fp_from_double_mr,(RR4 adr, FR s))
+
+LOWFUNC(NONE,READ,2,raw_fp_to_double_rm,(FW d, RR4 adr))
+{
+	ADD_rrr(REG_WORK3, adr, R_MEMSTART);
+#ifdef ALLOW_UNALIGNED_LDRD
+	LDRD_rRI(REG_WORK1, REG_WORK3, 0);
+#else
+        LDR_rRI(REG_WORK1, REG_WORK3, 0);
+        LDR_rRI(REG_WORK2, REG_WORK3, 4);
+#endif
+	VMOV64_drr(d, REG_WORK1, REG_WORK2);
+  VREV64_8_dd(d, d);
+}
+LENDFUNC(NONE,READ,2,raw_fp_to_double_rm,(FW d, RR4 adr))
+
+STATIC_INLINE void raw_fflags_into_flags(int r)
+{
+	VCMP64_d0(r);
+	VMRS_CPSR();
+}
+
+LOWFUNC(NONE,NONE,2,raw_fp_fscc_ri,(RW4 d, int cc))
+{
+	switch (cc) {
+		case NATIVE_CC_F_NEVER:
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_NE: // Set if not equal
+			CC_BIC_rri(NATIVE_CC_EQ, d, d, 0xff); // do not set if equal
+			CC_ORR_rri(NATIVE_CC_NE, d, d, 0xff);
+			break;
+
+		case NATIVE_CC_EQ: // Set if equal
+			CC_BIC_rri(NATIVE_CC_NE, d, d, 0xff); // do not set if not equal
+			CC_ORR_rri(NATIVE_CC_EQ, d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_OGT: // Set if valid and greater than
+		BVS_i(2);		// do not set if NaN
+			BLE_i(1);		// do not set if less or equal
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_OGE: // Set if valid and greater or equal
+			BVS_i(2);		// do not set if NaN
+			BCC_i(1);		// do not set if carry cleared
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_OLT: // Set if vaild and less than
+			BVS_i(2);		// do not set if NaN
+			BCS_i(1);		// do not set if carry set
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_OLE: // Set if valid and less or equal
+			BVS_i(2);		// do not set if NaN
+			BGT_i(1);		// do not set if greater than
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_OGL: // Set if valid and greator or less
+			BVS_i(2);		// do not set if NaN
+			BEQ_i(1);		// do not set if equal
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_OR: // Set if valid
+			CC_BIC_rri(NATIVE_CC_VS, d, d, 0xff); // do not set if NaN
+			CC_ORR_rri(NATIVE_CC_VC, d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_UN: // Set if NAN
+			CC_BIC_rri(NATIVE_CC_VC, d, d, 0xff);	// do not set if valid
+			CC_ORR_rri(NATIVE_CC_VS, d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_UEQ: // Set if NAN or equal
+			BVS_i(0); 	// set if NaN
+			BNE_i(1);		// do not set if greater or less
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_UGT: // Set if NAN or greater than
+			BVS_i(0); 	// set if NaN
+			BLS_i(1);		// do not set if lower or same
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_UGE: // Set if NAN or greater or equal
+			BVS_i(0); 	// set if NaN
+			BMI_i(1);		// do not set if lower
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_ULT: // Set if NAN or less than
+			BVS_i(0); 	// set if NaN
+			BGE_i(1);		// do not set if greater or equal
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+
+		case NATIVE_CC_F_ULE: // Set if NAN or less or equal
+			BVS_i(0); 	// set if NaN
+			BGT_i(1);		// do not set if greater
+			ORR_rri(d, d, 0xff);
+			B_i(0);
+			BIC_rri(d, d, 0xff);
+			break;
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fp_fscc_ri,(RW4 d, int cc))
+
+#endif // USE_JIT_FPU
diff --git a/jit/arm/codegen_arm.h b/jit/arm/codegen_arm.h
new file mode 100644
index 00000000..b4e35883
--- /dev/null
+++ b/jit/arm/codegen_arm.h
@@ -0,0 +1,1511 @@
+/*
+ * compiler/codegen_arm.h - ARM code generator
+ *
+ * Copyright (c) 2013 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ * This file is part of the ARAnyM project which builds a new and powerful
+ * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
+ *
+ * JIT compiler m68k -> ARM
+ *
+ * Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ * This file is derived from CCG, copyright 1999-2003 Ian Piumarta
+ * Adaptation for Basilisk II and improvements, copyright 2000-2004 Gwenole Beauchesne
+ * Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef ARM_RTASM_H
+#define ARM_RTASM_H
+
+/* NOTES
+ *
+ */
+
+/* --- Configuration ------------------------------------------------------- */
+
+/* CPSR flags */
+
+#define ARM_N_FLAG        0x80000000
+#define ARM_Z_FLAG        0x40000000
+#define ARM_C_FLAG        0x20000000
+#define ARM_V_FLAG        0x10000000
+#define ARM_Q_FLAG        0x08000000
+#define ARM_CV_FLAGS        (ARM_C_FLAG|ARM_V_FLAG)
+
+#define ARM_GE3                0x00080000
+#define ARM_GE2                0x00040000
+#define ARM_GE1                0x00020000
+#define ARM_GE0                0x00010000
+
+/* --- Macros -------------------------------------------------------------- */
+
+/* ========================================================================= */
+/* --- UTILITY ------------------------------------------------------------- */
+/* ========================================================================= */
+
+#define _W(c) emit_long(c)
+#define _LS2_ADDR(a) (((a) & 0x01f0000f) | (((a) & 0xf0) << 4))
+
+/* ========================================================================= */
+/* --- ENCODINGS ----------------------------------------------------------- */
+/* ========================================================================= */
+
+#define IMM32(c) (((c) & 0xffffff00) == 0 ? c : \
+                  ((c) & 0x3fffffc0) == 0 ? (0x100 | (((c) >> 30) & 0x3) | (((c) << 2) & 0xfc)) : \
+                  ((c) & 0x0ffffff0) == 0 ? (0x200 | (((c) >> 28) & 0xf) | (((c) << 4) & 0xf0)) : \
+                  ((c) & 0x03fffffc) == 0 ? (0x300 | (((c) >> 26) & 0x3f) | (((c) << 6) & 0xc0) ) : \
+                  ((c) & 0x00ffffff) == 0 ? (0x400 | (((c) >> 24) & 0xff)) : \
+                  ((c) & 0xc03fffff) == 0 ? (0x500 | ((c) >> 22)) : \
+                  ((c) & 0xf00fffff) == 0 ? (0x600 | ((c) >> 20)) : \
+                  ((c) & 0xfc03ffff) == 0 ? (0x700 | ((c) >> 18)) : \
+                  ((c) & 0xff00ffff) == 0 ? (0x800 | ((c) >> 16)) : \
+                  ((c) & 0xffc03fff) == 0 ? (0x900 | ((c) >> 14)) : \
+                  ((c) & 0xfff00fff) == 0 ? (0xa00 | ((c) >> 12)) : \
+                  ((c) & 0xfffc03ff) == 0 ? (0xb00 | ((c) >> 10)) : \
+                  ((c) & 0xffff00ff) == 0 ? (0xc00 | ((c) >> 8)) : \
+                  ((c) & 0xffffc03f) == 0 ? (0xd00 | ((c) >> 6)) : \
+                  ((c) & 0xfffff00f) == 0 ? (0xe00 | ((c) >> 4)) : \
+                  ((c) & 0xfffffc03) == 0 ? (0xf00 | ((c) >> 2)) : \
+                        0\
+                 )
+
+#define CHECK32(c) (((c) & 0xffffff00) == 0 || \
+                  ((c) & 0x3fffffc0) == 0 || \
+                  ((c) & 0x0ffffff0) == 0 || \
+                  ((c) & 0x03fffffc) == 0 || \
+                  ((c) & 0x00ffffff) == 0 || \
+                  ((c) & 0xc03fffff) == 0 || \
+                  ((c) & 0xf00fffff) == 0 || \
+                  ((c) & 0xfc03ffff) == 0 || \
+                  ((c) & 0xff00ffff) == 0 || \
+                  ((c) & 0xffc03fff) == 0 || \
+                  ((c) & 0xfff00fff) == 0 || \
+                  ((c) & 0xfffc03ff) == 0 || \
+                  ((c) & 0xffff00ff) == 0 || \
+                  ((c) & 0xffffc03f) == 0 || \
+                  ((c) & 0xfffff00f) == 0 || \
+                  ((c) & 0xfffffc03) == 0)
+
+#define SHIFT_IMM(c) (0x02000000 | (IMM32((c))))
+
+#define UNSHIFTED_IMM8(c) (0x02000000 | (c))
+#define SHIFT_IMM8_ROR(c,r) (0x02000000 | (c) | (((r) >> 1) << 8))
+
+#define SHIFT_REG(Rm) (Rm)
+#define SHIFT_LSL_i(Rm,s) ((Rm) | ((s) << 7))
+#define SHIFT_LSL_r(Rm,Rs) ((Rm) | ((Rs) << 8) | 0x10)
+#define SHIFT_LSR_i(Rm,s) ((Rm) | ((s) << 7) | 0x20)
+#define SHIFT_LSR_r(Rm,Rs) ((Rm) | ((Rs) << 8) | 0x30)
+#define SHIFT_ASR_i(Rm,s) ((Rm) | ((s) << 7) | 0x40)
+#define SHIFT_ASR_r(Rm,Rs) ((Rm) | ((Rs) << 8) | 0x50)
+#define SHIFT_ROR_i(Rm,s) ((Rm) | ((s) << 7) | 0x60)
+#define SHIFT_ROR_r(Rm,Rs) ((Rm) | ((Rs) << 8) | 0x70)
+#define SHIFT_RRX(Rm) ((Rm) | 0x60)
+#define SHIFT_PK(Rm,s) ((Rm) | ((s) << 7))
+
+// Load/Store addressings
+#define ADR_ADD(v) ((1 << 23) | (v))
+#define ADR_SUB(v) (v)
+
+#define ADR_IMM(v) ((v) | (1 << 24))
+#define ADR_IMMPOST(v) (v)
+#define ADR_REG(Rm) ((1 << 25) | (1 << 24) | (Rm))
+#define ADR_REGPOST(Rm) ((1 << 25) | (Rm))
+
+#define ADD_IMM(i) ADR_ADD(ADR_IMM(i))
+#define SUB_IMM(i) ADR_SUB(ADR_IMM(i))
+
+#define ADD_REG(Rm)	ADR_ADD(ADR_REG(Rm))
+#define SUB_REG(Rm)	ADR_SUB(ADR_REG(Rm))
+
+#define ADD_LSL(Rm,i) ADR_ADD(ADR_REG(Rm) | ((i) << 7))
+#define SUB_LSL(Rm,i) ADR_SUB(ADR_REG(Rm) | ((i) << 7))
+
+#define ADD_LSR(Rm,i) ADR_ADD(ADR_REG(Rm) | (((i) & 0x1f) << 7) | (1 << 5))
+#define SUB_LSR(Rm,i) ADR_SUB(ADR_REG(Rm) | (((i) & 0x1f) << 7) | (1 << 5))
+
+#define ADD_ASR(Rm,i) ADR_ADD(ADR_REG(Rm) | (((i) & 0x1f) << 7) | (2 << 5))
+#define SUB_ASR(Rm,i) ADR_SUB(ADR_REG(Rm) | (((i) & 0x1f) << 7) | (2 << 5))
+
+#define ADD_ROR(Rm,i) ADR_ADD(ADR_REG(Rm) | (((i) & 0x1f) << 7) | (3 << 5))
+#define SUB_ROR(Rm,i) ADR_SUB(ADR_REG(Rm) | (((i) & 0x1f) << 7) | (3 << 5))
+
+#define ADD_RRX(Rm) ADR_ADD(ADR_REG(Rm) | (3 << 5))
+#define SUB_RRX(Rm) ADR_SUB(ADR_REG(Rm) | (3 << 5))
+
+#define ADD2_IMM(i) ADR_ADD((i) | (1 << 22))
+#define SUB2_IMM(i) ADR_SUB((i) | (1 << 22))
+
+#define ADD2_REG(Rm)	ADR_ADD(Rm)
+#define SUB2_REG(Rm)	ADR_SUB(Rm)
+
+// MOV, MVN
+#define _OP1(cc,op,s,Rd,shift) _W(((cc) << 28) | ((op) << 21) | ((s) << 20) | ((Rd) << 12) | (shift))
+
+// CMP, CMN, TST, TEQ
+#define _OP2(cc,op,Rn,shift) _W(((cc) << 28) | ((op) << 21) | (1 << 20) | ((Rn) << 16) | (shift))
+
+// ADD, SUB, RSB, ADC, SBC, RSC, AND, BIC, EOR, ORR
+#define _OP3(cc,op,s,Rd,Rn,shift) _W(((cc) << 28) | ((op) << 21) | ((s) << 20) | ((Rn) << 16) | ((Rd) << 12) | (shift))
+
+// LDR, STR
+#define _LS1(cc,l,b,Rd,Rn,a) _W(((cc) << 28) | (0x01 << 26) | ((l) << 20) | ((b) << 22) | ((Rn) << 16) | ((Rd) << 12) | (a))
+#define _LS2(cc,p,l,s,h,Rd,Rn,a) _W(((cc) << 28) | ((p) << 24) | ((l) << 20) | ((Rn) << 16) | ((Rd) << 12) | ((s) << 6) | ((h) << 5) | 0x90 | _LS2_ADDR((a)))
+
+/* ========================================================================= */
+/* --- OPCODES ------------------------------------------------------------- */
+/* ========================================================================= */
+
+/* Branch instructions */
+#ifndef __ANDROID__
+enum {
+	_B, _BL, _BLX, _BX, _BXJ
+};
+#endif
+
+/* Data processing instructions */
+enum {
+	_AND = 0,
+	_EOR,
+	_SUB,
+	_RSB,
+	_ADD,
+	_ADC,
+	_SBC,
+	_RSC,
+	_TST,
+	_TEQ,
+	_CMP,
+	_CMN,
+	_ORR,
+	_MOV,
+	_BIC,
+	_MVN
+};
+
+/* Single instruction Multiple Data (SIMD) instructions */
+
+/* Multiply instructions */
+
+/* Parallel instructions */
+
+/* Extend instructions */
+
+/* Miscellaneous arithmetic instrations */
+
+/* Status register transfer instructions */
+
+/* Load and Store instructions */
+
+/* Coprocessor instructions */
+
+/* Exception generation instructions */
+
+/* ========================================================================= */
+/* --- ASSEMBLER ----------------------------------------------------------- */
+/* ========================================================================= */
+
+#define	NOP()								_W(0xe1a00000)
+#define SETEND_BE()							_W(0xf1010200)
+#define SETEND_LE()							_W(0xf1010000)
+
+/* Data processing instructions */
+
+/* Opcodes Type 1 */
+// MOVcc rd,#i
+#define CC_MOV_ri8(cc,Rd,i)                 _OP1(cc,_MOV,0,Rd,UNSHIFTED_IMM8(i))
+// MOVcc Rd,#i ROR #s
+#define CC_MOV_ri8RORi(cc,Rd,i,s)           _OP1(cc,_MOV,0,Rd,SHIFT_IMM8_ROR(i,s))
+#define CC_MOV_ri(cc,Rd,i)                  _OP1(cc,_MOV,0,Rd,SHIFT_IMM(i))
+#define CC_MOV_rr(cc,Rd,Rm)                 _OP1(cc,_MOV,0,Rd,SHIFT_REG(Rm))
+#define CC_MOV_rrLSLi(cc,Rd,Rm,i)           _OP1(cc,_MOV,0,Rd,SHIFT_LSL_i(Rm,i))
+#define CC_MOV_rrLSLr(cc,Rd,Rm,Rs)          _OP1(cc,_MOV,0,Rd,SHIFT_LSL_r(Rm,Rs))
+#define CC_MOV_rrLSRi(cc,Rd,Rm,i)           _OP1(cc,_MOV,0,Rd,SHIFT_LSR_i(Rm,i))
+#define CC_MOV_rrLSRr(cc,Rd,Rm,Rs)          _OP1(cc,_MOV,0,Rd,SHIFT_LSR_r(Rm,Rs))
+#define CC_MOV_rrASRi(cc,Rd,Rm,i)           _OP1(cc,_MOV,0,Rd,SHIFT_ASR_i(Rm,i))
+#define CC_MOV_rrASRr(cc,Rd,Rm,Rs)          _OP1(cc,_MOV,0,Rd,SHIFT_ASR_r(Rm,Rs))
+#define CC_MOV_rrRORi(cc,Rd,Rm,i)           _OP1(cc,_MOV,0,Rd,SHIFT_ROR_i(Rm,i))
+#define CC_MOV_rrRORr(cc,Rd,Rm,Rs)          _OP1(cc,_MOV,0,Rd,SHIFT_ROR_r(Rm,Rs))
+#define CC_MOV_rrRRX(cc,Rd,Rm)              _OP1(cc,_MOV,0,Rd,SHIFT_RRX(Rm))
+
+// MOV rd,#i
+#define MOV_ri8(Rd,i)                       CC_MOV_ri8(NATIVE_CC_AL,Rd,i)
+// MOV Rd,#i ROR #s
+#define MOV_ri8RORi(Rd,i,s)                 CC_MOV_ri8RORi(NATIVE_CC_AL,Rd,i,s)
+#define MOV_ri(Rd,i)                        CC_MOV_ri(NATIVE_CC_AL,Rd,i)
+#define MOV_rr(Rd,Rm)                       CC_MOV_rr(NATIVE_CC_AL,Rd,Rm)
+#define MOV_rrLSLi(Rd,Rm,i)                 CC_MOV_rrLSLi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOV_rrLSLr(Rd,Rm,Rs)                CC_MOV_rrLSLr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOV_rrLSRi(Rd,Rm,i)                 CC_MOV_rrLSRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOV_rrLSRr(Rd,Rm,Rs)                CC_MOV_rrLSRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOV_rrASRi(Rd,Rm,i)                 CC_MOV_rrASRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOV_rrASRr(Rd,Rm,Rs)                CC_MOV_rrASRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOV_rrRORi(Rd,Rm,i)                 CC_MOV_rrRORi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOV_rrRORr(Rd,Rm,Rs)                CC_MOV_rrRORr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOV_rrRRX(Rd,Rm)                    CC_MOV_rrRRX(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_MOVS_ri(cc,Rd,i)                 _OP1(cc,_MOV,1,Rd,SHIFT_IMM(i))
+#define CC_MOVS_rr(cc,Rd,Rm)                _OP1(cc,_MOV,1,Rd,SHIFT_REG(Rm))
+#define CC_MOVS_rrLSLi(cc,Rd,Rm,i)          _OP1(cc,_MOV,1,Rd,SHIFT_LSL_i(Rm,i))
+#define CC_MOVS_rrLSLr(cc,Rd,Rm,Rs)         _OP1(cc,_MOV,1,Rd,SHIFT_LSL_r(Rm,Rs))
+#define CC_MOVS_rrLSRi(cc,Rd,Rm,i)          _OP1(cc,_MOV,1,Rd,SHIFT_LSR_i(Rm,i))
+#define CC_MOVS_rrLSRr(cc,Rd,Rm,Rs)         _OP1(cc,_MOV,1,Rd,SHIFT_LSR_r(Rm,Rs))
+#define CC_MOVS_rrASRi(cc,Rd,Rm,i)          _OP1(cc,_MOV,1,Rd,SHIFT_ASR_i(Rm,i))
+#define CC_MOVS_rrASRr(cc,Rd,Rm,Rs)         _OP1(cc,_MOV,1,Rd,SHIFT_ASR_r(Rm,Rs))
+#define CC_MOVS_rrRORi(cc,Rd,Rm,i)          _OP1(cc,_MOV,1,Rd,SHIFT_ROR_i(Rm,i))
+#define CC_MOVS_rrRORr(cc,Rd,Rm,Rs)         _OP1(cc,_MOV,1,Rd,SHIFT_ROR_r(Rm,Rs))
+#define CC_MOVS_rrRRX(cc,Rd,Rm)             _OP1(cc,_MOV,1,Rd,SHIFT_RRX(Rm))
+
+#define MOVS_ri(Rd,i)                       CC_MOVS_ri(NATIVE_CC_AL,Rd,i)
+#define MOVS_rr(Rd,Rm)                      CC_MOVS_rr(NATIVE_CC_AL,Rd,Rm)
+#define MOVS_rrLSLi(Rd,Rm,i)                CC_MOVS_rrLSLi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOVS_rrLSLr(Rd,Rm,Rs)               CC_MOVS_rrLSLr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOVS_rrLSRi(Rd,Rm,i)                CC_MOVS_rrLSRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOVS_rrLSRr(Rd,Rm,Rs)               CC_MOVS_rrLSRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOVS_rrASRi(Rd,Rm,i)                CC_MOVS_rrASRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOVS_rrASRr(Rd,Rm,Rs)               CC_MOVS_rrASRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOVS_rrRORi(Rd,Rm,i)                CC_MOVS_rrRORi(NATIVE_CC_AL,Rd,Rm,i)
+#define MOVS_rrRORr(Rd,Rm,Rs)               CC_MOVS_rrRORr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MOVS_rrRRX(Rd,Rm)                   CC_MOVS_rrRRX(NATIVE_CC_AL,Rd,Rm)
+
+// MVNcc rd,#i
+#define CC_MVN_ri8(cc,Rd,i)                 _OP1(cc,_MVN,0,Rd,UNSHIFTED_IMM8(i))
+// MVNcc Rd,#i ROR #s
+#define CC_MVN_ri8RORi(cc,Rd,i,s)           _OP1(cc,_MVN,0,Rd,SHIFT_IMM8_ROR(i,s))
+#define CC_MVN_ri(cc,Rd,i)              	_OP1(cc,_MVN,0,Rd,SHIFT_IMM(i))
+#define CC_MVN_rr(cc,Rd,Rm)             	_OP1(cc,_MVN,0,Rd,SHIFT_REG(Rm))
+#define CC_MVN_rrLSLi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,0,Rd,SHIFT_LSL_i(Rm,i))
+#define CC_MVN_rrLSLr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,0,Rd,SHIFT_LSL_r(Rm,Rs))
+#define CC_MVN_rrLSRi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,0,Rd,SHIFT_LSR_i(Rm,i))
+#define CC_MVN_rrLSRr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,0,Rd,SHIFT_LSR_r(Rm,Rs))
+#define CC_MVN_rrASRi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,0,Rd,SHIFT_ASR_i(Rm,i))
+#define CC_MVN_rrASRr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,0,Rd,SHIFT_ASR_r(Rm,Rs))
+#define CC_MVN_rrRORi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,0,Rd,SHIFT_ROR_i(Rm,i))
+#define CC_MVN_rrRORr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,0,Rd,SHIFT_ROR_r(Rm,Rs))
+#define CC_MVN_rrRRX(cc,Rd,Rm)           	_OP1(cc,_MVN,0,Rd,SHIFT_RRX(Rm))
+
+// MVN rd,#i
+#define MVN_ri8(Rd,i)                       CC_MVN_ri8(NATIVE_CC_AL,Rd,i)
+// MVN Rd,#i ROR #s
+#define MVN_ri8RORi(Rd,i,s)                 CC_MVN_ri8RORi(NATIVE_CC_AL,Rd,i,s)
+#define MVN_ri(Rd,i)                        CC_MVN_ri(NATIVE_CC_AL,Rd,i)
+#define MVN_rr(Rd,Rm)                       CC_MVN_rr(NATIVE_CC_AL,Rd,Rm)
+#define MVN_rrLSLi(Rd,Rm,i)                 CC_MVN_rrLSLi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVN_rrLSLr(Rd,Rm,Rs)                CC_MVN_rrLSLr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVN_rrLSRi(Rd,Rm,i)                 CC_MVN_rrLSRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVN_rrLSRr(Rd,Rm,Rs)                CC_MVN_rrLSRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVN_rrASRi(Rd,Rm,i)                 CC_MVN_rrASRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVN_rrASRr(Rd,Rm,Rs)                CC_MVN_rrASRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVN_rrRORi(Rd,Rm,i)                 CC_MVN_rrRORi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVN_rrRORr(Rd,Rm,Rs)                CC_MVN_rrRORr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVN_rrRRX(Rd,Rm)                    CC_MVN_rrRRX(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_MVNS_ri(cc,Rd,i)              	_OP1(cc,_MVN,1,Rd,SHIFT_IMM(i))
+#define CC_MVNS_rr(cc,Rd,Rm)             	_OP1(cc,_MVN,1,Rd,SHIFT_REG(Rm))
+#define CC_MVNS_rrLSLi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,1,Rd,SHIFT_LSL_i(Rm,i))
+#define CC_MVNS_rrLSLr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,1,Rd,SHIFT_LSL_r(Rm,Rs))
+#define CC_MVNS_rrLSRi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,1,Rd,SHIFT_LSR_i(Rm,i))
+#define CC_MVNS_rrLSRr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,1,Rd,SHIFT_LSR_r(Rm,Rs))
+#define CC_MVNS_rrASRi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,1,Rd,SHIFT_ASR_i(Rm,i))
+#define CC_MVNS_rrASRr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,1,Rd,SHIFT_ASR_r(Rm,Rs))
+#define CC_MVNS_rrRORi(cc,Rd,Rm,i)       	_OP1(cc,_MVN,1,Rd,SHIFT_ROR_i(Rm,i))
+#define CC_MVNS_rrRORr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,1,Rd,SHIFT_ROR_r(Rm,Rs))
+#define CC_MVNS_rrRRX(cc,Rd,Rm)           	_OP1(cc,_MVN,1,Rd,SHIFT_RRX(Rm))
+
+#define MVNS_ri(Rd,i)                       CC_MVNS_ri(NATIVE_CC_AL,Rd,i)
+#define MVNS_rr(Rd,Rm)                      CC_MVNS_rr(NATIVE_CC_AL,Rd,Rm)
+#define MVNS_rrLSLi(Rd,Rm,i)                CC_MVNS_rrLSLi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVNS_rrLSLr(Rd,Rm,Rs)               CC_MVNS_rrLSLr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVNS_rrLSRi(Rd,Rm,i)                CC_MVNS_rrLSRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVNS_rrLSRr(Rd,Rm,Rs)               CC_MVNS_rrLSRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVNS_rrASRi(Rd,Rm,i)                CC_MVNS_rrASRi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVNS_rrASRr(Rd,Rm,Rs)               CC_MVNS_rrASRr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVNS_rrRORi(Rd,Rm,i)                CC_MVNS_rrRORi(NATIVE_CC_AL,Rd,Rm,i)
+#define MVNS_rrRORr(Rd,Rm,Rs)               CC_MVNS_rrRORr(NATIVE_CC_AL,Rd,Rm,Rs)
+#define MVNS_rrRRX(Rd,Rm)                   CC_MVNS_rrRRX(NATIVE_CC_AL,Rd,Rm)
+
+/* Opcodes Type 2 */
+#define CC_CMP_ri(cc,Rn,i)                	_OP2(cc,_CMP,Rn,SHIFT_IMM(i))
+#define CC_CMP_rr(cc,Rn,Rm)                	_OP2(cc,_CMP,Rn,SHIFT_REG(Rm))
+#define CC_CMP_rrLSLi(cc,Rn,Rm,i)        	_OP2(cc,_CMP,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_CMP_rrLSLr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMP,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_CMP_rrLSRi(cc,Rn,Rm,i)        	_OP2(cc,_CMP,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_CMP_rrLSRr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMP,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_CMP_rrASRi(cc,Rn,Rm,i)        	_OP2(cc,_CMP,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_CMP_rrASRr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMP,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_CMP_rrRORi(cc,Rn,Rm,i)        	_OP2(cc,_CMP,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_CMP_rrRORr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMP,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_CMP_rrRRX(cc,Rn,Rm)              _OP2(cc,_CMP,Rn,SHIFT_RRX(Rm))
+
+#define CMP_ri(Rn,i)                        CC_CMP_ri(NATIVE_CC_AL,Rn,i)
+#define CMP_rr(Rn,Rm)                        CC_CMP_rr(NATIVE_CC_AL,Rn,Rm)
+#define CMP_rrLSLi(Rn,Rm,i)                	CC_CMP_rrLSLi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMP_rrLSLr(Rn,Rm,Rs)                CC_CMP_rrLSLr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMP_rrLSRi(Rn,Rm,i)                	CC_CMP_rrLSRi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMP_rrLSRr(Rn,Rm,Rs)                CC_CMP_rrLSRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMP_rrASRi(Rn,Rm,i)                	CC_CMP_rrASRi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMP_rrASRr(Rn,Rm,Rs)                CC_CMP_rrASRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMP_rrRORi(Rn,Rm,i)                	CC_CMP_rrRORi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMP_rrRORr(Rn,Rm,Rs)                CC_CMP_rrRORr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMP_rrRRX(Rn,Rm)                	CC_CMP_rrRRX(NATIVE_CC_AL,Rn,Rm)
+
+#define CC_CMN_ri(cc,Rn,i)                	_OP2(cc,_CMN,Rn,SHIFT_IMM(i))
+#define CC_CMN_rr(cc,Rn,r)                	_OP2(cc,_CMN,Rn,SHIFT_REG(r))
+#define CC_CMN_rrLSLi(cc,Rn,Rm,i)        	_OP2(cc,_CMN,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_CMN_rrLSLr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMN,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_CMN_rrLSRi(cc,Rn,Rm,i)        	_OP2(cc,_CMN,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_CMN_rrLSRr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMN,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_CMN_rrASRi(cc,Rn,Rm,i)        	_OP2(cc,_CMN,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_CMN_rrASRr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMN,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_CMN_rrRORi(cc,Rn,Rm,i)        	_OP2(cc,_CMN,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_CMN_rrRORr(cc,Rn,Rm,Rs)        	_OP2(cc,_CMN,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_CMN_rrRRX(cc,Rn,Rm)              _OP2(cc,_CMN,Rn,SHIFT_RRX(Rm))
+
+#define CMN_ri(Rn,i)                    	CC_CMN_ri(NATIVE_CC_AL,Rn,i)
+#define CMN_rr(Rn,r)                    	CC_CMN_rr(NATIVE_CC_AL,Rn,r)
+#define CMN_rrLSLi(Rn,Rm,i)             	CC_CMN_rrLSLi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMN_rrLSLr(Rn,Rm,Rs)            	CC_CMN_rrLSLr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMN_rrLSRi(Rn,Rm,i)             	CC_CMN_rrLSRi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMN_rrLSRr(Rn,Rm,Rs)            	CC_CMN_rrLSRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMN_rrASRi(Rn,Rm,i)             	CC_CMN_rrASRi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMN_rrASRr(Rn,Rm,Rs)            	CC_CMN_rrASRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMN_rrRORi(Rn,Rm,i)             	CC_CMN_rrRORi(NATIVE_CC_AL,Rn,Rm,i)
+#define CMN_rrRORr(Rn,Rm,Rs)            	CC_CMN_rrRORr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define CMN_rrRRX(Rn,Rm)                	CC_CMN_rrRRX(NATIVE_CC_AL,Rn,Rm)
+
+#define CC_TST_ri(cc,Rn,i)              	_OP2(cc,_TST,Rn,SHIFT_IMM(i))
+#define CC_TST_rr(cc,Rn,r)              	_OP2(cc,_TST,Rn,SHIFT_REG(r))
+#define CC_TST_rrLSLi(cc,Rn,Rm,i)       	_OP2(cc,_TST,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_TST_rrLSLr(cc,Rn,Rm,Rs)      	_OP2(cc,_TST,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_TST_rrLSRi(cc,Rn,Rm,i)       	_OP2(cc,_TST,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_TST_rrLSRr(cc,Rn,Rm,Rs)      	_OP2(cc,_TST,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_TST_rrASRi(cc,Rn,Rm,i)       	_OP2(cc,_TST,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_TST_rrASRr(cc,Rn,Rm,Rs)      	_OP2(cc,_TST,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_TST_rrRORi(cc,Rn,Rm,i)       	_OP2(cc,_TST,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_TST_rrRORr(cc,Rn,Rm,Rs)      	_OP2(cc,_TST,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_TST_rrRRX(cc,Rn,Rm)          	_OP2(cc,_TST,Rn,SHIFT_RRX(Rm))
+
+#define TST_ri(Rn,i)                    	CC_TST_ri(NATIVE_CC_AL,Rn,i)
+#define TST_rr(Rn,r)                    	CC_TST_rr(NATIVE_CC_AL,Rn,r)
+#define TST_rrLSLi(Rn,Rm,i)             	CC_TST_rrLSLi(NATIVE_CC_AL,Rn,Rm,i)
+#define TST_rrLSLr(Rn,Rm,Rs)            	CC_TST_rrLSLr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TST_rrLSRi(Rn,Rm,i)             	CC_TST_rrLSRi(NATIVE_CC_AL,Rn,Rm,i)
+#define TST_rrLSRr(Rn,Rm,Rs)            	CC_TST_rrLSRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TST_rrASRi(Rn,Rm,i)             	CC_TST_rrASRi(NATIVE_CC_AL,Rn,Rm,i)
+#define TST_rrASRr(Rn,Rm,Rs)            	CC_TST_rrASRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TST_rrRORi(Rn,Rm,i)             	CC_TST_rrRORi(NATIVE_CC_AL,Rn,Rm,i)
+#define TST_rrRORr(Rn,Rm,Rs)            	CC_TST_rrRORr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TST_rrRRX(Rn,Rm)                	CC_TST_rrRRX(NATIVE_CC_AL,Rn,Rm)
+
+#define CC_TEQ_ri(cc,Rn,i)              	_OP2(cc,_TEQ,Rn,SHIFT_IMM(i))
+#define CC_TEQ_rr(cc,Rn,r)              	_OP2(cc,_TEQ,Rn,SHIFT_REG(r))
+#define CC_TEQ_rrLSLi(cc,Rn,Rm,i)       	_OP2(cc,_TEQ,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_TEQ_rrLSLr(cc,Rn,Rm,Rs)      	_OP2(cc,_TEQ,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_TEQ_rrLSRi(cc,Rn,Rm,i)       	_OP2(cc,_TEQ,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_TEQ_rrLSRr(cc,Rn,Rm,Rs)      	_OP2(cc,_TEQ,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_TEQ_rrASRi(cc,Rn,Rm,i)       	_OP2(cc,_TEQ,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_TEQ_rrASRr(cc,Rn,Rm,Rs)      	_OP2(cc,_TEQ,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_TEQ_rrRORi(cc,Rn,Rm,i)       	_OP2(cc,_TEQ,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_TEQ_rrRORr(cc,Rn,Rm,Rs)      	_OP2(cc,_TEQ,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_TEQ_rrRRX(cc,Rn,Rm)          	_OP2(cc,_TEQ,Rn,SHIFT_RRX(Rm))
+
+#define TEQ_ri(Rn,i)                    	CC_TEQ_ri(NATIVE_CC_AL,Rn,i)
+#define TEQ_rr(Rn,r)                    	CC_TEQ_rr(NATIVE_CC_AL,Rn,r)
+#define TEQ_rrLSLi(Rn,Rm,i)            		CC_TEQ_rrLSLi(NATIVE_CC_AL,Rn,Rm,i)
+#define TEQ_rrLSLr(Rn,Rm,Rs)           	 	CC_TEQ_rrLSLr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TEQ_rrLSRi(Rn,Rm,i)             	CC_TEQ_rrLSRi(NATIVE_CC_AL,Rn,Rm,i)
+#define TEQ_rrLSRr(Rn,Rm,Rs)            	CC_TEQ_rrLSRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TEQ_rrASRi(Rn,Rm,i)             	CC_TEQ_rrASRi(NATIVE_CC_AL,Rn,Rm,i)
+#define TEQ_rrASRr(Rn,Rm,Rs)            	CC_TEQ_rrASRr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TEQ_rrRORi(Rn,Rm,i)             	CC_TEQ_rrRORi(NATIVE_CC_AL,Rn,Rm,i)
+#define TEQ_rrRORr(Rn,Rm,Rs)            	CC_TEQ_rrRORr(NATIVE_CC_AL,Rn,Rm,Rs)
+#define TEQ_rrRRX(Rn,Rm)                	CC_TEQ_rrRRX(NATIVE_CC_AL,Rn,Rm)
+
+/* Opcodes Type 3 */
+#define CC_AND_rri(cc,Rd,Rn,i)              _OP3(cc,_AND,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_AND_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_AND,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_AND_rrrLSLi(cc,Rd,Rn,Rm,i)       _OP3(cc,_AND,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_AND_rrrLSLr(cc,Rd,Rn,Rm,Rs)      _OP3(cc,_AND,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_AND_rrrLSRi(cc,Rd,Rn,Rm,i)       _OP3(cc,_AND,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_AND_rrrLSRr(cc,Rd,Rn,Rm,Rs)      _OP3(cc,_AND,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_AND_rrrASRi(cc,Rd,Rn,Rm,i)       _OP3(cc,_AND,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_AND_rrrASRr(cc,Rd,Rn,Rm,Rs)      _OP3(cc,_AND,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_AND_rrrRORi(cc,Rd,Rn,Rm,i)       _OP3(cc,_AND,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_AND_rrrRORr(cc,Rd,Rn,Rm,Rs)      _OP3(cc,_AND,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_AND_rrrRRX(cc,Rd,Rn,Rm)         _OP3(cc,_AND,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define AND_rri(Rd,Rn,i)                 	CC_AND_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define AND_rrr(Rd,Rn,Rm)                 	CC_AND_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define AND_rrrLSLi(Rd,Rn,Rm,i)         	CC_AND_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define AND_rrrLSLr(Rd,Rn,Rm,Rs)         	CC_AND_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define AND_rrrLSRi(Rd,Rn,Rm,i)         	CC_AND_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define AND_rrrLSRr(Rd,Rn,Rm,Rs)         	CC_AND_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define AND_rrrASRi(Rd,Rn,Rm,i)         	CC_AND_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define AND_rrrASRr(Rd,Rn,Rm,Rs)         	CC_AND_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define AND_rrrRORi(Rd,Rn,Rm,i)         	CC_AND_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define AND_rrrRORr(Rd,Rn,Rm,Rs)         	CC_AND_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define AND_rrrRRX(Rd,Rn,Rm)                CC_AND_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_ANDS_rri(cc,Rd,Rn,i)         	_OP3(cc,_AND,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_ANDS_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_AND,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ANDS_rrrLSLi(cc,Rd,Rn,Rm,i)      _OP3(cc,_AND,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ANDS_rrrLSLr(cc,Rd,Rn,Rm,Rs)     _OP3(cc,_AND,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ANDS_rrrLSRi(cc,Rd,Rn,Rm,i)      _OP3(cc,_AND,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ANDS_rrrLSRr(cc,Rd,Rn,Rm,Rs)     _OP3(cc,_AND,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ANDS_rrrASRi(cc,Rd,Rn,Rm,i)      _OP3(cc,_AND,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ANDS_rrrASRr(cc,Rd,Rn,Rm,Rs)     _OP3(cc,_AND,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ANDS_rrrRORi(cc,Rd,Rn,Rm,i)      _OP3(cc,_AND,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ANDS_rrrRORr(cc,Rd,Rn,Rm,Rs)     _OP3(cc,_AND,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ANDS_rrrRRX(cc,Rd,Rn,Rm)         _OP3(cc,_AND,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define ANDS_rri(Rd,Rn,i)                 	CC_ANDS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ANDS_rrr(Rd,Rn,Rm)                 	CC_ANDS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ANDS_rrrLSLi(Rd,Rn,Rm,i)         	CC_ANDS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ANDS_rrrLSLr(Rd,Rn,Rm,Rs)         	CC_ANDS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ANDS_rrrLSRi(Rd,Rn,Rm,i)         	CC_ANDS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ANDS_rrrLSRr(Rd,Rn,Rm,Rs)         	CC_ANDS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ANDS_rrrASRi(Rd,Rn,Rm,i)         	CC_ANDS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ANDS_rrrASRr(Rd,Rn,Rm,Rs)         	CC_ANDS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ANDS_rrrRORi(Rd,Rn,Rm,i)         	CC_ANDS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ANDS_rrrRORr(Rd,Rn,Rm,Rs)         	CC_ANDS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ANDS_rrrRRX(Rd,Rn,Rm)   	        CC_ANDS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_EOR_rri(cc,Rd,Rn,i)          	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_EOR_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_EOR_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_EOR_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_EOR_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_EOR_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_EOR_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_EOR_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_EOR_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_EOR_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_EOR,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_EOR_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_EOR,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define EOR_rri(Rd,Rn,i)                	CC_EOR_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define EOR_rrr(Rd,Rn,Rm)               	CC_EOR_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define EOR_rrrLSLi(Rd,Rn,Rm,i)         	CC_EOR_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EOR_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_EOR_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EOR_rrrLSRi(Rd,Rn,Rm,i)         	CC_EOR_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EOR_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_EOR_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EOR_rrrASRi(Rd,Rn,Rm,i)         	CC_EOR_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EOR_rrrASRr(Rd,Rn,Rm,Rs)        	CC_EOR_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EOR_rrrRORi(Rd,Rn,Rm,i)         	CC_EOR_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EOR_rrrRORr(Rd,Rn,Rm,Rs)        	CC_EOR_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EOR_rrrRRX(Rd,Rn,Rm)            	CC_EOR_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_EORS_rri(cc,Rd,Rn,i)         	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_EORS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_EORS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_EORS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_EORS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_EORS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_EORS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_EORS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_EORS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_EORS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_EOR,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_EORS_rrrRRX(cc,Rd,Rn,Rm)    		_OP3(cc,_EOR,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define EORS_rri(Rd,Rn,i)               	CC_EORS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define EORS_rrr(Rd,Rn,Rm)              	CC_EORS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define EORS_rrrLSLi(Rd,Rn,Rm,i)        	CC_EORS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EORS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_EORS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EORS_rrrLSRi(Rd,Rn,Rm,i)        	CC_EORS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EORS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_EORS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EORS_rrrASRi(Rd,Rn,Rm,i)        	CC_EORS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EORS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_EORS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EORS_rrrRORi(Rd,Rn,Rm,i)        	CC_EORS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define EORS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_EORS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define EORS_rrrRRX(Rd,Rn,Rm)           	CC_EORS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_SUB_rri(cc,Rd,Rn,i)          	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_SUB_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_SUB_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_SUB_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_SUB_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_SUB_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_SUB_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_SUB_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_SUB_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_SUB_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SUB,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_SUB_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_SUB,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define SUB_rri(Rd,Rn,i)                	CC_SUB_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define SUB_rrr(Rd,Rn,Rm)               	CC_SUB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define SUB_rrrLSLi(Rd,Rn,Rm,i)         	CC_SUB_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUB_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_SUB_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUB_rrrLSRi(Rd,Rn,Rm,i)         	CC_SUB_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUB_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_SUB_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUB_rrrASRi(Rd,Rn,Rm,i)         	CC_SUB_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUB_rrrASRr(Rd,Rn,Rm,Rs)        	CC_SUB_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUB_rrrRORi(Rd,Rn,Rm,i)         	CC_SUB_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUB_rrrRORr(Rd,Rn,Rm,Rs)        	CC_SUB_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUB_rrrRRX(Rd,Rn,Rm)            	CC_SUB_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_SUBS_rri(cc,Rd,Rn,i)         	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_SUBS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_SUBS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_SUBS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_SUBS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_SUBS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_SUBS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_SUBS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_SUBS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_SUBS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_SUBS_rrrRRX(cc,Rd,Rn,Rm) 	   	_OP3(cc,_SUB,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define SUBS_rri(Rd,Rn,i)               	CC_SUBS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define SUBS_rrr(Rd,Rn,Rm)              	CC_SUBS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define SUBS_rrrLSLi(Rd,Rn,Rm,i)        	CC_SUBS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUBS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_SUBS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUBS_rrrLSRi(Rd,Rn,Rm,i)        	CC_SUBS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUBS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_SUBS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUBS_rrrASRi(Rd,Rn,Rm,i)        	CC_SUBS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUBS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_SUBS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUBS_rrrRORi(Rd,Rn,Rm,i)        	CC_SUBS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SUBS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_SUBS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SUBS_rrrRRX(Rd,Rn,Rm)           	CC_SUBS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_RSB_rri(cc,Rd,Rn,i)          	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_RSB_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_RSB_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_RSB_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_RSB_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_RSB_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_RSB_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_RSB_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_RSB_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_RSB_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSB,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_RSB_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_RSB,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define RSB_rri(Rd,Rn,i)                	CC_RSB_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define RSB_rrr(Rd,Rn,Rm)               	CC_RSB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define RSB_rrrLSLi(Rd,Rn,Rm,i)         	CC_RSB_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSB_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_RSB_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSB_rrrLSRi(Rd,Rn,Rm,i)         	CC_RSB_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSB_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_RSB_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSB_rrrASRi(Rd,Rn,Rm,i)         	CC_RSB_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSB_rrrASRr(Rd,Rn,Rm,Rs)        	CC_RSB_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSB_rrrRORi(Rd,Rn,Rm,i)         	CC_RSB_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSB_rrrRORr(Rd,Rn,Rm,Rs)        	CC_RSB_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSB_rrrRRX(Rd,Rn,Rm)            	CC_RSB_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_RSBS_rri(cc,Rd,Rn,i)         	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_RSBS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_RSBS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_RSBS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_RSBS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_RSBS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_RSBS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_RSBS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_RSBS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_RSBS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSB,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_RSBS_rrrRRX(cc,Rd,Rn,Rm)    		_OP3(cc,_RSB,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define RSBS_rri(Rd,Rn,i)               	CC_RSBS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define RSBS_rrr(Rd,Rn,Rm)              	CC_RSBS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define RSBS_rrrLSLi(Rd,Rn,Rm,i)        	CC_RSBS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSBS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_RSBS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSBS_rrrLSRi(Rd,Rn,Rm,i)        	CC_RSBS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSBS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_RSBS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSBS_rrrASRi(Rd,Rn,Rm,i)        	CC_RSBS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSBS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_RSBS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSBS_rrrRORi(Rd,Rn,Rm,i)        	CC_RSBS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSBS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_RSBS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSBS_rrrRRX(Rd,Rn,Rm)           	CC_RSBS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_ADD_rri8(cc,Rd,Rn,i)          	_OP3(cc,_ADD,0,Rd,Rn,UNSHIFTED_IMM8(i))
+#define CC_ADD_rri8RORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_IMM8_ROR(Rm,i))
+
+#define CC_ADD_rri(cc,Rd,Rn,i)          	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_ADD_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ADD_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ADD_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ADD_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ADD_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ADD_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ADD_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ADD_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ADD_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADD,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ADD_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_ADD,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define ADD_rri8(Rd,Rn,i)          				CC_ADD_rri8(NATIVE_CC_AL,Rd,Rn,i)
+#define ADD_rri8RORi(Rd,Rn,Rm,i)   				CC_ADD_rri8RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+
+#define ADD_rri(Rd,Rn,i)                	CC_ADD_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ADD_rrr(Rd,Rn,Rm)               	CC_ADD_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ADD_rrrLSLi(Rd,Rn,Rm,i)         	CC_ADD_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADD_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_ADD_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADD_rrrLSRi(Rd,Rn,Rm,i)         	CC_ADD_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADD_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_ADD_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADD_rrrASRi(Rd,Rn,Rm,i)         	CC_ADD_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADD_rrrASRr(Rd,Rn,Rm,Rs)        	CC_ADD_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADD_rrrRORi(Rd,Rn,Rm,i)         	CC_ADD_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADD_rrrRORr(Rd,Rn,Rm,Rs)        	CC_ADD_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADD_rrrRRX(Rd,Rn,Rm)            	CC_ADD_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_ADDS_rri(cc,Rd,Rn,i)         	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_ADDS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ADDS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ADDS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ADDS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ADDS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ADDS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ADDS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ADDS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ADDS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADD,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ADDS_rrrRRX(cc,Rd,Rn,Rm)    		_OP3(cc,_ADD,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define ADDS_rri(Rd,Rn,i)               	CC_ADDS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ADDS_rrr(Rd,Rn,Rm)              	CC_ADDS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ADDS_rrrLSLi(Rd,Rn,Rm,i)        	CC_ADDS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADDS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_ADDS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADDS_rrrLSRi(Rd,Rn,Rm,i)        	CC_ADDS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADDS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_ADDS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADDS_rrrASRi(Rd,Rn,Rm,i)        	CC_ADDS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADDS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_ADDS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADDS_rrrRORi(Rd,Rn,Rm,i)        	CC_ADDS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADDS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_ADDS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADDS_rrrRRX(Rd,Rn,Rm)           	CC_ADDS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_ADC_rri(cc,Rd,Rn,i)          	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_ADC_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ADC_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ADC_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ADC_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ADC_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ADC_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ADC_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ADC_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ADC_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ADC,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ADC_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_ADC,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define ADC_rri(Rd,Rn,i)                	CC_ADC_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ADC_rrr(Rd,Rn,Rm)               	CC_ADC_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ADC_rrrLSLi(Rd,Rn,Rm,i)         	CC_ADC_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADC_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_ADC_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADC_rrrLSRi(Rd,Rn,Rm,i)         	CC_ADC_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADC_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_ADC_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADC_rrrASRi(Rd,Rn,Rm,i)         	CC_ADC_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADC_rrrASRr(Rd,Rn,Rm,Rs)        	CC_ADC_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADC_rrrRORi(Rd,Rn,Rm,i)         	CC_ADC_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADC_rrrRORr(Rd,Rn,Rm,Rs)        	CC_ADC_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADC_rrrRRX(Rd,Rn,Rm)            	CC_ADC_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_ADCS_rri(cc,Rd,Rn,i)         	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_ADCS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ADCS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ADCS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ADCS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ADCS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ADCS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ADCS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ADCS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ADCS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ADC,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ADCS_rrrRRX(cc,Rd,Rn,Rm)    		_OP3(cc,_ADC,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define ADCS_rri(Rd,Rn,i)               	CC_ADCS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ADCS_rrr(Rd,Rn,Rm)              	CC_ADCS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ADCS_rrrLSLi(Rd,Rn,Rm,i)        	CC_ADCS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADCS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_ADCS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADCS_rrrLSRi(Rd,Rn,Rm,i)        	CC_ADCS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADCS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_ADCS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADCS_rrrASRi(Rd,Rn,Rm,i)        	CC_ADCS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADCS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_ADCS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADCS_rrrRORi(Rd,Rn,Rm,i)        	CC_ADCS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ADCS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_ADCS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ADCS_rrrRRX(Rd,Rn,Rm)           	CC_ADCS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_SBC_rri(cc,Rd,Rn,i)          	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_SBC_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_SBC_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_SBC_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_SBC_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_SBC_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_SBC_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_SBC_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_SBC_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_SBC_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_SBC,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_SBC_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_SBC,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define SBC_rri(Rd,Rn,i)                	CC_SBC_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define SBC_rrr(Rd,Rn,Rm)               	CC_SBC_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define SBC_rrrLSLi(Rd,Rn,Rm,i)         	CC_SBC_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBC_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_SBC_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBC_rrrLSRi(Rd,Rn,Rm,i)         	CC_SBC_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBC_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_SBC_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBC_rrrASRi(Rd,Rn,Rm,i)         	CC_SBC_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBC_rrrASRr(Rd,Rn,Rm,Rs)        	CC_SBC_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBC_rrrRORi(Rd,Rn,Rm,i)         	CC_SBC_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBC_rrrRORr(Rd,Rn,Rm,Rs)        	CC_SBC_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBC_rrrRRX(Rd,Rn,Rm)            	CC_SBC_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_SBCS_rri(cc,Rd,Rn,i)         	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_SBCS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_SBCS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_SBCS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_SBCS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_SBCS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_SBCS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_SBCS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_SBCS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_SBCS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_SBC,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_SBCS_rrrRRX(cc,Rd,Rn,Rm)    		_OP3(cc,_SBC,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define SBCS_rri(Rd,Rn,i)               	CC_SBCS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define SBCS_rrr(Rd,Rn,Rm)              	CC_SBCS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define SBCS_rrrLSLi(Rd,Rn,Rm,i)        	CC_SBCS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBCS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_SBCS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBCS_rrrLSRi(Rd,Rn,Rm,i)        	CC_SBCS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBCS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_SBCS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBCS_rrrASRi(Rd,Rn,Rm,i)        	CC_SBCS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBCS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_SBCS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBCS_rrrRORi(Rd,Rn,Rm,i)        	CC_SBCS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define SBCS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_SBCS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define SBCS_rrrRRX(Rd,Rn,Rm)           	CC_SBCS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_RSC_rri(cc,Rd,Rn,i)          	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_RSC_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_RSC_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_RSC_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_RSC_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_RSC_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_RSC_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_RSC_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_RSC_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_RSC_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_RSC,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_RSC_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_RSC,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define RSC_rri(Rd,Rn,i)                	CC_RSC_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define RSC_rrr(Rd,Rn,Rm)               	CC_RSC_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define RSC_rrrLSLi(Rd,Rn,Rm,i)         	CC_RSC_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSC_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_RSC_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSC_rrrLSRi(Rd,Rn,Rm,i)         	CC_RSC_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSC_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_RSC_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSC_rrrASRi(Rd,Rn,Rm,i)         	CC_RSC_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSC_rrrASRr(Rd,Rn,Rm,Rs)        	CC_RSC_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSC_rrrRORi(Rd,Rn,Rm,i)         	CC_RSC_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSC_rrrRORr(Rd,Rn,Rm,Rs)        	CC_RSC_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSC_rrrRRX(Rd,Rn,Rm)            	CC_RSC_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_RSCS_rri(cc,Rd,Rn,i)         	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_RSCS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_RSCS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_RSCS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_RSCS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_RSCS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_RSCS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_RSCS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_RSCS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_RSCS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_RSC,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_RSCS_rrrRRX(cc,Rd,Rn,Rm)    		_OP3(cc,_RSC,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define RSCS_rri(Rd,Rn,i)               	CC_RSCS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define RSCS_rrr(Rd,Rn,Rm)              	CC_RSCS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define RSCS_rrrLSLi(Rd,Rn,Rm,i)        	CC_RSCS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSCS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_RSCS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSCS_rrrLSRi(Rd,Rn,Rm,i)        	CC_RSCS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSCS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_RSCS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSCS_rrrASRi(Rd,Rn,Rm,i)        	CC_RSCS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSCS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_RSCS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSCS_rrrRORi(Rd,Rn,Rm,i)        	CC_RSCS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define RSCS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_RSCS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define RSCS_rrrRRX(Rd,Rn,Rm)           	CC_RSCS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+// ORRcc Rd,Rn,#i
+#define CC_ORR_rri8(cc,Rd,Rn,i)          	_OP3(cc,_ORR,0,Rd,Rn,UNSHIFTED_IMM8(i))
+// ORRcc Rd,Rn,#i ROR #s
+#define CC_ORR_rri8RORi(cc,Rd,Rn,i,s)      	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_IMM8_ROR(i,s))
+
+#define CC_ORR_rri(cc,Rd,Rn,i)          	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_ORR_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ORR_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ORR_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ORR_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ORR_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ORR_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ORR_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ORR_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ORR_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ORR_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_ORR,0,Rd,Rn,SHIFT_RRX(Rm))
+
+// ORR Rd,Rn,#i
+#define ORR_rri8(Rd,Rn,i)          			CC_ORR_rri8(NATIVE_CC_AL,Rd,Rn,i)
+// ORR Rd,Rn,#i ROR #s
+#define ORR_rri8RORi(Rd,Rn,i,s)      		CC_ORR_rri8RORi(NATIVE_CC_AL,Rd,Rn,i,s)
+
+#define ORR_rri(Rd,Rn,i)                	CC_ORR_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ORR_rrr(Rd,Rn,Rm)               	CC_ORR_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ORR_rrrLSLi(Rd,Rn,Rm,i)         	CC_ORR_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORR_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_ORR_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORR_rrrLSRi(Rd,Rn,Rm,i)         	CC_ORR_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORR_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_ORR_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORR_rrrASRi(Rd,Rn,Rm,i)         	CC_ORR_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORR_rrrASRr(Rd,Rn,Rm,Rs)        	CC_ORR_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORR_rrrRORi(Rd,Rn,Rm,i)         	CC_ORR_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORR_rrrRORr(Rd,Rn,Rm,Rs)        	CC_ORR_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORR_rrrRRX(Rd,Rn,Rm)            	CC_ORR_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_ORRS_rri(cc,Rd,Rn,i)         	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_ORRS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_ORRS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_ORRS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_ORRS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_ORRS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_ORRS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_ORRS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_ORRS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_ORRS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_ORRS_rrrRRX(cc,Rd,Rn,Rm)  	  	_OP3(cc,_ORR,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define ORRS_rri(Rd,Rn,i)               	CC_ORRS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define ORRS_rrr(Rd,Rn,Rm)              	CC_ORRS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define ORRS_rrrLSLi(Rd,Rn,Rm,i)        	CC_ORRS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORRS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_ORRS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORRS_rrrLSRi(Rd,Rn,Rm,i)        	CC_ORRS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORRS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_ORRS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORRS_rrrASRi(Rd,Rn,Rm,i)        	CC_ORRS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORRS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_ORRS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORRS_rrrRORi(Rd,Rn,Rm,i)        	CC_ORRS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define ORRS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_ORRS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define ORRS_rrrRRX(Rd,Rn,Rm)           	CC_ORRS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_BIC_rri(cc,Rd,Rn,i)          	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_IMM(i))
+#define CC_BIC_rrr(cc,Rd,Rn,Rm)         	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_REG(Rm))
+#define CC_BIC_rrrLSLi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_BIC_rrrLSLr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_BIC_rrrLSRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_BIC_rrrLSRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_BIC_rrrASRi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_BIC_rrrASRr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_BIC_rrrRORi(cc,Rd,Rn,Rm,i)   	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_BIC_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_BIC,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_BIC_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_BIC,0,Rd,Rn,SHIFT_RRX(Rm))
+
+#define BIC_rri(Rd,Rn,i)                	CC_BIC_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define BIC_rrr(Rd,Rn,Rm)               	CC_BIC_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define BIC_rrrLSLi(Rd,Rn,Rm,i)         	CC_BIC_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BIC_rrrLSLr(Rd,Rn,Rm,Rs)        	CC_BIC_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BIC_rrrLSRi(Rd,Rn,Rm,i)         	CC_BIC_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BIC_rrrLSRr(Rd,Rn,Rm,Rs)        	CC_BIC_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BIC_rrrASRi(Rd,Rn,Rm,i)         	CC_BIC_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BIC_rrrASRr(Rd,Rn,Rm,Rs)        	CC_BIC_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BIC_rrrRORi(Rd,Rn,Rm,i)         	CC_BIC_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BIC_rrrRORr(Rd,Rn,Rm,Rs)        	CC_BIC_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BIC_rrrRRX(Rd,Rn,Rm)            	CC_BIC_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_BICS_rri(cc,Rd,Rn,i)         	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_IMM(i))
+#define CC_BICS_rrr(cc,Rd,Rn,Rm)        	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_REG(Rm))
+#define CC_BICS_rrrLSLi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_LSL_i(Rm,i))
+#define CC_BICS_rrrLSLr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_LSL_r(Rm,Rs))
+#define CC_BICS_rrrLSRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_LSR_i(Rm,i))
+#define CC_BICS_rrrLSRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_LSR_r(Rm,Rs))
+#define CC_BICS_rrrASRi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_ASR_i(Rm,i))
+#define CC_BICS_rrrASRr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_ASR_r(Rm,Rs))
+#define CC_BICS_rrrRORi(cc,Rd,Rn,Rm,i)  	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_ROR_i(Rm,i))
+#define CC_BICS_rrrRORr(cc,Rd,Rn,Rm,Rs) 	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
+#define CC_BICS_rrrRRX(cc,Rd,Rn,Rm)	    	_OP3(cc,_BIC,1,Rd,Rn,SHIFT_RRX(Rm))
+
+#define BICS_rri(Rd,Rn,i)               	CC_BICS_rri(NATIVE_CC_AL,Rd,Rn,i)
+#define BICS_rrr(Rd,Rn,Rm)              	CC_BICS_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define BICS_rrrLSLi(Rd,Rn,Rm,i)        	CC_BICS_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BICS_rrrLSLr(Rd,Rn,Rm,Rs)       	CC_BICS_rrrLSLr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BICS_rrrLSRi(Rd,Rn,Rm,i)        	CC_BICS_rrrLSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BICS_rrrLSRr(Rd,Rn,Rm,Rs)       	CC_BICS_rrrLSRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BICS_rrrASRi(Rd,Rn,Rm,i)        	CC_BICS_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BICS_rrrASRr(Rd,Rn,Rm,Rs)       	CC_BICS_rrrASRr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BICS_rrrRORi(Rd,Rn,Rm,i)        	CC_BICS_rrrRORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define BICS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_BICS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
+#define BICS_rrrRRX(Rd,Rn,Rm)           	CC_BICS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+/* Branch instructions */
+#define CC_B_i(cc,i)                        _W(((cc) << 28) | (10 << 24) | ((i) & 0x00ffffff))
+#define CC_BL_i(cc,i)                       _W(((cc) << 28) | (11 << 24) | ((i) & 0x00ffffff))
+#define CC_BLX_r(cc,r)                      _W(((cc) << 28) | (0x12 << 20) | (3 << 4) | (0xfff << 8) | (r))
+#define CC_BX_r(cc,r)                       _W(((cc) << 28) | (0x12 << 20) | (1 << 4) | (0xfff << 8) | (r))
+#define CC_BXJ_r(cc,r)                      _W(((cc) << 28) | (0x12 << 20) | (2 << 4) | (0xfff << 8) | (r))
+
+#define BEQ_i(i)                            CC_B_i(NATIVE_CC_EQ,i)
+#define BNE_i(i)                            CC_B_i(NATIVE_CC_NE,i)
+#define BCS_i(i)                            CC_B_i(NATIVE_CC_CS,i)
+#define BCC_i(i)                            CC_B_i(NATIVE_CC_CC,i)
+#define BMI_i(i)                            CC_B_i(NATIVE_CC_MI,i)
+#define BPL_i(i)                            CC_B_i(NATIVE_CC_PL,i)
+#define BVS_i(i)                            CC_B_i(NATIVE_CC_VS,i)
+#define BVC_i(i)                            CC_B_i(NATIVE_CC_VC,i)
+#define BHI_i(i)                            CC_B_i(NATIVE_CC_HI,i)
+#define BLS_i(i)                            CC_B_i(NATIVE_CC_LS,i)
+#define BGE_i(i)                            CC_B_i(NATIVE_CC_GE,i)
+#define BLT_i(i)                            CC_B_i(NATIVE_CC_LT,i)
+#define BGT_i(i)                            CC_B_i(NATIVE_CC_GT,i)
+#define BLE_i(i)                            CC_B_i(NATIVE_CC_LE,i)
+#define B_i(i)                              CC_B_i(NATIVE_CC_AL,i)
+
+#define BL_i(i)                             CC_BL_i(NATIVE_CC_AL,i)
+#define BLX_i(i)                            _W((NATIVE_CC_AL << 28) | (10 << 24) | (i))
+#define BLX_r(r)                            CC_BLX_r(NATIVE_CC_AL,r)
+#define BX_r(r)                             CC_BX_r(NATIVE_CC_AL,r)
+#define BXJ_r(r)                            CC_BXJ_r(NATIVE_CC_AL,r)
+
+/* Status register instructions */
+#define CC_MRS_CPSR(cc,Rd)					_W(((cc) << 28) | (0x10 << 20) | ((Rd) << 12) | (0xf << 16))
+#define MRS_CPSR(Rd)						CC_MRS_CPSR(NATIVE_CC_AL,Rd)
+#define CC_MRS_SPSR(cc,Rd)					_W(((cc) << 28) | (0x14 << 20) | ((Rd) << 12) | (0xf << 16))
+#define MRS_SPSR(Rd)						CC_MRS_SPSR(NATIVE_CC_AL,Rd)
+
+// Never use these, they are for system level and slower...
+//#define CC_MSR_CPSR_i(cc,i)					_W(((cc) << 28) | (0x32 << 20) | (0x9 << 16) | (0xf << 12) | SHIFT_IMM(i))
+//#define CC_MSR_CPSR_r(cc,Rm)				_W(((cc) << 28) | (0x12 << 20) | (0x9 << 16) | (0xf << 12) | (Rm))
+//#define MSR_CPSR_i(i)						CC_MSR_CPSR_i(NATIVE_CC_AL,(i))
+//#define MSR_CPSR_r(Rm)						CC_MSR_CPSR_r(NATIVE_CC_AL,(Rm))
+
+#define CC_MSR_CPSRf_i(cc,i)				_W(((cc) << 28) | (0x32 << 20) | (0x8 << 16) | (0xf << 12) | SHIFT_IMM(i))
+#define CC_MSR_CPSRf_r(cc,Rm)				_W(((cc) << 28) | (0x12 << 20) | (0x8 << 16) | (0xf << 12) | (Rm))
+
+#define MSR_CPSRf_i(i)						CC_MSR_CPSRf_i(NATIVE_CC_AL,(i))
+#define MSR_CPSRf_r(Rm)						CC_MSR_CPSRf_r(NATIVE_CC_AL,(Rm))
+
+// Never use these, they are for system level and slower...
+//#define CC_MSR_CPSRc_i(cc,i)				_W(((cc) << 28) | (0x32 << 20) | (0x1 << 16) | (0xf << 12) | SHIFT_IMM(i))
+//#define CC_MSR_CPSRc_r(cc,Rm)				_W(((cc) << 28) | (0x12 << 20) | (0x1 << 16) | (0xf << 12) | (Rm))
+//#define MSR_CPSRc_i(i)						CC_MSR_CPSRc_i(NATIVE_CC_AL,(i))
+//#define MSR_CPSRc_r(Rm)						CC_MSR_CPSRc_r(NATIVE_CC_AL,(Rm))
+
+/* Load Store instructions */
+
+#define CC_PUSH(cc,r)						_W(((cc) << 28) | (0x92d << 16) | (1 << (r)))
+#define PUSH(r)								CC_PUSH(NATIVE_CC_AL, r)
+
+#define CC_PUSH_REGS(cc,r)					_W(((cc) << 28) | (0x92d << 16) | (r))
+#define PUSH_REGS(r)						CC_PUSH_REGS(NATIVE_CC_AL, r)
+
+#define CC_POP(cc,r)						_W(((cc) << 28) | (0x8bd << 16) | (1 << (r)))
+#define POP(r)								CC_POP(NATIVE_CC_AL, r)
+
+#define CC_POP_REGS(cc,r)					_W(((cc) << 28) | (0x8bd << 16) | (r))
+#define POP_REGS(r)							CC_POP_REGS(NATIVE_CC_AL, r)
+
+#define CC_LDR_rR(cc,Rd,Rn)					_LS1(cc,1,0,Rd,Rn,ADD_IMM(0))
+#define CC_LDR_rRI(cc,Rd,Rn,i)				_LS1(cc,1,0,Rd,Rn,(i) >= 0 ? ADD_IMM(i) : SUB_IMM(-(i)))
+#define CC_LDR_rRi(cc,Rd,Rn,i)				_LS1(cc,1,0,Rd,Rn,SUB_IMM(i))
+#define CC_LDR_rRR(cc,Rd,Rn,Rm)				_LS1(cc,1,0,Rd,Rn,ADD_REG(Rm))
+#define CC_LDR_rRr(cc,Rd,Rn,Rm)				_LS1(cc,1,0,Rd,Rn,SUB_REG(Rm))
+#define CC_LDR_rRR_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,ADD_LSL(Rm,i))
+#define CC_LDR_rRr_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,SUB_LSL(Rm,i))
+#define CC_LDR_rRR_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,ADD_LSR(Rm,i))
+#define CC_LDR_rRr_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,SUB_LSR(Rm,i))
+#define CC_LDR_rRR_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,ADD_ASR(Rm,i))
+#define CC_LDR_rRr_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,SUB_ASR(Rm,i))
+#define CC_LDR_rRR_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,ADD_ROR(Rm,i))
+#define CC_LDR_rRr_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,0,Rd,Rn,SUB_ROR(Rm,i))
+#define CC_LDR_rRR_RRX(cc,Rd,Rn,Rm)			_LS1(cc,1,0,Rd,Rn,ADD_RRX(Rm))
+#define CC_LDR_rRr_RRX(cc,Rd,Rn,Rm)			_LS1(cc,1,0,Rd,Rn,SUB_RRX(Rm))
+
+#define LDR_rR(Rd,Rn)						CC_LDR_rR(NATIVE_CC_AL,Rd,Rn)
+#define LDR_rRI(Rd,Rn,i)					CC_LDR_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define LDR_rRi(Rd,Rn,i)					CC_LDR_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define LDR_rRR(Rd,Rn,Rm)					CC_LDR_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDR_rRr(Rd,Rn,Rm)					CC_LDR_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDR_rRR_LSLi(Rd,Rn,Rm,i)			CC_LDR_rRR_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRr_LSLi(Rd,Rn,Rm,i)			CC_LDR_rRr_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRR_LSRi(Rd,Rn,Rm,i)			CC_LDR_rRR_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRr_LSRi(Rd,Rn,Rm,i)			CC_LDR_rRr_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRR_ASRi(Rd,Rn,Rm,i)			CC_LDR_rRR_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRr_ASRi(Rd,Rn,Rm,i)			CC_LDR_rRr_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRR_RORi(Rd,Rn,Rm,i)			CC_LDR_rRR_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRr_RORi(Rd,Rn,Rm,i)			CC_LDR_rRr_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDR_rRR_RRX(Rd,Rn,Rm)				CC_LDR_rRR_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDR_rRr_RRX(Rd,Rn,Rm)				CC_LDR_rRr_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_STR_rR(cc,Rd,Rn)					_LS1(cc,0,0,Rd,Rn,ADD_IMM(0))
+#define CC_STR_rRI(cc,Rd,Rn,i)				_LS1(cc,0,0,Rd,Rn,ADD_IMM(i))
+#define CC_STR_rRi(cc,Rd,Rn,i)				_LS1(cc,0,0,Rd,Rn,SUB_IMM(i))
+#define CC_STR_rRR(cc,Rd,Rn,Rm)				_LS1(cc,0,0,Rd,Rn,ADD_REG(Rm))
+#define CC_STR_rRr(cc,Rd,Rn,Rm)				_LS1(cc,0,0,Rd,Rn,SUB_REG(Rm))
+#define CC_STR_rRR_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,ADD_LSL(Rm,i))
+#define CC_STR_rRr_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,SUB_LSL(Rm,i))
+#define CC_STR_rRR_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,ADD_LSR(Rm,i))
+#define CC_STR_rRr_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,SUB_LSR(Rm,i))
+#define CC_STR_rRR_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,ADD_ASR(Rm,i))
+#define CC_STR_rRr_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,SUB_ASR(Rm,i))
+#define CC_STR_rRR_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,ADD_ROR(Rm,i))
+#define CC_STR_rRr_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,0,Rd,Rn,SUB_ROR(Rm,i))
+#define CC_STR_rRR_RRX(cc,Rd,Rn,Rm)			_LS1(cc,0,0,Rd,Rn,ADD_RRX(Rm))
+#define CC_STR_rRr_RRX(cc,Rd,Rn,Rm)			_LS1(cc,0,0,Rd,Rn,SUB_RRX(Rm))
+
+#define STR_rR(Rd,Rn)						CC_STR_rR(NATIVE_CC_AL,Rd,Rn)
+#define STR_rRI(Rd,Rn,i)					CC_STR_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define STR_rRi(Rd,Rn,i)					CC_STR_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define STR_rRR(Rd,Rn,Rm)					CC_STR_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STR_rRr(Rd,Rn,Rm)					CC_STR_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STR_rRR_LSLi(Rd,Rn,Rm,i)			CC_STR_rRR_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRr_LSLi(Rd,Rn,Rm,i)			CC_STR_rRr_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRR_LSRi(Rd,Rn,Rm,i)			CC_STR_rRR_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRr_LSRi(Rd,Rn,Rm,i)			CC_STR_rRr_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRR_ASRi(Rd,Rn,Rm,i)			CC_STR_rRR_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRr_ASRi(Rd,Rn,Rm,i)			CC_STR_rRr_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRR_RORi(Rd,Rn,Rm,i)			CC_STR_rRR_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRr_RORi(Rd,Rn,Rm,i)			CC_STR_rRr_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STR_rRR_RRX(Rd,Rn,Rm)				CC_STR_rRR_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STR_rRr_RRX(Rd,Rn,Rm)				CC_STR_rRr_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_LDRB_rR(cc,Rd,Rn)				_LS1(cc,1,1,Rd,Rn,ADD_IMM(0))
+#define CC_LDRB_rRI(cc,Rd,Rn,i)				_LS1(cc,1,1,Rd,Rn,ADD_IMM(i))
+#define CC_LDRB_rRi(cc,Rd,Rn,i)				_LS1(cc,1,1,Rd,Rn,SUB_IMM(i))
+#define CC_LDRB_rRR(cc,Rd,Rn,Rm)			_LS1(cc,1,1,Rd,Rn,ADD_REG(Rm))
+#define CC_LDRB_rRr(cc,Rd,Rn,Rm)			_LS1(cc,1,1,Rd,Rn,SUB_REG(Rm))
+#define CC_LDRB_rRR_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,ADD_LSL(Rm,i))
+#define CC_LDRB_rRr_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,SUB_LSL(Rm,i))
+#define CC_LDRB_rRR_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,ADD_LSR(Rm,i))
+#define CC_LDRB_rRr_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,SUB_LSR(Rm,i))
+#define CC_LDRB_rRR_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,ADD_ASR(Rm,i))
+#define CC_LDRB_rRr_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,SUB_ASR(Rm,i))
+#define CC_LDRB_rRR_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,ADD_ROR(Rm,i))
+#define CC_LDRB_rRr_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,1,1,Rd,Rn,SUB_ROR(Rm,i))
+#define CC_LDRB_rRR_RRX(cc,Rd,Rn,Rm)		_LS1(cc,1,1,Rd,Rn,ADD_RRX(Rm))
+#define CC_LDRB_rRr_RRX(cc,Rd,Rn,Rm)		_LS1(cc,1,1,Rd,Rn,SUB_RRX(Rm))
+
+#define LDRB_rR(Rd,Rn)						CC_LDRB_rR(NATIVE_CC_AL,Rd,Rn)
+#define LDRB_rRI(Rd,Rn,i)					CC_LDRB_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRB_rRi(Rd,Rn,i)					CC_LDRB_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRB_rRR(Rd,Rn,Rm)					CC_LDRB_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRB_rRr(Rd,Rn,Rm)					CC_LDRB_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRB_rRR_LSLi(Rd,Rn,Rm,i)			CC_LDRB_rRR_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRr_LSLi(Rd,Rn,Rm,i)			CC_LDRB_rRr_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRR_LSRi(Rd,Rn,Rm,i)			CC_LDRB_rRR_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRr_LSRi(Rd,Rn,Rm,i)			CC_LDRB_rRr_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRR_ASRi(Rd,Rn,Rm,i)			CC_LDRB_rRR_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRr_ASRi(Rd,Rn,Rm,i)			CC_LDRB_rRr_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRR_RORi(Rd,Rn,Rm,i)			CC_LDRB_rRR_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRr_RORi(Rd,Rn,Rm,i)			CC_LDRB_rRr_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define LDRB_rRR_RRX(Rd,Rn,Rm)				CC_LDRB_rRR_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRB_rRr_RRX(Rd,Rn,Rm)				CC_LDRB_rRr_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_STRB_rR(cc,Rd,Rn)				_LS1(cc,0,1,Rd,Rn,ADD_IMM(0))
+#define CC_STRB_rRI(cc,Rd,Rn,i)				_LS1(cc,0,1,Rd,Rn,ADD_IMM(i))
+#define CC_STRB_rRi(cc,Rd,Rn,i)				_LS1(cc,0,1,Rd,Rn,SUB_IMM(i))
+#define CC_STRB_rRR(cc,Rd,Rn,Rm)			_LS1(cc,0,1,Rd,Rn,ADD_REG(Rm))
+#define CC_STRB_rRr(cc,Rd,Rn,Rm)			_LS1(cc,0,1,Rd,Rn,SUB_REG(Rm))
+#define CC_STRB_rRR_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,ADD_LSL(Rm,i))
+#define CC_STRB_rRr_LSLi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,SUB_LSL(Rm,i))
+#define CC_STRB_rRR_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,ADD_LSR(Rm,i))
+#define CC_STRB_rRr_LSRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,SUB_LSR(Rm,i))
+#define CC_STRB_rRR_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,ADD_ASR(Rm,i))
+#define CC_STRB_rRr_ASRi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,SUB_ASR(Rm,i))
+#define CC_STRB_rRR_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,ADD_ROR(Rm,i))
+#define CC_STRB_rRr_RORi(cc,Rd,Rn,Rm,i)		_LS1(cc,0,1,Rd,Rn,SUB_ROR(Rm,i))
+#define CC_STRB_rRR_RRX(cc,Rd,Rn,Rm)		_LS1(cc,0,1,Rd,Rn,ADD_RRX(Rm))
+#define CC_STRB_rRr_RRX(cc,Rd,Rn,Rm)		_LS1(cc,0,1,Rd,Rn,SUB_RRX(Rm))
+
+#define STRB_rR(Rd,Rn)						CC_STRB_rR(NATIVE_CC_AL,Rd,Rn)
+#define STRB_rRI(Rd,Rn,i)					CC_STRB_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define STRB_rRi(Rd,Rn,i)					CC_STRB_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define STRB_rRR(Rd,Rn,Rm)					CC_STRB_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STRB_rRr(Rd,Rn,Rm)					CC_STRB_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STRB_rRR_LSLi(Rd,Rn,Rm,i)			CC_STRB_rRR_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRr_LSLi(Rd,Rn,Rm,i)			CC_STRB_rRr_LSLi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRR_LSRi(Rd,Rn,Rm,i)			CC_STRB_rRR_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRr_LSRi(Rd,Rn,Rm,i)			CC_STRB_rRr_LSRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRR_ASRi(Rd,Rn,Rm,i)			CC_STRB_rRR_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRr_ASRi(Rd,Rn,Rm,i)			CC_STRB_rRr_ASRi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRR_RORi(Rd,Rn,Rm,i)			CC_STRB_rRR_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRr_RORi(Rd,Rn,Rm,i)			CC_STRB_rRr_RORi(NATIVE_CC_AL,Rd,Rn,Rm,i)
+#define STRB_rRR_RRX(Rd,Rn,Rm)				CC_STRB_rRR_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STRB_rRr_RRX(Rd,Rn,Rm)				CC_STRB_rRr_RRX(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_LDRSH_rR(cc,Rd,Rn)                   _LS2(cc,1,1,1,1,Rd,Rn,ADD2_IMM(0))
+#define CC_LDRSH_rRI(cc,Rd,Rn,i)                _LS2(cc,1,1,1,1,Rd,Rn,ADD2_IMM(i))
+#define CC_LDRSH_rRi(cc,Rd,Rn,i)                _LS2(cc,1,1,1,1,Rd,Rn,SUB2_IMM(i))
+#define CC_LDRSH_rRR(cc,Rd,Rn,Rm)               _LS2(cc,1,1,1,1,Rd,Rn,ADD2_REG(Rm))
+#define CC_LDRSH_rRr(cc,Rd,Rn,Rm)               _LS2(cc,1,1,1,1,Rd,Rn,SUB2_REG(Rm))
+
+#define LDRSH_rR(Rd,Rn)                         CC_LDRSH_rR(NATIVE_CC_AL,Rd,Rn)
+#define LDRSH_rRI(Rd,Rn,i)                      CC_LDRSH_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRSH_rRi(Rd,Rn,i)                      CC_LDRSH_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRSH_rRR(Rd,Rn,Rm)                     CC_LDRSH_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRSH_rRr(Rd,Rn,Rm)                     CC_LDRSH_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_LDRH_rR(cc,Rd,Rn)                    _LS2(cc,1,1,0,1,Rd,Rn,ADD2_IMM(0))
+#define CC_LDRH_rRI(cc,Rd,Rn,i)                 _LS2(cc,1,1,0,1,Rd,Rn,(i) >= 0 ? ADD2_IMM(i) : SUB2_IMM(-(i)))
+#define CC_LDRH_rRi(cc,Rd,Rn,i)                 _LS2(cc,1,1,0,1,Rd,Rn,SUB2_IMM(i))
+#define CC_LDRH_rRR(cc,Rd,Rn,Rm)                _LS2(cc,1,1,0,1,Rd,Rn,ADD2_REG(Rm))
+#define CC_LDRH_rRr(cc,Rd,Rn,Rm)                _LS2(cc,1,1,0,1,Rd,Rn,SUB2_REG(Rm))
+
+#define LDRH_rR(Rd,Rn)                          CC_LDRH_rR(NATIVE_CC_AL,Rd,Rn)
+#define LDRH_rRI(Rd,Rn,i)                       CC_LDRH_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRH_rRi(Rd,Rn,i)                       CC_LDRH_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRH_rRR(Rd,Rn,Rm)                      CC_LDRH_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRH_rRr(Rd,Rn,Rm)                      CC_LDRH_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_STRD_rR(cc,Rd,Rn)                   _LS2(cc,1,0,1,1,Rd,Rn,ADD2_IMM(0))
+#define CC_STRD_rRI(cc,Rd,Rn,i)                _LS2(cc,1,0,1,1,Rd,Rn,ADD2_IMM(i))
+#define CC_STRD_rRi(cc,Rd,Rn,i)                _LS2(cc,1,0,1,1,Rd,Rn,SUB2_IMM(i))
+#define CC_STRD_rRR(cc,Rd,Rn,Rm)               _LS2(cc,1,0,1,1,Rd,Rn,ADD2_REG(Rm))
+#define CC_STRD_rRr(cc,Rd,Rn,Rm)               _LS2(cc,1,0,1,1,Rd,Rn,SUB2_REG(Rm))
+
+#define STRD_rR(Rd,Rn)                         CC_STRD_rR(NATIVE_CC_AL,Rd,Rn)
+#define STRD_rRI(Rd,Rn,i)                      CC_STRD_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define STRD_rRi(Rd,Rn,i)                      CC_STRD_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define STRD_rRR(Rd,Rn,Rm)                     CC_STRD_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STRD_rRr(Rd,Rn,Rm)                     CC_STRD_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_STRH_rR(cc,Rd,Rn)                    _LS2(cc,1,0,0,1,Rd,Rn,ADD2_IMM(0))
+#define CC_STRH_rRI(cc,Rd,Rn,i)                 _LS2(cc,1,0,0,1,Rd,Rn,ADD2_IMM(i))
+#define CC_STRH_rRi(cc,Rd,Rn,i)                 _LS2(cc,1,0,0,1,Rd,Rn,SUB2_IMM(i))
+#define CC_STRH_rRR(cc,Rd,Rn,Rm)                _LS2(cc,1,0,0,1,Rd,Rn,ADD2_REG(Rm))
+#define CC_STRH_rRr(cc,Rd,Rn,Rm)                _LS2(cc,1,0,0,1,Rd,Rn,SUB2_REG(Rm))
+
+#define STRH_rR(Rd,Rn)                          CC_STRH_rR(NATIVE_CC_AL,Rd,Rn)
+#define STRH_rRI(Rd,Rn,i)                       CC_STRH_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define STRH_rRi(Rd,Rn,i)                       CC_STRH_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define STRH_rRR(Rd,Rn,Rm)                      CC_STRH_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define STRH_rRr(Rd,Rn,Rm)                      CC_STRH_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_LDRSB_rR(cc,Rd,Rn)                   _LS2(cc,1,1,1,0,Rd,Rn,ADD2_IMM(0))
+#define CC_LDRSB_rRI(cc,Rd,Rn,i)                _LS2(cc,1,1,1,0,Rd,Rn,ADD2_IMM(i))
+#define CC_LDRSB_rRi(cc,Rd,Rn,i)                _LS2(cc,1,1,1,0,Rd,Rn,SUB2_IMM(i))
+#define CC_LDRSB_rRR(cc,Rd,Rn,Rm)               _LS2(cc,1,1,1,0,Rd,Rn,ADD2_REG(Rm))
+#define CC_LDRSB_rRr(cc,Rd,Rn,Rm)               _LS2(cc,1,1,1,0,Rd,Rn,SUB2_REG(Rm))
+
+#define LDRSB_rR(Rd,Rn)                         CC_LDRSB_rR(NATIVE_CC_AL,Rd,Rn)
+#define LDRSB_rRI(Rd,Rn,i)                      CC_LDRSB_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRSB_rRi(Rd,Rn,i)                      CC_LDRSB_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRSB_rRR(Rd,Rn,Rm)                     CC_LDRSB_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRSB_rRr(Rd,Rn,Rm)                     CC_LDRSB_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_LDRD_rR(cc,Rd,Rn)                   _LS2(cc,1,0,1,0,Rd,Rn,ADD2_IMM(0))
+#define CC_LDRD_rRI(cc,Rd,Rn,i)                _LS2(cc,1,0,1,0,Rd,Rn,ADD2_IMM(i))
+#define CC_LDRD_rRi(cc,Rd,Rn,i)                _LS2(cc,1,0,1,0,Rd,Rn,SUB2_IMM(i))
+#define CC_LDRD_rRR(cc,Rd,Rn,Rm)               _LS2(cc,1,0,1,0,Rd,Rn,ADD2_REG(Rm))
+#define CC_LDRD_rRr(cc,Rd,Rn,Rm)               _LS2(cc,1,0,1,0,Rd,Rn,SUB2_REG(Rm))
+
+#define LDRD_rR(Rd,Rn)                         CC_LDRD_rR(NATIVE_CC_AL,Rd,Rn)
+#define LDRD_rRI(Rd,Rn,i)                      CC_LDRD_rRI(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRD_rRi(Rd,Rn,i)                      CC_LDRD_rRi(NATIVE_CC_AL,Rd,Rn,i)
+#define LDRD_rRR(Rd,Rn,Rm)                     CC_LDRD_rRR(NATIVE_CC_AL,Rd,Rn,Rm)
+#define LDRD_rRr(Rd,Rn,Rm)                     CC_LDRD_rRr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+/* Multiply */
+#define CC_SMULL_rrrr(cc, RdLo, RdHi, Rm, Rs)	_W(((cc) << 28) | (0x0C << 20) | ((RdHi) << 16) | ((RdLo) << 12) | ((Rs) << 8) | (0x9 << 4) | (Rm))
+#define SMULL_rrrr(RdLo,RdHi,Rm,Rs)				CC_SMULL_rrrr(NATIVE_CC_AL,RdLo,RdHi,Rm,Rs)
+#define CC_SMULLS_rrrr(cc, RdLo, RdHi, Rm, Rs)	_W(((cc) << 28) | (0x0D << 20) | ((RdHi) << 16) | ((RdLo) << 12) | ((Rs) << 8) | (0x9 << 4) | (Rm))
+#define SMULLS_rrrr(RdLo,RdHi,Rm,Rs)			CC_SMULLS_rrrr(NATIVE_CC_AL,RdLo,RdHi,Rm,Rs)
+#define CC_MUL_rrr(cc, Rd, Rm, Rs)				_W(((cc) << 28) | (0x00 << 20) | ((Rd) << 16) | ((Rs) << 8) | (0x9 << 4) | (Rm))
+#define MUL_rrr(Rd, Rm, Rs)						CC_MUL_rrr(NATIVE_CC_AL, Rd, Rm, Rs)
+#define CC_MULS_rrr(cc, Rd, Rm, Rs)				_W(((cc) << 28) | (0x01 << 20) | ((Rd) << 16) | ((Rs) << 8) | (0x9 << 4) | (Rm))
+#define MULS_rrr(Rd, Rm, Rs)					CC_MULS_rrr(NATIVE_CC_AL, Rd, Rm, Rs)
+
+#define CC_UMULL_rrrr(cc, RdLo, RdHi, Rm, Rs)	_W(((cc) << 28) | (0x08 << 20) | ((RdHi) << 16) | ((RdLo) << 12) | ((Rs) << 8) | (0x9 << 4) | (Rm))
+#define UMULL_rrrr(RdLo,RdHi,Rm,Rs)				CC_UMULL_rrrr(NATIVE_CC_AL,RdLo,RdHi,Rm,Rs)
+#define CC_UMULLS_rrrr(cc, RdLo, RdHi, Rm, Rs)	_W(((cc) << 28) | (0x09 << 20) | ((RdHi) << 16) | ((RdLo) << 12) | ((Rs) << 8) | (0x9 << 4) | (Rm))
+#define UMULLS_rrrr(RdLo,RdHi,Rm,Rs)			CC_UMULLS_rrrr(NATIVE_CC_AL,RdLo,RdHi,Rm,Rs)
+
+/* Others */
+#define CC_CLZ_rr(cc,Rd,Rm)					_W(((cc) << 28) | (0x16 << 20) | (0xf << 16) | ((Rd) << 12) | (0xf << 8) | (0x1 << 4) | SHIFT_REG(Rm))
+#define CLZ_rr(Rd,Rm)						CC_CLZ_rr(NATIVE_CC_AL,Rd,Rm)
+
+/* Alias */
+#define LSL_rri(Rd,Rm,i)                    MOV_rrLSLi(Rd,Rm,i)
+#define LSL_rrr(Rd,Rm,Rs)                	MOV_rrLSLr(Rd,Rm,Rs)
+#define LSR_rri(Rd,Rm,i)                    MOV_rrLSRi(Rd,Rm,i)
+#define LSR_rrr(Rd,Rm,Rs)                	MOV_rrLSRr(Rd,Rm,Rs)
+#define ASR_rri(Rd,Rm,i)                    MOV_rrASRi(Rd,Rm,i)
+#define ASR_rrr(Rd,Rm,Rs)                	MOV_rrASRr(Rd,Rm,Rs)
+#define ROR_rri(Rd,Rm,i)                    MOV_rrRORi(Rd,Rm,i)
+#define ROR_rrr(Rd,Rm,Rs)                	MOV_rrRORr(Rd,Rm,Rs)
+#define RRX_rr(Rd,Rm)                       MOV_rrRRX(Rd,Rm)
+#define LSLS_rri(Rd,Rm,i)                   MOVS_rrLSLi(Rd,Rm,i)
+#define LSLS_rrr(Rd,Rm,Rs)                	MOVS_rrLSLr(Rd,Rm,Rs)
+#define LSRS_rri(Rd,Rm,i)                   MOVS_rrLSRi(Rd,Rm,i)
+#define LSRS_rrr(Rd,Rm,Rs)                	MOVS_rrLSRr(Rd,Rm,Rs)
+#define ASRS_rri(Rd,Rm,i)                   MOVS_rrASRi(Rd,Rm,i)
+#define ASRS_rrr(Rd,Rm,Rs)                	MOVS_rrASRr(Rd,Rm,Rs)
+#define RORS_rri(Rd,Rm,i)                   MOVS_rrRORi(Rd,Rm,i)
+#define RORS_rrr(Rd,Rm,Rs)                	MOVS_rrRORr(Rd,Rm,Rs)
+#define RRXS_rr(Rd,Rm)                      MOVS_rrRRX(Rd,Rm)
+
+/* ARMV6 ops */
+#define CC_SXTB_rr(cc,Rd,Rm)				_W(((cc) << 28) | (0x6a << 20) | (0xf << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTB_rr(Rd,Rm)						CC_SXTB_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTB_rr_ROR8(cc,Rd,Rm)			_W(((cc) << 28) | (0x6a << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTB_rr_ROR8(Rd,Rm)					CC_SXTB_rr_ROR8(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTB_rr_ROR16(cc,Rd,Rm)			_W(((cc) << 28) | (0x6a << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTB_rr_ROR16(Rd,Rm)				CC_SXTB_rr_ROR16(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTB_rr_ROR24(cc,Rd,Rm)			_W(((cc) << 28) | (0x6a << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTB_rr_ROR24(Rd,Rm)				CC_SXTB_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTH_rr(cc,Rd,Rm)				_W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTH_rr(Rd,Rm)						CC_SXTH_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTH_rr_ROR8(cc,Rd,Rm)			_W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTH_rr_ROR8(Rd,Rm)					CC_SXTH_rr_ROR8(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTH_rr_ROR16(cc,Rd,Rm)			_W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTH_rr_ROR16(Rd,Rm)				CC_SXTH_rr_ROR16(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_SXTH_rr_ROR24(cc,Rd,Rm)			_W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTH_rr_ROR24(Rd,Rm)				CC_SXTH_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTB_rr(cc,Rd,Rm)				_W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTB_rr(Rd,Rm)							CC_UXTB_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTB_rr_ROR8(cc,Rd,Rm)		_W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTB_rr_ROR8(Rd,Rm)					CC_UXTB_rr_ROR8(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTB_rr_ROR16(cc,Rd,Rm)	_W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTB_rr_ROR16(Rd,Rm)				CC_UXTB_rr_ROR16(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTB_rr_ROR24(cc,Rd,Rm)	_W(((cc) << 28) | (0x6e << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTB_rr_ROR24(Rd,Rm)				CC_UXTB_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTH_rr(cc,Rd,Rm)				_W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTH_rr(Rd,Rm)							CC_UXTH_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTH_rr_ROR8(cc,Rd,Rm)		_W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (1 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTH_rr_ROR8(Rd,Rm)					CC_UXTH_rr_ROR8(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTH_rr_ROR16(cc,Rd,Rm)	_W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (2 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTH_rr_ROR16(Rd,Rm)				CC_UXTH_rr_ROR16(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_UXTH_rr_ROR24(cc,Rd,Rm)	_W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | ((Rd) << 12) | (3 << 10) | (0x7 << 4) | SHIFT_REG(Rm))
+#define UXTH_rr_ROR24(Rd,Rm)				CC_UXTH_rr_ROR24(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_REV_rr(cc,Rd,Rm)					_W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | (0xf << 8) | ((Rd) << 12) | (0x3 << 4) | SHIFT_REG(Rm))
+#define REV_rr(Rd,Rm)								CC_REV_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_REV16_rr(cc,Rd,Rm)				_W(((cc) << 28) | (0x6b << 20) | (0xf << 16) | (0xf << 8) | ((Rd) << 12) | (0xB << 4) | SHIFT_REG(Rm))
+#define REV16_rr(Rd,Rm)							CC_REV16_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_REVSH_rr(cc,Rd,Rm)				_W(((cc) << 28) | (0x6f << 20) | (0xf << 16) | (0xf << 8) | ((Rd) << 12) | (0xB << 4) | SHIFT_REG(Rm))
+#define REVSH_rr(Rd,Rm)							CC_REVSH_rr(NATIVE_CC_AL,Rd,Rm)
+
+#define CC_PKHBT_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x68 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x1 << 4) | (Rm))
+#define CC_PKHBT_rrrLSLi(cc,Rd,Rn,Rm,s)		_W(((cc) << 28) | (0x68 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x1 << 4) | SHIFT_PK(Rm, s))
+#define PKHBT_rrr(Rd,Rn,Rm)					CC_PKHBT_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+#define PKHBT_rrrLSLi(Rd,Rn,Rm,s)		CC_PKHBT_rrrLSLi(NATIVE_CC_AL,Rd,Rn,Rm,s)
+
+#define CC_PKHTB_rrrASRi(cc,Rd,Rn,Rm,s)		_W(((cc) << 28) | (0x68 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x5 << 4) | SHIFT_PK(Rm, s))
+#define PKHTB_rrrASRi(Rd,Rn,Rm,s)		CC_PKHTB_rrrASRi(NATIVE_CC_AL,Rd,Rn,Rm,s)
+#define CC_PKHTB_rrr(cc,Rd,Rn,Rm)		CC_PKHBT_rrr(cc,Rd,Rm,Rn)
+#define PKHTB_rrr(Rd,Rn,Rm)			    PKHBT_rrr(Rd,Rm,Rn)
+
+#define CC_SADD16_rrr(cc,Rd,Rn,Rm)  _W(((cc) << 28) | (0x61 << 20) | ((Rn) << 16) | ((Rd) << 12) | (0xf1 << 4) | (Rm))
+#define SADD16_rrr(Rd,Rn,Rm)				CC_SADD16_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_SXTAB_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x6a << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTAB_rrr(Rd,Rn,Rm)          CC_SXTAB_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_SXTAH_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x6b << 20) | ((Rn) << 16) | ((Rd) << 12) | (0x7 << 4) | SHIFT_REG(Rm))
+#define SXTAH_rrr(Rd,Rn,Rm)          CC_SXTAH_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_STM_Ri(cc,Rn,i)					_W(((cc) << 28) | (0x8 << 24) | (0x8 << 20) | ((Rn) << 16) | (i))
+#define STM_Ri(Rn,i)								CC_STM_Ri(NATIVE_CC_AL,Rn,i)
+
+#define CC_MLS_rrrr(cc,Rd,Rn,Rm,Ra)			_W(((cc) << 28) | (0x0 << 24) | (0x6 << 20) | ((Rd) << 16) | ((Ra) << 12) | ((Rm) << 8) | (0x9 << 4) | (Rn))
+#define MLS_rrrr(Rd,Rn,Rm,Ra)           CC_MLS_rrrr(NATIVE_CC_AL,Rd,Rn,Rm,Ra)
+
+#define CC_SMULxy_rrr(cc,Rd,Rn,Rm,x,y)	_W(((cc) << 28) | (0x1 << 24) | (0x6 << 20) | ((Rd) << 16) | (0x0 << 12) | ((Rm) << 8) | (0x8 << 4) | (Rn) | ((x) << 5) | ((y) << 6))
+#define SMULxy_rrr(Rd,Rn,Rm,x,y)        CC_SMULxy_rrr(NATIVE_CC_AL,Rd,Rn,Rm,x,y)
+
+// ARMv6T2
+#ifdef ARMV6T2
+
+#define CC_BFI_rrii(cc,Rd,Rn,lsb,msb)   _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | ((Rd) << 12) | ((lsb) << 7) | (0x1 << 4) | (Rn))
+#define BFI_rrii(Rd,Rn,lsb,msb)         CC_BFI_rrii(NATIVE_CC_AL,Rd,Rn,lsb,msb)
+
+#define CC_BFC_rii(cc,Rd,lsb,msb)       _W(((cc) << 28) | (0x3e << 21) | ((msb) << 16) | ((Rd) << 12) | ((lsb) << 7) | (0x1 << 4) | 15)
+#define BFC_rii(Rd,lsb,msb)             CC_BFC_rii(NATIVE_CC_AL,Rd,lsb,msb)
+
+#define CC_UBFX_rrii(cc,Rd,Rn,lsb,width)   _W(((cc) << 28) | (0x3f << 21) | ((width-1) << 16) | ((Rd) << 12) | ((lsb) << 7) | (0x5 << 4) | (Rn))
+#define UBFX_rrii(Rd,Rn,lsb,width)         CC_UBFX_rrii(NATIVE_CC_AL,Rd,Rn,lsb,width)
+
+#define CC_MOVW_ri16(cc,Rd,i)           _W(((cc) << 28) | (0x30 << 20) | ((((i) >> 12) & 0xf) << 16) | ((Rd) << 12) | ((i) & 0x0fff))
+#define MOVW_ri16(Rd,i)					        CC_MOVW_ri16(NATIVE_CC_AL,Rd,i)
+
+#define CC_MOVT_ri16(cc,Rd,i)           _W(((cc) << 28) | (0x34 << 20) | ((((i) >> 12) & 0xf) << 16) | ((Rd) << 12) | ((i) & 0x0fff))
+#define MOVT_ri16(Rd,i)					        CC_MOVT_ri16(NATIVE_CC_AL,Rd,i)
+
+#define CC_SSAT_rir(cc,Rd,i,Rn)			_W(((cc) << 28) | (0x6a << 20) | ((i) << 16) | ((Rd) << 12) | (0x1 << 4) | (Rn))
+#define SSAT_rir(Rd,i,Rn)						CC_SSAT_rir(NATIVE_CC_AL,Rd,i,Rn)
+
+#define CC_SDIV_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x7 << 24) | (0x1 << 20) | ((Rd) << 16) | (0xf << 12) | ((Rm) << 8) | (0x1 << 4) | (Rn))
+#define SDIV_rrr(Rd,Rn,Rm)					CC_SDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#define CC_UDIV_rrr(cc,Rd,Rn,Rm)		_W(((cc) << 28) | (0x7 << 24) | (0x3 << 20) | ((Rd) << 16) | (0xf << 12) | ((Rm) << 8) | (0x1 << 4) | (Rn))
+#define UDIV_rrr(Rd,Rn,Rm)					CC_UDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
+
+#endif
+
+// Floatingpoint
+#define FADR_ADD(offs)              ((1 << 23) | (offs) >> 2)
+#define FADR_SUB(offs)              ((0 << 23) | (offs) >> 2)
+#define FOFFSET8(offs)              ((offs) >= 0 ? FADR_ADD(offs) : FADR_SUB(-offs))
+
+#define MAKE_Dd(Dd)                 ((((Dd) & 0x10) << 18) | (((Dd) & 0x0f) << 12))
+#define MAKE_Dm(Dm)                 ((((Dm) & 0x10) <<  1) | (((Dm) & 0x0f) <<  0))
+#define MAKE_Dn(Dn)                 ((((Dn) & 0x10) <<  3) | (((Dn) & 0x0f) << 16))
+#define MAKE_Sd(Sd)                 ((((Sd) & 0x01) << 22) | (((Sd) & 0x1e) << 11))
+#define MAKE_Sm(Sm)                 ((((Sm) & 0x01) <<  5) | (((Sm) & 0x1e) >>  1))
+#define MAKE_Sn(Sn)                 ((((Sn) & 0x01) <<  7) | (((Sn) & 0x1e) << 15))
+
+
+#define CC_VLDR64_dRi(cc,Dd,Rn,offs)    _W(((cc) << 28) | (0xd << 24) | (0x1 << 20) | ((Rn) << 16) | (0xb << 8) | FOFFSET8(offs) | MAKE_Dd(Dd))
+#define VLDR64_dRi(Dd,Rn,offs)          CC_VLDR64_dRi(NATIVE_CC_AL,Dd,Rn,offs)
+#define CC_VLDR32_sRi(cc,Sd,Rn,offs)    _W(((cc) << 28) | (0xd << 24) | (0x1 << 20) | ((Rn) << 16) | (0xa << 8) | FOFFSET8(offs) | MAKE_Sd(Sd))
+#define VLDR32_sRi(Sd,Rn,offs)          CC_VLDR32_sRi(NATIVE_CC_AL,Sd,Rn,offs)
+
+#define CC_VSTR64_dRi(cc,Dd,Rn,offs)    _W(((cc) << 28) | (0xd << 24) | (0x0 << 20) | ((Rn) << 16) | (0xb << 8) | FOFFSET8(offs) | MAKE_Dd(Dd))
+#define VSTR64_dRi(Dd,Rn,offs)          CC_VSTR64_dRi(NATIVE_CC_AL,Dd,Rn,offs)
+#define CC_VSTR32_sRi(cc,Sd,Rn,offs)    _W(((cc) << 28) | (0xd << 24) | (0x0 << 20) | ((Rn) << 16) | (0xa << 8) | FOFFSET8(offs) | MAKE_Sd(Sd))
+#define VSTR32_sRi(Sd,Rn,offs)          CC_VSTR32_sRi(NATIVE_CC_AL,Sd,Rn,offs)
+
+#define CC_VMOV64_dd(cc,Dd,Dm)					_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xb << 8) | (0x4 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
+#define VMOV64_dd(Dd,Dm)								CC_VMOV64_dd(NATIVE_CC_AL,Dd,Dm)
+#define CC_VMOV32_ss(cc,Sd,Sm)					_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xa << 8) | (0x4 << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VMOV32_ss(Sd,Sm)								CC_VMOV32_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VMOV32_rs(cc,Rt,Sn)        	_W(((cc) << 28) | (0xe << 24) | (0x1 << 20) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4) | MAKE_Sn(Sn))
+#define VMOV32_rs(Rt,Sn)              	CC_VMOV32_rs(NATIVE_CC_AL,Rt,Sn)
+#define CC_VMOV32_sr(cc,Sn,Rt)      		_W(((cc) << 28) | (0xe << 24) | (0x0 << 20) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4) | MAKE_Sn(Sn))
+#define VMOV32_sr(Sn,Rt)            		CC_VMOV32_sr(NATIVE_CC_AL,Sn,Rt)
+
+#define CC_VMOVi_from_ARM_dr(cc,Dn,Rt,x)  _W(((cc) << 28) | (0xe << 24) | (0x0 << 20) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | ((x) << 21) | MAKE_Dn(Dn))
+#define VMOVi_from_ARM_dr(Dn,Rt,x)        CC_VMOVi_from_ARM_dr(NATIVE_CC_AL,Dn,Rt,x)
+#define CC_VMOVi_to_ARM_rd(cc,Rt,Dn,x)  _W(((cc) << 28) | (0xe << 24) | (0x1 << 20) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | ((x) << 21) | MAKE_Dn(Dn))
+#define VMOVi_to_ARM_rd(Rt,Dn,x)        CC_VMOVi_to_ARM_rd(NATIVE_CC_AL,Rt,Dn,x)
+
+#define CC_VMOV64_rrd(cc,Rt,Rt2,Dm)    	_W(((cc) << 28) | (0xc << 24) | (0x5 << 20) | ((Rt2) << 16) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | MAKE_Dm(Dm))
+#define VMOV64_rrd(Rt,Rt2,Dm)          	CC_VMOV64_rrd(NATIVE_CC_AL,Rt,Rt2,Dm)
+#define CC_VMOV64_drr(cc,Dm,Rt,Rt2)  		_W(((cc) << 28) | (0xc << 24) | (0x4 << 20) | ((Rt2) << 16) | ((Rt) << 12) | (0xb << 8) | (0x1 << 4) | MAKE_Dm(Dm))
+#define VMOV64_drr(Dm,Rt,Rt2)        		CC_VMOV64_drr(NATIVE_CC_AL,Dm,Rt,Rt2)
+
+#define CC_VCVT64to32_sd(cc,Sd,Dm)  		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x7 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Dm(Dm))
+#define VCVT64to32_sd(Sd,Dm)        		CC_VCVT64to32_sd(NATIVE_CC_AL,Sd,Dm)
+#define CC_VCVT32to64_ds(cc,Dd,Sm)  		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x7 << 16) | (0xa << 8) | (0xc << 4) | MAKE_Dd(Dd) | MAKE_Sm(Sm))
+#define VCVT32to64_ds(Dd,Sm)        		CC_VCVT32to64_ds(NATIVE_CC_AL,Dd,Sm)
+
+#define CC_VCVTR64toI_sd(cc,Sd,Dm)  		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xd << 16) | (0xb << 8) | (0x4 << 4) | MAKE_Sd(Sd) | MAKE_Dm(Dm))
+#define VCVTR64toI_sd(Sd,Dm)        		CC_VCVTR64toI_sd(NATIVE_CC_AL,Sd,Dm)
+#define CC_VCVTR32toI_ss(cc,Sd,Sm)  		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xd << 16) | (0xa << 8) | (0x4 << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VCVTR32toI_ss(Sd,Sm)        		CC_VCVTR32toI_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VCVT64toI_sd(cc,Sd,Dm)   		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xd << 16) | (0xb << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Dm(Dm))
+#define VCVT64toI_sd(Sd,Dm)         		CC_VCVT64toI_sd(NATIVE_CC_AL,Sd,Dm)
+#define CC_VCVT32toI_ss(cc,Sd,Sm)   		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xd << 16) | (0xa << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VCVT32toI_ss(Sd,Sm)         		CC_VCVT32toI_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VCVT64toIu_sd(cc,Sd,Dm)   		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xd << 16) | (0xb << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Dm(Dm))
+#define VCVT64toIu_sd(Sd,Dm)         		CC_VCVT64toIu_sd(NATIVE_CC_AL,Sd,Dm)
+
+#define CC_VCVTIto64_ds(cc,Dd,Sm) 			_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x8 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Dd(Dd) | MAKE_Sm(Sm))
+#define VCVTIto64_ds(Dd,Sm)       			CC_VCVTIto64_ds(NATIVE_CC_AL,Dd,Sm)
+#define CC_VCVTIto32_ss(cc,Sd,Sm) 			_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x8 << 16) | (0xa << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VCVTIto32_ss(Sd,Sm)       			CC_VCVTIto32_ss(NATIVE_CC_AL,Dd,Sm)
+
+#define CC_VCVTIuto64_ds(cc,Dd,Sm) 			_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x8 << 16) | (0xb << 8) | (0x4 << 4) | MAKE_Dd(Dd) | MAKE_Sm(Sm))
+#define VCVTIuto64_ds(Dd,Sm)       			CC_VCVTIuto64_ds(NATIVE_CC_AL,Dd,Sm)
+
+#define CC_VADD64_ddd(cc,Dd,Dn,Dm)      _W(((cc) << 28) | (0xe << 24) | (0x3 << 20) | (0xb << 8) | (0x0 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+#define VADD64_ddd(Dd,Dn,Dm)            CC_VADD64_ddd(NATIVE_CC_AL,Dd,Dn,Dm)
+#define CC_VADD32_sss(cc,Sd,Sn,Sm)      _W(((cc) << 28) | (0xe << 24) | (0x3 << 20) | (0xa << 8) | (0x0 << 4) | MAKE_Sd(Sd) | MAKE_Sn(Sn) | MAKE_Sm(Sm))
+#define VADD32_sss(Sd,Sn,Sm)            CC_VADD32_sss(NATIVE_CC_AL,Sd,Sn,Sm)
+
+#define CC_VSUB64_ddd(cc,Dd,Dn,Dm)      _W(((cc) << 28) | (0xe << 24) | (0x3 << 20) | (0xb << 8) | (0x4 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+#define VSUB64_ddd(Dd,Dn,Dm)            CC_VSUB64_ddd(NATIVE_CC_AL,Dd,Dn,Dm)
+#define CC_VSUB32_sss(cc,Sd,Sn,Sm)      _W(((cc) << 28) | (0xe << 24) | (0x3 << 20) | (0xa << 8) | (0x4 << 4) | MAKE_Sd(Sd) | MAKE_Sn(Sn) | MAKE_Sm(Sm))
+#define VSUB32_sss(Sd,Sn,Sm)            CC_VSUB32_sss(NATIVE_CC_AL,Sd,Sn,Sm)
+
+#define CC_VMUL64_ddd(cc,Dd,Dn,Dm)      _W(((cc) << 28) | (0xe << 24) | (0x2 << 20) | (0xb << 8) | (0x0 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+#define VMUL64_ddd(Dd,Dn,Dm)            CC_VMUL64_ddd(NATIVE_CC_AL,Dd,Dn,Dm)
+#define CC_VMUL32_sss(cc,Sd,Sn,Sm)      _W(((cc) << 28) | (0xe << 24) | (0x2 << 20) | (0xa << 8) | (0x0 << 4) | MAKE_Sd(Sd) | MAKE_Sn(Sn) | MAKE_Sm(Sm))
+#define VMUL32_sss(Sd,Sn,Sm)            CC_VMUL32_sss(NATIVE_CC_AL,Sd,Sn,Sm)
+
+#define CC_VDIV64_ddd(cc,Dd,Dn,Dm)      _W(((cc) << 28) | (0xe << 24) | (0x8 << 20) | (0xb << 8) | (0x0 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+#define VDIV64_ddd(Dd,Dn,Dm)            CC_VDIV64_ddd(NATIVE_CC_AL,Dd,Dn,Dm)
+#define CC_VDIV32_sss(cc,Sd,Sn,Sm)      _W(((cc) << 28) | (0xe << 24) | (0x8 << 20) | (0xa << 8) | (0x0 << 4) | MAKE_Sd(Sd) | MAKE_Sn(Sn) | MAKE_Sm(Sm))
+#define VDIV32_sss(Sd,Sn,Sm)            CC_VDIV32_sss(NATIVE_CC_AL,Sd,Sn,Sm)
+
+#define CC_VABS64_dd(cc,Dd,Dm)         	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xb << 8) | (0xc << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
+#define VABS64_dd(Dd,Dm)               	CC_VABS64_dd(NATIVE_CC_AL,Dd,Dm)
+#define CC_VABS32_ss(cc,Sd,Sm)         	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xa << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VABS32_ss(Sd,Sm)               	CC_VABS32_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VNEG64_dd(cc,Dd,Dm)         	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x1 << 16) | (0xb << 8) | (0x4 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
+#define VNEG64_dd(Dd,Dm)               	CC_VNEG64_dd(NATIVE_CC_AL,Dd,Dm)
+#define CC_VNEG32_ss(cc,Sd,Sm)         	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x1 << 16) | (0xa << 8) | (0x4 << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VNEG32_ss(Sd,Sm)               	CC_VNEG32_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VSQRT64_dd(cc,Dd,Dm)        	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x1 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
+#define VSQRT64_dd(Dd,Dm)              	CC_VSQRT64_dd(NATIVE_CC_AL,Dd,Dm)
+#define CC_VSQRT32_ss(cc,Sd,Sm)        	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x1 << 16) | (0xa << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VSQRT32_ss(Sd,Sm)              	CC_VSQRT32_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VCMP64_dd(cc,Dd,Dm)         	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x4 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
+#define VCMP64_dd(Dd,Dm)               	CC_VCMP64_dd(NATIVE_CC_AL,Dd,Dm)
+#define CC_VCMP32_ss(cc,Sd,Sm)         	_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x4 << 16) | (0xa << 8) | (0xc << 4) | MAKE_Sd(Sd) | MAKE_Sm(Sm))
+#define VCMP32_ss(Sd,Sm)               	CC_VCMP32_ss(NATIVE_CC_AL,Sd,Sm)
+
+#define CC_VCMP64_d0(cc,Dd)          		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0x5 << 16) | (0xb << 8) | (0xc << 4) | MAKE_Dd(Dd))
+#define VCMP64_d0(Dd)                		CC_VCMP64_d0(NATIVE_CC_AL,Dd)
+
+#define CC_VMRS_r(cc,Rt)  							_W(((cc) << 28) | (0xe << 24) | (0xf << 20) | (0x1 << 16) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4))
+#define VMRS_r(Rt)											CC_VMRS_r(NATIVE_CC_AL,Rt)
+#define VMRS_CPSR()											VMRS_r(15)
+
+#define CC_VMSR_r(cc,Rt)  							_W(((cc) << 28) | (0xe << 24) | (0xe << 20) | (0x1 << 16) | ((Rt) << 12) | (0xa << 8) | (0x1 << 4))
+#define VMSR_r(Rt)											CC_VMSR_r(NATIVE_CC_AL,Rt)
+
+#define VBIT64_ddd(Dd,Dn,Dm)            _W(((0xf) << 28) | (0x3 << 24) | (0x2 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+#define VBIF64_ddd(Dd,Dn,Dm)            _W(((0xf) << 28) | (0x3 << 24) | (0x3 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+
+// Immediate values for VBIC, VMOV (I32), VMVN (I32) and VORR
+#define FIMMVAL(imm)             ((((imm) & 0x80) << 17) | (((imm) & 0x70) << 12) | (((imm) & 0x0f) << 0))
+#define FIMM32(imm)               (((imm) & 0xffffff00) == 0 ? (FIMMVAL((imm) >>  0) | (0x0 << 8)) : \
+                                   ((imm) & 0xffff00ff) == 0 ? (FIMMVAL((imm) >>  8) | (0x1 << 8)) : \
+                                   ((imm) & 0xff00ffff) == 0 ? (FIMMVAL((imm) >> 16) | (0x2 << 8)) : \
+                                                             (FIMMVAL((imm) >> 24) | (0x3 << 8))
+
+// VMOV I64: each bit of imm defines the value for an entire byte
+//           imm <abcdefgh> -> aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
+#define VMOV_I64_dimmI(Dd,imm)      		_W((0xf << 28) | (0x2 << 24) | (0x8 << 20) | (0x0 << 16) | (0xe << 8) | (0x3 << 4) | MAKE_Dd(Dd) | FIMMVAL(imm))
+
+// VMOV F64: imm <abcdefgh> -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = not b)
+#define FIMMF64(imm)                    ((((imm) & 0xf0) << 12) | (((imm) & 0x0f) << 0))
+#define CC_VMOV_F64_dimmF(cc,Dd,imm)	  _W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xb << 8) | MAKE_Dd(Dd) | FIMMF64(imm))
+#define VMOV_F64_dimmF(Dd,imm)				  CC_VMOV_F64_dimmF(NATIVE_CC_AL,Dd,imm)
+
+// VMOV F32: imm <abcdefgh> -> aBbbbbbc defgh000 00000000 00000000 (B = not b)
+#define CC_VMOV_F32_si(cc,Sd,imm)	  		_W(((cc) << 28) | (0xe << 24) | (0xb << 20) | (0xa << 8) | MAKE_Sd(Sd) | FIMMF64(imm))
+#define VMOV_F32_si(Sd,imm)				  		CC_VMOV_F32_si(NATIVE_CC_AL,sd,imm)
+
+// Immediate value for shift
+#define FIMM6(imm)                  ((imm) << 16)
+#define VSHL64_ddi(Dd,Dm,imm)       		_W((0xf << 28) | (0x2 << 24) | (0x8 << 20) | (0x5 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(imm))
+#define VSHR64_ddi(Dd,Dm,imm)       		_W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x0 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(64-(imm)))
+#define VSLI64_ddi(Dd,Dm,i)      				_W((0xf << 28) | (0x3 << 24) | (0x8 << 20) | (0x5 << 8) | (0x9 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm) | FIMM6(i))
+#define VSHL64_ddd(Dd,Dm,Dn)       		  _W((0xf << 28) | (0x3 << 24) | (0x3 << 20) | (0x4 << 8) | (0x0 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+
+#define VORR_ddd(Dd,Dn,Dm)       				_W((0xf << 28) | (0x2 << 24) | (0x2 << 20) | (0x1 << 8) | (0x1 << 4) | MAKE_Dd(Dd) | MAKE_Dn(Dn) | MAKE_Dm(Dm))
+
+#define VREV64_8_dd(Dd,Dm)      				_W((0xf << 28) | (0x3 << 24) | (0xb << 20) | (0x0 << 16) | (0x0 << 8) | (0x0 << 4) | MAKE_Dd(Dd) | MAKE_Dm(Dm))
+
+#endif /* ARM_RTASM_H */
diff --git a/jit/arm/codegen_arm64.cpp b/jit/arm/codegen_arm64.cpp
new file mode 100644
index 00000000..ead97225
--- /dev/null
+++ b/jit/arm/codegen_arm64.cpp
@@ -0,0 +1,1169 @@
+/*
+ * compiler/codegen_arm.cpp - AARCH64 code generator
+ *
+ * Copyright (c) 2019 TomB
+ *
+ * This file is part of the UAE4ARM project.
+ *
+ * JIT compiler m68k -> ARMv8.0
+ *
+ * Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ * This file is derived from CCG, copyright 1999-2003 Ian Piumarta
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Note: JIT for aarch64 only works if memory for Amiga part (regs.natmen_offset
+ *       to additional_mem + ADDITIONAL_MEMSIZE + BARRIER) is allocated in lower
+ *       32 bit address space. See alloc_AmigaMem() in generic_mem.cpp.
+ */
+
+#include "flags_arm.h"
+#include <cmath>
+
+/*************************************************************************
+ * Some basic information about the the target CPU                       *
+ *************************************************************************/
+
+#define R0_INDEX 0
+#define R1_INDEX 1
+#define R2_INDEX 2
+#define R3_INDEX 3
+#define R4_INDEX 4
+#define R5_INDEX 5
+#define R6_INDEX 6
+#define R7_INDEX 7
+#define R8_INDEX  8
+#define R9_INDEX  9
+#define R10_INDEX 10
+#define R11_INDEX 11
+#define R12_INDEX 12
+#define R13_INDEX 13
+#define R14_INDEX 14
+#define R15_INDEX 15
+#define R16_INDEX 16
+#define R17_INDEX 17
+#define R18_INDEX 18
+#define R27_INDEX 27
+#define R28_INDEX 28
+
+#define RSP_INDEX 31
+#define RLR_INDEX 30
+#define RFP_INDEX 29
+
+/* The register in which subroutines return an integer return value */
+#define REG_RESULT R0_INDEX
+
+/* The registers subroutines take their first and second argument in */
+#define REG_PAR1 R0_INDEX
+#define REG_PAR2 R1_INDEX
+
+#define REG_WORK1 R2_INDEX
+#define REG_WORK2 R3_INDEX
+#define REG_WORK3 R4_INDEX
+#define REG_WORK4 R5_INDEX
+
+#define REG_PC_TMP R1_INDEX /* Another register that is not the above */
+
+#define R_MEMSTART 27
+#define R_REGSTRUCT 28
+uae_s8 always_used[] = {2,3,4,5,18,R_MEMSTART,R_REGSTRUCT,-1}; // r2-r5 are work register in emitted code, r18 special use reg
+
+uae_u8 call_saved[] = {0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,1, 1,1,1,1, 1,1,1,1, 1,0,0,0};
+
+/* This *should* be the same as call_saved. But:
+   - We might not really know which registers are saved, and which aren't,
+	 so we need to preserve some, but don't want to rely on everyone else
+	 also saving those registers
+   - Special registers (such like the stack pointer) should not be "preserved"
+	 by pushing, even though they are "saved" across function calls
+   - r19 - r26 not in use, so no need to preserve
+   - if you change need_to_preserve, modify raw_push_regs_to_preserve() and raw_pop_preserved_regs()
+*/
+static const uae_u8 need_to_preserve[] = {0,0,0,0, 0,0,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,0, 0,0,0,0, 0,0,0,1, 1,0,0,0};
+
+#include "codegen_arm64.h"
+
+#define FIX_INVERTED_CARRY              \
+  if(flags_carry_inverted) {            \
+	MRS_NZCV_x(REG_WORK1);              \
+	EOR_xxCflag(REG_WORK1, REG_WORK1);  \
+	MSR_NZCV_x(REG_WORK1);              \
+	flags_carry_inverted = false;       \
+  }
+
+
+STATIC_INLINE void SIGNED8_IMM_2_REG(W4 r, IM8 v) {
+	uae_s16 v16 = (uae_s16)(uae_s8)v;
+	if (v16 & 0x8000) {
+		// Use 32-bit MOVN to keep upper 32 bits clean.
+		// MOVN_xi produces a 64-bit result with dirty upper bits for negative values
+		// (e.g., MOVN_xi for byte -1 -> 0xFFFFFFFFFFFFFFFF).
+		MOVN_wi(r, (uae_u16) ~v16);
+	} else {
+		MOV_wi(r, (uae_u16) v16);
+	}
+}
+
+STATIC_INLINE void UNSIGNED16_IMM_2_REG(W4 r, IM16 v) {
+	// Use 32-bit MOV to keep upper 32 bits clean.
+	MOV_wi(r, v);
+}
+
+STATIC_INLINE void SIGNED16_IMM_2_REG(W4 r, IM16 v) {
+	if (v & 0x8000) {
+		// Use 32-bit MOVN to keep upper 32 bits clean.
+		MOVN_wi(r, (uae_u16) ~v);
+	} else {
+		MOV_wi(r, (uae_u16) v);
+	}
+}
+
+STATIC_INLINE void UNSIGNED8_REG_2_REG(W4 d, RR4 s) {
+	UXTB_xx(d, s);
+}
+
+STATIC_INLINE void SIGNED8_REG_2_REG(W4 d, RR4 s) {
+	// Use 32-bit sign extension to keep upper 32 bits clean.
+	// SXTB_xx sign-extends to 64 bits, leaving dirty upper 32 bits
+	// for negative values (e.g., SXTB_xx of 0xFF -> 0xFFFFFFFFFFFFFFFF).
+	SXTB_ww(d, s);
+}
+
+STATIC_INLINE void UNSIGNED16_REG_2_REG(W4 d, RR4 s) {
+	UXTH_xx(d, s);
+}
+
+STATIC_INLINE void SIGNED16_REG_2_REG(W4 d, RR4 s) {
+	// Use 32-bit sign extension to keep upper 32 bits clean.
+	// SXTH_xx sign-extends to 64 bits, leaving dirty upper 32 bits
+	// for negative values (e.g., SXTH_xx of 0xFFFF -> 0xFFFFFFFFFFFFFFFF).
+	SXTH_ww(d, s);
+}
+
+STATIC_INLINE void LOAD_U32(int r, uae_u32 val)
+{
+	// Use 32-bit W-register instructions so upper 32 bits are always zeroed.
+	// The 64-bit variants (MOVN_xi, MOV_xi) would sign-extend values like
+	// 0xFFFFxxxx to 0xFFFFFFFFFFFFxxxx, corrupting Amiga addresses used
+	// in register-indexed addressing [Xn, X27].
+	if((val & 0xffff0000) == 0xffff0000) {
+		MOVN_wi(r, ~val);
+	} else {
+		MOV_wi(r, val);
+		if(val >> 16)
+			MOVK_wish(r, val >> 16, 16);
+	}
+}
+
+STATIC_INLINE void LOAD_U64(int r, uae_u64 val)
+{
+	MOV_xi(r, val);
+	if((val >> 16) & 0xffff)
+		MOVK_xish(r, val >> 16, 16);
+	if((val >> 32) & 0xffff)
+		MOVK_xish(r, val >> 32, 32);
+	if(val >> 48)
+		MOVK_xish(r, val >> 48, 48);
+}
+
+
+#define NUM_PUSH_CMDS 1
+#define NUM_POP_CMDS 1
+STATIC_INLINE void raw_push_regs_to_preserve(void) {
+	STP_xxXpre(27, 28, RSP_INDEX, -16);
+}
+
+STATIC_INLINE void raw_pop_preserved_regs(void) {
+	LDP_xxXpost(27, 28, RSP_INDEX, 16);
+}
+
+STATIC_INLINE void raw_flags_to_reg(int r)
+{
+	MRS_NZCV_x(r);
+	if(flags_carry_inverted) {
+		EOR_xxCflag(r, r);
+		MSR_NZCV_x(r);
+		flags_carry_inverted = false;
+	}
+	// Use absolute address for regflags.nzcv instead of offset from regs,
+	// because LDR/STR unsigned immediate truncates offsets >32760 bytes.
+	LOAD_U64(REG_WORK3, (uintptr)&(regflags.nzcv));
+	STR_wXi(r, REG_WORK3, 0);
+
+	live.state[FLAGTMP].status = INMEM;
+	live.state[FLAGTMP].realreg = -1;
+	/* We just "evicted" FLAGTMP. */
+	live.nat[r].nholds = 0;
+}
+
+STATIC_INLINE void raw_reg_to_flags(int r)
+{
+	MSR_NZCV_x(r);
+}
+
+
+//
+// compuemu_support used raw calls
+//
+LOWFUNC(WRITE,RMW,2,compemu_raw_inc_opcount,(IM16 op))
+{
+  uintptr idx = (uintptr) &(regs.raw_cputbl_count) - (uintptr) &regs;
+  LDR_xXi(REG_WORK2, R_REGSTRUCT, idx);
+  MOV_xi(REG_WORK3, op);
+  LDR_wXxLSLi(REG_WORK1, REG_WORK2, REG_WORK3, 1);
+  ADD_wwi(REG_WORK1, REG_WORK1, 1);
+  STR_wXxLSLi(REG_WORK1, REG_WORK2, REG_WORK3, 1);
+}
+LENDFUNC(WRITE,RMW,1,compemu_raw_inc_opcount,(IM16 op))
+
+LOWFUNC(WRITE,READ,1,compemu_raw_cmp_pc,(IMPTR s))
+{
+	/* s is always >= NATMEM_OFFSET and < NATMEM_OFFSET + max. Amiga mem */
+	clobber_flags();
+
+	uintptr idx = (uintptr) &(regs.pc_p) - (uintptr) &regs;
+	LDR_xXi(REG_WORK1, R_REGSTRUCT, idx); // regs.pc_p is 64 bit
+
+	LOAD_U64(REG_WORK2, s);
+	CMP_xx(REG_WORK1, REG_WORK2);
+}
+LENDFUNC(WRITE,READ,1,compemu_raw_cmp_pc,(IMPTR s))
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_set_pc_i,(IMPTR s))
+{
+	LOAD_U64(REG_WORK1, s);
+	uintptr idx = (uintptr) &(regs.pc_p) - (uintptr) &regs;
+	STR_xXi(REG_WORK1, R_REGSTRUCT, idx);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_set_pc_i,(IMPTR s))
+
+LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IMPTR s))
+{
+	uintptr idx = d - (uintptr) &regs;
+	if(d == (uintptr) &(regs.pc_p) || d == (uintptr) &(regs.pc_oldp)) {
+		LOAD_U64(REG_WORK2, s);  // pc_p/pc_oldp are 64-bit host pointers
+		STR_xXi(REG_WORK2, R_REGSTRUCT, idx);
+	} else if(idx <= 16380 && (idx & 3) == 0) {
+		// Within R_REGSTRUCT unsigned-offset range (covers regs + nearby
+		// globals like regflags that the linker places close by).
+		LOAD_U32(REG_WORK2, (uae_u32)s);
+		STR_wXi(REG_WORK2, R_REGSTRUCT, idx);
+	} else {
+		// Address too far from R_REGSTRUCT - use absolute address.
+		LOAD_U64(REG_WORK1, d);
+		LOAD_U32(REG_WORK2, (uae_u32)s);
+		STR_wXi(REG_WORK2, REG_WORK1, 0);
+	}
+}
+LENDFUNC(NONE,WRITE,2,compemu_raw_mov_l_mi,(MEMW d, IMPTR s))
+
+LOWFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(MEMW d, RR4 s))
+{
+	uintptr idx = d - (uintptr) &regs;
+	if(d == (uintptr) &(regs.pc_p) || d == (uintptr) &(regs.pc_oldp)) {
+		STR_xXi(s, R_REGSTRUCT, idx);
+	} else if(idx <= 16380 && (idx & 3) == 0) {
+		// Within R_REGSTRUCT unsigned-offset range (covers regs + nearby
+		// globals like regflags that the linker places close by).
+		STR_wXi(s, R_REGSTRUCT, idx);
+	} else {
+		// Address too far from R_REGSTRUCT - use absolute address.
+		LOAD_U64(REG_WORK1, d);
+		STR_wXi(s, REG_WORK1, 0);
+	}
+}
+LENDFUNC(NONE,WRITE,2,compemu_raw_mov_l_mr,(MEMW d, RR4 s))
+
+LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IM32 s))
+{
+	LOAD_U32(d, s);
+}
+LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_ri,(W4 d, IM32 s))
+
+LOWFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s))
+{
+	uintptr idx = s - (uintptr) &regs;
+	if(s == (uintptr) &(regs.pc_p) || s == (uintptr) &(regs.pc_oldp)) {
+		LDR_xXi(d, R_REGSTRUCT, idx);
+	} else if(idx <= 16380 && (idx & 3) == 0) {
+		// Within R_REGSTRUCT unsigned-offset range.
+		LDR_wXi(d, R_REGSTRUCT, idx);
+	} else {
+		// Address too far from R_REGSTRUCT - use absolute address.
+		LOAD_U64(REG_WORK1, s);
+		LDR_wXi(d, REG_WORK1, 0);
+	}
+}
+LENDFUNC(NONE,READ,2,compemu_raw_mov_l_rm,(W4 d, MEMR s))
+
+LOWFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s))
+{
+	// Use 64-bit MOV to preserve full register width.  PC_P holds a
+	// 64-bit host pointer; all other virtual registers hold 32-bit M68k
+	// values whose upper 32 bits are already zeroed by W-register ops
+	// upstream, so MOV_xx is safe for both cases.
+	MOV_xx(d, s);
+}
+LENDFUNC(NONE,NONE,2,compemu_raw_mov_l_rr,(W4 d, RR4 s))
+
+LOWFUNC(WRITE,RMW,1,compemu_raw_dec_m,(MEMRW d))
+{
+	clobber_flags();
+
+	LOAD_U64(REG_WORK1, d);
+	LDR_wXi(REG_WORK2, REG_WORK1, 0);
+	SUBS_wwi(REG_WORK2, REG_WORK2, 1);
+	STR_wXi(REG_WORK2, REG_WORK1, 0);
+}
+LENDFUNC(WRITE,RMW,1,compemu_raw_dec_m,(MEMRW ds))
+
+STATIC_INLINE void compemu_raw_call(uintptr t)
+{
+	LOAD_U64(REG_WORK1, t);
+
+	STR_xXpre(RLR_INDEX, RSP_INDEX, -16);
+	BLR_x(REG_WORK1);
+	LDR_xXpost(RLR_INDEX, RSP_INDEX, 16);
+}
+
+STATIC_INLINE void compemu_raw_call_r(RR4 r)
+{
+	STR_xXpre(RLR_INDEX, RSP_INDEX, -16);
+	BLR_x(r);
+	LDR_xXpost(RLR_INDEX, RSP_INDEX, 16);
+}
+
+STATIC_INLINE void compemu_raw_jcc_l_oponly(int cc)
+{
+	FIX_INVERTED_CARRY
+
+	switch (cc) {
+		case NATIVE_CC_HI: // HI
+			BEQ_i(2);										// beq no jump
+			BCC_i(0);										// bcc jump
+			break;
+
+		case NATIVE_CC_LS: // LS
+			BEQ_i(2);										// beq jump
+			BCC_i(2);										// bcc no jump
+			// jump
+			B_i(0);
+			// no jump
+			break;
+
+		case NATIVE_CC_F_OGT: // Jump if valid and greater than
+			BVS_i(2);		// do not jump if NaN
+			BGT_i(0);		// jump if greater than
+			break;
+
+		case NATIVE_CC_F_OGE: // Jump if valid and greater or equal
+			BVS_i(2);		// do not jump if NaN
+			BCS_i(0);		// jump if carry set
+			break;
+
+		case NATIVE_CC_F_OLT: // Jump if vaild and less than
+			BVS_i(2);		// do not jump if NaN
+			BCC_i(0);		// jump if carry cleared
+			break;
+
+		case NATIVE_CC_F_OLE: // Jump if valid and less or equal
+			BVS_i(2);		// do not jump if NaN
+			BLE_i(0);		// jump if less or equal
+			break;
+
+		case NATIVE_CC_F_OGL: // Jump if valid and greator or less
+			BVS_i(2);		// do not jump if NaN
+			BNE_i(0);		// jump if not equal
+			break;
+
+		case NATIVE_CC_F_OR: // Jump if valid
+			BVC_i(0);
+			break;
+
+		case NATIVE_CC_F_UN: // Jump if NAN
+			BVS_i(0);
+			break;
+
+		case NATIVE_CC_F_UEQ: // Jump if NAN or equal
+			BVS_i(2); 	// jump if NaN
+			BNE_i(2);		// do not jump if greater or less
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_UGT: // Jump if NAN or greater than
+			BVS_i(2); 	// jump if NaN
+			BLS_i(2);		// do not jump if lower or same
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_UGE: // Jump if NAN or greater or equal
+			BVS_i(2); 	// jump if NaN
+			BMI_i(2);		// do not jump if lower
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_ULT: // Jump if NAN or less than
+			BVS_i(2); 	// jump if NaN
+			BGE_i(2);		// do not jump if greater or equal
+			// jump
+			B_i(0);
+			break;
+
+		case NATIVE_CC_F_ULE: // Jump if NAN or less or equal
+			BVS_i(2); 	// jump if NaN
+			BGT_i(2);		// do not jump if greater
+			// jump
+			B_i(0);
+			break;
+
+		default:
+			CC_B_i(cc, 0);
+			break;
+	}
+	// emit of target into last branch will be done by caller
+}
+
+STATIC_INLINE void compemu_raw_handle_except(IM32 cycles)
+{
+	uae_u32* branchadd;
+
+	clobber_flags();
+
+	uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+	LDR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+	branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);  // no exception, jump to next instruction
+
+	LOAD_U32(REG_PAR1, cycles);
+	uae_u32* branchadd2 = (uae_u32*)get_target();
+	B_i(0); // <exec_nostats>
+	write_jmp_target(branchadd2, (uintptr)popall_execute_exception);
+
+	// Write target of next instruction
+	write_jmp_target(branchadd, (uintptr)get_target());
+}
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_execute_normal,(MEMR s))
+{
+	LOAD_U64(REG_WORK1, s);
+	LDR_xXi(REG_WORK1, REG_WORK1, 0);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <exec_nostats>
+	write_jmp_target(branchadd, (uintptr)popall_execute_normal_setpc);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_execute_normal,(MEMR s))
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_check_checksum,(MEMR s))
+{
+	LOAD_U64(REG_WORK1, s);
+	LDR_xXi(REG_WORK1, REG_WORK1, 0);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <exec_nostats>
+	write_jmp_target(branchadd, (uintptr)popall_check_checksum_setpc);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_check_checksum,(MEMR s))
+
+LOWFUNC(NONE,WRITE,1,compemu_raw_exec_nostats,(IMPTR s))
+{
+	LOAD_U64(REG_WORK1, s);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <exec_nostats>
+	write_jmp_target(branchadd, (uintptr)popall_exec_nostats_setpc);
+}
+LENDFUNC(NONE,WRITE,1,compemu_raw_exec_nostats,(IMPTR s))
+
+STATIC_INLINE void compemu_raw_maybe_recompile(void)
+{
+	BGE_i(2);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);
+	write_jmp_target(branchadd, (uintptr)popall_recompile_block);
+}
+
+STATIC_INLINE void compemu_raw_jmp(uintptr t)
+{
+	uintptr loc = (uintptr)get_target();
+	if(t > loc - 127 * 1024 * 1024 && t < loc + 127 * 1024 * 1024) {
+		B_i(0);
+		write_jmp_target((uae_u32*)loc, t);
+	} else {
+		LDR_xPCi(REG_WORK1, 8);
+		BR_x(REG_WORK1);
+		emit_quad(t);
+	}
+}
+
+STATIC_INLINE void compemu_raw_jmp_pc_tag(void)
+{
+	uintptr idx = (uintptr)&regs.pc_p - (uintptr)&regs;
+	LDRH_wXi(REG_WORK1, R_REGSTRUCT, idx);
+	idx = (uintptr)&regs.cache_tags - (uintptr)&regs;
+	LDR_xXi(REG_WORK2, R_REGSTRUCT, idx);
+	LDR_xXxLSLi(REG_WORK1, REG_WORK2, REG_WORK1, 1);
+	BR_x(REG_WORK1);
+}
+
+STATIC_INLINE void compemu_raw_maybe_cachemiss(void)
+{
+	BEQ_i(2);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);
+	write_jmp_target(branchadd, (uintptr)popall_cache_miss);
+}
+
+STATIC_INLINE void compemu_raw_maybe_do_nothing(IM32 cycles)
+{
+	uintptr idx = (uintptr)&regs.spcflags - (uintptr) &regs;
+	LDR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+	uae_s8 *branchadd = (uae_s8 *)get_target();
+	CBZ_wi(REG_WORK1, 0);  // <end>
+
+	// Use absolute address for countdown (global variable, may be >32KB from regs)
+	LOAD_U64(REG_WORK3, (uintptr)&countdown);
+	LDR_wXi(REG_WORK2, REG_WORK3, 0);
+	if(cycles >= 0 && cycles <= 0xfff) {
+		SUB_wwi(REG_WORK2, REG_WORK2, cycles);
+	} else {
+		LOAD_U32(REG_WORK1, cycles);
+		SUB_www(REG_WORK2, REG_WORK2, REG_WORK1);
+	}
+	STR_wXi(REG_WORK2, REG_WORK3, 0);
+
+	uae_u32* branchadd2 = (uae_u32*)get_target();
+	B_i(0);
+	write_jmp_target(branchadd2, (uintptr)popall_do_nothing);
+
+	// <end>
+	write_jmp_target((uae_u32 *)branchadd, (uintptr)get_target());
+}
+
+// Optimize access to struct regstruct with and memory with fixed registers
+
+LOWFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMPTR s))
+{
+	LOAD_U64(R_REGSTRUCT, s);
+	// Load NATMEM_OFFSET via its absolute address instead of offset from regs.
+	// The old approach used LDR_xXi with offset = &NATMEM_OFFSET - &regs, but
+	// LDR_xXi silently truncates offsets >32760 bytes (12-bit field), which
+	// corrupts R27 when the global natmem_offset is far from regs in memory.
+	LOAD_U64(R_MEMSTART, (uintptr)&NATMEM_OFFSET);
+	LDR_xXi(R_MEMSTART, R_MEMSTART, 0);
+}
+LENDFUNC(NONE,NONE,1,compemu_raw_init_r_regstruct,(IMPTR s))
+
+// Handle end of compiled block
+LOWFUNC(NONE,NONE,2,compemu_raw_endblock_pc_inreg,(RR4 rr_pc, IM32 cycles))
+{
+	// countdown -= scaled_cycles(totcycles);
+	// Use absolute address for countdown (global variable, may be >32KB from regs)
+	LOAD_U64(REG_WORK3, (uintptr)&countdown);
+	LDR_wXi(REG_WORK1, REG_WORK3, 0);
+	if(cycles >= 0 && cycles <= 0xfff) {
+		SUB_wwi(REG_WORK1, REG_WORK1, cycles);
+	} else {
+		LOAD_U32(REG_WORK2, cycles);
+		SUB_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	}
+	STR_wXi(REG_WORK1, REG_WORK3, 0);
+
+	TBNZ_xii(REG_WORK1, 31, 5); // test sign and branch if set (negative)
+	UBFIZ_xxii(rr_pc, rr_pc, 0, 16);  // apply TAGMASK
+	uintptr offs = (uintptr)(&regs.cache_tags) - (uintptr)&regs;
+	LDR_xXi(REG_WORK1, R_REGSTRUCT, offs);
+	LDR_xXxLSLi(REG_WORK1, REG_WORK1, rr_pc, 3); // cacheline holds pointer -> multiply with 8
+	BR_x(REG_WORK1);
+
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);
+	write_jmp_target(branchadd, (uintptr)popall_do_nothing);
+}
+LENDFUNC(NONE,NONE,2,compemu_raw_endblock_pc_inreg,(RR4 rr_pc, IM32 cycles))
+
+STATIC_INLINE uae_u32* compemu_raw_endblock_pc_isconst(IM32 cycles, IMPTR v)
+{
+	/* v is always >= NATMEM_OFFSET and < NATMEM_OFFSET + max. Amiga mem */
+	uae_u32* tba;
+
+	// countdown -= scaled_cycles(totcycles);
+	// Use absolute address for countdown (global variable, may be >32KB from regs)
+	LOAD_U64(REG_WORK3, (uintptr)&countdown);
+	LDR_wXi(REG_WORK1, REG_WORK3, 0);
+	if(cycles >= 0 && cycles <= 0xfff) {
+		SUB_wwi(REG_WORK1, REG_WORK1, cycles);
+	} else {
+		LOAD_U32(REG_WORK2, cycles);
+		SUB_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	}
+	STR_wXi(REG_WORK1, REG_WORK3, 0);
+
+	TBNZ_xii(REG_WORK1, 31, 2); // test sign and branch if set (negative)
+	tba = (uae_u32*)get_target();
+	B_i(0); // <target set by caller>
+
+	LDR_xPCi(REG_WORK1, 12); // <v>
+	uintptr offs = (uintptr)&regs.pc_p - (uintptr)&regs;
+	STR_xXi(REG_WORK1, R_REGSTRUCT, offs);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);
+	write_jmp_target(branchadd, (uintptr)popall_do_nothing);
+
+	emit_quad(v);
+
+	return tba;
+}
+
+/*************************************************************************
+* FPU stuff                                                             *
+*************************************************************************/
+
+LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
+{
+	FMOV_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
+
+LOWFUNC(NONE,WRITE,2,compemu_raw_fmov_mr_drop,(MEMW mem, FR s))
+{
+	if(mem >= (uintptr) &regs && mem < (uintptr) &regs + 32760 && ((mem - (uintptr) &regs) & 0x7) == 0) {
+		STR_dXi(s, R_REGSTRUCT, (mem - (uintptr) &regs));
+	} else {
+		LOAD_U64(REG_WORK1, mem);
+		STR_dXi(s, REG_WORK1, 0);
+	}
+}
+LENDFUNC(NONE,WRITE,2,compemu_raw_fmov_mr_drop,(MEMW mem, FR s))
+
+LOWFUNC(NONE,READ,2,compemu_raw_fmov_rm,(FW d, MEMR mem))
+{
+	if(mem >= (uintptr) &regs && mem < (uintptr) &regs + 32760 && ((mem - (uintptr) &regs) & 0x7) == 0) {
+		LDR_dXi(d, R_REGSTRUCT, (mem - (uintptr) &regs));
+	} else {
+		LOAD_U64(REG_WORK1, mem);
+		LDR_dXi(d, REG_WORK1, 0);
+	}
+}
+LENDFUNC(NONE,READ,2,compemu_raw_fmov_rm,(FW d, MEMW mem))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_l_rr,(FW d, RR4 s))
+{
+	SCVTF_dw(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_l_rr,(FW d, RR4 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_s_rr,(FW d, RR4 s))
+{
+	FMOV_sw(SCRATCH_F64_1, s);
+	FCVT_ds(d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_s_rr,(FW d, RR4 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_w_rr,(FW d, RR2 s))
+{
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	SCVTF_dw(d, REG_WORK1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_w_rr,(FW d, RR2 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_b_rr,(FW d, RR1 s))
+{
+	SIGNED8_REG_2_REG(REG_WORK1, s);
+	SCVTF_dw(d, REG_WORK1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_b_rr,(FW d, RR1 s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+{
+	BFI_xxii(s1, s2, 32, 32);
+	FMOV_dx(d, s1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_to_l_rr,(W4 d, FR s))
+{
+	FRINTI_dd(SCRATCH_F64_1, s);
+	FCVTAS_wd(d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_to_l_rr,(W4 d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_to_s_rr,(W4 d, FR s))
+{
+	FCVT_sd(SCRATCH_F64_1, s);
+	FMOV_ws(d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_to_s_rr,(W4 d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s, int targetIsReg))
+{
+	FRINTI_dd(SCRATCH_F64_1, s);
+	FCVTAS_wd(REG_WORK1, SCRATCH_F64_1);
+
+	// maybe saturate...
+	TBZ_xii(REG_WORK1, 31, 6); // positive
+	CLS_ww(REG_WORK2, REG_WORK1); // negative: if 17 bits are 1 -> no saturate
+	SUB_wwi(REG_WORK2, REG_WORK2, 16);
+	TBZ_xii(REG_WORK2, 31, 7); // done
+	MOVK_wi(d, 0x8000); // max. negative value in 16 bit
+	B_i(6);
+
+	// positive
+	CLZ_ww(REG_WORK2, REG_WORK1); // positive: if 17 bits are 0 -> no saturate
+	SUB_wwi(REG_WORK2, REG_WORK2, 17);
+	TBZ_xii(REG_WORK2, 31, 2);
+	MOV_wi(REG_WORK1, 0x7fff); // max. positive value in 16 bit
+
+	// done
+	BFI_wwii(d, REG_WORK1, 0, 16);
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_to_w_rr,(W4 d, FR s, int targetIsReg))
+
+LOWFUNC(NONE,NONE,3,raw_fmov_to_b_rr,(W4 d, FR s, int targetIsReg))
+{
+	FRINTI_dd(SCRATCH_F64_1, s);
+	FCVTAS_wd(REG_WORK1, SCRATCH_F64_1);
+
+	// maybe saturate...
+	TBZ_xii(REG_WORK1, 31, 6); // positive
+	CLS_ww(REG_WORK2, REG_WORK1); // negative: if 25 bits are 1 -> no saturate
+	SUB_wwi(REG_WORK2, REG_WORK2, 24);
+	TBZ_xii(REG_WORK2, 31, 7); // done
+	MOV_wi(REG_WORK1, 0x80); // max. negative value in 8 bit
+	B_i(5);
+
+	// positive
+	CLZ_ww(REG_WORK2, REG_WORK1); // positive: if 25 bits are 0 -> no saturate
+	SUB_wwi(REG_WORK2, REG_WORK2, 25);
+	TBZ_xii(REG_WORK2, 31, 2);
+	MOV_wi(REG_WORK1, 0x7f); // max. positive value in 8 bit
+
+	// done
+	BFI_wwii(d, REG_WORK1, 0, 8);
+}
+LENDFUNC(NONE,NONE,3,raw_fmov_to_b_rr,(W4 d, FR s, int targetIsReg))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_0,(FW r))
+{
+	MOVI_di(r, 0);
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_0,(FW r))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_1,(FW r))
+{
+	FMOV_di(r, 0b01110000);
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_1,(FW r))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_10,(FW r))
+{
+	FMOV_di(r, 0b00100100);
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_10,(FW r))
+
+LOWFUNC(NONE,NONE,1,raw_fmov_d_ri_100,(FW r))
+{
+	MOV_wi(REG_WORK1, 100);
+	SCVTF_dw(r, REG_WORK1);
+}
+LENDFUNC(NONE,NONE,1,raw_fmov_d_ri_100,(FW r))
+
+LOWFUNC(NONE,READ,2,raw_fmov_d_rm,(FW r, MEMR m))
+{
+	LOAD_U64(REG_WORK1, m);
+	LDR_dXi(r, REG_WORK1, 0);
+}
+LENDFUNC(NONE,READ,2,raw_fmov_d_rm,(FW r, MEMR m))
+
+LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
+{
+	LOAD_U64(REG_WORK1, m);
+	LDR_sXi(r, REG_WORK1, 0);
+	FCVT_ds(r, r);
+}
+LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
+
+LOWFUNC(NONE,NONE,3,raw_fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+{
+	FMOV_xd(d1, s);
+	LSR_xxi(d2, d1, 32);
+}
+LENDFUNC(NONE,NONE,3,raw_fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+{
+	FSQRT_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+{
+	FABS_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+{
+	FNEG_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+{
+	FDIV_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+{
+	FADD_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+{
+	FMUL_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+{
+	FSUB_ddd(d, d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+{
+	FRINTI_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frndintz_rr,(FW d, FR s))
+{
+	FRINTZ_dd(d, s);
+}
+LENDFUNC(NONE,NONE,2,raw_frndintz_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmod_rr,(FRW d, FR s))
+{
+	FDIV_ddd(SCRATCH_F64_1, d, s);
+	FRINTZ_dd(SCRATCH_F64_1, SCRATCH_F64_1);
+	FMSUB_dddd(d, SCRATCH_F64_1, s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_fmod_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsgldiv_rr,(FRW d, FR s))
+{
+	FCVT_sd(SCRATCH_F64_1, d);
+	FCVT_sd(SCRATCH_F64_2, s);
+	FDIV_sss(SCRATCH_F64_1, SCRATCH_F64_1, SCRATCH_F64_2);
+	FCVT_ds(d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fsgldiv_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,1,raw_fcuts_r,(FRW r))
+{
+	FCVT_sd(SCRATCH_F64_1, r);
+	FCVT_ds(r, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,1,raw_fcuts_r,(FRW r))
+
+LOWFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+{
+	FDIV_ddd(SCRATCH_F64_2, d, s);
+	FRINTA_dd(SCRATCH_F64_2, SCRATCH_F64_2);
+	FMSUB_dddd(d, SCRATCH_F64_2, s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsglmul_rr,(FRW d, FR s))
+{
+	FCVT_sd(SCRATCH_F64_1, d);
+	FCVT_sd(SCRATCH_F64_2, s);
+	FMUL_sss(SCRATCH_F64_1, SCRATCH_F64_1, SCRATCH_F64_2);
+	FCVT_ds(d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fsglmul_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmovs_rr,(FW d, FR s))
+{
+	FCVT_sd(SCRATCH_F64_1, s);
+	FCVT_ds(d, SCRATCH_F64_1);
+}
+LENDFUNC(NONE,NONE,2,raw_fmovs_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,3,raw_ffunc_rr,(double (*func)(double), FW d, FR s))
+{
+	FMOV_dd(0, s);
+
+	LOAD_U64(REG_WORK1, (uintptr)func);
+
+	STR_xXpre(RLR_INDEX, RSP_INDEX, -16);
+	BLR_x(REG_WORK1);
+	LDR_xXpost(RLR_INDEX, RSP_INDEX, 16);
+
+	FMOV_dd(d, 0);
+}
+LENDFUNC(NONE,NONE,3,raw_ffunc_rr,(double (*func)(double), FW d, FR s))
+
+LOWFUNC(NONE,NONE,3,raw_fpowx_rr,(uae_u32 x, FW d, FR s))
+{
+	double (*func)(double,double) = pow;
+
+	if(x == 2) {
+		FMOV_di(0, 0b00000000); // load imm #2 into first reg
+	} else {
+		FMOV_di(0, 0b00100100); // load imm #10 into first reg
+	}
+
+	FMOV_dd(1, s);
+
+	LOAD_U64(REG_WORK1, (uintptr)func);
+
+	STR_xXpre(RLR_INDEX, RSP_INDEX, -16);
+	BLR_x(REG_WORK1);
+	LDR_xXpost(RLR_INDEX, RSP_INDEX, 16);
+
+	FMOV_dd(d, 0);
+}
+LENDFUNC(NONE,NONE,3,raw_fpowx_rr,(uae_u32 x, FW d, FR s))
+
+LOWFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
+{
+	FMOV_xd(REG_WORK1, s);
+	FCMP_d0(s);
+	ADD_xxx(REG_WORK4, adr, R_MEMSTART);
+
+	uae_u32* branchadd_iszero = (uae_u32*)get_target();
+	BEQ_i(0); // iszero
+
+	UBFX_xxii(REG_WORK2, REG_WORK1, 52, 11); // get exponent
+	CMP_xi(REG_WORK2, 2047);
+
+	uae_u32* branchadd_isnan = (uae_u32*)get_target();
+	BEQ_i(0); 				// isnan
+
+	MOV_xi(REG_WORK3, 15360);              	    // diff of bias between double and long double
+	ADD_xxx(REG_WORK2, REG_WORK2, REG_WORK3); 	// exponent done
+	UBFX_xxii(REG_WORK3, REG_WORK1, 63, 1);     // extract sign
+	LSL_xxi(REG_WORK3, REG_WORK3, 31);
+	ORR_xxxLSLi(REG_WORK2, REG_WORK3, REG_WORK2, 16); // merge sign and exponent
+
+	REV32_xx(REG_WORK2, REG_WORK2);
+	STRH_wXi(REG_WORK2, REG_WORK4, 0);         	// write exponent
+	ADD_xxi(REG_WORK4, REG_WORK4, 4);
+
+	LSL_xxi(REG_WORK1, REG_WORK1, 11);          // shift mantissa to correct position
+	REV_xx(REG_WORK1, REG_WORK1);
+	SET_xxbit(REG_WORK1, REG_WORK1, 7);        // insert explicit 1
+	STR_xXi(REG_WORK1, REG_WORK4, 0);
+	uae_u32* branchadd_end = (uae_u32*)get_target();
+	B_i(0);            // end_of_op
+
+	// isnan
+	write_jmp_target(branchadd_isnan, (uintptr)get_target());
+	MOV_xish(REG_WORK1, 0x7fff, 16);
+	MOVN_xi(REG_WORK2, 0);
+	B_i(4);
+
+	// iszero
+	write_jmp_target(branchadd_iszero, (uintptr)get_target());
+	UBFX_xxii(REG_WORK1, REG_WORK1, 63, 1);     // extract sign
+	LSL_xxi(REG_WORK1, REG_WORK1, 31);
+	MOV_xi(REG_WORK2, 0);
+
+	REV32_xx(REG_WORK1, REG_WORK1);
+	STR_wXi(REG_WORK1, REG_WORK4, 0);
+	STP_wwXi(REG_WORK2, REG_WORK2, REG_WORK4, 4);
+
+	// end_of_op
+	write_jmp_target(branchadd_end, (uintptr)get_target());
+}
+LENDFUNC(NONE,WRITE,2,raw_fp_from_exten_mr,(RR4 adr, FR s))
+
+LOWFUNC(NONE,READ,2,raw_fp_to_exten_rm,(FW d, RR4 adr))
+{
+	ADD_xxx(REG_WORK3, adr, R_MEMSTART);
+
+	ADD_xxi(REG_WORK1, REG_WORK3, 4);
+	LDR_xXi(REG_WORK1, REG_WORK1, 0);
+	CLEAR_xxbit(REG_WORK1, REG_WORK1, 7); 	// clear explicit 1
+	REV_xx(REG_WORK1, REG_WORK1);
+
+	LDRH_wXi(REG_WORK4, REG_WORK3, 0);
+	REV16_xx(REG_WORK4, REG_WORK4);				// exponent now in lower half
+
+	ANDS_xx7fff(REG_WORK2, REG_WORK4);
+	uae_u32* branchadd_notzero = (uae_u32*)get_target();
+	BNE_i(0);				// not_zero
+
+	uae_u32* branchadd_notzero2 = (uae_u32*)get_target();
+	CBNZ_xi(REG_WORK1, 0);          // not zero
+
+	// zero
+	MOVI_di(d, 0);
+	uae_u32* branchadd_end = (uae_u32*)get_target();
+	TBZ_xii(REG_WORK4, 15, 0); // end_of_op
+	MOV_xish(REG_WORK1, 0x8000, 48);
+	FMOV_dx(d, REG_WORK1);
+	uae_u32* branchadd_end2 = (uae_u32*)get_target();
+	B_i(0);					// end_of_op
+
+	// not_zero
+	write_jmp_target(branchadd_notzero, (uintptr)get_target());
+	write_jmp_target(branchadd_notzero2, (uintptr)get_target());
+	MOV_xi(REG_WORK3, 15360);                 // diff of bias between double and long double
+	SUB_xxx(REG_WORK2, REG_WORK2, REG_WORK3);	// exponent done, ToDo: check for carry -> result gets Inf in double
+	UBFX_xxii(REG_WORK4, REG_WORK4, 15, 1);		// extract sign
+	BFI_xxii(REG_WORK2, REG_WORK4, 11, 1);		// insert sign
+	LSR_xxi(REG_WORK1, REG_WORK1, 11);				// shift mantissa to correct position
+	LSL_xxi(REG_WORK2, REG_WORK2, 52);
+	ORR_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+	FMOV_dx(d, REG_WORK1);
+
+	// end_of_op
+	write_jmp_target(branchadd_end, (uintptr)get_target());
+	write_jmp_target(branchadd_end2, (uintptr)get_target());
+}
+LENDFUNC(NONE,READ,2,raw_fp_to_exten_rm,(FW d, RR4 adr))
+
+LOWFUNC(NONE,WRITE,2,raw_fp_from_double_mr,(RR4 adr, FR s))
+{
+	REV64_dd(SCRATCH_F64_1, s);
+	STR_dXx(SCRATCH_F64_1, adr, R_MEMSTART);
+}
+LENDFUNC(NONE,WRITE,2,raw_fp_from_double_mr,(RR4 adr, FR s))
+
+LOWFUNC(NONE,READ,2,raw_fp_to_double_rm,(FW d, RR4 adr))
+{
+	LDR_dXx(d, adr, R_MEMSTART);
+	REV64_dd(d, d);
+}
+LENDFUNC(NONE,READ,2,raw_fp_to_double_rm,(FW d, RR4 adr))
+
+STATIC_INLINE void raw_fflags_into_flags(int r)
+{
+	FCMP_d0(r);
+}
+
+LOWFUNC(NONE,NONE,2,raw_fp_fscc_ri,(RW4 d, int cc))
+{
+	switch (cc) {
+		case NATIVE_CC_F_NEVER:
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_NE: // Set if not equal
+			CSETM_wc(REG_WORK1, NATIVE_CC_NE);
+			BFXIL_xxii(d, REG_WORK1, 0, 8);
+			break;
+
+		case NATIVE_CC_EQ: // Set if equal
+			CSETM_wc(REG_WORK1, NATIVE_CC_EQ);
+			BFXIL_xxii(d, REG_WORK1, 0, 8);
+			break;
+
+		case NATIVE_CC_F_OGT: // Set if valid and greater than
+			BVS_i(4);		// do not set if NaN
+			BLE_i(3);		// do not set if less or equal
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_OGE: // Set if valid and greater or equal
+			BVS_i(4);		// do not set if NaN
+			BCC_i(3);		// do not set if carry cleared
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_OLT: // Set if vaild and less than
+			BVS_i(4);		// do not set if NaN
+			BCS_i(3);		// do not set if carry set
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_OLE: // Set if valid and less or equal
+			BVS_i(4);		// do not set if NaN
+			BGT_i(3);		// do not set if greater than
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_OGL: // Set if valid and greator or less
+			BVS_i(4);		// do not set if NaN
+			BEQ_i(3);		// do not set if equal
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_OR: // Set if valid
+			CSETM_wc(REG_WORK1, NATIVE_CC_VC);    // do not set if NaN
+			BFXIL_xxii(d, REG_WORK1, 0, 8);
+			break;
+
+		case NATIVE_CC_F_UN: // Set if NAN
+			CSETM_wc(REG_WORK1, NATIVE_CC_VS);    // do not set if valid
+			BFXIL_xxii(d, REG_WORK1, 0, 8);
+			break;
+
+		case NATIVE_CC_F_UEQ: // Set if NAN or equal
+			BVS_i(2); 	// set if NaN
+			BNE_i(3);		// do not set if greater or less
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_UGT: // Set if NAN or greater than
+			BVS_i(2); 	// set if NaN
+			BLS_i(3);		// do not set if lower or same
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_UGE: // Set if NAN or greater or equal
+			BVS_i(2); 	// set if NaN
+			BMI_i(3);		// do not set if lower
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_ULT: // Set if NAN or less than
+			BVS_i(2); 	// set if NaN
+			BGE_i(3);		// do not set if greater or equal
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+
+		case NATIVE_CC_F_ULE: // Set if NAN or less or equal
+			BVS_i(2); 	// set if NaN
+			BGT_i(3);		// do not set if greater
+			SET_LOW8_xx(d, d);
+			B_i(2);
+			CLEAR_LOW8_xx(d, d);
+			break;
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fp_fscc_ri,(RW4 d, int cc))
diff --git a/jit/arm/codegen_arm64.h b/jit/arm/codegen_arm64.h
new file mode 100644
index 00000000..a94000ae
--- /dev/null
+++ b/jit/arm/codegen_arm64.h
@@ -0,0 +1,493 @@
+/*
+ * compiler/codegen_armA64.h - AARCH64 code generator
+ *
+ * Copyright (c) 2019 TomB
+ *
+ * This file is part of the UAE4ARM project.
+ *
+ * JIT compiler m68k -> ARMv8.1
+ *
+ * Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ * This file is derived from CCG, copyright 1999-2003 Ian Piumarta
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef ARM_ASMA64_H
+#define ARM_ASMA64_H
+
+
+/* CPSR flags */
+
+#define ARM_N_FLAG        0x80000000
+#define ARM_Z_FLAG        0x40000000
+#define ARM_C_FLAG        0x20000000
+#define ARM_V_FLAG        0x10000000
+#define ARM_CV_FLAGS      (ARM_C_FLAG|ARM_V_FLAG)
+
+
+#define _W(c) emit_long(c)
+
+
+#define MIN_EL0           0b011
+
+#define EX_UXTB   0b000
+#define EX_UXTH   0b001
+#define EX_UXTW   0b010
+#define EX_UXTX   0b011
+#define EX_SXTB   0b100
+#define EX_SXTH   0b101
+#define EX_SXTW   0b110
+#define EX_SXTX   0b111
+
+#define immEncode(N,immr,imms)    (N << 22) | (immr << 16) | (imms << 10)
+
+
+/* read/write flags */
+// move from sysreg
+#define MRS_NZCV_x(Xt)    _W((0b1101010100111 << 19) | (MIN_EL0 << 16) | (0b0100 << 12) | (0b0010 << 8) | (0b000 << 5) | (Xt))
+#define MRS_FPCR_x(Xt)    _W((0b1101010100111 << 19) | (MIN_EL0 << 16) | (0b0100 << 12) | (0b0100 << 8) | (0b000 << 5) | (Xt))
+// move to sysreg
+#define MSR_NZCV_x(Xt)		_W((0b1101010100011 << 19) | (MIN_EL0 << 16) | (0b0100 << 12) | (0b0010 << 8) | (0b000 << 5) | (Xt))
+#define MSR_FPCR_x(Xt)    _W((0b1101010100011 << 19) | (MIN_EL0 << 16) | (0b0100 << 12) | (0b0100 << 8) | (0b000 << 5) | (Xt))
+
+
+/*----------------------------------------
+ * branch instructions
+ *----------------------------------------*/
+// i is the number of instructions, i.e. 4 bytes
+#define B_i(i)            _W((0b000101 << 26) | ((i) & 0x03ffffff))
+#define BL_i(i)           _W((0b100101 << 26) | ((i) & 0x03ffffff))
+#define BLR_x(Xn)         _W((0b11010110001 << 21) | (0b11111 << 16) | (0 << 10) | ((Xn) << 5) | 0)
+#define BR_x(Xn)          _W((0b11010110000 << 21) | (0b11111 << 16) | (0 << 10) | ((Xn) << 5) | 0)
+
+#define CC_B_i(cc,i)      _W((0b01010100 << 24) | (((i) & 0x0007ffff) << 5) | (cc))
+#define BEQ_i(i)          CC_B_i(NATIVE_CC_EQ,i)
+#define BNE_i(i)          CC_B_i(NATIVE_CC_NE,i)
+#define BCS_i(i)          CC_B_i(NATIVE_CC_CS,i)
+#define BCC_i(i)          CC_B_i(NATIVE_CC_CC,i)
+#define BMI_i(i)          CC_B_i(NATIVE_CC_MI,i)
+#define BPL_i(i)          CC_B_i(NATIVE_CC_PL,i)
+#define BVS_i(i)          CC_B_i(NATIVE_CC_VS,i)
+#define BVC_i(i)          CC_B_i(NATIVE_CC_VC,i)
+#define BHI_i(i)          CC_B_i(NATIVE_CC_HI,i)
+#define BLS_i(i)          CC_B_i(NATIVE_CC_LS,i)
+#define BGE_i(i)          CC_B_i(NATIVE_CC_GE,i)
+#define BLT_i(i)          CC_B_i(NATIVE_CC_LT,i)
+#define BGT_i(i)          CC_B_i(NATIVE_CC_GT,i)
+#define BLE_i(i)          CC_B_i(NATIVE_CC_LE,i)
+
+#define RET               _W((0b11010110010 << 21) | (0b11111 << 16) | (0 << 10) | ((30) << 5) | (0))
+
+/* compare and branch */
+// these instructions do not affect condition flags
+#define CBNZ_wi(Wt,i)       _W((0b00110101 << 24) | (((i) & 0x0007ffff) << 5) | (Wt))
+#define CBNZ_xi(Xt,i)       _W((0b10110101 << 24) | (((i) & 0x0007ffff) << 5) | (Xt))
+#define CBZ_wi(Wt,i)        _W((0b00110100 << 24) | (((i) & 0x0007ffff) << 5) | (Wt))
+#define CBZ_xi(Xt,i)        _W((0b10110100 << 24) | (((i) & 0x0007ffff) << 5) | (Xt))
+
+/* test bit and branch */
+// these instructions do not affect condition flags
+#define TBNZ_xii(Xt,bit,i)  _W(((((bit) & 0x20) >> 5) << 31) | (0b0110111 << 24) | (((bit) & 0x1f) << 19) | ((((i)) % 0x3fff) << 5) | (Xt))
+#define TBNZ_wii(Wt,bit,i)  _W((0 << 31) | (0b0110111 << 24) | (((bit) & 0x1f) << 19) | ((((i)) % 0x3fff) << 5) | (Wt))
+#define TBZ_xii(Xt,bit,i)   _W(((((bit) & 0x20) >> 5) << 31) | (0b0110110 << 24) | (((bit) & 0x1f) << 19) | ((((i)) % 0x3fff) << 5) | (Xt))
+#define TBZ_wii(Wt,bit,i)   _W((0 << 31) | (0b0110110 << 24) | (((bit) & 0x1f) << 19) | ((((i)) % 0x3fff) << 5) | (Wt))
+
+
+/*----------------------------------------
+ * load/store registers
+ *---------------------------------------- */
+// i is number of bytes
+#define LDP_wwXi(Wt1,Wt2,Xn,i)    _W((0b0010100101 << 22) | ((((i)/4) & 0x7f) << 15) | ((Wt2) << 10) | ((Xn) << 5) | (Wt1))
+#define LDP_xxXi(Xt1,Xt2,Xn,i)    _W((0b1010100101 << 22) | ((((i)/8) & 0x7f) << 15) | ((Xt2) << 10) | ((Xn) << 5) | (Xt1))
+#define LDP_xxXpost(Xt1,Xt2,Xn,i) _W((0b1010100011 << 22) | ((((i)/8) & 0x7f) << 15) | ((Xt2) << 10) | ((Xn) << 5) | (Xt1))
+#define LDR_wXi(Wt,Xn,i)          _W((0b1011100101 << 22) | ((((i)/4) & 0xfff) << 10) | ((Xn) << 5) | (Wt))
+#define LDR_xXi(Xt,Xn,i)          _W((0b1111100101 << 22) | ((((i)/8) & 0xfff) << 10) | ((Xn) << 5) | (Xt))
+#define LDR_xXpost(Xt,Xn,i)       _W((0b11111000010 << 21) | (((i) & 0x1ff) << 12) | (0b01 << 10) | ((Xn) << 5) | (Xt))
+#define LDR_wPCi(Wt,i)            _W((0b00011000 << 24) | ((((i)/4) & 0x7ffff) << 5) | (Wt))
+#define LDR_xPCi(Xt,i)            _W((0b01011000 << 24) | ((((i)/4) & 0x7ffff) << 5) | (Xt))
+/* JIT direct memory helpers pass (addr_reg, R_MEMSTART).
+ * Use UXTW to zero-extend 32-bit M68k addresses to 64-bit host offsets.
+ * SXTW was used historically when natmem lived at 0x80000000, but sign-extending
+ * addresses with bit 31 set wraps BELOW natmem on platforms where natmem > 2GB
+ * (e.g., macOS ARM64 at 0x300000000), causing SIGBUS. */
+#define LDR_wXx(Wt,Xn,Xm)         _W((0b10111000011 << 21) | ((Xn) << 16) | (EX_UXTW << 13) | (0 << 12) | (0b10 << 10) | ((Xm) << 5) | (Wt))
+#define LDR_xXx(Xt,Xn,Xm)         _W((0b11111000011 << 21) | ((Xm) << 16) | (0b011 << 13) | (0 << 12) | (0b10 << 10) | ((Xn) << 5) | (Xt))
+// i=0 no shift, i=1 LSL 2 (W) or LSL 3 (X)
+#define LDR_wXxLSLi(Wt,Xn,Xm,i)   _W((0b10111000011 << 21) | ((Xm) << 16) | (0b011 << 13) | (((i)&1) << 12) | (0b10 << 10) | ((Xn) << 5) | (Wt))
+#define LDR_xXxLSLi(Xt,Xn,Xm,i)   _W((0b11111000011 << 21) | ((Xm) << 16) | (0b011 << 13) | (((i)&1) << 12) | (0b10 << 10) | ((Xn) << 5) | (Xt))
+#define LDRB_wXi(Wt,Xn,i)         _W((0b0011100101 << 22) | (((i) & 0xfff) << 10) | ((Xn) << 5) | (Wt))
+#define LDRB_wXx(Wt,Xn,Xm)        _W((0b00111000011 << 21) | ((Xn) << 16) | (EX_UXTW << 13) | (0 << 12) | (0b10 << 10) | ((Xm) << 5) | (Wt))
+#define LDRH_wXi(Wt,Xn,i)         _W((0b0111100101 << 22) | ((((i)/2) &0xfff) << 10) | ((Xn) << 5) | (Wt))
+#define LDRH_wXx(Wt,Xn,Xm)        _W((0b01111000011 << 21) | ((Xn) << 16) | (EX_UXTW << 13) | (0 << 12) | (0b10 << 10) | ((Xm) << 5) | (Wt))
+
+#define STP_wwXi(Wt1,Wt2,Xn,i)    _W((0b0010100100 << 22) | ((((i)/4) & 0x7f) << 15) | ((Wt2) << 10) | ((Xn) << 5) | (Wt1))
+#define STP_xxXi(Xt1,Xt2,Xn,i)    _W((0b1010100100 << 22) | ((((i)/8) & 0x7f) << 15) | ((Xt2) << 10) | ((Xn) << 5) | (Xt1))
+#define STP_xxXpre(Xt1,Xt2,Xn,i)  _W((0b1010100110 << 22) | ((((i)/8) & 0x7f) << 15) | ((Xt2) << 10) | ((Xn) << 5) | (Xt1))
+#define STR_wXi(Wt,Xn,i)          _W((0b1011100100 << 22) | ((((i)/4) & 0xfff) << 10) | ((Xn) << 5) | (Wt))
+#define STR_xXi(Xt,Xn,i)          _W((0b1111100100 << 22) | ((((i)/8) & 0xfff) << 10) | ((Xn) << 5) | (Xt))
+#define STR_xXpre(Xt,Xn,i)        _W((0b11111000000 << 21) | (((i) & 0x1ff) << 12) | (0b11 << 10) | ((Xn) << 5) | (Xt))
+#define STR_wXx(Wt,Xn,Xm)         _W((0b10111000001 << 21) | ((Xn) << 16) | (EX_UXTW << 13) | (0 << 12) | (0b10 << 10) | ((Xm) << 5) | (Wt))
+#define STR_xXx(Xt,Xn,Xm)         _W((0b11111000001 << 21) | ((Xm) << 16) | (0b011 << 13) | (0 << 12) | (0b10 << 10) | ((Xn) << 5) | (Xt))
+// i=0 no shift, i=1 LSL 2 (W) or LSL 3 (X)
+#define STR_wXxLSLi(Wt,Xn,Xm,i)   _W((0b10111000001 << 21) | ((Xm) << 16) | (0b011 << 13) | (((i)&1) << 12) | (0b10 << 10) | ((Xn) << 5) | (Wt))
+#define STRB_wXi(Wt,Xn,i)         _W((0b0011100100 << 22) | (((i) & 0xfff) << 10) | ((Xn) << 5) | (Wt))
+#define STRB_wXx(Wt,Xn,Xm)        _W((0b00111000001 << 21) | ((Xn) << 16) | (EX_UXTW << 13) | (0 << 12) | (0b10 << 10) | ((Xm) << 5) | (Wt))
+#define STRH_wXi(Wt,Xn,i)         _W((0b0111100100 << 22) | ((((i)/2) &0xfff) << 10) | ((Xn) << 5) | (Wt))
+#define STRH_wXx(Wt,Xn,Xm)        _W((0b01111000001 << 21) | ((Xn) << 16) | (EX_UXTW << 13) | (0 << 12) | (0b10 << 10) | ((Xm) << 5) | (Wt))
+
+#define STUR_wXi(Wt,Xn,i)         _W((0b10111000000 << 21) | ((i & 0x1ff) << 12) | ((Xn) << 5) | (Wt))
+#define STURH_wXi(Wt,Xn,i)        _W((0b01111000000 << 21) | ((i & 0x1ff) << 12) | ((Xn) << 5) | (Wt))
+
+/*----------------------------------------
+ * move immediate/register
+ *----------------------------------------*/
+#define MOV_wi(Wd,i16)            _W((0b01010010100 << 21) | (((i16) & 0xffff) << 5) | (Wd))
+#define MOV_xi(Xd,i16)            _W((0b11010010100 << 21) | (((i16) & 0xffff) << 5) | (Xd))
+// sh in bits (multiple of 16)
+#define MOV_wish(Wd,i16,sh)       _W((0b010100101 << 23) | (((sh)/16) << 21) | (((i16) & 0xffff) << 5) | (Wd))
+#define MOV_xish(Xd,i16,sh)       _W((0b110100101 << 23) | (((sh)/16) << 21) | (((i16) & 0xffff) << 5) | (Xd))
+#define MOV_ww(Wd,Wm)             _W((0b00101010000 << 21) | ((Wm) << 16) | (0 << 10) | (0b11111 << 5) | (Wd))
+#define MOV_xx(Xd,Xm)             _W((0b10101010000 << 21) | ((Xm) << 16) | (0 << 10) | (0b11111 << 5) | (Xd))
+#define MOVK_wi(Wd,i16)           _W((0b01110010100 << 21) | (((i16) & 0xffff) << 5) | (Wd))
+#define MOVK_xi(Xd,i16)           _W((0b11110010100 << 21) | (((i16) & 0xffff) << 5) | (Xd))
+#define MOVK_wish(Wd,i16,sh)      _W((0b011100101 << 23) | (((sh)/16) << 21) | (((i16) & 0xffff) << 5) | (Wd))
+#define MOVK_xish(Xd,i16,sh)      _W((0b111100101 << 23) | (((sh)/16) << 21) | (((i16) & 0xffff) << 5) | (Xd))
+#define MOVN_wi(Wd,i16)           _W((0b00010010100 << 21) | (((i16) & 0xffff) << 5) | (Wd))
+#define MOVN_xi(Xd,i16)           _W((0b10010010100 << 21) | (((i16) & 0xffff) << 5) | (Xd))
+#define MOVN_wish(Wd,i16,sh)      _W((0b000100101 << 23) | (((sh)/16) << 21) | (((i16) & 0xffff) << 5) | (Wd))
+#define MOVN_xish(Xd,i16,sh)      _W((0b100100101 << 23) | (((sh)/16) << 21) | (((i16) & 0xffff) << 5) | (Xd))
+#define MVN_ww(Wd,Wm)             _W((0b00101010001 << 21) | ((Wm) << 16) | (0 << 10) | (0b11111 << 5) | (Wd))
+#define MVN_xx(Xd,Xm)             _W((0b10101010001 << 21) | ((Xm) << 16) | (0 << 10) | (0b11111 << 5) | (Xd))
+
+
+/*----------------------------------------
+ * arithmetic
+ *----------------------------------------*/
+/* ADD */
+#define ADC_www(Wd,Wn,Wm)         _W((0b00011010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ADC_xxx(Xd,Xn,Xm)         _W((0b10011010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ADCS_www(Wd,Wn,Wm)        _W((0b00111010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ADCS_xxx(Xd,Xn,Xm)        _W((0b10111010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ADD_wwwEX(Wd,Wn,Wm,ex)    _W((0b00001011001 << 21) | ((Wm) << 16) | ((ex) << 13) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ADD_xxwEX(Xd,Xn,Wm,ex)    _W((0b10001011001 << 21) | ((Wm) << 16) | ((ex) << 13) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ADD_wwi(Wd,Wn,i12)        _W((0b0001000100 << 22) | (((i12) & 0xfff) << 10) | ((Wn) << 5) | (Wd))
+#define ADD_xxi(Xd,Xn,i12)        _W((0b1001000100 << 22) | (((i12) & 0xfff) << 10) | ((Xn) << 5) | (Xd))
+#define ADD_www(Wd,Wn,Wm)         _W((0b00001011000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ADD_xxx(Xd,Xn,Xm)         _W((0b10001011000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ADD_wwwLSLi(Wd,Wn,Wm,i)   _W((0b00001011000 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define ADD_xxxLSLi(Xd,Xn,Xm,i)   _W((0b10001011000 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define ADDS_wwi(Wd,Wn,i12)       _W((0b0011000100 << 22) | (((i12) & 0xfff) << 10) | ((Wn) << 5) | (Wd))
+#define ADDS_xxi(Xd,Xn,i12)       _W((0b1011000100 << 22) | (((i12) & 0xfff) << 10) | ((Xn) << 5) | (Xd))
+#define ADDS_www(Wd,Wn,Wm)        _W((0b00101011000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ADDS_xxx(Xd,Xn,Xm)        _W((0b10101011000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ADDS_wwwLSLi(Wd,Wn,Wm,i)  _W((0b00101011000 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define ADDS_xxxLSLi(Xd,Xn,Xm,i)  _W((0b10101011000 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+/* compare */
+#define CMP_wi(Wn,i12)            _W((0b0111000100 << 22) | (((i12) & 0xfff) << 10) | ((Wn) << 5) | (0b11111))
+#define CMP_xi(Xn,i12)            _W((0b1111000100 << 22) | (((i12) & 0xfff) << 10) | ((Xn) << 5) | (0b11111))
+#define CMP_ww(Wn,Wm)             _W((0b01101011000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (0b11111))
+#define CMP_xx(Xn,Xm)             _W((0b11101011000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (0b11111))
+#define CMP_wwLSLi(Wn,Wm,i)       _W((0b01101011000 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (0b11111))
+#define CMP_xxLSLi(Xn,Xm,i)       _W((0b11101011000 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (0b11111))
+#define CMP_wwEX(Wn,Wm,ex)        _W((0b01101011001 << 21) | ((Wm) << 16) | ((ex) << 13) | (0 << 10) | ((Wn) << 5) | (0b11111))
+
+/* MUL */
+#define MUL_www(Wd,Wn,Wm)         _W((0b00011011000 << 21) | ((Wm) << 16) | (0b011111 << 10) | ((Wn) << 5) | (Wd))
+#define MUL_xxx(Xd,Xn,Xm)         _W((0b10011011000 << 21) | ((Xm) << 16) | (0b011111 << 10) | ((Xn) << 5) | (Xd))
+// Xd = (Xn*Xm)[127...64]
+#define SMULH_xxx(Xd,Xn,Xm)       _W((0b10011011010 << 21) | ((Xm) << 16) | (0b011111 << 10) | ((Xn) << 5) | (Xd))
+#define UMULH_xxx(Xd,Xn,Xm)       _W((0b10011011110 << 21) | ((Xm) << 16) | (0b011111 << 10) | ((Xn) << 5) | (Xd))
+// Xd = (Wn*Wm)[63...0]
+#define SMULL_xww(Xd,Wn,Wm)       _W((0b10011011001 << 21) | ((Wm) << 16) | (0b011111 << 10) | ((Wn) << 5) | (Xd))
+#define UMULL_xww(Xd,Wn,Wm)       _W((0b10011011101 << 21) | ((Wm) << 16) | (0b011111 << 10) | ((Wn) << 5) | (Xd))
+
+/* multiply sub */
+// Wd = Wa - (Wn * Wm)
+#define MSUB_wwww(Wd,Wn,Wm,Wa)    _W((0b00011011000 << 21) | ((Wm) << 16) | (1 << 15) | ((Wa) << 10) | ((Wn) << 5) | (Wd))
+#define MSUB_xxxx(Xd,Xn,Xm,Xa)    _W((0b10011011000 << 21) | ((Xm) << 16) | (1 << 15) | ((Xa) << 10) | ((Xn) << 5) | (Xd))
+
+/* DIV */
+// Wd = Wn / Wm
+#define SDIV_www(Wd,Wn,Wm)        _W((0b00011010110 << 21) | ((Wm) << 16) | (0b000011 << 10) | ((Wn) << 5) | (Wd))
+#define SDIV_xxx(Xd,Xn,Xm)        _W((0b10011010110 << 21) | ((Xm) << 16) | (0b000011 << 10) | ((Xn) << 5) | (Xd))
+#define UDIV_www(Wd,Wn,Wm)        _W((0b00011010110 << 21) | ((Wm) << 16) | (0b000010 << 10) | ((Wn) << 5) | (Wd))
+#define UDIV_xxx(Xd,Xn,Xm)        _W((0b10011010110 << 21) | ((Xm) << 16) | (0b000010 << 10) | ((Xn) << 5) | (Xd))
+
+/* NEG */
+#define NEG_ww(Wd,Wm)             _W((0b01001011000 << 21) | ((Wm) << 16) | (0 << 10) | (0b11111 << 5) | (Wd))
+#define NEG_xx(Xd,Xm)             _W((0b11001011000 << 21) | ((Xm) << 16) | (0 << 10) | (0b11111 << 5) | (Xd))
+#define NEGS_ww(Wd,Wm)            _W((0b01101011000 << 21) | ((Wm) << 16) | (0 << 10) | (0b11111 << 5) | (Wd))
+#define NEGS_xx(Xd,Xm)            _W((0b11101011000 << 21) | ((Xm) << 16) | (0 << 10) | (0b11111 << 5) | (Xd))
+#define NGC_ww(Wd,Wm)             _W((0b01011010000 << 21) | ((Wm) << 16) | (0 << 10) | (0b11111 << 5) | (Wd))
+#define NGC_xx(Xd,Xm)             _W((0b11011010000 << 21) | ((Xm) << 16) | (0 << 10) | (0b11111 << 5) | (Xd))
+#define NGCS_ww(Wd,Wm)            _W((0b01111010000 << 21) | ((Wm) << 16) | (0 << 10) | (0b11111 << 5) | (Wd))
+#define NGCS_xx(Xd,Xm)            _W((0b11111010000 << 21) | ((Xm) << 16) | (0 << 10) | (0b11111 << 5) | (Xd))
+
+/* SUB */
+// Wd = Wn - Wm
+#define SBC_www(Wd,Wn,Wm)         _W((0b01011010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define SBC_xxx(Xd,Xn,Xm)         _W((0b11011010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define SBCS_www(Wd,Wn,Wm)        _W((0b01111010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define SBCS_xxx(Xd,Xn,Xm)        _W((0b11111010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define SUB_wwi(Wd,Wn,i12)        _W((0b0101000100 << 22) | (((i12) & 0xfff) << 10) | ((Wn) << 5) | (Wd))
+#define SUB_xxi(Xd,Xn,i12)        _W((0b1101000100 << 22) | (((i12) & 0xfff) << 10) | ((Xn) << 5) | (Xd))
+#define SUB_www(Wd,Wn,Wm)         _W((0b01001011000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define SUB_xxx(Xd,Xn,Xm)         _W((0b11001011000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define SUB_wwwEX(Wd,Wn,Wm,ex)    _W((0b11001011001 << 21) | ((Wm) << 16) | ((ex) << 13) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define SUBS_wwi(Wd,Wn,i12)       _W((0b0111000100 << 22) | (((i12) & 0xfff) << 10) | ((Wn) << 5) | (Wd))
+#define SUBS_xxi(Xd,Xn,i12)       _W((0b1111000100 << 22) | (((i12) & 0xfff) << 10) | ((Xn) << 5) | (Xd))
+// sh: 0 - no shift, 1 - LSL 12
+#define SUBS_wwish(Wd,Wn,i12,sh)  _W((0b011100010 << 23) | (((sh) & 1) << 22) | (((i12) & 0xfff) << 10) | ((Wn) << 5) | (Wd))
+#define SUBS_xxish(Xd,Xn,i12,sh)  _W((0b111100010 << 23) | (((sh) & 1) << 22) | (((i12) & 0xfff) << 10) | ((Xn) << 5) | (Xd))
+#define SUBS_www(Wd,Wn,Wm)        _W((0b01101011000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define SUBS_xxx(Xd,Xn,Xm)        _W((0b11101011000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define SUBS_wwwLSLi(Wd,Wn,Wm,i)  _W((0b01101011000 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define SUBS_xxxLSLi(Xd,Xn,Xm,i)  _W((0b11101011000 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+/* signed extend */
+#define SBFM_wwii(Wd,Wn,immr,imms)  _W((0b0001001100 << 22) | ((immr) << 16) | ((imms) << 10) | ((Wn) << 5) | (Wd))
+#define SBFM_xxii(Xd,Xn,immr,imms)  _W((0b1001001101 << 22) | ((immr) << 16) | ((imms) << 10) | ((Xn) << 5) | (Xd))
+#define SXTB_ww(Wd,Wn)              SBFM_wwii(Wd,Wn,0,7)
+#define SXTB_xx(Xd,Xn)              SBFM_xxii(Xd,Xn,0,7)
+#define SXTH_ww(Wd,Wn)              SBFM_wwii(Wd,Wn,0,15)
+#define SXTH_xx(Xd,Xn)              SBFM_xxii(Xd,Xn,0,15)
+#define SXTW_xw(Xd,Wn)              SBFM_xxii(Xd,Wn,0,31)
+
+/* unsigned extend */
+#define UBFM_wwii(Wd,Wn,immr,imms)  _W((0b0101001100 << 22) | ((immr) << 16) | ((imms) << 10) | ((Wn) << 5) | (Wd))
+#define UBFM_xxii(Xd,Xn,immr,imms)  _W((0b1101001101 << 22) | ((immr) << 16) | ((imms) << 10) | ((Xn) << 5) | (Xd))
+#define UXTB_ww(Wd,Wn)              UBFM_wwii(Wd,Wn,0,7)
+#define UXTB_xx(Xd,Xn)              UBFM_xxii(Xd,Xn,0,7)
+#define UXTH_ww(Wd,Wn)              UBFM_wwii(Wd,Wn,0,15)
+#define UXTH_xx(Xd,Xn)              UBFM_xxii(Xd,Xn,0,15)
+
+
+/*----------------------------------------
+ * logical
+ *----------------------------------------*/
+/* AND */
+#define AND_www(Wd,Wn,Wm)         _W((0b00001010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define AND_xxx(Xd,Xn,Xm)         _W((0b10001010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define AND_xx1f(Xd,Xn)           _W((0b100100100 << 23) | immEncode(1,0b000000,0b000100) | ((Xn) << 5) | (Xd))
+#define AND_ww3f(Wd,Wn)           _W((0b000100100 << 23) | immEncode(0,0b000000,0b000101) | ((Wn) << 5) | (Wd))
+#define AND_ww1f(Wd,Wn)           _W((0b000100100 << 23) | immEncode(0,0b000000,0b000100) | ((Wn) << 5) | (Wd))
+#define ANDS_www(Wd,Wn,Wm)        _W((0b01101010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ANDS_xxx(Xd,Xn,Xm)        _W((0b11101010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ANDS_xx7fff(Xd,Xn)        _W((0b111100100 << 23) | immEncode(1,0b000000,0b001110) | ((Xn) << 5) | (Xd))
+#define ANDS_xx1f(Xd,Xn)          _W((0b111100100 << 23) | immEncode(1,0b000000,0b000100) | ((Xn) << 5) | (Xd))
+#define ANDS_ww7f(Wd,Wn)          _W((0b011100100 << 23) | immEncode(0,0b000000,0b000110) | ((Wn) << 5) | (Wd))
+#define ANDS_ww3f(Wd,Wn)          _W((0b011100100 << 23) | immEncode(0,0b000000,0b000101) | ((Wn) << 5) | (Wd))
+#define ANDS_ww1f(Wd,Wn)          _W((0b011100100 << 23) | immEncode(0,0b000000,0b000100) | ((Wn) << 5) | (Wd))
+
+/* EOR */
+#define EOR_www(Wd,Wn,Wm)         _W((0b01001010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define EOR_xxx(Xd,Xn,Xm)         _W((0b11001010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define EOR_wwwLSLi(Wd,Wn,Wm,i)   _W((0b01001010000 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define EOR_xxxLSLi(Xd,Xn,Xm,i)   _W((0b11001010000 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+/* ORR */
+#define ORR_www(Wd,Wn,Wm)         _W((0b00101010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define ORR_xxx(Xd,Xn,Xm)         _W((0b10101010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+#define ORR_wwwLSLi(Wd,Wn,Wm,i)   _W((0b00101010000 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define ORR_xxxLSLi(Xd,Xn,Xm,i)   _W((0b10101010000 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define ORR_wwwLSRi(Wd,Wn,Wm,i)   _W((0b00101010010 << 21) | ((Wm) << 16) | (((i) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define ORR_xxxLSRi(Xd,Xn,Xm,i)   _W((0b10101010010 << 21) | ((Xm) << 16) | (((i) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+/* TST */
+#define TST_ww(Wn,Wm)             _W((0b01101010000 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (0b11111))
+#define TST_xx(Xn,Xm)             _W((0b11101010000 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (0b11111))
+
+
+/*----------------------------------------
+ * shift
+ *----------------------------------------*/
+#define ASR_www(Wd,Wn,Wm)         _W((0b00011010110 << 21) | ((Wm) << 16) | (0b001010 << 10) | ((Wn) << 5) | (Wd))
+#define ASR_xxx(Xd,Xn,Xm)         _W((0b10011010110 << 21) | ((Xm) << 16) | (0b001010 << 10) | ((Xn) << 5) | (Xd))
+#define ASR_wwi(Wd,Wn,i)          _W((0b0001001100 << 22) | (((i) & 0x1f) << 16) | (0b011111 << 10) | ((Wn) << 5) | (Wd))
+#define ASR_xxi(Xd,Xn,i)          _W((0b1001001101 << 22) | (((i) & 0x3f) << 16) | (0b111111 << 10) | ((Xn) << 5) | (Xd))
+#define LSL_www(Wd,Wn,Wm)         _W((0b00011010110 << 21) | ((Wm) << 16) | (0b001000 << 10) | ((Wn) << 5) | (Wd))
+#define LSL_xxx(Xd,Xn,Xm)         _W((0b10011010110 << 21) | ((Xm) << 16) | (0b001000 << 10) | ((Xn) << 5) | (Xd))
+#define LSL_wwi(Wd,Wn,i)          _W((0b0101001100 << 22) | (((32-(i)) & 0x1f) << 16) | (((31-(i)) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define LSL_xxi(Xd,Xn,i)          _W((0b1101001101 << 22) | (((64-(i)) & 0x3f) << 16) | (((63-(i)) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define LSR_www(Wd,Wn,Wm)         _W((0b00011010110 << 21) | ((Wm) << 16) | (0b001001 << 10) | ((Wn) << 5) | (Wd))
+#define LSR_xxx(Xd,Xn,Xm)         _W((0b10011010110 << 21) | ((Xm) << 16) | (0b001001 << 10) | ((Xn) << 5) | (Xd))
+#define LSR_wwi(Wd,Wn,i)          _W((0b0101001100 << 22) | (((i) & 0x1f) << 16) | (0b011111 << 10) | ((Wn) << 5) | (Wd))
+#define LSR_xxi(Xd,Xn,i)          _W((0b1101001101 << 22) | (((i) & 0x3f) << 16) | (0b111111 << 10) | ((Xn) << 5) | (Xd))
+#define ROR_wwi(Wd,Ws,i)          _W((0b00010011100 << 21) | ((Ws) << 16) | (((i) & 0x1f) << 10) | ((Ws) << 5) | (Wd))
+#define ROR_xxi(Xd,Xs,i)          _W((0b10010011110 << 21) | ((Xs) << 16) | (((i) & 0x3f) << 10) | ((Xs) << 5) | (Xd))
+#define ROR_www(Wd,Wn,Wm)         _W((0b00011010110 << 21) | ((Wm) << 16) | (0b001011 << 10) | ((Wn) << 5) | (Wd))
+#define ROR_xxx(Xd,Xn,Xm)         _W((0b10011010110 << 21) | ((Xm) << 16) | (0b001011 << 10) | ((Xn) << 5) | (Xd))
+
+
+/*----------------------------------------
+ * bit ops
+ *----------------------------------------*/
+/* extract */
+// Wd[31...0] = Wn[31-lsb...0]Wm[31...lsb]
+// Xd[63...0] = Xn[63-lsb...0]Xm[63...lsb]
+#define EXTR_wwwi(Wd,Wn,Wm,lsb)   _W((0b00010011100 << 21) | ((Wm) << 16) | (((lsb) & 0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define EXTR_xxxi(Xd,Xn,Xm,lsb)   _W((0b10010011110 << 21) | ((Xm) << 16) | (((lsb) & 0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+/* bitfield */
+// dst[lsb+width-1...lsb] = src[width-1...0]
+#define BFI_wwii(Wd,Wn,lsb,width)     _W((0b0011001100 << 22) | (((32-(lsb))&0x1f) << 16) | ((((width)-1)&0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define BFI_xxii(Xd,Xn,lsb,width)     _W((0b1011001101 << 22) | (((64-(lsb))&0x3f) << 16) | ((((width)-1)&0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define SBFIZ_wwii(Wd,Wn,lsb,width)   _W((0b0001001100 << 22) | (((32-(lsb))&0x1f) << 16) | ((((width)-1)&0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define SBFIZ_xxii(Xd,Xn,lsb,width)   _W((0b1001001101 << 22) | (((64-(lsb))&0x3f) << 16) | ((((width)-1)&0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define UBFIZ_wwii(Wd,Wn,lsb,width)   _W((0b0101001100 << 22) | (((32-(lsb))&0x1f) << 16) | ((((width)-1)&0x1f) << 10) | ((Wn) << 5) | (Wd))
+#define UBFIZ_xxii(Xd,Xn,lsb,width)   _W((0b1101001101 << 22) | (((64-(lsb))&0x3f) << 16) | ((((width)-1)&0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+// dst[width-1...0] = src[lsb+width-1...lsb]
+#define BFXIL_wwii(Wd,Wn,lsb,width)   _W((0b0011001100 << 22) | (((lsb)&0x1f) << 16) | ((((lsb)+(width)-1)&0x3f) << 10) | ((Wn) << 5) | (Wd))
+#define BFXIL_xxii(Xd,Xn,lsb,width)   _W((0b1011001101 << 22) | (((lsb)&0x3f) << 16) | ((((lsb)+(width)-1)&0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define SBFX_wwii(Wd,Wn,lsb,width)    _W((0b0001001100 << 22) | (((lsb)&0x1f) << 16) | ((((lsb)+(width)-1)&0x3f) << 10) | ((Wn) << 5) | (Wd))
+#define SBFX_xxii(Xd,Xn,lsb,width)    _W((0b1001001101 << 22) | (((lsb)&0x3f) << 16) | ((((lsb)+(width)-1)&0x3f) << 10) | ((Xn) << 5) | (Xd))
+#define UBFX_wwii(Wd,Wn,lsb,width)    _W((0b0101001100 << 22) | (((lsb)&0x1f) << 16) | ((((lsb)+(width)-1)&0x3f) << 10) | ((Wn) << 5) | (Wd))
+#define UBFX_xxii(Xd,Xn,lsb,width)    _W((0b1101001101 << 22) | (((lsb)&0x3f) << 16) | ((((lsb)+(width)-1)&0x3f) << 10) | ((Xn) << 5) | (Xd))
+
+#define BIC_www(Wd,Wn,Wm)         _W((0b00001010001 << 21) | ((Wm) << 16) | (0 << 10) | ((Wn) << 5) | (Wd))
+#define BIC_xxx(Xd,Xn,Xm)         _W((0b10001010001 << 21) | ((Xm) << 16) | (0 << 10) | ((Xn) << 5) | (Xd))
+
+/* reverse */
+#define REV_ww(Wd,Wn)             _W((0b01011010110 << 21) | (0b00000 << 16) | (0b000010 << 10) | ((Wn) << 5) | (Wd))
+#define REV_xx(Xd,Xn)             _W((0b11011010110 << 21) | (0b00000 << 16) | (0b000011 << 10) | ((Xn) << 5) | (Xd))
+#define REV16_ww(Wd,Wn)           _W((0b01011010110 << 21) | (0b00000 << 16) | (0b000001 << 10) | ((Wn) << 5) | (Wd))
+#define REV16_xx(Xd,Xn)           _W((0b11011010110 << 21) | (0b00000 << 16) | (0b000001 << 10) | ((Xn) << 5) | (Xd))
+#define REV32_xx(Xd,Xn)           _W((0b11011010110 << 21) | (0b00000 << 16) | (0b000010 << 10) | ((Xn) << 5) | (Xd))
+
+#define CLS_ww(Wd,Wn)             _W((0b01011010110 << 21) | (0b00000000101 << 10) | ((Wn) << 5) | (Wd))
+#define CLZ_ww(Wd,Wn)             _W((0b01011010110 << 21) | (0b00000000100 << 10) | ((Wn) << 5) | (Wd))
+
+
+/*----------------------------------------
+ * conditional ops
+ *----------------------------------------*/
+/* conditional compare */
+#define CCMP_wwfc(Wn,Wm,nzcv,cond)  _W((0b01111010010 << 21) | ((Wm) << 16) | ((cond) << 12) | (0b00 << 10) | ((Wn) << 5) | (nzcv))
+#define CCMP_xxfc(Xn,Xm,nzcv,cond)  _W((0b11111010010 << 21) | ((Xm) << 16) | ((cond) << 12) | (0b00 << 10) | ((Xn) << 5) | (nzcv))
+
+/* conditional select */
+#define CSEL_wwwc(Wd,Wn,Wm,cond)  _W((0b00011010100 << 21) | ((Wm) << 16) | ((cond) << 12) | (0b00 << 10) | ((Wn) << 5) | (Wd))
+#define CSEL_xxxc(Xd,Xn,Xm,cond)  _W((0b10011010100 << 21) | ((Xm) << 16) | ((cond) << 12) | (0b00 << 10) | ((Xn) << 5) | (Xd))
+
+/* conditional set */
+#define CSET_wc(Wd,cond)          _W((0b00011010100 << 21) | (0b11111 << 16) | ((cond^1) << 12) | (0b01 << 10) | (0b11111 << 5) | (Wd))
+#define CSET_xc(Xd,cond)          _W((0b10011010100 << 21) | (0b11111 << 16) | ((cond^1) << 12) | (0b01 << 10) | (0b11111 << 5) | (Xd))
+
+/* conditional set mask */
+#define CSETM_wc(Wd,cond)         _W((0b01011010100 << 21) | (0b11111 << 16) | ((cond^1) << 12) | (0b00 << 10) | (0b11111 << 5) | (Wd))
+#define CSETM_xc(Xd,cond)         _W((0b11011010100 << 21) | (0b11111 << 16) | ((cond^1) << 12) | (0b00 << 10) | (0b11111 << 5) | (Xd))
+
+
+/*----------------------------------------
+ * some special defines
+ *----------------------------------------*/
+// immediate encoding for flags:
+//   N  N=1 immr=100001 imms=000000
+//   Z  N=1 immr=100010 imms=000000
+//   C  N=1 immr=100011 imms=000000
+//   V  N=1 immr=100100 imms=000000
+//  ~N  N=1 immr=100000 imms=111110
+//  ~Z  N=1 immr=100001 imms=111110
+//  ~C  N=1 immr=100010 imms=111110
+//  ~V  N=1 immr=100011 imms=111110
+#define immNflag                  immEncode(1, 0b100001, 0b000000)
+#define immZflag                  immEncode(1, 0b100010, 0b000000)
+#define immCflag                  immEncode(1, 0b100011, 0b000000)
+#define immVflag                  immEncode(1, 0b100100, 0b000000)
+
+#define immNflagInv               immEncode(1, 0b100000, 0b111110)
+#define immZflagInv               immEncode(1, 0b100001, 0b111110)
+#define immCflagInv               immEncode(1, 0b100010, 0b111110)
+#define immVflagInv               immEncode(1, 0b100011, 0b111110)
+
+#define immOP_EOR                 (0b110100100 << 23)
+#define immOP_AND                 (0b100100100 << 23)
+#define immOP_ORR                 (0b101100100 << 23)
+
+// R_MEMSTART is in 32bit address space and never 0, so CCMN(R_MEMSTART, #0, #0, #<any cond>) will always clear NZCV
+#define CLEAR_NZCV()              _W((0b10111010010 << 21) | (0 << 16) | (NATIVE_CC_EQ << 12) | (0b10 << 10) | (R_MEMSTART << 5) | (0))
+
+#define EOR_xxCflag(Xd,Xn)        _W(immCflag | immOP_EOR | ((Xn) << 5) | (Xd))
+#define CLEAR_xxZflag(Xd,Xn)      _W(immZflagInv | immOP_AND | ((Xn) << 5) | (Xd))
+#define CLEAR_xxCflag(Xd,Xn)      _W(immCflagInv | immOP_AND | ((Xn) << 5) | (Xd))
+#define SET_xxZflag(Xd,Xn)        _W(immZflag | immOP_ORR | ((Xn) << 5) | (Xd))
+#define SET_xxVflag(Xd,Xn)        _W(immVflag | immOP_ORR | ((Xn) << 5) | (Xd))
+#define SET_xxCflag(Xd,Xn)        _W(immCflag | immOP_ORR | ((Xn) << 5) | (Xd))
+
+#define EOR_xxbit(Xd,Xn,bit)      _W(immOP_EOR | immEncode(1, ((-(bit)) & 0x3f), 0b000000) | ((Xn) << 5) | (Xd))
+#define CLEAR_xxbit(Xd,Xn,bit)    _W(immOP_AND | immEncode(1, ((-((bit)+1)) & 0x3f), 0b111110) | ((Xn) << 5) | (Xd))
+#define SET_xxbit(Xd,Xn,bit)      _W(immOP_ORR | immEncode(1, ((-(bit)) & 0x3f), 0b000000) | ((Xn) << 5) | (Xd))
+
+#define CLEAR_LOW4_xx(Xd,Xn)      _W(immOP_AND | immEncode(1, 0b111100, 0b111011) | ((Xn) << 5) | (Xd))
+#define CLEAR_LOW8_xx(Xd,Xn)      _W(immOP_AND | immEncode(1, 0b111000, 0b110111) | ((Xn) << 5) | (Xd))
+#define CLEAR_LOW16_xx(Xd,Xn)     _W(immOP_AND | immEncode(1, 0b110000, 0b101111) | ((Xn) << 5) | (Xd))
+
+#define SET_LOW8_xx(Xd,Xn)        _W(immOP_ORR | immEncode(1, 0b000000, 0b000111) | ((Xn) << 5) | (Xd))
+
+// Floatingpoint
+
+#define LDR_dXi(Dt,Xn,i)      _W((0b1111110101 << 22) | (((i)/8) << 10) | ((Xn) << 5) | (Dt))
+#define LDR_sXi(St,Xn,i)      _W((0b1011110101 << 22) | (((i)/4) << 10) | ((Xn) << 5) | (St))
+#define LDR_dXx(Dt,Xn,Xm)     _W((0b11111100011 << 21) | ((Xm) << 16) | (0b011010 << 10) | ((Xn) << 5) | (Dt))
+
+#define STR_dXi(Dt,Xn,i)      _W((0b1111110100 << 22) | (((i)/8) << 10) | ((Xn) << 5) | (Dt))
+#define STR_sXi(St,Xn,i)      _W((0b1011110100 << 22) | (((i)/4) << 10) | ((Xn) << 5) | (St))
+#define STR_dXx(Dt,Xn,Xm)     _W((0b11111100001 << 21) | ((Xm) << 16) | (0b011010 << 10) | ((Xn) << 5) | (Dt))
+#define FMOV_dd(Dd,Dn)        _W((0b00011110011 << 21) | (0b00000010000 << 10) | ((Dn) << 5) | (Dd))
+#define FMOV_ss(Sd,Sn)        _W((0b00011110001 << 21) | (0b00000010000 << 10) | ((Sn) << 5) | (Sd))
+#define FMOV_dx(Dd,Xn)        _W((0b10011110011 << 21) | (0b00111000000 << 10) | ((Xn) << 5) | (Dd))
+#define FMOV_xd(Xd,Dn)        _W((0b10011110011 << 21) | (0b00110000000 << 10) | ((Dn) << 5) | (Xd))
+#define FMOV_sw(Sd,Wn)        _W((0b00011110001 << 21) | (0b00111000000 << 10) | ((Wn) << 5) | (Sd))
+#define FMOV_ws(Wd,Sn)        _W((0b00011110001 << 21) | (0b00110000000 << 10) | ((Sn) << 5) | (Wd))
+#define FMOV_di(Dd,i)         _W((0b00011110011 << 21) | ((i) << 13) | (0b10000000 << 5) | (Dd))
+#define FMOV_si(Sd,i)         _W((0b00011110001 << 21) | ((i) << 13) | (0b10000000 << 5) | (Sd))
+#define MOVI_di(Dd,i)         _W((0b0010111100000 << 19) | ((((i) >> 5) & 0x7) << 16) | (0b111001 << 10) | (((i) & 0x1f) << 5) | (Dd))
+#define FCVT_ds(Dd,Sn)        _W((0b00011110001 << 21) | (0b00010110000 << 10) | ((Sn) << 5) | (Dd))
+#define FCVT_sd(Sd,Dn)        _W((0b00011110011 << 21) | (0b00010010000 << 10) | ((Dn) << 5) | (Sd))
+#define FRINTA_dd(Dd,Dn)      _W((0b00011110011 << 21) | (0b00110010000 << 10) | ((Dn) << 5) | (Dd))
+#define FRINTI_dd(Dd,Dn)      _W((0b00011110011 << 21) | (0b00111110000 << 10) | ((Dn) << 5) | (Dd))
+#define FRINTZ_dd(Dd,Dn)      _W((0b00011110011 << 21) | (0b00101110000 << 10) | ((Dn) << 5) | (Dd))
+#define FCVTAS_wd(Wd,Dn)      _W((0b00011110011 << 21) | (0b00100000000 << 10) | ((Dn) << 5) | (Wd))
+#define FCVTAS_xd(Xd,Dn)      _W((0b10011110011 << 21) | (0b00100000000 << 10) | ((Dn) << 5) | (Xd))
+#define FCVTZS_xd(Xd,Dn)      _W((0b10011110011 << 21) | (0b11000000000 << 10) | ((Dn) << 5) | (Xd))
+#define SCVTF_dw(Dd,Wn)       _W((0b00011110011 << 21) | (0b00010000000 << 10) | ((Wn) << 5) | (Dd))
+#define SCVTF_sw(Sd,Wn)       _W((0b00011110001 << 21) | (0b00010000000 << 10) | ((Wn) << 5) | (Sd))
+#define SCVTF_dx(Dd,Xn)       _W((0b10011110011 << 21) | (0b00010000000 << 10) | ((Xn) << 5) | (Dd))
+
+#define FABS_dd(Dd,Dn)        _W((0b00011110011 << 21) | (0b00000110000 << 10) | ((Dn) << 5) | (Dd))
+#define FABS_ss(Sd,Sn)        _W((0b00011110001 << 21) | (0b00000110000 << 10) | ((Sn) << 5) | (Sd))
+#define FADD_ddd(Dd,Dn,Dm)    _W((0b00011110011 << 21) | ((Dm) << 16) | (0b001010 << 10) | ((Dn) << 5) | (Dd))
+#define FADD_sss(Sd,Sn,Sm)    _W((0b00011110001 << 21) | ((Sm) << 16) | (0b001010 << 10) | ((Sn) << 5) | (Sd))
+#define FCMP_dd(Dn,Dm)        _W((0b00011110011 << 21) | ((Dm) << 16) | (0b001000 << 10) | ((Dn) << 5) | (0b00000))
+#define FCMP_d0(Dn)           _W((0b00011110011 << 21) | (0 << 16) | (0b001000 << 10) | ((Dn) << 5) | (0b01000))
+#define FCMP_ss(Sn,Sm)        _W((0b00011110001 << 21) | ((Sm) << 16) | (0b001000 << 10) | ((Sn) << 5) | (0b00000))
+#define FDIV_ddd(Dd,Dn,Dm)    _W((0b00011110011 << 21) | ((Dm) << 16) | (0b000110 << 10) | ((Dn) << 5) | (Dd))
+#define FDIV_sss(Sd,Sn,Sm)    _W((0b00011110001 << 21) | ((Sm) << 16) | (0b000110 << 10) | ((Sn) << 5) | (Sd))
+#define FMUL_ddd(Dd,Dn,Dm)    _W((0b00011110011 << 21) | ((Dm) << 16) | (0b000010 << 10) | ((Dn) << 5) | (Dd))
+#define FMUL_sss(Sd,Sn,Sm)    _W((0b00011110001 << 21) | ((Sm) << 16) | (0b000010 << 10) | ((Sn) << 5) | (Sd))
+#define FMSUB_dddd(Dd,Dn,Dm,Da) _W((0b00011111010 << 21) | ((Dm) << 16) | (1 << 15) | ((Da) << 10) | ((Dn) << 5) | (Dd))
+#define FNEG_dd(Dd,Dn)        _W((0b00011110011 << 21) | (0b00001010000 << 10) | ((Dn) << 5) | (Dd))
+#define FNEG_ss(Sd,Sn)        _W((0b00011110001 << 21) | (0b00001010000 << 10) | ((Sn) << 5) | (Sd))
+#define FSQRT_dd(Dd,Dn)       _W((0b00011110011 << 21) | (0b00001110000 << 10) | ((Dn) << 5) | (Dd))
+#define FSQRT_ss(Sd,Sn)       _W((0b00011110001 << 21) | (0b00001110000 << 10) | ((Sn) << 5) | (Sd))
+#define FSUB_ddd(Dd,Dn,Dm)    _W((0b00011110011 << 21) | ((Dm) << 16) | (0b001110 << 10) | ((Dn) << 5) | (Dd))
+#define FSUB_sss(Sd,Sn,Sm)    _W((0b00011110001 << 21) | ((Sm) << 16) | (0b001110 << 10) | ((Sn) << 5) | (Sd))
+
+#define REV64_dd(Vd,Vn)       _W((0b0000111000 << 22) | (0b100000000010 << 10) | ((Vn) << 5) | (Vd))
+
+#endif /* ARM_ASMA64_H */
diff --git a/jit/arm/compemu_arm.cpp b/jit/arm/compemu_arm.cpp
new file mode 100644
index 00000000..56e0c80b
--- /dev/null
+++ b/jit/arm/compemu_arm.cpp
@@ -0,0 +1,54104 @@
+#include "sysconfig.h"
+#if defined(JIT)
+#include "sysdeps.h"
+#include "options.h"
+#include "memory.h"
+#include "newcpu.h"
+#include "custom.h"
+#include "comptbl_arm.h"
+#include "compemu_arm.h"
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef USE_JIT_FPU
+extern void comp_fpp_opp();
+extern void comp_fscc_opp();
+extern void comp_fbcc_opp();
+#endif
+
+#ifdef PART_1
+
+/* OR.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_10_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_18_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_20_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_28_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_30_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_38_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_39_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ORSR.B #<data>.W */
+uae_u32 REGPARAM2 op_3c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	make_flags_live();
+	jff_ORSR(ARM_CCR_MAP[src & 0xF], ((src & 0x10) >> 4));
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_40_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_50_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_58_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_60_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_68_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_70_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_78_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_79_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_80_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_90_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_98_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_a0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_a8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 op_100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	make_flags_live();
+	jff_BTST_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 op_110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 op_120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 op_13a_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_13b_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,#<data>.B */
+uae_u32 REGPARAM2 op_13c_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = alloc_scratch();
+	mov_l_ri(dst, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	make_flags_live();
+	jff_BTST_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 op_140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	make_flags_live();
+	jff_BCHG_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 op_150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 op_160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 op_180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	make_flags_live();
+	jff_BCLR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 op_190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 op_1a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_1a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_1b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_1b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 op_1c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	make_flags_live();
+	jff_BSET_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 op_1d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_1d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 op_1e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_1e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_1f8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_1f9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_200_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_210_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_218_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_220_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_228_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_230_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_238_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_239_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ANDSR.B #<data>.W */
+uae_u32 REGPARAM2 op_23c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	make_flags_live();
+	jff_ANDSR(ARM_CCR_MAP[src & 0xF], (src & 0x10));
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_240_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_250_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_258_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_260_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_268_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_270_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_278_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_279_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_280_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_290_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_298_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_2a0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_2a8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2b0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_2b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_2b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_400_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_410_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_418_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_420_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_428_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_430_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_438_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_439_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_440_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_450_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_458_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_460_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_468_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_470_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_478_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_479_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_480_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_490_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_498_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_4a0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_4a8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4b0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_4b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_4b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_600_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_610_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_618_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_620_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_628_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_630_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_638_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_639_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_640_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_650_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_658_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_660_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_668_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_670_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_678_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_679_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_680_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_690_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_698_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_6a0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_6a8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_6b0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_6b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_6b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_800_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	make_flags_live();
+	jff_BTST_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_810_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_818_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_820_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_828_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_830_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_838_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_839_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_83a_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_83b_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BTST_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_840_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	make_flags_live();
+	jff_BCHG_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_850_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_858_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_860_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_868_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_870_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_878_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_879_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCHG_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_880_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	make_flags_live();
+	jff_BCLR_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_890_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_898_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_8a0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_8a8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8b0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_8b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_8b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BCLR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_8c0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	make_flags_live();
+	jff_BSET_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_8d0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_8d8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_8e0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_8e8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8f0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_8f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_8f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	make_flags_live();
+	jff_BSET_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_a00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_a10_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_a18_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_a20_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_a28_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_a30_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_a38_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_a39_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b_imm(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EORSR.B #<data>.W */
+uae_u32 REGPARAM2 op_a3c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	make_flags_live();
+	jff_EORSR(ARM_CCR_MAP[src & 0xF], ((src & 0x10) >> 4));
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_a40_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_a50_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_a58_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_a60_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_a68_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_a70_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_a78_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_a79_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w_imm(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_a80_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_a90_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_a98_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_aa0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_aa8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_ab0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_ab8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_ab9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l_imm(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_2
+
+/* CMP.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_c00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_c10_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_c18_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_c20_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_c28_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c30_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_c38_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_c39_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d16,PC) */
+uae_u32 REGPARAM2 op_c3a_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_c3b_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c40_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_c50_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_c58_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_c60_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_c68_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c70_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_c78_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_c79_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_c7a_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_c7b_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_c80_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_c90_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_c98_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_ca0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_ca8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_cb0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_cb8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_cb9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d16,PC) */
+uae_u32 REGPARAM2 op_cba_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_cbb_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 op_1000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 op_1010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 op_1018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 op_1020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_1028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_1030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_1038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_1039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_103a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_103b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_103c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 op_1080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 op_1090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 op_1098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 op_10a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 op_10a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 op_10b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 op_10b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 op_10b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 op_10ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 op_10bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_10bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_10c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 op_10d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 op_10d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 op_10e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 op_10e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 op_10f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 op_10f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_10f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 op_10fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 op_10fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_10fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 op_1100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 op_1110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 op_1118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 op_1120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 op_1128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 op_1130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 op_1138_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 op_1139_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 op_113a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 op_113b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_113c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_1140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 op_1150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 op_1158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 op_1160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 op_1168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_1170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 op_1178_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 op_1179_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 op_117a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_117b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_117c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_11c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 op_11d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 op_11d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 op_11e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 op_11e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_11f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 op_11f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 op_11f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 op_11fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_11fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_11fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_13c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 op_13d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_13d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 op_13e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 op_13e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_13f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 op_13f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 op_13f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 op_13fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_13fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_13fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 op_2000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 op_2008_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 op_2010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 op_2018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 op_2020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_2028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_2030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_2038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_2039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_203a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_203b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_203c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 op_2040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 op_2048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 op_2050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 op_2058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 op_2060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 op_2068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_2070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_2078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_2079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_207a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_207b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_207c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 op_2080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 op_2088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 op_2090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 op_2098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 op_20a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 op_20a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 op_20b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 op_20b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 op_20b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 op_20ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 op_20bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_20bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_20c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 op_20c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 op_20d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 op_20d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 op_20e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 op_20e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 op_20f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 op_20f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_20f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 op_20fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 op_20fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_20fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 op_2100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 op_2108_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 op_2110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 op_2118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 op_2120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 op_2128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 op_2130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 op_2138_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 op_2139_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 op_213a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 op_213b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_213c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_2140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 op_2148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 op_2150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 op_2158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 op_2160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 op_2168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_2170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 op_2178_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 op_2179_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 op_217a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_217b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_217c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_3
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_21c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 op_21c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 op_21d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 op_21d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 op_21e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 op_21e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_21f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 op_21f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 op_21f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 op_21fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_21fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_21fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_23c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 op_23c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 op_23d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_23d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 op_23e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 op_23e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_23f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 op_23f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 op_23f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 op_23fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_23fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_23fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 op_3000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 op_3008_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 op_3010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 op_3018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 op_3020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_3028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_3030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_3038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_3039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_303a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_303b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_303c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_w_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 op_3040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 op_3048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 op_3050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 op_3058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 op_3060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 op_3068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_3070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_3078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_3079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_307a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_307b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_307c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 op_3080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 op_3088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 op_3090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 op_3098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 op_30a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 op_30a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 op_30b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 op_30b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 op_30b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 op_30ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 op_30bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_30bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_30c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 op_30c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 op_30d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 op_30d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 op_30e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 op_30e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 op_30f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 op_30f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_30f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 op_30fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 op_30fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_30fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 op_3100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 op_3108_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 op_3110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 op_3118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 op_3120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 op_3128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 op_3130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 op_3138_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 op_3139_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 op_313a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 op_313b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_313c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_3140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 op_3148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 op_3150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 op_3158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 op_3160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 op_3168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_3170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 op_3178_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 op_3179_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 op_317a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_317b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_317c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_31c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 op_31c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 op_31d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 op_31d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 op_31e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 op_31e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_31f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 op_31f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 op_31f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 op_31fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_31fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_31fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_33c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 op_33c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 op_33d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_33d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 op_33e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 op_33e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_33f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 op_33f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 op_33f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 op_33fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_33fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_33fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 op_4000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 op_4010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 op_4018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 op_4020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 op_4028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 op_4038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 op_4039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	make_flags_live();
+	jff_NEGX_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 op_4040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 op_4050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 op_4058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 op_4060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 op_4068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 op_4078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 op_4079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	make_flags_live();
+	jff_NEGX_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 op_4080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 op_4090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 op_4098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 op_40a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 op_40a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_40b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 op_40b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 op_40b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	make_flags_live();
+	jff_NEGX_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 op_41d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 op_41e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_41f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_41f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_41f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_41fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_41fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 op_4200_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 op_4210_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 op_4218_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 op_4220_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 op_4228_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4230_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 op_4238_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 op_4239_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 op_4240_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 op_4250_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 op_4258_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 op_4260_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 op_4268_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4270_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 op_4278_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 op_4279_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 op_4280_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 op_4290_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 op_4298_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 op_42a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 op_42a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_42b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 op_42b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 op_42b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	dont_care_flags();
+	jff_CLR_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_4
+
+/* NEG.B Dn */
+uae_u32 REGPARAM2 op_4400_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (An) */
+uae_u32 REGPARAM2 op_4410_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 op_4418_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 op_4420_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 op_4428_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4430_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 op_4438_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 op_4439_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jff_NEG_b(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 op_4440_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 op_4450_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 op_4458_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 op_4460_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 op_4468_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4470_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 op_4478_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 op_4479_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_NEG_w(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 op_4480_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 op_4490_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 op_4498_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 op_44a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 op_44a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_44b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 op_44b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 op_44b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jff_NEG_l(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 op_4600_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 op_4610_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 op_4618_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 op_4620_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 op_4628_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4630_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 op_4638_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 op_4639_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_NOT_b(src);
+	live_flags();
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 op_4640_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 op_4650_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 op_4658_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 op_4660_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 op_4668_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4670_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 op_4678_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 op_4679_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_NOT_w(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 op_4680_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 op_4690_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 op_4698_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 op_46a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 op_46a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_46b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 op_46b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 op_46b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_NOT_l(src);
+	live_flags();
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LINK.L An,#<data>.L */
+uae_u32 REGPARAM2 op_4808_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int src = dodgy ? alloc_scratch() : srcreg + 8;
+	if (dodgy)
+		mov_l_rr(src, srcreg + 8);
+	uae_s32 offs = comp_get_ilong((m68k_pc_offset += 4) - 4); /* absl */
+	sub_l_ri(15, 4);
+	writelong_clobber(15, src);
+	if (!dodgy)
+		mov_l_rr(src, 15);
+	arm_ADD_l_ri(15, offs);
+	if (srcreg + 8 != src)
+		mov_l_rr(srcreg + 8, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 op_4840_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_SWAP(src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (An) */
+uae_u32 REGPARAM2 op_4850_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int srca = dodgy ? alloc_scratch() : srcreg + 8;
+	if (dodgy)
+		mov_l_rr(srca, srcreg + 8);
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 op_4868_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4870_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 op_4878_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 op_4879_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 op_487a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_487b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	{
+		mov_l_ri(pctmp, address);
+		calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+		release_scratch(pctmp);
+		{
+			int dsta = dodgy ? alloc_scratch() : 7 + 8;
+			arm_SUB_l_ri8(7 + 8, 4);
+			if (dodgy)
+				mov_l_rr(dsta, 8 + 7);
+			writelong(dsta, srca);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 op_4880_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_EXT_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4890_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_48a0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				offset -= 2;
+				jnf_MVMLE_w(native, 15 - i, offset);
+			}
+		}
+		lea_l_brr(8 + dstreg, srca, (uae_s32) offset);
+	} else {
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				arm_SUB_l_ri8(srca, 2);
+				writeword(srca, 15 - i);
+			}
+		}
+		mov_l_rr(8 + dstreg, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_48a8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_48b0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_48b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_48b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 op_48c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_EXT_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_48d0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_48e0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				offset -= 4;
+				jnf_MVMLE_l(native, 15 - i, offset);
+			}
+		}
+		lea_l_brr(8 + dstreg, srca, (uae_s32) offset);
+	} else {
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				arm_SUB_l_ri8(srca, 4);
+				writelong(srca, 15 - i);
+			}
+		}
+		mov_l_rr(8 + dstreg, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_48e8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_48f0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_48f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_48f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXT.B Dn */
+uae_u32 REGPARAM2 op_49c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_EXT_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B Dn */
+uae_u32 REGPARAM2 op_4a00_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 op_4a10_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 op_4a18_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 op_4a20_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 op_4a28_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4a30_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 op_4a38_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 op_4a39_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d16,PC) */
+uae_u32 REGPARAM2 op_4a3a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4a3b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B #<data>.B */
+uae_u32 REGPARAM2 op_4a3c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_b(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W Dn */
+uae_u32 REGPARAM2 op_4a40_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W An */
+uae_u32 REGPARAM2 op_4a48_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (An) */
+uae_u32 REGPARAM2 op_4a50_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 op_4a58_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 op_4a60_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 op_4a68_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4a70_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 op_4a78_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 op_4a79_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d16,PC) */
+uae_u32 REGPARAM2 op_4a7a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4a7b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W #<data>.W */
+uae_u32 REGPARAM2 op_4a7c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	jff_TST_w(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L Dn */
+uae_u32 REGPARAM2 op_4a80_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L An */
+uae_u32 REGPARAM2 op_4a88_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (An) */
+uae_u32 REGPARAM2 op_4a90_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 op_4a98_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 op_4aa0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 op_4aa8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4ab0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 op_4ab8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 op_4ab9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d16,PC) */
+uae_u32 REGPARAM2 op_4aba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4abb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L #<data>.L */
+uae_u32 REGPARAM2 op_4abc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	dont_care_flags();
+	jff_TST_l(src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_4c00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dst = dstreg;
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c10_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c18_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_4c20_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4c28_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4c30_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4c38_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4c39_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4c3a_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4c3b_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_4c3c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dst = alloc_scratch();
+	mov_l_ri(dst, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jff_MULS64(r2, r3);
+		} else {
+			jff_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jff_MULS32(r2, dst);
+		} else {
+			jff_MULU32(r2, dst);
+		}
+	}
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DIVL.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_4c40_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dst=dstreg;
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c50_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=dstreg+8;
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c58_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=dstreg+8;
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dstreg+8,4);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_4c60_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=dstreg+8;
+	arm_SUB_l_ri8(dstreg+8,4);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4c68_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	lea_l_brr(dsta,8+dstreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4c70_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4c78_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4c79_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4c7a_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(dsta,address+PC16off);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4c7b_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	int pctmp=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
+	release_scratch(pctmp);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_4c7c_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dst=alloc_scratch();
+	mov_l_ri(dst,comp_get_ilong((m68k_pc_offset+=4)-4));
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+		} else {
+	   if (extra & 0x0800) {
+	     jff_DIVLS32(r2,dst,r3);
+		} else {
+			  jff_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* MVMEL.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c90_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c98_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				if (srca != i)
+					jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+		jnf_ADD_im8(8 + dstreg, srca, offset);
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+		mov_l_rr(8 + dstreg, tmp);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4ca8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4cb0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4cb8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4cb9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4cba_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4cbb_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4cd0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4cd8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				if (srca != i)
+					jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+		jnf_ADD_im8(8 + dstreg, srca, offset);
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+		mov_l_rr(8 + dstreg, tmp);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4ce8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4cf0_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4cf8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4cf9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4cfa_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4cfb_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LINK.W An,#<data>.W */
+uae_u32 REGPARAM2 op_4e50_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int src = dodgy ? alloc_scratch() : srcreg + 8;
+	if (dodgy)
+		mov_l_rr(src, srcreg + 8);
+	uae_s32 offs = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	sub_l_ri(15, 4);
+	writelong_clobber(15, src);
+	if (!dodgy)
+		mov_l_rr(src, 15);
+	arm_ADD_l_ri(15, offs);
+	if (srcreg + 8 != src)
+		mov_l_rr(srcreg + 8, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 op_4e58_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (src == 15) {
+		readlong(15, src);
+	} else {
+		mov_l_rr(15, src);
+		readlong(15, src);
+		arm_ADD_l_ri8(15, 4);
+	}
+	if (srcreg + 8 != src)
+		mov_l_rr(srcreg + 8, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 op_4e71_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RTD.L #<data>.W */
+uae_u32 REGPARAM2 op_4e74_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 offs = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	offs += 4;
+	{
+		int newad = alloc_scratch();
+		readlong(15, newad);
+		mov_l_mr((uintptr) &regs.pc, newad);
+		get_n_addr_jmp(newad, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+		arm_ADD_l_ri(15, offs);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RTS.L  */
+uae_u32 REGPARAM2 op_4e75_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int newad = alloc_scratch();
+	readlong(15, newad);
+	mov_l_mr((uintptr) &regs.pc, newad);
+	get_n_addr_jmp(newad, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	arm_ADD_l_ri8(15, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (An) */
+uae_u32 REGPARAM2 op_4e90_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 op_4ea8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4eb0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 op_4eb8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 op_4eb9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 op_4eba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4ebb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 op_4ed0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 op_4ee8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4ef0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 op_4ef8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 op_4ef9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 op_4efa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4efb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_5000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(An) */
+uae_u32 REGPARAM2 op_5010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,-(An) */
+uae_u32 REGPARAM2 op_5020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5038_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5039_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_5040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDAQ.W #<data>,An */
+uae_u32 REGPARAM2 op_5048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(An) */
+uae_u32 REGPARAM2 op_5050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,-(An) */
+uae_u32 REGPARAM2 op_5060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5078_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5079_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_5080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDAQ.L #<data>,An */
+uae_u32 REGPARAM2 op_5088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(An) */
+uae_u32 REGPARAM2 op_5090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_5
+
+/* ADDQ.L #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,-(An) */
+uae_u32 REGPARAM2 op_50a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_50a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_50b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_50b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_50b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_50c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	mov_b_ri(srcreg, 0xff);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_50c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_50d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_50d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_50e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_50e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_50f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_50f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_50f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_5100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(An) */
+uae_u32 REGPARAM2 op_5110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,-(An) */
+uae_u32 REGPARAM2 op_5120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_5140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBAQ.W #<data>,An */
+uae_u32 REGPARAM2 op_5148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(An) */
+uae_u32 REGPARAM2 op_5150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,-(An) */
+uae_u32 REGPARAM2 op_5160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_5180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBAQ.L #<data>,An */
+uae_u32 REGPARAM2 op_5188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(An) */
+uae_u32 REGPARAM2 op_5190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,-(An) */
+uae_u32 REGPARAM2 op_51a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_51a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_51b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_51b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_51b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_51c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	mov_b_ri(srcreg, 0);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_51c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	sub_w_ri(src, 1);
+	uintptr v2;
+	uintptr v1 = get_const(PC_P);
+	v2 = get_const(offs);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_51d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_51d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_51e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_51e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_51f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_51f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_51f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_52c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 8);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_52c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 8);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_52d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_52d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_52e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_52e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_52f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_52f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_52f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_53c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 9);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_53c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 9);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_53d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_53d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_53e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_53e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_53f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_53f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_53f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_54c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 3);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_54c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 3);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_54d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_54d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_54e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_54e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_54f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_54f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_54f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_55c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_55c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 2);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_55d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_55d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_55e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_55e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_55f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_55f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_55f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_56c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 1);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_56c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 1);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_56d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_56d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_56e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_56e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_56f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_56f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_56f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_57c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 0);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_57c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 0);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_57d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_57d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_57e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_57e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_57f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_57f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_57f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_58c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 7);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_58c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 7);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_58d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_58d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_58e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_58e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_58f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_58f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_58f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_59c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 6);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_59c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 6);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_59d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_59d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_59e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_59e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_59f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_59f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_59f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5ac0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 5);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5ac8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 5);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5ad0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5ad8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5ae0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5ae8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5af0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5af8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5af9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5bc0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5bc8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 4);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5bd0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5bd8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5be0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5be8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5bf0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5bf8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5bf9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5cc0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 10);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5cc8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 10);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5cd0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5cd8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5ce0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5ce8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5cf0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5cf8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5cf9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5dc0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 11);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5dc8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 11);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5dd0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5dd8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5de0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5de8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5df0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5df8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5df9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5ec0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 12);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5ec8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 12);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5ed0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5ed8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5ee0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5ee8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5ef0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5ef8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5ef9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5fc0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 13);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5fc8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 13);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5fd0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5fd8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5fe0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5fe8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5ff0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5ff8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5ff9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6000_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	mov_l_rr(PC_P, src);
+	comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6001_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	mov_l_rr(PC_P, src);
+	comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_60ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	mov_l_rr(PC_P, src);
+	comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSR.W #<data>.W */
+uae_u32 REGPARAM2 op_6100_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		arm_ADD_l_ri(src, m68k_pc_offset_thisinst + 2);
+		m68k_pc_offset = 0;
+		arm_ADD_l(PC_P, src);
+		comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSRQ.B #<data> */
+uae_u32 REGPARAM2 op_6101_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		arm_ADD_l_ri(src, m68k_pc_offset_thisinst + 2);
+		m68k_pc_offset = 0;
+		arm_ADD_l(PC_P, src);
+		comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSR.L #<data>.L */
+uae_u32 REGPARAM2 op_61ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		arm_ADD_l_ri(src, m68k_pc_offset_thisinst + 2);
+		m68k_pc_offset = 0;
+		arm_ADD_l(PC_P, src);
+		comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6200_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 8);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6201_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 8);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_62ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 8);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_6
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6300_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 9);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6301_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 9);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_63ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 9);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6400_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 3);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6401_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 3);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_64ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 3);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6500_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 2);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6501_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 2);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_65ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 2);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6600_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 1);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6601_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 1);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_66ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 1);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6700_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 0);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6701_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 0);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_67ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 0);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6800_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 7);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6801_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 7);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_68ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 7);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6900_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 6);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6901_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 6);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_69ff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 6);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6a00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 5);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6a01_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 5);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6aff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 5);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6b00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 4);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6b01_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 4);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6bff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 4);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6c00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 10);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6c01_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 10);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6cff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 10);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6d00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 11);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6d01_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 11);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6dff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 11);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6e00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 12);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6e01_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 12);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6eff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 12);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6f00_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 13);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6f01_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 13);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6fff_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 13);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_7000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_MOVE_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 op_8000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 op_8010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 op_8018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 op_8020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_8028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_8030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_8038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_8039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_803a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_803b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_803c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 op_8040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 op_8050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 op_8058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 op_8060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_8068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_8070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_8078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_8079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_807a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_807b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_807c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_w_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 op_8080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 op_8090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 op_8098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 op_80a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_80a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_80b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_80b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_80b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_80ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_80bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_80bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_OR_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 op_80c0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=srcreg;
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 op_80d0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 op_80d8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	arm_ADD_l_ri8(srcreg+8,2);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 op_80e0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	arm_SUB_l_ri8(srcreg+8,2);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_80e8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	lea_l_brr(srca,8+srcreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_80f0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	calc_disp_ea_020(srcreg+8,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_80f8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_80f9_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_80fa_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(srca,address+PC16off);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_80fb_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	int pctmp=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	release_scratch(pctmp);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_80fc_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=alloc_scratch();
+	mov_l_ri(src,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVU(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 op_8110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_8118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 op_8120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_8128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_8138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_8139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_OR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 op_8150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_8158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 op_8160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_8168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_8178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_8179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_OR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 op_8190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_8198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 op_81a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_81a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_81b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_81b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_81b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_OR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 op_81c0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=srcreg;
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 op_81d0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 op_81d8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	arm_ADD_l_ri8(srcreg+8,2);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 op_81e0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	arm_SUB_l_ri8(srcreg+8,2);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_81e8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	lea_l_brr(srca,8+srcreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_81f0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	calc_disp_ea_020(srcreg+8,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_81f8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_81f9_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_81fa_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(srca,address+PC16off);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_81fb_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	int pctmp=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	release_scratch(pctmp);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_81fc_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=alloc_scratch();
+	mov_l_ri(src,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=dstreg;
+	register_possible_exception();
+	jff_DIVS(dst,src);
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 op_9000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 op_9010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 op_9018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 op_9020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_9028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_9030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_9038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_9039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_903a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_903b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_903c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 op_9040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 op_9048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 op_9050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 op_9058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 op_9060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_9068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_9070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_9078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_9079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_907a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_907b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_907c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 op_9080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 op_9088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 op_9090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 op_9098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 op_90a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_90a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_90b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_90b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_90b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_90ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_90bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_90bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_SUB_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 op_90c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 op_90c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 op_90d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 op_90d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 op_90e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 op_90e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_90f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_90f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_90f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_90fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_90fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_90fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg + 8;
+	jnf_SUBA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 op_9100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	make_flags_live();
+	jff_SUBX_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 op_9108_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	make_flags_live();
+	jff_SUBX_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 op_9110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_9118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 op_9120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_9128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_9130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_9138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_9139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_SUB_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 op_9140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	make_flags_live();
+	jff_SUBX_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 op_9148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	make_flags_live();
+	jff_SUBX_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 op_9150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_9158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 op_9160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_9168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_9170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_9178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_9179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_SUB_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 op_9180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	make_flags_live();
+	jff_SUBX_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 op_9188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	make_flags_live();
+	jff_SUBX_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 op_9190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_9198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 op_91a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_91a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_91b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_91b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_91b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_SUB_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 op_91c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 op_91c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 op_91d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 op_91d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 op_91e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 op_91e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_91f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_91f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_91f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_91fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_91fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_91fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg + 8;
+	jnf_SUBA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 op_b000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 op_b010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 op_b018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 op_b020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_b028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_b030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_b038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_b039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_b03a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_b03b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_b03c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 op_b040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 op_b048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 op_b050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 op_b058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 op_b060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_b068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_b070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_b078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_b079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_b07a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_b07b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_b07c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 op_b080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 op_b088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 op_b090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_7
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 op_b098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 op_b0a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_b0a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_b0b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_b0b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_b0b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_b0ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_b0bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_b0bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_CMP_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 op_b0c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 op_b0c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 op_b0d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 op_b0d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 op_b0e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 op_b0e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_b0f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_b0f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_b0f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_b0fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_b0fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_b0fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 op_b100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 op_b108_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_CMP_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 op_b110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_b118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 op_b120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_b128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_b138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_b139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_EOR_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 op_b140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 op_b148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_CMP_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 op_b150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_b158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 op_b160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_b168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_b178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_b179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_EOR_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 op_b180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 op_b188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_CMP_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 op_b190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_b198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 op_b1a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_b1a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b1b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_b1b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_b1b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_EOR_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 op_b1c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 op_b1c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 op_b1d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 op_b1d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 op_b1e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 op_b1e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_b1f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_b1f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_b1f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_b1fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_b1fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_b1fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg + 8;
+	dont_care_flags();
+	jff_CMPA_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 op_c000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 op_c010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 op_c018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 op_c020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_c028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c03a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c03b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_c03c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_b_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 op_c040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 op_c050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 op_c058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 op_c060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_c068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c07a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c07b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c07c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_w_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 op_c080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 op_c090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 op_c098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 op_c0a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_c0a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c0b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c0b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c0b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c0ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c0bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_c0bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_AND_l_imm(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 op_c0c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = srcreg;
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 op_c0d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 op_c0d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 op_c0e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_c0e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c0f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c0f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c0f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c0fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c0fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c0fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg;
+	jff_MULU(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 op_c110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_c118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 op_c120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_c128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_c138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_c139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_AND_b(dst, src);
+	live_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 op_c140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	int tmp = alloc_scratch();
+	mov_l_rr(tmp, src);
+	if (srcreg != dst)
+		mov_l_rr(srcreg, dst);
+	if (dstreg != tmp)
+		mov_l_rr(dstreg, tmp);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 op_c148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	int tmp = alloc_scratch();
+	mov_l_rr(tmp, src);
+	if (srcreg + 8 != dst)
+		mov_l_rr(srcreg + 8, dst);
+	if (dstreg + 8 != tmp)
+		mov_l_rr(dstreg + 8, tmp);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 op_c150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_c158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 op_c160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_c168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_c178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_c179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_AND_w(dst, src);
+	live_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 op_c188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	int tmp = alloc_scratch();
+	mov_l_rr(tmp, src);
+	if (srcreg != dst)
+		mov_l_rr(srcreg, dst);
+	if (dstreg + 8 != tmp)
+		mov_l_rr(dstreg + 8, tmp);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 op_c190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_c198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 op_c1a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_c1a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c1b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_c1b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_c1b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_AND_l(dst, src);
+	live_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 op_c1c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = srcreg;
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 op_c1d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 op_c1d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 op_c1e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_c1e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c1f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c1f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c1f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c1fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c1fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c1fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg;
+	jff_MULS(dst, src);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 op_d000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 op_d010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 op_d018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 op_d020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_d028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_d030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_d038_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_d039_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_d03a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_d03b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_d03c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_b_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 op_d040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 op_d048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 op_d050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 op_d058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 op_d060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_d068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_d070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_d078_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_d079_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_d07a_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_d07b_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_d07c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_w_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 op_d080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 op_d088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 op_d090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 op_d098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 op_d0a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_d0a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_d0b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_d0b8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_d0b9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_d0ba_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_d0bb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_d0bc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jff_ADD_l_imm(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 op_d0c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 op_d0c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 op_d0d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 op_d0d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 op_d0e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 op_d0e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_d0f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_d0f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_d0f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_d0fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_d0fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_d0fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg + 8;
+	jnf_ADDA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 op_d100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	make_flags_live();
+	jff_ADDX_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 op_d108_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	make_flags_live();
+	jff_ADDX_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 op_d110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_d118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 op_d120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_d128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_d130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_d138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_d139_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jff_ADD_b(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 op_d140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	make_flags_live();
+	jff_ADDX_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 op_d148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	make_flags_live();
+	jff_ADDX_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 op_d150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_d158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 op_d160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_d168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_d170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_d178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_d179_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jff_ADD_w(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 op_d180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	make_flags_live();
+	jff_ADDX_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 op_d188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	make_flags_live();
+	jff_ADDX_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 op_d190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_d198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 op_d1a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_d1a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_d1b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_d1b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_d1b9_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jff_ADD_l(dst, src);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 op_d1c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 op_d1c8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 op_d1d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 op_d1d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 op_d1e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 op_d1e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_d1f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_d1f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_d1f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_d1fa_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_d1fb_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_d1fc_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg + 8;
+	jnf_ADDA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e000_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASR_b_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e008_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSR_b_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXRQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e010_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXR_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e018_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jff_ROR_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e020_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASR_b_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e028_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSR_b_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_8
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e030_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXR_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e038_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jff_ROR_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e040_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASR_w_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e048_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSR_w_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXRQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e050_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXR_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e058_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jff_ROR_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e060_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASR_w_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e068_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSR_w_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e070_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXR_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e078_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jff_ROR_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e080_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASR_l_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e088_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSR_l_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXRQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e090_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXR_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e098_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jff_ROR_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASR_l_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSR_l_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXR_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jff_ROR_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 op_e0d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 op_e0d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 op_e0e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 op_e0e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e0f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 op_e0f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 op_e0f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e100_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASL_b_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e108_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSL_b_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e110_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXL_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e118_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jff_ROL_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e120_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASL_b_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e128_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSL_b_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e130_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXL_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e138_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jff_ROL_b(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e140_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASL_w_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e148_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSL_w_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e150_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXL_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e158_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jff_ROL_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e160_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASL_w_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e168_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSL_w_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e170_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXL_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e178_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jff_ROL_w(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e180_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASL_l_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e188_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSL_l_imm(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e190_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXL_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e198_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jff_ROL_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1a0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_ASL_l_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1a8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jff_LSL_l_reg(data, srcreg);
+	live_flags();
+	if (!(needed_flags & FLAG_CZNV)) dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1b0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	make_flags_live();
+	jff_ROXL_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1b8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jff_ROL_l(data, cnt);
+	live_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 op_e1d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 op_e1d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 op_e1e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 op_e1e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e1f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 op_e1f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 op_e1f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ASLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 op_e2d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 op_e2d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 op_e2e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 op_e2e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e2f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 op_e2f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 op_e2f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSRW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 op_e3d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 op_e3d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 op_e3e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 op_e3e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e3f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 op_e3f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 op_e3f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_LSLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 op_e6d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 op_e6d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 op_e6e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 op_e6e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e6f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 op_e6f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 op_e6f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_RORW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 op_e7d0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 op_e7d8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 op_e7e0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 op_e7e8_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e7f0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 op_e7f8_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 op_e7f9_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jff_ROLW(src);
+	live_flags();
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BFINS.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_efc0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dst=dstreg;
+	if ((extra & 0x0820) == 0x0000) {
+	  jff_BFINS_ii(dst, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0800) {
+	  jff_BFINS_di(dst, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	  jff_BFINS_id(dst, srcreg, offs, width);
+	} else {
+	  jff_BFINS_dd(dst, srcreg, offs, width);
+	}
+	live_flags();
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_efd0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	mov_l_rr(dsta,dstreg+8);
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jff_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jff_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jff_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	live_flags();
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_efe8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	lea_l_brr(dsta,8+dstreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jff_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jff_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jff_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	live_flags();
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_eff0_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jff_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jff_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jff_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	live_flags();
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_eff8_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jff_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jff_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jff_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	live_flags();
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_eff9_0_comp_ff(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jff_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jff_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jff_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jff_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jff_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	live_flags();
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* FPP.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_f200_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,An */
+uae_u32 REGPARAM2 op_f208_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_f210_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_f218_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_f220_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_f228_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_f230_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_f238_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_f239_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_f23a_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_f23b_0_comp_ff(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_f23c_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_f240_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_f250_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_f258_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_f260_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_f268_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_f270_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_f278_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_f279_0_comp_ff(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FBccQ.L #<data>,#<data>.W */
+uae_u32 REGPARAM2 op_f280_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 63);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	comp_fbcc_opp(opcode);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FBccQ.L #<data>,#<data>.L */
+uae_u32 REGPARAM2 op_f2c0_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 63);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	comp_fbcc_opp(opcode);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_f600_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	jnf_ADD_im8(srcreg + 8, srcreg + 8, 16);
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_f608_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dsta = dstreg + 8;
+	jnf_ADD_im8(dstreg + 8, dstreg + 8, 16);
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (An),(xxx).L */
+uae_u32 REGPARAM2 op_f610_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (xxx).L,(An) */
+uae_u32 REGPARAM2 op_f618_0_comp_ff(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dsta = dstreg + 8;
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (An)+,(An)+ */
+uae_u32 REGPARAM2 op_f620_0_comp_ff(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_s32 dstreg = 0;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	{
+		uae_u16 dstreg = ((comp_get_iword((m68k_pc_offset += 2) - 2)) >> 12) & 0x07;
+		int srca = srcreg + 8;
+		int dsta = dstreg + 8;
+		jnf_MOVE16(dsta, srca);
+		if (srcreg != dstreg)
+			jnf_ADD_im8(srcreg + 8, srcreg + 8, 16);
+		jnf_ADD_im8(dstreg + 8, dstreg + 8, 16);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+																														#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+extern void comp_fpp_opp();
+
+extern void comp_fscc_opp();
+
+extern void comp_fbcc_opp();
+
+#ifdef PART_1
+
+/* OR.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_10_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_18_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_20_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_28_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_30_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_38_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_39_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ORSR.B #<data>.W */
+uae_u32 REGPARAM2 op_3c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_40_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_50_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_58_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_60_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_68_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_70_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_78_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_79_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_80_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_90_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_98_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_a0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_a8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 op_100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 op_110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 op_120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 op_13a_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_13b_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B Dn,#<data>.B */
+uae_u32 REGPARAM2 op_13c_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = alloc_scratch();
+	mov_l_ri(dst, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 op_140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	jnf_BCHG_l(dst, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 op_150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 op_160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 op_180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	jnf_BCLR_l(dst, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 op_190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 op_1a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_1a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_1b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_1b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 op_1c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	jnf_BSET_l(dst, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 op_1d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_1d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 op_1e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_1e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_1f8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_1f9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_200_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_210_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_218_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_220_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_228_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_230_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_238_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_239_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ANDSR.B #<data>.W */
+uae_u32 REGPARAM2 op_23c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_240_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_250_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_258_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_260_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_268_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_270_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_278_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_279_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_280_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_290_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_298_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_2a0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_2a8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2b0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_2b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_2b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_400_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_410_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_418_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_420_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_428_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_430_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_438_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_439_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_440_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_450_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_458_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_460_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_468_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_470_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_478_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_479_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_480_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_490_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_498_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_4a0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_4a8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4b0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_4b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_4b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_600_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_610_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_618_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_620_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_628_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_630_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_638_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_639_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_640_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_650_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_658_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_660_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_668_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_670_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_678_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_679_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_680_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_690_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_698_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_6a0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_6a8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_6b0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_6b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_6b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_800_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_810_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_818_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_820_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_828_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_830_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_838_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_839_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_83a_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BTST.B #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_83b_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_840_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	jnf_BCHG_l_imm(dst, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_850_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_858_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_860_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_868_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_870_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_878_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCHG.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_879_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCHG_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_880_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	jnf_BCLR_l_imm(dst, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_890_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_898_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_8a0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_8a8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8b0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_8b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BCLR.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_8b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BCLR_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_8c0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	jnf_BSET_l_imm(dst, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(An) */
+uae_u32 REGPARAM2 op_8d0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_8d8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_8e0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_8e8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8f0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_8f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSET.B #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_8f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	jnf_BSET_b_imm(dst, src);
+	dont_care_flags();
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_a00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_a10_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_a18_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_a20_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_a28_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_a30_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_a38_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_a39_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EORSR.B #<data>.W */
+uae_u32 REGPARAM2 op_a3c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_a40_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_a50_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_a58_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_a60_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_a68_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_a70_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_a78_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_a79_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_a80_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_a90_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_a98_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_aa0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_aa8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_ab0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_ab8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_ab9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_2
+
+/* CMP.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_c00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_c10_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_c18_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_c20_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_c28_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c30_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_c38_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_c39_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d16,PC) */
+uae_u32 REGPARAM2 op_c3a_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_c3b_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c40_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_c50_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_c58_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_c60_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_c68_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c70_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_c78_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_c79_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_c7a_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_c7b_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_c80_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_c90_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_c98_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_ca0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_ca8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_cb0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_cb8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_cb9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d16,PC) */
+uae_u32 REGPARAM2 op_cba_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_cbb_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 op_1000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 op_1010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 op_1018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 op_1020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_1028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_1030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_1038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_1039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_103a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_103b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_103c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 op_1080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 op_1090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 op_1098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 op_10a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 op_10a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 op_10b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 op_10b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 op_10b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 op_10ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 op_10bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(An) */
+uae_u32 REGPARAM2 op_10bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_10c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 op_10d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 op_10d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 op_10e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 op_10e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 op_10f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 op_10f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_10f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 op_10fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 op_10fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(An)+ */
+uae_u32 REGPARAM2 op_10fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writebyte(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 op_1100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 op_1110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 op_1118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 op_1120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 op_1128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 op_1130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 op_1138_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 op_1139_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 op_113a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 op_113b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,-(An) */
+uae_u32 REGPARAM2 op_113c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_1140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 op_1150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 op_1158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 op_1160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 op_1168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_1170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 op_1178_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 op_1179_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 op_117a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_117b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(d16,An) */
+uae_u32 REGPARAM2 op_117c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_1198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_11bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_11c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 op_11d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 op_11d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 op_11e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 op_11e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_11f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 op_11f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 op_11f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 op_11fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_11fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(xxx).W */
+uae_u32 REGPARAM2 op_11fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_13c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 op_13d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_13d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 op_13e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 op_13e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_13f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 op_13f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 op_13f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 op_13fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_13fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.B #<data>.B,(xxx).L */
+uae_u32 REGPARAM2 op_13fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writebyte(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 op_2000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 op_2008_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 op_2010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 op_2018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 op_2020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_2028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_2030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_2038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_2039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_203a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_203b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_203c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 op_2040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 op_2048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 op_2050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 op_2058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 op_2060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 op_2068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_2070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_2078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_2079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_207a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_207b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_207c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dst = dstreg + 8;
+	jnf_MOVEA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 op_2080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 op_2088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 op_2090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 op_2098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 op_20a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 op_20a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 op_20b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 op_20b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 op_20b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 op_20ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 op_20bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(An) */
+uae_u32 REGPARAM2 op_20bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_20c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 op_20c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 op_20d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 op_20d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 op_20e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 op_20e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 op_20f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 op_20f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_20f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 op_20fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 op_20fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(An)+ */
+uae_u32 REGPARAM2 op_20fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writelong(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 op_2100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 op_2108_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 op_2110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 op_2118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 op_2120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 op_2128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 op_2130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 op_2138_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 op_2139_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 op_213a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 op_213b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,-(An) */
+uae_u32 REGPARAM2 op_213c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_2140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 op_2148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 op_2150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 op_2158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 op_2160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 op_2168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_2170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 op_2178_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 op_2179_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 op_217a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_217b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(d16,An) */
+uae_u32 REGPARAM2 op_217c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_3
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_2198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_21bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_21c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 op_21c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 op_21d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 op_21d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 op_21e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 op_21e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_21f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 op_21f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 op_21f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 op_21fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_21fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(xxx).W */
+uae_u32 REGPARAM2 op_21fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_23c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 op_23c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 op_23d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_23d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 op_23e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 op_23e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_23f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 op_23f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 op_23f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 op_23fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_23fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.L #<data>.L,(xxx).L */
+uae_u32 REGPARAM2 op_23fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writelong(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 op_3000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 op_3008_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 op_3010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 op_3018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 op_3020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_3028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_3030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_3038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_3039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_303a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_303b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_303c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 op_3040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 op_3048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 op_3050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 op_3058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 op_3060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 op_3068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_3070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_3078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_3079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_307a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_307b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_307c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg + 8;
+	jnf_MOVEA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 op_3080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 op_3088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 op_3090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 op_3098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 op_30a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 op_30a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 op_30b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 op_30b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 op_30b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 op_30ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 op_30bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_30bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_30c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 op_30c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 op_30d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 op_30d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 op_30e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 op_30e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 op_30f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 op_30f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_30f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 op_30fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 op_30fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_30fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	dont_care_flags();
+	writeword(dsta, src);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 op_3100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 op_3108_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (srcreg == (uae_s32) dstreg) {
+		src = alloc_scratch();
+		mov_l_rr(src, srcreg + 8);
+	}
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 op_3110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 op_3118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 op_3120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 op_3128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 op_3130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 op_3138_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 op_3139_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 op_313a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 op_313b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_313c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_3140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 op_3148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 op_3150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 op_3158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 op_3160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 op_3168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_3170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 op_3178_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 op_3179_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 op_317a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 op_317b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_317c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_3198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_31bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_31c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 op_31c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 op_31d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 op_31d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 op_31e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 op_31e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_31f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 op_31f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 op_31f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 op_31fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 op_31fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_31fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_33c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 op_33c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 op_33d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_33d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 op_33e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 op_33e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_33f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 op_33f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 op_33f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 op_33fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 op_33fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	release_scratch(srca);
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVE.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_33fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	dont_care_flags();
+	writeword(dsta, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 op_4000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jnf_NEGX_b(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 op_4010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 op_4018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 op_4020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 op_4028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 op_4038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 op_4039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEGX_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 op_4040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jnf_NEGX_w(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 op_4050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 op_4058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 op_4060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 op_4068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 op_4078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 op_4079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEGX_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 op_4080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jnf_NEGX_l(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 op_4090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 op_4098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 op_40a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 op_40a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_40b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 op_40b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 op_40b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEGX_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 op_41d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 op_41e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_41f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_41f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_41f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_41fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_41fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int dst = dstreg + 8;
+	if (dstreg + 8 != srca)
+		mov_l_rr(dstreg + 8, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 op_4200_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_CLR_b(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 op_4210_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 op_4218_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 op_4220_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 op_4228_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4230_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 op_4238_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 op_4239_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 op_4240_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_CLR_w(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 op_4250_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 op_4258_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 op_4260_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 op_4268_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4270_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 op_4278_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 op_4279_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 op_4280_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_CLR_l(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 op_4290_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 op_4298_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 op_42a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 op_42a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_42b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 op_42b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 op_42b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	dont_care_flags();
+	jnf_CLR_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_4
+
+/* NEG.B Dn */
+uae_u32 REGPARAM2 op_4400_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jnf_NEG_b(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (An) */
+uae_u32 REGPARAM2 op_4410_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 op_4418_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 op_4420_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 op_4428_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4430_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 op_4438_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 op_4439_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	jnf_NEG_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 op_4440_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jnf_NEG_w(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 op_4450_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 op_4458_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 op_4460_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 op_4468_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4470_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 op_4478_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 op_4479_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_NEG_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 op_4480_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	jnf_NEG_l(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 op_4490_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 op_4498_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 op_44a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 op_44a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_44b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 op_44b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 op_44b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	jnf_NEG_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 op_4600_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_NOT_b(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 op_4610_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 op_4618_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 op_4620_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 op_4628_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4630_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 op_4638_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 op_4639_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	jnf_NOT_b(src);
+	writebyte(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 op_4640_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_NOT_w(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 op_4650_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 op_4658_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 op_4660_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 op_4668_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4670_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 op_4678_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 op_4679_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	jnf_NOT_w(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 op_4680_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_NOT_l(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 op_4690_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 op_4698_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 op_46a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 op_46a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_46b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 op_46b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 op_46b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	jnf_NOT_l(src);
+	writelong(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LINK.L An,#<data>.L */
+uae_u32 REGPARAM2 op_4808_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int src = dodgy ? alloc_scratch() : srcreg + 8;
+	if (dodgy)
+		mov_l_rr(src, srcreg + 8);
+	uae_s32 offs = comp_get_ilong((m68k_pc_offset += 4) - 4); /* absl */
+	sub_l_ri(15, 4);
+	writelong_clobber(15, src);
+	if (!dodgy)
+		mov_l_rr(src, 15);
+	arm_ADD_l_ri(15, offs);
+	if (srcreg + 8 != src)
+		mov_l_rr(srcreg + 8, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 op_4840_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_SWAP(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (An) */
+uae_u32 REGPARAM2 op_4850_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int srca = dodgy ? alloc_scratch() : srcreg + 8;
+	if (dodgy)
+		mov_l_rr(srca, srcreg + 8);
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 op_4868_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4870_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 op_4878_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 op_4879_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 op_487a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	{
+		int dsta = dodgy ? alloc_scratch() : 7 + 8;
+		arm_SUB_l_ri8(7 + 8, 4);
+		if (dodgy)
+			mov_l_rr(dsta, 8 + 7);
+		writelong(dsta, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_487b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	{
+		mov_l_ri(pctmp, address);
+		calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+		release_scratch(pctmp);
+		{
+			int dsta = dodgy ? alloc_scratch() : 7 + 8;
+			arm_SUB_l_ri8(7 + 8, 4);
+			if (dodgy)
+				mov_l_rr(dsta, 8 + 7);
+			writelong(dsta, srca);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 op_4880_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_EXT_w(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4890_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_48a0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				offset -= 2;
+				jnf_MVMLE_w(native, 15 - i, offset);
+			}
+		}
+		lea_l_brr(8 + dstreg, srca, (uae_s32) offset);
+	} else {
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				arm_SUB_l_ri8(srca, 2);
+				writeword(srca, 15 - i);
+			}
+		}
+		mov_l_rr(8 + dstreg, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_48a8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_48b0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_48b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_48b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_w(native, i, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writeword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 op_48c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_EXT_l(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_48d0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_48e0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				offset -= 4;
+				jnf_MVMLE_l(native, 15 - i, offset);
+			}
+		}
+		lea_l_brr(8 + dstreg, srca, (uae_s32) offset);
+	} else {
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				arm_SUB_l_ri8(srca, 4);
+				writelong(srca, 15 - i);
+			}
+		}
+		mov_l_rr(8 + dstreg, srca);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_48e8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_48f0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_48f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMLE.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_48f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMLE_l(native, i, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				writelong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXT.B Dn */
+uae_u32 REGPARAM2 op_49c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	jnf_EXT_b(src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B Dn */
+uae_u32 REGPARAM2 op_4a00_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 op_4a10_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 op_4a18_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 op_4a20_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 op_4a28_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4a30_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 op_4a38_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 op_4a39_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d16,PC) */
+uae_u32 REGPARAM2 op_4a3a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4a3b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.B #<data>.B */
+uae_u32 REGPARAM2 op_4a3c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W Dn */
+uae_u32 REGPARAM2 op_4a40_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W An */
+uae_u32 REGPARAM2 op_4a48_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (An) */
+uae_u32 REGPARAM2 op_4a50_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 op_4a58_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 op_4a60_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 op_4a68_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4a70_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 op_4a78_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 op_4a79_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d16,PC) */
+uae_u32 REGPARAM2 op_4a7a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4a7b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.W #<data>.W */
+uae_u32 REGPARAM2 op_4a7c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L Dn */
+uae_u32 REGPARAM2 op_4a80_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L An */
+uae_u32 REGPARAM2 op_4a88_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (An) */
+uae_u32 REGPARAM2 op_4a90_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 op_4a98_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 op_4aa0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 op_4aa8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4ab0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 op_4ab8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 op_4ab9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d16,PC) */
+uae_u32 REGPARAM2 op_4aba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4abb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* TST.L #<data>.L */
+uae_u32 REGPARAM2 op_4abc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	dont_care_flags();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_4c00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dst = dstreg;
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c10_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c18_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_4c20_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4c28_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4c30_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4c38_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4c39_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4c3a_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(dsta, address + PC16off);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4c3b_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dsta = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	release_scratch(pctmp);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULL.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_4c3c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int r2 = (extra >> 12) & 7;
+	int dst = alloc_scratch();
+	mov_l_ri(dst, comp_get_ilong((m68k_pc_offset += 4) - 4));
+	if (extra & 0x0400) {
+		int r3 = (extra & 7);
+		mov_l_rr(r3, dst);
+		if (extra & 0x0800) {
+			jnf_MULS64(r2, r3);
+		} else {
+			jnf_MULU64(r2, r3);
+		}
+	} else {
+		if (extra & 0x0800) {
+			jnf_MULS32(r2, dst);
+		} else {
+			jnf_MULU32(r2, dst);
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DIVL.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_4c40_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dst=dstreg;
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c50_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=dstreg+8;
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c58_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=dstreg+8;
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dstreg+8,4);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_4c60_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=dstreg+8;
+	arm_SUB_l_ri8(dstreg+8,4);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4c68_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	lea_l_brr(dsta,8+dstreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4c70_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4c78_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4c79_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4c7a_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(dsta,address+PC16off);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4c7b_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dsta=alloc_scratch();
+	int pctmp=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
+	release_scratch(pctmp);
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVL.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_4c7c_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	 uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	 int r2=(extra>>12)&7;
+	 int r3=extra&7;
+	int dst=alloc_scratch();
+	mov_l_ri(dst,comp_get_ilong((m68k_pc_offset+=4)-4));
+	register_possible_exception();
+	 if (extra & 0x0400) {
+	   FAIL(1);
+	   m68k_pc_offset=m68k_pc_offset_thisinst;
+	  return 0;
+	 } else {
+	   if (extra & 0x0800) {
+	     jnf_DIVLS32(r2,dst,r3);
+		} else {
+			  jnf_DIVLU32(r2,dst,r3);
+		}
+	 }
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* MVMEL.W #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4c90_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4c98_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				if (srca != i)
+					jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+		jnf_ADD_im8(8 + dstreg, srca, offset);
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+		mov_l_rr(8 + dstreg, tmp);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4ca8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4cb0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4cb8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4cb9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4cba_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.W #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4cbb_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_w(i, native, offset);
+				offset += 2;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readword(tmp, i);
+				arm_ADD_l_ri8(tmp, 2);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_4cd0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_4cd8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = dstreg + 8;
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				if (srca != i)
+					jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+		jnf_ADD_im8(8 + dstreg, srca, offset);
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+		mov_l_rr(8 + dstreg, tmp);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_4ce8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_4cf0_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_4cf8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_4cf9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_4cfa_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MVMEL.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4cfb_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_u16 mask = comp_get_iword((m68k_pc_offset += 2) - 2);
+	int i;
+	signed char offset = 0;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	if (!special_mem) {
+		int native = alloc_scratch();
+		get_n_addr(srca, native);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				jnf_MVMEL_l(i, native, offset);
+				offset += 4;
+			}
+		}
+	} else {
+		int tmp = alloc_scratch();
+		mov_l_rr(tmp, srca);
+		for (i = 0; i < 16; i++) {
+			if ((mask >> i) & 1) {
+				readlong(tmp, i);
+				arm_ADD_l_ri8(tmp, 4);
+			}
+		}
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LINK.W An,#<data>.W */
+uae_u32 REGPARAM2 op_4e50_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int dodgy = 0;
+	if (srcreg == 7) dodgy = 1;
+	int src = dodgy ? alloc_scratch() : srcreg + 8;
+	if (dodgy)
+		mov_l_rr(src, srcreg + 8);
+	uae_s32 offs = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	sub_l_ri(15, 4);
+	writelong_clobber(15, src);
+	if (!dodgy)
+		mov_l_rr(src, 15);
+	arm_ADD_l_ri(15, offs);
+	if (srcreg + 8 != src)
+		mov_l_rr(srcreg + 8, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 op_4e58_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	if (src == 15) {
+		readlong(15, src);
+	} else {
+		mov_l_rr(15, src);
+		readlong(15, src);
+		arm_ADD_l_ri8(15, 4);
+	}
+	if (srcreg + 8 != src)
+		mov_l_rr(srcreg + 8, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 op_4e71_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RTD.L #<data>.W */
+uae_u32 REGPARAM2 op_4e74_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 offs = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	offs += 4;
+	{
+		int newad = alloc_scratch();
+		readlong(15, newad);
+		mov_l_mr((uintptr) &regs.pc, newad);
+		get_n_addr_jmp(newad, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+		arm_ADD_l_ri(15, offs);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RTS.L  */
+uae_u32 REGPARAM2 op_4e75_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int newad = alloc_scratch();
+	readlong(15, newad);
+	mov_l_mr((uintptr) &regs.pc, newad);
+	get_n_addr_jmp(newad, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	arm_ADD_l_ri8(15, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (An) */
+uae_u32 REGPARAM2 op_4e90_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 op_4ea8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4eb0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 op_4eb8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 op_4eb9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 op_4eba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4ebb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		mov_l_mr((uintptr) &regs.pc, srca);
+		get_n_addr_jmp(srca, PC_P);
+		mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+		m68k_pc_offset = 0;
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 op_4ed0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 op_4ee8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 op_4ef0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 op_4ef8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 op_4ef9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 op_4efa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 op_4efb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	mov_l_mr((uintptr) &regs.pc, srca);
+	get_n_addr_jmp(srca, PC_P);
+	mov_l_mr((uintptr) &regs.pc_oldp, PC_P);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_5000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(An) */
+uae_u32 REGPARAM2 op_5010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,-(An) */
+uae_u32 REGPARAM2 op_5020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5038_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.B #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5039_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_5040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDAQ.W #<data>,An */
+uae_u32 REGPARAM2 op_5048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(An) */
+uae_u32 REGPARAM2 op_5050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,-(An) */
+uae_u32 REGPARAM2 op_5060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5078_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.W #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5079_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_5080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDAQ.L #<data>,An */
+uae_u32 REGPARAM2 op_5088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(An) */
+uae_u32 REGPARAM2 op_5090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_5
+
+/* ADDQ.L #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,-(An) */
+uae_u32 REGPARAM2 op_50a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_50a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_50b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_50b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDQ.L #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_50b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_50c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	mov_b_ri(srcreg, 0xff);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_50c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_50d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_50d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_50e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_50e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_50f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_50f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_50f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	mov_b_ri(val, 0xff);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_5100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(An) */
+uae_u32 REGPARAM2 op_5110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,-(An) */
+uae_u32 REGPARAM2 op_5120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.B #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_5140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBAQ.W #<data>,An */
+uae_u32 REGPARAM2 op_5148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(An) */
+uae_u32 REGPARAM2 op_5150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,-(An) */
+uae_u32 REGPARAM2 op_5160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_5168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_5170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_5178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.W #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_5179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_5180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBAQ.L #<data>,An */
+uae_u32 REGPARAM2 op_5188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(An) */
+uae_u32 REGPARAM2 op_5190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(An)+ */
+uae_u32 REGPARAM2 op_5198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,-(An) */
+uae_u32 REGPARAM2 op_51a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(d16,An) */
+uae_u32 REGPARAM2 op_51a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_51b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(xxx).W */
+uae_u32 REGPARAM2 op_51b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBQ.L #<data>,(xxx).L */
+uae_u32 REGPARAM2 op_51b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_51c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	mov_b_ri(srcreg, 0);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_51c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	sub_w_ri(src, 1);
+	uintptr v2;
+	uintptr v1 = get_const(PC_P);
+	v2 = get_const(offs);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_51d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_51d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_51e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_51e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_51f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_51f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_51f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	mov_b_ri(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_52c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 8);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_52c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 8);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_52d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_52d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_52e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_52e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_52f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_52f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_52f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 8);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_53c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 9);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_53c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 9);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_53d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_53d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_53e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_53e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_53f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_53f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_53f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 9);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_54c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 3);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_54c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 3);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_54d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_54d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_54e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_54e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_54f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_54f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_54f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 3);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_55c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_55c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 2);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_55d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_55d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_55e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_55e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_55f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_55f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_55f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 2);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_56c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 1);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_56c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 1);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_56d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_56d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_56e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_56e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_56f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_56f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_56f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 1);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_57c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 0);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_57c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 0);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_57d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_57d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_57e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_57e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_57f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_57f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_57f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 0);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_58c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 7);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_58c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 7);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_58d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_58d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_58e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_58e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_58f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_58f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_58f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 7);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_59c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 6);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_59c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 6);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_59d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_59d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_59e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_59e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_59f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_59f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_59f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 6);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5ac0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 5);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5ac8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 5);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5ad0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5ad8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5ae0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5ae8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5af0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5af8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5af9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 5);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5bc0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5bc8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 4);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5bd0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5bd8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5be0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5be8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5bf0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5bf8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5bf9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 4);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5cc0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 10);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5cc8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 10);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5cd0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5cd8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5ce0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5ce8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5cf0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5cf8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5cf9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 10);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5dc0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 11);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5dc8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 11);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5dd0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5dd8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5de0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5de8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5df0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5df8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5df9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 11);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5ec0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 12);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5ec8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 12);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5ed0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5ed8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5ee0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5ee8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5ef0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5ef8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5ef9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 12);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B Dn */
+uae_u32 REGPARAM2 op_5fc0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	make_flags_live();
+	jnf_SCC(srcreg, 13);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DBcc.W Dn,#<data>.W */
+uae_u32 REGPARAM2 op_5fc8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int offs = alloc_scratch();
+	mov_l_ri(offs, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(offs, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(offs, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(offs, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	make_flags_live();
+	uintptr v1 = get_const(PC_P);
+	uintptr v2 = get_const(offs);
+	jff_DBCC(src, 13);
+	register_branch(v1, v2, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An) */
+uae_u32 REGPARAM2 op_5fd0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (An)+ */
+uae_u32 REGPARAM2 op_5fd8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B -(An) */
+uae_u32 REGPARAM2 op_5fe0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d16,An) */
+uae_u32 REGPARAM2 op_5fe8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (d8,An,Xn) */
+uae_u32 REGPARAM2 op_5ff0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).W */
+uae_u32 REGPARAM2 op_5ff8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Scc.B (xxx).L */
+uae_u32 REGPARAM2 op_5ff9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int val = alloc_scratch();
+	make_flags_live();
+	jnf_SCC(val, 13);
+	writebyte(srca, val);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6000_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	mov_l_rr(PC_P, src);
+	comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6001_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	mov_l_rr(PC_P, src);
+	comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_60ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	mov_l_rr(PC_P, src);
+	comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSR.W #<data>.W */
+uae_u32 REGPARAM2 op_6100_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		arm_ADD_l_ri(src, m68k_pc_offset_thisinst + 2);
+		m68k_pc_offset = 0;
+		arm_ADD_l(PC_P, src);
+		comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSRQ.B #<data> */
+uae_u32 REGPARAM2 op_6101_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		arm_ADD_l_ri(src, m68k_pc_offset_thisinst + 2);
+		m68k_pc_offset = 0;
+		arm_ADD_l(PC_P, src);
+		comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BSR.L #<data>.L */
+uae_u32 REGPARAM2 op_61ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	{
+		uae_u32 retadd = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+		int ret = alloc_scratch();
+		mov_l_ri(ret, retadd);
+		sub_l_ri(15, 4);
+		writelong_clobber(15, ret);
+		arm_ADD_l_ri(src, m68k_pc_offset_thisinst + 2);
+		m68k_pc_offset = 0;
+		arm_ADD_l(PC_P, src);
+		comp_pc_p = compemu_host_pc_from_const(get_const(PC_P));
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6200_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 8);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6201_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 8);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_62ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 8);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_6
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6300_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 9);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6301_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 9);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_63ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 9);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6400_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 3);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6401_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 3);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_64ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 3);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6500_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 2);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6501_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 2);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_65ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 2);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6600_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 1);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6601_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 1);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_66ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 1);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6700_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 0);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6701_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 0);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_67ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 0);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6800_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 7);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6801_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 7);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_68ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 7);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6900_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 6);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6901_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 6);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_69ff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 6);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6a00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 5);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6a01_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 5);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6aff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 5);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6b00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 4);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6b01_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 4);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6bff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 4);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6c00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 10);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6c01_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 10);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6cff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 10);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6d00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 11);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6d01_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 11);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6dff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 11);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6e00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 12);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6e01_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 12);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6eff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 12);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.W #<data>.W */
+uae_u32 REGPARAM2 op_6f00_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 13);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BccQ.B #<data> */
+uae_u32 REGPARAM2 op_6f01_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 13);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* Bcc.L #<data>.L */
+uae_u32 REGPARAM2 op_6fff_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uintptr v1, v2;
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32)comp_get_ilong((m68k_pc_offset += 4) - 4));
+	sub_l_ri(src, m68k_pc_offset - m68k_pc_offset_thisinst - 2);
+	arm_ADD_l_ri(src, (uintptr) comp_pc_p);
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+	arm_ADD_l_ri(src, m68k_pc_offset);
+	arm_ADD_l_ri(PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+	v1 = get_const(PC_P);
+	v2 = get_const(src);
+	register_branch(v1, v2, 13);
+	make_flags_live();
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MOVEQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_7000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (uae_s32) (uae_s8) (opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = alloc_scratch();
+	mov_l_ri(src, srcreg);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_MOVE_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 op_8000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 op_8010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 op_8018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 op_8020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_8028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_8030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_8038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_8039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_803a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_803b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_803c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 op_8040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 op_8050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 op_8058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 op_8060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_8068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_8070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_8078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_8079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_807a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_807b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_807c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 op_8080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 op_8090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 op_8098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 op_80a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_80a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_80b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_80b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_80b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_80ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_80bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_80bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_OR_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 op_80c0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=srcreg;
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 op_80d0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 op_80d8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	arm_ADD_l_ri8(srcreg+8,2);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 op_80e0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	arm_SUB_l_ri8(srcreg+8,2);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_80e8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	lea_l_brr(srca,8+srcreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_80f0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	calc_disp_ea_020(srcreg+8,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_80f8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_80f9_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_80fa_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(srca,address+PC16off);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_80fb_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	int pctmp=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	release_scratch(pctmp);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVU.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_80fc_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=alloc_scratch();
+	mov_l_ri(src,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVU(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 op_8110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_8118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 op_8120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_8128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_8138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_8139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_OR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 op_8150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_8158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 op_8160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_8168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_8170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_8178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_8179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_OR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 op_8190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_8198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 op_81a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_81a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_81b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_81b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_81b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_OR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 op_81c0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=srcreg;
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 op_81d0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 op_81d8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	int src=alloc_scratch();
+	readword(srca,src);
+	arm_ADD_l_ri8(srcreg+8,2);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 op_81e0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=srcreg+8;
+	arm_SUB_l_ri8(srcreg+8,2);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_81e8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	lea_l_brr(srca,8+srcreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_81f0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	calc_disp_ea_020(srcreg+8,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_81f8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_81f9_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	mov_l_ri(srca,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_81fa_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	mov_l_ri(srca,address+PC16off);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_81fb_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int srca=alloc_scratch();
+	int pctmp=alloc_scratch();
+	uae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;
+	mov_l_ri(pctmp,address);
+	calc_disp_ea_020(pctmp,comp_get_iword((m68k_pc_offset+=2)-2),srca);
+	release_scratch(pctmp);
+	int src=alloc_scratch();
+	readword(srca,src);
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* DIVS.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_81fc_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	 dont_care_flags();
+	int src=alloc_scratch();
+	mov_l_ri(src,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	int dst=dstreg;
+	register_possible_exception();
+	jnf_DIVS(dst,src);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 op_9000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 op_9010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 op_9018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 op_9020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_9028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_9030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_9038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_9039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_903a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_903b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_903c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 op_9040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 op_9048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 op_9050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 op_9058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 op_9060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_9068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_9070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_9078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_9079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_907a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_907b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_907c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 op_9080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 op_9088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 op_9090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 op_9098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 op_90a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_90a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_90b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_90b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_90b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_90ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_90bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_90bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUB_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 op_90c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 op_90c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 op_90d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 op_90d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 op_90e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 op_90e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_90f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_90f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_90f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_90fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_90fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_90fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg + 8;
+	jnf_SUBA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 op_9100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUBX_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 op_9108_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUBX_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 op_9110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_9118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 op_9120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_9128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_9130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_9138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_9139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 op_9140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUBX_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 op_9148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUBX_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 op_9150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_9158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 op_9160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_9168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_9170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_9178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_9179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 op_9180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_SUBX_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 op_9188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUBX_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 op_9190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_9198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 op_91a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_91a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_91b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_91b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_91b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_SUB_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 op_91c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 op_91c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 op_91d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 op_91d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 op_91e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 op_91e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_91f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_91f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_91f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_91fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_91fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_SUBA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* SUBA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_91fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg + 8;
+	jnf_SUBA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 op_b000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 op_b010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 op_b018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 op_b020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_b028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_b030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_b038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_b039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_b03a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_b03b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_b03c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 op_b040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 op_b048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 op_b050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 op_b058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 op_b060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_b068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_b070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_b078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_b079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_b07a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_b07b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_b07c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 op_b080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 op_b088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 op_b090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_7
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 op_b098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 op_b0a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_b0a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_b0b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_b0b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_b0b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_b0ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_b0bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMP.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_b0bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 op_b0c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 op_b0c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 op_b0d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 op_b0d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 op_b0e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 op_b0e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_b0f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_b0f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_b0f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_b0fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_b0fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_b0fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 op_b100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 op_b108_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 op_b110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_b118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 op_b120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_b128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_b138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_b139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 op_b140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 op_b148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 op_b150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_b158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 op_b160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_b168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_b178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_b179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 op_b180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 op_b188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 op_b190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_b198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 op_b1a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_b1a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_b1b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_b1b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_b1b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_EOR_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 op_b1c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 op_b1c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 op_b1d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 op_b1d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 op_b1e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 op_b1e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_b1f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_b1f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_b1f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_b1fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_b1fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* CMPA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_b1fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg + 8;
+	dont_care_flags();
+/* Weird --- CMP with noflags ;-) */
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 op_c000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 op_c010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 op_c018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 op_c020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_c028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c03a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c03b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_c03c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 op_c040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 op_c050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 op_c058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 op_c060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_c068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c07a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c07b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c07c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 op_c080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 op_c090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 op_c098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 op_c0a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_c0a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c0b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c0b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c0b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c0ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c0bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_c0bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_AND_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 op_c0c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = srcreg;
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 op_c0d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 op_c0d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 op_c0e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_c0e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c0f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c0f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c0f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c0fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c0fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULU.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c0fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg;
+	jnf_MULU(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 op_c110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_c118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 op_c120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_c128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_c138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_c139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_AND_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 op_c140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	int tmp = alloc_scratch();
+	mov_l_rr(tmp, src);
+	if (srcreg != dst)
+		mov_l_rr(srcreg, dst);
+	if (dstreg != tmp)
+		mov_l_rr(dstreg, tmp);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 op_c148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	int tmp = alloc_scratch();
+	mov_l_rr(tmp, src);
+	if (srcreg + 8 != dst)
+		mov_l_rr(srcreg + 8, dst);
+	if (dstreg + 8 != tmp)
+		mov_l_rr(dstreg + 8, tmp);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 op_c150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_c158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 op_c160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_c168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_c178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_c179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_AND_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 op_c188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	int tmp = alloc_scratch();
+	mov_l_rr(tmp, src);
+	if (srcreg != dst)
+		mov_l_rr(srcreg, dst);
+	if (dstreg + 8 != tmp)
+		mov_l_rr(dstreg + 8, tmp);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 op_c190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_c198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 op_c1a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_c1a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_c1b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_c1b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_c1b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_AND_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 op_c1c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = srcreg;
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 op_c1d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 op_c1d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 op_c1e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_c1e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_c1f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_c1f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_c1f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_c1fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_c1fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* MULS.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_c1fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int src = alloc_scratch();
+	mov_l_ri(src, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = dstreg;
+	jnf_MULS(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 op_d000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 op_d010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 op_d018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 op_d020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 op_d028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_d030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 op_d038_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 op_d039_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 op_d03a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_d03b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B #<data>.B,Dn */
+uae_u32 REGPARAM2 op_d03c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s8) comp_get_ibyte((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_b_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 op_d040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 op_d048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 op_d050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 op_d058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 op_d060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 op_d068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_d070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 op_d078_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 op_d079_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 op_d07a_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_d07b_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W #<data>.W,Dn */
+uae_u32 REGPARAM2 op_d07c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 op_d080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 op_d088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 op_d090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 op_d098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 op_d0a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 op_d0a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 op_d0b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 op_d0b8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 op_d0b9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 op_d0ba_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 op_d0bb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L #<data>.L,Dn */
+uae_u32 REGPARAM2 op_d0bc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADD_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 op_d0c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 op_d0c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 op_d0d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 op_d0d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 op_d0e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 op_d0e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_d0f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 op_d0f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 op_d0f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 op_d0fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_d0fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.W #<data>.W,An */
+uae_u32 REGPARAM2 op_d0fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	int dst = dstreg + 8;
+	jnf_ADDA_w_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 op_d100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADDX_b(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 op_d108_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, areg_byteinc[srcreg]);
+	int src = alloc_scratch();
+	readbyte(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADDX_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 op_d110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 op_d118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 op_d120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, areg_byteinc[dstreg]);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 op_d128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_d130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 op_d138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 op_d139_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readbyte(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_b(dst, src);
+	writebyte(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 op_d140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADDX_w(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 op_d148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADDX_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 op_d150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 op_d158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 op_d160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 2);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 op_d168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_d170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 op_d178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 op_d179_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readword(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_w(dst, src);
+	writeword(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 op_d180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg;
+	dont_care_flags();
+	jnf_ADDX_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 op_d188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADDX_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 op_d190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 op_d198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	arm_ADD_l_ri8(dstreg + 8, 4);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 op_d1a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = dstreg + 8;
+	arm_SUB_l_ri8(dstreg + 8, 4);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 op_d1a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	lea_l_brr(dsta, 8 + dstreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_d1b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	calc_disp_ea_020(dstreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), dsta);
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 op_d1b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 op_d1b9_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dst = alloc_scratch();
+	readlong(dsta, dst);
+	dont_care_flags();
+	jnf_ADD_l(dst, src);
+	writelong(dsta, dst);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 op_d1c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg;
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 op_d1c8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int src = srcreg + 8;
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 op_d1d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 op_d1d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readlong(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 4);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 op_d1e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 4);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 op_d1e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 op_d1f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 op_d1f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 op_d1f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 op_d1fa_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
+	mov_l_ri(srca, address + PC16off);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 op_d1fb_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	int srca = alloc_scratch();
+	int pctmp = alloc_scratch();
+	uae_u32 address = start_pc + ((char *) comp_pc_p - (char *) start_pc_p) + m68k_pc_offset;
+	mov_l_ri(pctmp, address);
+	calc_disp_ea_020(pctmp, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	release_scratch(pctmp);
+	int src = alloc_scratch();
+	readlong(srca, src);
+	int dst = dstreg + 8;
+	jnf_ADDA_l(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ADDA.L #<data>.L,An */
+uae_u32 REGPARAM2 op_d1fc_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	uae_s32 src = comp_get_ilong((m68k_pc_offset += 4) - 4);
+	int dst = dstreg + 8;
+	jnf_ADDA_l_imm(dst, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e000_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_ASR_b_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e008_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSR_b_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXRQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e010_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROXR_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e018_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROR_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e020_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_ASR_b_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e028_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSR_b_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+#endif
+
+#ifdef PART_8
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e030_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROXR_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 op_e038_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROR_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e040_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_ASR_w_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e048_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSR_w_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXRQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e050_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROXR_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e058_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROR_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e060_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_ASR_w_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e068_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSR_w_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e070_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROXR_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 op_e078_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROR_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e080_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_ASR_l_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e088_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSR_l_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXRQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e090_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROXR_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e098_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROR_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_ASR_l_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSR_l_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROXR_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 op_e0b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROR_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 op_e0d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 op_e0d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 op_e0e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 op_e0e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e0f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 op_e0f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 op_e0f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e100_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_b_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e108_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_b_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e110_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROXL_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLQ.B #<data>,Dn */
+uae_u32 REGPARAM2 op_e118_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROL_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e120_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_b_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e128_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_b_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e130_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROXL_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 op_e138_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROL_b(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e140_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_w_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e148_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_w_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e150_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROXL_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLQ.W #<data>,Dn */
+uae_u32 REGPARAM2 op_e158_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROL_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e160_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_w_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e168_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_w_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e170_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROXL_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 op_e178_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROL_w(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e180_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_l_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e188_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_l_imm(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e190_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROXL_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLQ.L #<data>,Dn */
+uae_u32 REGPARAM2 op_e198_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = alloc_scratch();
+	mov_l_ri(cnt, srcreg);
+	int data = dstreg;
+	jnf_ROL_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1a0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_l_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1a8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int data = dstreg;
+	jnf_LSL_l_reg(data, srcreg);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1b0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROXL_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 op_e1b8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int cnt = srcreg;
+	int data = dstreg;
+	jnf_ROL_l(data, cnt);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 op_e1d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 op_e1d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 op_e1e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 op_e1e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e1f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 op_e1f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 op_e1f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ASLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 op_e2d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 op_e2d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 op_e2e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 op_e2e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e2f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 op_e2f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 op_e2f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSRW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 op_e3d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 op_e3d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 op_e3e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 op_e3e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e3f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 op_e3f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 op_e3f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_LSLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 op_e6d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 op_e6d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 op_e6e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 op_e6e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e6f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 op_e6f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 op_e6f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_RORW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 op_e7d0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 op_e7d8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	arm_ADD_l_ri8(srcreg + 8, 2);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 op_e7e0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = srcreg + 8;
+	arm_SUB_l_ri8(srcreg + 8, 2);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 op_e7e8_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	lea_l_brr(srca, 8 + srcreg, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 op_e7f0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	calc_disp_ea_020(srcreg + 8, comp_get_iword((m68k_pc_offset += 2) - 2), srca);
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 op_e7f8_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2));
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 op_e7f9_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	dont_care_flags();
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int src = alloc_scratch();
+	readword(srca, src);
+	jnf_ROLW(src);
+	writeword(srca, src);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	return 0;
+}
+
+/* BFINS.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_efc0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dst=dstreg;
+	if ((extra & 0x0820) == 0x0000) {
+	  jnf_BFINS_ii(dst, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0800) {
+	  jnf_BFINS_di(dst, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	  jnf_BFINS_id(dst, srcreg, offs, width);
+	} else {
+	  jnf_BFINS_dd(dst, srcreg, offs, width);
+	}
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_efd0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	mov_l_rr(dsta,dstreg+8);
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jnf_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_efe8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	lea_l_brr(dsta,8+dstreg,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jnf_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_eff0_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	calc_disp_ea_020(dstreg+8,comp_get_iword((m68k_pc_offset+=2)-2),dsta);
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jnf_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_eff8_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,(uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2));
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jnf_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* BFINS.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_eff9_0_comp_nf(uae_u32 opcode) {
+#if !defined(ARMV6T2) && !defined(CPU_AARCH64)
+	FAIL(1);
+	return 0;
+#else
+																															uae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;
+	m68k_pc_offset+=2;
+	dont_care_flags();
+	uae_u16 extra=comp_get_iword((m68k_pc_offset+=2)-2);
+	int srcreg = (extra >> 12) & 7;
+	int offs, width;
+	if ((extra & 0x0800) == 0x0000)
+	  offs = (extra >> 6) & 0x1f;
+	else
+	  offs = (extra >> 6) & 0x07;
+	if ((extra & 0x0020) == 0x0000)
+	  width = ((extra - 1) & 0x1f) + 1;
+	else
+	  width = (extra & 0x07);
+	int dsta=alloc_scratch();
+	mov_l_ri(dsta,comp_get_ilong((m68k_pc_offset+=4)-4)); /* absl */
+	if ((extra & 0x0800) == 0x0800) {
+	  arm_ADD_ldiv8(dsta,offs);
+	}
+	int dst=alloc_scratch();
+	readlong(dsta,dst);
+	arm_ADD_l_ri8(dsta, 4);
+	int dst2=alloc_scratch();
+	readlong(dsta,dst2);
+	if ((extra & 0x0820) == 0x0000) {
+	  if(32 - offs - width >= 0) {
+	    jnf_BFINS_ii(dst, srcreg, offs, width);
+	  } else {
+	    jnf_BFINS2_ii(dst, dst2, srcreg, offs, width);
+	  }
+	} else if ((extra & 0x0820) == 0x0800) {
+	    jnf_BFINS2_di(dst, dst2, srcreg, offs, width);
+	} else if ((extra & 0x0820) == 0x0020) {
+	    jnf_BFINS2_id(dst, dst2, srcreg, offs, width);
+	} else {
+	    jnf_BFINS2_dd(dst, dst2, srcreg, offs, width);
+	}
+	writelong(dsta,dst2);
+	arm_SUB_l_ri8(dsta, 4);
+	writelong(dsta,dst);
+	 if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();
+return 0;
+#endif
+}
+
+/* FPP.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_f200_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,An */
+uae_u32 REGPARAM2 op_f208_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_f210_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_f218_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_f220_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_f228_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_f230_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_f238_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_f239_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d16,PC) */
+uae_u32 REGPARAM2 op_f23a_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 2;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 op_f23b_0_comp_nf(uae_u32 opcode) {
+	uae_s32 dstreg = 3;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FPP.L #<data>.W,#<data>.L */
+uae_u32 REGPARAM2 op_f23c_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fpp_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,Dn */
+uae_u32 REGPARAM2 op_f240_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(An) */
+uae_u32 REGPARAM2 op_f250_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(An)+ */
+uae_u32 REGPARAM2 op_f258_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,-(An) */
+uae_u32 REGPARAM2 op_f260_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(d16,An) */
+uae_u32 REGPARAM2 op_f268_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 op_f270_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(xxx).W */
+uae_u32 REGPARAM2 op_f278_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FScc.L #<data>.W,(xxx).L */
+uae_u32 REGPARAM2 op_f279_0_comp_nf(uae_u32 opcode) {
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	uae_u16 extra = comp_get_iword((m68k_pc_offset += 2) - 2);
+	comp_fscc_opp(opcode, extra);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FBccQ.L #<data>,#<data>.W */
+uae_u32 REGPARAM2 op_f280_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 63);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	comp_fbcc_opp(opcode);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* FBccQ.L #<data>,#<data>.L */
+uae_u32 REGPARAM2 op_f2c0_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 63);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+#ifdef USE_JIT_FPU
+	comp_fbcc_opp(opcode);
+#else
+	failure = 1;
+#endif
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 op_f600_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	jnf_ADD_im8(srcreg + 8, srcreg + 8, 16);
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 op_f608_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dsta = dstreg + 8;
+	jnf_ADD_im8(dstreg + 8, dstreg + 8, 16);
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (An),(xxx).L */
+uae_u32 REGPARAM2 op_f610_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = srcreg + 8;
+	int dsta = alloc_scratch();
+	mov_l_ri(dsta, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (xxx).L,(An) */
+uae_u32 REGPARAM2 op_f618_0_comp_nf(uae_u32 opcode) {
+	uae_u32 dstreg = opcode & 7;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	int srca = alloc_scratch();
+	mov_l_ri(srca, comp_get_ilong((m68k_pc_offset += 4) - 4)); /* absl */
+	int dsta = dstreg + 8;
+	jnf_MOVE16(dsta, srca);
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+/* MOVE16.L (An)+,(An)+ */
+uae_u32 REGPARAM2 op_f620_0_comp_nf(uae_u32 opcode) {
+	uae_s32 srcreg = (opcode & 7);
+	uae_s32 dstreg = 0;
+	uae_u32 m68k_pc_offset_thisinst = m68k_pc_offset;
+	m68k_pc_offset += 2;
+	if (special_mem) {
+		FAIL(1);
+		return 0;
+	}
+	{
+		uae_u16 dstreg = ((comp_get_iword((m68k_pc_offset += 2) - 2)) >> 12) & 0x07;
+		int srca = srcreg + 8;
+		int dsta = dstreg + 8;
+		jnf_MOVE16(dsta, srca);
+		if (srcreg != dstreg)
+			jnf_ADD_im8(srcreg + 8, srcreg + 8, 16);
+		jnf_ADD_im8(dstreg + 8, dstreg + 8, 16);
+	}
+	if (m68k_pc_offset > SYNC_PC_OFFSET) sync_m68k_pc();
+	if (failure) m68k_pc_offset = m68k_pc_offset_thisinst;
+	return 0;
+}
+
+#endif
+
+#endif
diff --git a/jit/arm/compemu_arm.h b/jit/arm/compemu_arm.h
new file mode 100644
index 00000000..bca82c0a
--- /dev/null
+++ b/jit/arm/compemu_arm.h
@@ -0,0 +1,410 @@
+/*
+ * compiler/compemu.h - Public interface and definitions
+ *
+ * Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ * This file is part of the ARAnyM project which builds a new and powerful
+ * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
+ *
+ * JIT compiler m68k -> IA-32 and AMD64
+ *
+ * Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ * Adaptation for Basilisk II and improvements, copyright 2000-2004 Gwenole Beauchesne
+ * Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
+ *
+ * ARAnyM is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * ARAnyM is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with ARAnyM; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef COMPEMU_H
+#define COMPEMU_H
+
+#include "sysconfig.h"
+#include "newcpu.h"
+
+#ifdef UAE
+#ifdef CPU_64_BIT
+typedef uae_u64 uintptr;
+typedef uae_s64 intptr;
+#else
+typedef uae_u32 uintptr;
+#endif
+/* FIXME: cpummu.cpp also checks for USE_JIT, possibly others */
+#define USE_JIT
+#endif
+
+#define JITPTR (uintptr)
+
+/* Now that we do block chaining, and also have linked lists on each tag,
+   TAGMASK can be much smaller and still do its job. Saves several megs
+   of memory! */
+#define TAGMASK 0x0000ffff
+#define TAGSIZE (TAGMASK+1)
+#define MAXRUN 1024
+#define cacheline(x) (((uintptr)x)&TAGMASK)
+
+extern uae_u8* start_pc_p;
+extern uae_u32 start_pc;
+
+struct blockinfo_t;
+
+typedef struct {
+  uae_u16* location;
+  uae_u8  specmem;
+} cpu_history;
+
+typedef union {
+  cpuop_func* handler;
+  struct blockinfo_t* bi;
+} cacheline;
+
+#define USE_F_ALIAS 1
+#define USE_OFFSET 1
+#define COMP_DEBUG 1
+
+#if COMP_DEBUG
+#define Dif(x) if (x)
+#else
+#define Dif(x) if (0)
+#endif
+
+#define SCALE 2
+#define MAXCYCLES (1000 * CYCLE_UNIT)
+
+#define BYTES_PER_INST 10240  /* paranoid ;-) */
+#if defined(CPU_arm)
+#define LONGEST_68K_INST 256 /* The number of bytes the longest possible
+			       68k instruction takes */
+#else
+#define LONGEST_68K_INST 16 /* The number of bytes the longest possible
+			       68k instruction takes */
+#endif
+#define MAX_CHECKSUM_LEN 2048 /* The maximum size we calculate checksums
+				 for. Anything larger will be flushed
+				 unconditionally even with SOFT_FLUSH */
+#define MAX_HOLD_BI 3  /* One for the current block, and up to two
+			  for jump targets */
+
+#if 1
+// gb-- my format from readcpu.cpp is not the same
+#define FLAG_X    0x0010
+#define FLAG_N    0x0008
+#define FLAG_Z    0x0004
+#define FLAG_V    0x0002
+#define FLAG_C    0x0001
+#else
+#define FLAG_C    0x0010
+#define FLAG_V    0x0008
+#define FLAG_Z    0x0004
+#define FLAG_N    0x0002
+#define FLAG_X    0x0001
+#endif
+#define FLAG_CZNV (FLAG_C | FLAG_Z | FLAG_N | FLAG_V)
+#define FLAG_ALL  (FLAG_C | FLAG_Z | FLAG_N | FLAG_V | FLAG_X)
+#define FLAG_ZNV  (FLAG_Z | FLAG_N | FLAG_V)
+
+#if defined(CPU_arm) && !defined(ARMV6T2) && !defined(CPU_AARCH64)
+#define USE_DATA_BUFFER
+#elif defined(CPU_AARCH64)
+#define N_REGS 18   /* really 32, but 29 to 31 are FP, LR, SP; 18 has special meaning; 27 holds memstart and 28 holds regs-struct */
+#else
+#define N_REGS 11  /* really 16, but 13 to 15 are SP, LR, PC; 11 holds memstart and 12 is scratch register */
+#endif
+
+#define N_FREGS 16  // We use 10 regs: 6 - FP_RESULT, 7 - SCRATCH, 8-15 - Amiga regs FP0-FP7
+
+/* Functions exposed to newcpu, or to what was moved from newcpu.c to
+ * compemu_support.c */
+extern void compiler_init(void);
+extern void compiler_exit(void);
+extern void build_comp(void);
+extern void set_cache_state(int enabled);
+#ifdef JIT
+extern void (*flush_icache)(int);
+#endif
+extern void alloc_cache(void);
+extern void compile_block(cpu_history* pc_hist, int blocklen, int totcyles);
+extern int check_for_cache_miss(void);
+
+#define scaled_cycles(x) (currprefs.m68k_speed<0?(((x)/SCALE)?(((x)/SCALE<MAXCYCLES?((x)/SCALE):MAXCYCLES)):1):(x))
+
+/* JIT FPU compilation */
+extern void comp_fpp_opp (uae_u32 opcode, uae_u16 extra);
+extern void comp_fbcc_opp (uae_u32 opcode);
+extern void comp_fscc_opp (uae_u32 opcode, uae_u16 extra);
+
+extern uae_u32 needed_flags;
+extern uae_u8* comp_pc_p;
+extern void* pushall_call_handler;
+
+#define VREGS 22
+#define VFREGS 10
+
+#define INMEM 1
+#define CLEAN 2
+#define DIRTY 3
+#define UNDEF 4
+#define ISCONST 5
+
+typedef struct {
+  uae_u32* mem;
+  uintptr val;  /* Must be pointer-width: PC_P holds a host pointer (64-bit on ARM64) */
+  uae_u8 status;
+  uae_s8 realreg; /* gb-- realreg can hold -1 */
+  uae_u8 realind; /* The index in the holds[] array */
+  uae_u8 needflush;
+} reg_status;
+
+typedef struct {
+  uae_u32* mem;
+  uae_u8 status;
+  uae_s8 realreg; /* gb-- realreg can hold -1 */
+  uae_u8 needflush;
+} freg_status;
+
+typedef struct {
+  uae_u8 use_flags;
+  uae_u8 set_flags;
+  uae_u8 is_addx;
+  uae_u8 cflow;
+} op_properties;
+
+extern op_properties prop[65536];
+
+STATIC_INLINE int end_block(uae_u16 opcode)
+{
+	return (prop[opcode].cflow & fl_end_block);
+}
+
+#define SP_REG 15
+#define PC_P 16
+#define FLAGX 17
+#define FLAGTMP 18
+
+#define S1 19
+#define S2 20
+#define S3 21
+#define SCRATCH_REGS 3
+
+#define FP_RESULT 8
+#define FS1 9
+
+#define SCRATCH_F64_1  1
+#define SCRATCH_F64_2  2
+#define SCRATCH_F64_3  3
+#define SCRATCH_F64_4  4
+#define SCRATCH_F32_1  2
+#define SCRATCH_F32_2  4
+#define SCRATCH_F32_3  6
+#define SCRATCH_F32_4  8
+
+typedef struct {
+  uae_u32 touched;
+  uae_s8 holds[VREGS];
+  uae_u8 nholds;
+  uae_u8 locked;
+} n_status;
+
+typedef struct {
+  uae_s8 holds;
+  uae_u8 nholds;
+} fn_status;
+
+/* For flag handling */
+#define NADA 1
+#define TRASH 2
+#define VALID 3
+
+/* needflush values */
+#define NF_SCRATCH   0
+#define NF_TOMEM     1
+#define NF_HANDLER   2
+
+typedef struct {
+  /* Integer part */
+  reg_status state[VREGS];
+  n_status   nat[N_REGS];
+  uae_u32 flags_on_stack;
+  uae_u32 flags_in_flags;
+  uae_u32 flags_are_important;
+  uae_u32 scratch_in_use[SCRATCH_REGS];
+  /* FPU part */
+  freg_status fate[VFREGS];
+  fn_status   fat[N_FREGS];
+} bigstate;
+
+typedef struct {
+	/* Integer part */
+	uae_s8 virt[VREGS];
+	uae_s8 nat[N_REGS];
+} smallstate;
+
+#define IM8 uae_s32
+#define IM16 uae_s32
+#define IM32 uae_s32
+#define IMPTR uintptr
+#define RR1 uae_u32
+#define RR2 uae_u32
+#define RR4 uae_u32
+#define W1  uae_u32
+#define W2  uae_u32
+#define W4  uae_u32
+#define RW1 uae_u32
+#define RW2 uae_u32
+#define RW4 uae_u32
+#define MEMR uintptr
+#define MEMW uintptr
+#define MEMRW uintptr
+
+#define FW   uae_u32
+#define FR   uae_u32
+#define FRW  uae_u32
+
+#define MIDFUNC(nargs,func,args) void func args
+#define MENDFUNC(nargs,func,args)
+#define COMPCALL(func) func
+
+#define LOWFUNC(flags,mem,nargs,func,args) STATIC_INLINE void func args
+#define LENDFUNC(flags,mem,nargs,func,args)
+
+/* What we expose to the outside */
+#define DECLARE_MIDFUNC(func) extern void func
+
+#if defined(CPU_arm)
+#include "compemu_midfunc_arm.h"
+#include "compemu_midfunc_arm2.h"
+#endif
+
+#undef DECLARE_MIDFUNC
+
+extern int failure;
+#define FAIL(x) do { failure|=x; } while (0)
+
+/* Convenience functions exposed to gencomp */
+extern uae_u32 m68k_pc_offset;
+/* address and dest are virtual register numbers */
+extern void readbyte(int address, int dest);
+extern void readword(int address, int dest);
+extern void readlong(int address, int dest);
+extern void writebyte(int address, int source);
+extern void writeword(int address, int source);
+extern void writelong(int address, int source);
+extern void writeword_clobber(int address, int source);
+extern void writelong_clobber(int address, int source);
+extern void get_n_addr(int address, int dest);
+extern void get_n_addr_jmp(int address, int dest);
+extern void calc_disp_ea_020(int base, uae_u32 dp, int target);
+#define SYNC_PC_OFFSET 124
+extern void sync_m68k_pc(void);
+extern uintptr get_const(int r);
+extern uae_u8* compemu_host_pc_from_const(uintptr pc_const);
+extern void register_branch(uintptr not_taken, uintptr taken, uae_u8 cond);
+extern void register_possible_exception(void);
+
+#define comp_get_ibyte(o) do_get_mem_byte((uae_u8 *)(comp_pc_p + (o) + 1))
+#define comp_get_iword(o) do_get_mem_word((uae_u16 *)(comp_pc_p + (o)))
+#define comp_get_ilong(o) do_get_mem_long((uae_u32 *)(comp_pc_p + (o)))
+
+extern int alloc_scratch(void);
+extern void release_scratch(int i);
+
+struct blockinfo_t;
+
+typedef struct dep_t {
+  uae_u32*            jmp_off;
+  struct blockinfo_t* target;
+  struct blockinfo_t* source;
+  struct dep_t**      prev_p;
+  struct dep_t*       next;
+} dependency;
+
+typedef struct checksum_info_t {
+  uae_u8 *start_p;
+  uae_u32 length;
+  struct checksum_info_t *next;
+} checksum_info;
+
+typedef struct blockinfo_t {
+  uae_s32 count;
+  cpuop_func* direct_handler_to_use;
+  cpuop_func* handler_to_use;
+  /* The direct handler does not check for the correct address */
+
+  cpuop_func* handler;
+  cpuop_func* direct_handler;
+
+  cpuop_func* direct_pen;
+  cpuop_func* direct_pcc;
+
+  uae_u8* nexthandler;
+  uae_u8* pc_p;
+
+  uae_u32 c1;
+  uae_u32 c2;
+  checksum_info *csi;
+
+  struct blockinfo_t* next_same_cl;
+  struct blockinfo_t** prev_same_cl_p;
+  struct blockinfo_t* next;
+  struct blockinfo_t** prev_p;
+
+  uae_u8 optlevel;
+  uae_u8 needed_flags;
+  uae_u8 status;
+
+  dependency  dep[2];  /* Holds things we depend on */
+  dependency* deplist; /* List of things that depend on this */
+} blockinfo;
+
+#define BI_INVALID 0
+#define BI_ACTIVE 1
+#define BI_NEED_RECOMP 2
+#define BI_NEED_CHECK 3
+#define BI_CHECKING 4
+#define BI_COMPILING 5
+#define BI_FINALIZING 6
+
+extern const int POPALLSPACE_SIZE;
+
+void execute_normal(void);
+void exec_nostats(void);
+void do_nothing(void);
+void execute_exception(uae_u32 cycles);
+
+typedef fptype fpu_register;
+
+/* Flags for Bernie during development/debugging. Should go away eventually */
+#define DISTRUST_CONSISTENT_MEM 0
+
+void jit_abort(const TCHAR *format,...);
+
+#ifdef CPU_64_BIT
+static inline uae_u32 check_uae_p32(uintptr address, const char* file, int line)
+{
+	if (address > (uintptr_t)0xffffffff) {
+#if !defined(CPU_AARCH64)
+		jit_abort("JIT: 64-bit pointer (0x%llx) at %s:%d (fatal)",
+			(unsigned long long)address, file, line);
+#endif
+	}
+	return (uae_u32)address;
+}
+#define uae_p32(x) (check_uae_p32((uintptr)(x), __FILE__, __LINE__))
+#else
+#define uae_p32(x) ((uae_u32)(x))
+#endif
+
+#endif /* COMPEMU_H */
diff --git a/jit/arm/compemu_fpp_arm.cpp b/jit/arm/compemu_fpp_arm.cpp
new file mode 100644
index 00000000..b4050d8f
--- /dev/null
+++ b/jit/arm/compemu_fpp_arm.cpp
@@ -0,0 +1,973 @@
+/*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * MC68881 emulation
+  *
+  * Copyright 1996 Herman ten Brugge
+  * Adapted for JIT compilation (c) Bernd Meyer, 2000
+  * Modified 2005 Peter Keunecke
+ */
+
+#include <cmath>
+
+#include "sysdeps.h"
+
+#include "options.h"
+#include "memory.h"
+#include "newcpu.h"
+#include "compemu_arm.h"
+#include "flags_arm.h"
+
+#if defined(USE_JIT_FPU)
+
+extern void fp_to_exten(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3);
+
+static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
+static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
+
+/* return the required floating point precision or -1 for failure, 0=E, 1=S, 2=D */
+STATIC_INLINE int comp_fp_get (uae_u32 opcode, uae_u16 extra, int treg)
+{
+	int reg = opcode & 7;
+	int mode = (opcode >> 3) & 7;
+	int size = (extra >> 10) & 7;
+
+	if (size == 3 || size == 7) /* 3 = packed decimal, 7 is not defined */
+		return -1;
+	switch (mode) {
+		case 0: /* Dn */
+		switch (size) {
+			case 0: /* Long */
+			fmov_l_rr (treg, reg);
+			return 2;
+			case 1: /* Single */
+			fmov_s_rr (treg, reg);
+			return 1;
+			case 4: /* Word */
+			fmov_w_rr (treg, reg);
+			return 1;
+			case 6: /* Byte */
+			  fmov_b_rr (treg, reg);
+			return 1;
+			default:
+			return -1;
+		}
+		case 1: /* An,  invalid mode */
+		return -1;
+		case 2: /* (An) */
+		mov_l_rr (S1, reg + 8);
+		break;
+		case 3: /* (An)+ */
+		mov_l_rr (S1, reg + 8);
+      arm_ADD_l_ri8(reg + 8, (reg == 7 ? sz2[size] : sz1[size]));
+		break;
+		case 4: /* -(An) */
+		  arm_SUB_l_ri8(reg + 8, (reg == 7 ? sz2[size] : sz1[size]));
+		mov_l_rr (S1, reg + 8);
+		break;
+		case 5: /* (d16,An)  */
+		{
+			uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+			mov_l_rr (S1, reg + 8);
+			lea_l_brr (S1, S1, off);
+			break;
+		}
+		case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
+		{
+			uae_u32 dp = comp_get_iword ((m68k_pc_offset += 2) - 2);
+			calc_disp_ea_020 (reg + 8, dp, S1);
+			break;
+		}
+		case 7:
+		switch (reg) {
+			case 0: /* (xxx).W */
+			{
+				uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+				mov_l_ri (S1, off);
+				break;
+			}
+			case 1: /* (xxx).L */
+			{
+				uae_u32 off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				mov_l_ri (S1, off);
+				break;
+			}
+			case 2: /* (d16,PC) */
+			{
+				uae_u32 address = start_pc + ((uae_char*) comp_pc_p - (uae_char*) start_pc_p) +	m68k_pc_offset;
+				uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+				mov_l_ri (S1, address + PC16off);
+				break;
+			}
+			case 3: /* (d8,PC,Xn) or (bd,PC,Xn) or ([bd,PC,Xn],od) or ([bd,PC],Xn,od) */
+			  return -1; /* rarely used, fallback to non-JIT */
+			case 4: /* # < data >; Constants should be converted just once by the JIT */
+			m68k_pc_offset += sz2[size];
+			switch (size) {
+				case 0:
+				{
+					uae_s32 li = comp_get_ilong(m68k_pc_offset - 4);
+					float si = (float)li;
+
+					if (li == (int)si) {
+						    //write_log ("converted immediate LONG constant to SINGLE\n");
+						fmov_s_ri(treg, *(uae_u32 *)&si);
+						return 1;
+					}
+					    //write_log ("immediate LONG constant\n");
+					fmov_l_ri(treg, *(uae_u32 *)&li);
+					return 2;
+				}
+				case 1:
+				      //write_log (_T("immediate SINGLE constant\n"));
+				fmov_s_ri(treg, comp_get_ilong(m68k_pc_offset - 4));
+				return 1;
+				case 2:
+            {
+				      //write_log (_T("immediate LONG DOUBLE constant\n"));
+              uae_u32 wrd1, wrd2, wrd3;
+              fpdata tmp;
+              wrd3 = comp_get_ilong(m68k_pc_offset - 4);
+              wrd2 = comp_get_ilong(m68k_pc_offset - 8);
+              wrd1 = comp_get_iword(m68k_pc_offset - 12) << 16;
+			  fp_to_exten(&tmp, wrd1, wrd2, wrd3);
+              mov_l_ri(S1, ((uae_u32*)&tmp)[0]);
+              mov_l_ri(S2, ((uae_u32*)&tmp)[1]);
+              fmov_d_rrr (treg, S1, S2);
+				return 0;
+            }
+				case 4:
+				{
+					float si = (float)(uae_s16)comp_get_iword(m68k_pc_offset-2);
+
+					    //write_log (_T("converted immediate WORD constant %f to SINGLE\n"), si);
+					fmov_s_ri(treg, *(uae_u32 *)&si);
+					return 1;
+				}
+				case 5:
+				{
+					    //write_log (_T("immediate DOUBLE constant\n"));
+              mov_l_ri(S1, comp_get_ilong(m68k_pc_offset - 4));
+              mov_l_ri(S2, comp_get_ilong(m68k_pc_offset - 8));
+              fmov_d_rrr (treg, S1, S2);
+					return 2;
+				}
+				case 6:
+				{
+					float si = (float)(uae_s8)comp_get_ibyte(m68k_pc_offset - 2);
+
+					//write_log (_T("converted immediate BYTE constant to SINGLE\n"));
+					fmov_s_ri(treg, *(uae_u32 *)&si);
+					return 1;
+				}
+				default: /* never reached */
+				return -1;
+          }
+			default: /* never reached */
+			return -1;
+     }
+  }
+
+	switch (size) {
+		case 0: /* Long */
+		readlong (S1, S2);
+		fmov_l_rr (treg, S2);
+		return 2;
+		case 1: /* Single */
+		readlong (S1, S2);
+			fmov_s_rr (treg, S2);
+		return 1;
+		case 2: /* Long Double */
+		  fp_to_exten_rm (treg, S1);
+		  return 0;
+		case 4: /* Word */
+		readword (S1, S2);
+			fmov_w_rr (treg, S2);
+		return 1;
+		case 5: /* Double */
+		  fp_to_double_rm (treg, S1);
+		return 2;
+		case 6: /* Byte */
+		readbyte (S1, S2);
+		  fmov_b_rr (treg, S2);
+		return 1;
+		default:
+		return -1;
+  }
+	return -1;
+}
+
+/* return of -1 means failure, >=0 means OK */
+STATIC_INLINE int comp_fp_put (uae_u32 opcode, uae_u16 extra)
+{
+	int reg = opcode & 7;
+	int sreg = (extra >> 7) & 7;
+	int mode = (opcode >> 3) & 7;
+	int size = (extra >> 10) & 7;
+
+	if (size == 3 || size == 7) /* 3 = packed decimal, 7 is not defined */
+		return -1;
+	switch (mode) {
+		case 0: /* Dn */
+		switch (size) {
+			case 0: /* FMOVE.L FPx, Dn */
+			  fmov_to_l_rr(reg, sreg);
+			return 0;
+			case 1: /* FMOVE.S FPx, Dn */
+			  fmov_to_s_rr(reg, sreg);
+			return 0;
+			case 4: /* FMOVE.W FPx, Dn */
+			  fmov_to_w_rr(reg, sreg);
+			return 0;
+			case 6: /* FMOVE.B FPx, Dn */
+			  fmov_to_b_rr(reg, sreg);
+			    return 0;
+			  default:
+			    return -1;
+      }
+		case 1: /* An, invalid mode */
+		return -1;
+		case 2: /* (An) */
+		  mov_l_rr (S1, reg + 8);
+		  break;
+		case 3: /* (An)+ */
+		  mov_l_rr (S1, reg + 8);
+      arm_ADD_l_ri8(reg + 8, (reg == 7 ? sz2[size] : sz1[size]));
+		  break;
+		case 4: /* -(An) */
+	    arm_SUB_l_ri8(reg + 8, (reg == 7 ? sz2[size] : sz1[size]));
+		  mov_l_rr (S1, reg + 8);
+		  break;
+		case 5: /* (d16,An) */
+		{
+			uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+			mov_l_rr (S1, reg + 8);
+			arm_ADD_l_ri (S1, off);
+			break;
+		}
+		case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
+		{
+			uae_u32 dp = comp_get_iword ((m68k_pc_offset += 2) - 2);
+			calc_disp_ea_020 (reg + 8, dp, S1);
+			break;
+		}
+		case 7:
+		  switch (reg) {
+			  case 0: /* (xxx).W */
+			  {
+				  uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+				  mov_l_ri (S1, off);
+				  break;
+			  }
+			  case 1: /* (xxx).L */
+			  {
+				  uae_u32 off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				  mov_l_ri (S1, off);
+				  break;
+			  }
+			  default: /* All other modes are not allowed for FPx to <EA> */
+			    write_log (_T ("JIT FMOVE FPx,<EA> Mode is not allowed %04x %04x\n"), opcode, extra);
+		    return -1;
+		  }
+  }
+	switch (size) {
+		case 0: /* Long */
+	fmov_to_l_rr(S2, sreg);
+		  writelong_clobber (S1, S2);
+		  return 0;
+		case 1: /* Single */
+      fmov_to_s_rr(S2, sreg);
+	    writelong_clobber (S1, S2);
+	    return 0;
+		case 2:/* Long Double */
+		  fp_from_exten_mr (S1, sreg);
+		  return 0;
+		case 4: /* Word */
+		  fmov_to_w_rr(S2, sreg);
+		  writeword_clobber (S1, S2);
+		  return 0;
+		case 5: /* Double */
+			fp_from_double_mr(S1, sreg);
+		  return 0;
+		case 6: /* Byte */
+      fmov_to_b_rr(S2, sreg);
+		  writebyte (S1, S2);
+		  return 0;
+		default:
+		return -1;
+  }
+	return -1;
+}
+
+/* return -1 for failure, or register number for success */
+STATIC_INLINE int comp_fp_adr (uae_u32 opcode)
+{
+	uae_s32 off;
+	int mode = (opcode >> 3) & 7;
+	int reg = opcode & 7;
+
+	switch (mode) {
+		case 2:
+		case 3:
+		case 4:
+		  mov_l_rr (S1, 8 + reg);
+		  return S1;
+		case 5:
+		  off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+      mov_l_rr (S1, 8 + reg);
+		  arm_ADD_l_ri (S1, off);
+		  return S1;
+		case 7:
+		  switch (reg) {
+			  case 0:
+			    off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+			    mov_l_ri (S1, off);
+			    return S1;
+			  case 1:
+			    off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+			    mov_l_ri (S1, off);
+			    return S1;
+		  }
+		default:
+		return -1;
+	}
+}
+
+void comp_fscc_opp (uae_u32 opcode, uae_u16 extra)
+{
+	int reg;
+
+	if (!currprefs.compfpu) {
+		FAIL (1);
+		return;
+	}
+
+	if (extra & 0x20) {  /* only cc from 00 to 1f are defined */
+	  FAIL (1);
+	  return;
+	}
+	if ((opcode & 0x38) != 0) { /* We can only do to integer register */
+		FAIL (1);
+		return;
+	}
+
+	fflags_into_flags ();
+	reg = (opcode & 7);
+
+	if (!(opcode & 0x38)) {
+	  switch (extra & 0x0f) { /* according to fpp.c, the 0x10 bit is ignored */
+		  case 0: fp_fscc_ri(reg, NATIVE_CC_F_NEVER); break;
+		  case 1: fp_fscc_ri(reg, NATIVE_CC_EQ); break;
+		  case 2: fp_fscc_ri(reg, NATIVE_CC_F_OGT); break;
+		  case 3: fp_fscc_ri(reg, NATIVE_CC_F_OGE); break;
+		  case 4: fp_fscc_ri(reg, NATIVE_CC_F_OLT); break;
+		  case 5: fp_fscc_ri(reg, NATIVE_CC_F_OLE); break;
+		  case 6: fp_fscc_ri(reg, NATIVE_CC_F_OGL); break;
+		  case 7: fp_fscc_ri(reg, NATIVE_CC_F_OR); break;
+		  case 8: fp_fscc_ri(reg, NATIVE_CC_F_UN); break;
+		  case 9: fp_fscc_ri(reg, NATIVE_CC_F_UEQ); break;
+		  case 10: fp_fscc_ri(reg, NATIVE_CC_F_UGT); break;
+		  case 11: fp_fscc_ri(reg, NATIVE_CC_F_UGE); break;
+		  case 12: fp_fscc_ri(reg, NATIVE_CC_F_ULT); break;
+		  case 13: fp_fscc_ri(reg, NATIVE_CC_F_ULE); break;
+		  case 14: fp_fscc_ri(reg, NATIVE_CC_NE); break;
+		  case 15: fp_fscc_ri(reg, NATIVE_CC_AL); break;
+	  }
+  }
+}
+
+void comp_fbcc_opp (uae_u32 opcode)
+{
+	uae_u32 start_68k_offset = m68k_pc_offset;
+	uae_s32 off;
+	uintptr v1, v2;
+	int cc;
+
+	if (!currprefs.compfpu) {
+		FAIL (1);
+		return;
+	}
+
+	if (opcode & 0x20) {  /* only cc from 00 to 1f are defined */
+		FAIL (1);
+		return;
+	}
+	if (!(opcode & 0x40)) {
+		off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+	}
+	else {
+		off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+	}
+
+	/* according to fpp.c, the 0x10 bit is ignored
+	   (it handles exception handling, which we don't
+	   do, anyway ;-) */
+	cc = opcode & 0x0f;
+  if(cc == 0)
+    return; /* jump never */
+
+	/* ARM64 fix: split the branch target computation so that the
+	 * displacement and the host pointer addition are separate.
+	 * On 32-bit, mov_l_ri folds everything into a single value,
+	 * but on 64-bit, set_const masks non-PC_P registers to 32 bits,
+	 * truncating the host pointer.  Match the pattern used by the
+	 * integer Bcc handlers: load signed displacement first, then
+	 * add the 64-bit comp_pc_p via arm_ADD_l_ri. */
+	{
+		uae_s32 displacement = off - (uae_s32)(m68k_pc_offset - start_68k_offset);
+		mov_l_ri(S1, (uae_s32)displacement);
+		arm_ADD_l_ri(S1, (uintptr)comp_pc_p);
+	}
+	mov_l_ri(PC_P, (uintptr) comp_pc_p);
+
+	/* Now they are both constant. Fold in m68k_pc_offset */
+	arm_ADD_l_ri (S1, m68k_pc_offset);
+	arm_ADD_l_ri (PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+
+	v1 = get_const (PC_P);
+	v2 = get_const (S1);
+	fflags_into_flags ();
+
+	switch (cc) {
+		case 1: register_branch (v1, v2, NATIVE_CC_EQ); break;
+		case 2: register_branch (v1, v2, NATIVE_CC_F_OGT); break;
+		case 3: register_branch (v1, v2, NATIVE_CC_F_OGE); break;
+		case 4: register_branch (v1, v2, NATIVE_CC_F_OLT); break;
+		case 5: register_branch (v1, v2, NATIVE_CC_F_OLE); break;
+		case 6: register_branch (v1, v2, NATIVE_CC_F_OGL); break;
+		case 7: register_branch (v1, v2, NATIVE_CC_F_OR); break;
+		case 8: register_branch (v1, v2, NATIVE_CC_F_UN); break;
+		case 9: register_branch (v1, v2, NATIVE_CC_F_UEQ); break;
+		case 10: register_branch (v1, v2, NATIVE_CC_F_UGT); break;
+		case 11: register_branch (v1, v2, NATIVE_CC_F_UGE); break;
+		case 12: register_branch (v1, v2, NATIVE_CC_F_ULT); break;
+		case 13: register_branch (v1, v2, NATIVE_CC_F_ULE); break;
+		case 14: register_branch (v1, v2, NATIVE_CC_NE); break;
+		case 15: register_branch (v2, v2, NATIVE_CC_AL); break;
+	}
+}
+
+static uae_u32 dhex_pi[]    ={0x54442D18, 0x400921FB};
+static uae_u32 dhex_exp_1[] ={0x8B145769, 0x4005BF0A};
+static uae_u32 dhex_l2_e[]  ={0x652B82FE, 0x3FF71547};
+static uae_u32 dhex_ln_2[]  ={0xFEFA39EF, 0x3FE62E42};
+static uae_u32 dhex_ln_10[] ={0xBBB55516, 0x40026BB1};
+static uae_u32 dhex_l10_2[] ={0x509F79FF, 0x3FD34413};
+static uae_u32 dhex_l10_e[] ={0x1526E50E, 0x3FDBCB7B};
+static uae_u32 dhex_1e16[]  ={0x37E08000, 0x4341C379};
+static uae_u32 dhex_1e32[]  ={0xB5056E17, 0x4693B8B5};
+static uae_u32 dhex_1e64[]  ={0xE93FF9F5, 0x4D384F03};
+static uae_u32 dhex_1e128[] ={0xF9301D32, 0x5A827748};
+static uae_u32 dhex_1e256[] ={0x7F73BF3C, 0x75154FDD};
+static double fp_1e8;
+
+void comp_fpp_opp (uae_u32 opcode, uae_u16 extra)
+{
+	int reg;
+	int sreg, prec = 0;
+	int	dreg = (extra >> 7) & 7;
+	int source = (extra >> 13) & 7;
+	int	opmode = extra & 0x7f;
+
+  if (special_mem) {
+    FAIL(1);
+    return;
+  }
+
+	if (!currprefs.compfpu) {
+		FAIL (1);
+		return;
+	}
+	switch (source) {
+		case 3: /* FMOVE FPx, <EA> */
+		  if (comp_fp_put (opcode, extra) < 0)
+			  FAIL (1);
+		  return;
+		case 4: /* FMOVE.L  <EA>, ControlReg */
+			if ((opcode & 0x38) == 0) {
+				// Dn
+				// Only single selected control register is allowed
+				// All control register bits unset = FPIAR
+				uae_u16 bits = extra & (0x1000 | 0x0800 | 0x0400);
+				if (bits && bits != 0x1000 && bits != 0x0800 && bits != 0x400) {
+					FAIL(1);
+					return;
+				}
+				if (extra & 0x1000) { /* FPCR */
+				  FAIL (1);
+				}
+				if (extra & 0x0800) { /* FPSR */
+				  FAIL (1);
+				}
+				if ((extra & 0x0400) || !bits) /* FPIAR */
+				  mov_l_mr ((uintptr)&regs.fpiar, opcode & 15);
+				return;
+			} else if ((opcode & 0x38) == 0x08) {
+				// An
+				// Only FPIAR can be moved to/from address register
+				// All bits unset = FPIAR
+				uae_u16 bits = extra & (0x1000 | 0x0800 | 0x0400);
+				if (bits && bits != 0x0400) {
+					FAIL(1);
+					return;
+				}
+			  mov_l_mr ((uintptr)&regs.fpiar, opcode & 15);
+				return;
+      }
+		  else if ((opcode & 0x3f) == 0x3c) {
+			  if (extra & 0x1000) { /* FPCR */
+          FAIL(1);
+				  return;
+			  }
+			  if (extra & 0x0800) { /* FPSR */
+				  FAIL (1);
+				  return;
+			  }
+			  if (extra & 0x0400) { /* FPIAR */
+				  uae_u32 val = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				  mov_l_mi ((uintptr)&regs.fpiar, val);
+				  return;
+			  }
+		  }
+		  FAIL (1);
+		  return;
+		case 5: /* FMOVE.L  ControlReg, <EA> */
+			if ((opcode & 0x38) == 0) {
+				// Dn
+				// Only single selected control register is allowed
+				// All control register bits unset = FPIAR
+				uae_u16 bits = extra & (0x1000 | 0x0800 | 0x0400);
+				if (bits && bits != 0x1000 && bits != 0x0800 && bits != 0x400) {
+					FAIL(1);
+					return;
+				}
+				if (extra & 0x1000) /* FPCR */
+				  mov_l_rm (opcode & 15, (uintptr)&regs.fpcr);
+				if (extra & 0x0800) { /* FPSR */
+				  FAIL (1);
+				}
+				if ((extra & 0x0400) || !bits) /* FPIAR */
+				  mov_l_rm (opcode & 15, (uintptr)&regs.fpiar);
+				return;
+			} else if ((opcode & 0x38) == 0x08) {
+				// An
+				// Only FPIAR can be moved to/from address register
+				// All bits unset = FPIAR
+				uae_u16 bits = extra & (0x1000 | 0x0800 | 0x0400);
+				if (bits && bits != 0x0400) {
+					FAIL(1);
+					return;
+				}
+			  mov_l_rm (opcode & 15, (uintptr)&regs.fpiar);
+				return;
+      }
+		  FAIL (1);
+		  return;
+		case 6:
+		case 7:
+		{
+			uae_u32 list = 0;
+			int incr = 0;
+			if (extra & 0x2000) {
+				int ad;
+
+				/* FMOVEM FPP->memory */
+				switch ((extra >> 11) & 3) { /* Get out early if failure */
+					case 0:
+					case 2:
+					  break;
+					case 1:
+					case 3:
+					default:
+					  FAIL (1);
+            return;
+				}
+				ad = comp_fp_adr (opcode);
+				if (ad < 0) {
+					m68k_setpc (m68k_getpc () - 4);
+					op_illg (opcode);
+					return;
+				}
+				switch ((extra >> 11) & 3) {
+					case 0:	/* static pred */
+					  list = extra & 0xff;
+					  incr = -1;
+					  break;
+					case 2:	/* static postinc */
+					  list = extra & 0xff;
+					  incr = 1;
+					  break;
+					case 1:	/* dynamic pred */
+					case 3:	/* dynamic postinc */
+					abort ();
+				}
+				if (incr < 0) { /* Predecrement */
+					for (reg = 7; reg >= 0; reg--) {
+						if (list & 0x80) {
+							sub_l_ri (ad, 12);
+							fp_from_exten_mr (ad, reg);
+						}
+						list <<= 1;
+					}
+				} else { /* Postincrement */
+					for (reg = 0; reg <= 7; reg++) {
+						if (list & 0x80) {
+							fp_from_exten_mr (ad, reg);
+							arm_ADD_l_ri (ad, 12);
+						}
+						list <<= 1;
+					}
+				}
+				if ((opcode & 0x38) == 0x18)
+					mov_l_rr ((opcode & 7) + 8, ad);
+				if ((opcode & 0x38) == 0x20)
+					mov_l_rr ((opcode & 7) + 8, ad);
+			} else {
+				/* FMOVEM memory->FPP */
+				int ad;
+				switch ((extra >> 11) & 3) { /* Get out early if failure */
+					case 0:
+					case 2:
+					  break;
+					case 1:
+					case 3:
+					default:
+					  FAIL (1);
+            return;
+				}
+				ad = comp_fp_adr (opcode);
+				if (ad < 0) {
+					m68k_setpc (m68k_getpc () - 4);
+					op_illg (opcode);
+					return;
+				}
+				switch ((extra >> 11) & 3) {
+					case 0:	/* static pred */
+					  list = extra & 0xff;
+					  incr = -1;
+					  break;
+					case 2:	/* static postinc */
+					  list = extra & 0xff;
+					  incr = 1;
+					  break;
+					case 1:	/* dynamic pred */
+					case 3:	/* dynamic postinc */
+					abort ();
+				}
+
+				if (incr < 0) {
+					// not reached
+					for (reg = 7; reg >= 0; reg--) {
+						if (list & 0x80) {
+							sub_l_ri (ad, 12);
+              fp_to_exten_rm(reg, ad);
+						}
+						list <<= 1;
+					}
+				} else {
+					for (reg = 0; reg <= 7; reg++) {
+						if (list & 0x80) {
+              fp_to_exten_rm(reg, ad);
+							arm_ADD_l_ri (ad, 12);
+						}
+						list <<= 1;
+					}
+				}
+				if ((opcode & 0x38) == 0x18)
+					mov_l_rr ((opcode & 7) + 8, ad);
+				if ((opcode & 0x38) == 0x20)
+					mov_l_rr ((opcode & 7) + 8, ad);
+			}
+		}
+    return;
+		case 2: /* from <EA> to FPx */
+		  dont_care_fflags ();
+		  if ((extra & 0xfc00) == 0x5c00) { /* FMOVECR */
+			  //write_log (_T("JIT FMOVECR %x\n"), opmode);
+			  switch (opmode) {
+				  case 0x00:
+				    fmov_d_rm (dreg, (uintptr)&dhex_pi);
+				    break;
+				  case 0x0b:
+				    fmov_d_rm (dreg, (uintptr)&dhex_l10_2);
+				    break;
+				  case 0x0c:
+				    fmov_d_rm (dreg, (uintptr)&dhex_exp_1);
+				    break;
+				  case 0x0d:
+				    fmov_d_rm (dreg, (uintptr)&dhex_l2_e);
+				    break;
+				  case 0x0e:
+				    fmov_d_rm (dreg, (uintptr)&dhex_l10_e);
+				    break;
+				  case 0x0f:
+            fmov_d_ri_0 (dreg);
+				    break;
+				  case 0x30:
+				    fmov_d_rm (dreg, (uintptr)&dhex_ln_2);
+				    break;
+				  case 0x31:
+				    fmov_d_rm (dreg, (uintptr)&dhex_ln_10);
+				    break;
+				  case 0x32:
+            fmov_d_ri_1 (dreg);
+				    break;
+				  case 0x33:
+            fmov_d_ri_10 (dreg);
+				    break;
+				  case 0x34:
+				    fmov_d_ri_100 (dreg);
+				    break;
+				  case 0x35:
+				    fmov_l_ri (dreg, 10000);
+				    break;
+				  case 0x36:
+				    fmov_rm (dreg, (uintptr)&fp_1e8);
+				    break;
+				  case 0x37:
+				    fmov_d_rm (dreg, (uintptr)&dhex_1e16);
+				    break;
+				  case 0x38:
+				    fmov_d_rm (dreg, (uintptr)&dhex_1e32);
+				    break;
+				  case 0x39:
+				    fmov_d_rm (dreg, (uintptr)&dhex_1e64);
+				    break;
+				  case 0x3a:
+				    fmov_d_rm (dreg, (uintptr)&dhex_1e128);
+				    break;
+				  case 0x3b:
+				    fmov_d_rm (dreg, (uintptr)&dhex_1e256);
+				    break;
+				  default:
+				    FAIL (1);
+				    return;
+			  }
+			  fmov_rr (FP_RESULT, dreg);
+			  return;
+      }
+		  if (opmode & 0x20) /* two operands, so we need a scratch reg */
+			  sreg = FS1;
+		  else /* one operand only, thus we can load the argument into dreg */
+			  sreg = dreg;
+		  if(opmode >= 0x30 && opmode <= 0x37) {
+				// get out early for unsupported ops
+			  FAIL (1);
+			  return;
+		  }
+		  if ((prec = comp_fp_get (opcode, extra, sreg)) < 0) {
+			  FAIL (1);
+			  return;
+		  }
+		  if (!opmode) { /* FMOVE  <EA>,FPx */
+			  fmov_rr (FP_RESULT, dreg);
+			  return;
+		  }
+		  /* no break here for <EA> to dreg */
+		case 0: /* directly from sreg to dreg */
+		  if (!source) { /* no <EA> */
+			  dont_care_fflags ();
+			  sreg = (extra >> 10) & 7;
+		  }
+		  switch (opmode) {
+			  case 0x00: /* FMOVE */
+			    fmov_rr (dreg, sreg);
+			    break;
+			  case 0x01: /* FINT */
+			    frndint_rr (dreg, sreg);
+			    break;
+			  case 0x02: /* FSINH */
+			    ffunc_rr (sinh, dreg, sreg);
+			    break;
+			  case 0x03: /* FINTRZ */
+			    frndintz_rr (dreg, sreg);
+			    break;
+		    case 0x04: /* FSQRT */
+		      fsqrt_rr (dreg, sreg);
+		      break;
+		    case 0x06: /* FLOGNP1 */
+		      ffunc_rr (log1p, dreg, sreg);
+		      break;
+		    case 0x08: /* FETOXM1 */
+		      ffunc_rr (expm1, dreg, sreg);
+		      break;
+		    case 0x09: /* FTANH */
+		      ffunc_rr (tanh, dreg, sreg);
+		      break;
+		    case 0x0a: /* FATAN */
+		      ffunc_rr (atan, dreg, sreg);
+		      break;
+		    case 0x0c: /* FASIN */
+		      ffunc_rr (asin, dreg, sreg);
+		      break;
+		    case 0x0d: /* FATANH */
+		      ffunc_rr (atanh, dreg, sreg);
+		      break;
+		    case 0x0e: /* FSIN */
+		      ffunc_rr (sin, dreg, sreg);
+		      break;
+		    case 0x0f: /* FTAN */
+		      ffunc_rr (tan, dreg, sreg);
+		      break;
+		    case 0x10: /* FETOX */
+		      ffunc_rr (exp, dreg, sreg);
+		      break;
+		    case 0x11: /* FTWOTOX */
+		      fpowx_rr (2, dreg, sreg);
+		      break;
+		    case 0x12: /* FTENTOX */
+		      fpowx_rr (10, dreg, sreg);
+		      break;
+			  case 0x14: /* FLOGN */
+			    ffunc_rr (log, dreg, sreg);
+			    break;
+			  case 0x15: /* FLOG10 */
+			    ffunc_rr (log10, dreg, sreg);
+			    break;
+			  case 0x16: /* FLOG2 */
+			    ffunc_rr (log2, dreg, sreg);
+			    break;
+			  case 0x18: /* FABS */
+			    fabs_rr (dreg, sreg);
+			    break;
+			  case 0x19: /* FCOSH */
+			    ffunc_rr (cosh, dreg, sreg);
+			    break;
+			  case 0x1a: /* FNEG */
+			    fneg_rr (dreg, sreg);
+			    break;
+			case 0x1c: /* FACOS */
+			    ffunc_rr (acos, dreg, sreg);
+			    break;
+			  case 0x1d: /* FCOS */
+			    ffunc_rr (cos, dreg, sreg);
+			    break;
+			  case 0x20: /* FDIV */
+			    fdiv_rr (dreg, sreg);
+			    break;
+			  case 0x21: /* FMOD */
+			    fmod_rr (dreg, sreg);
+			    break;
+			  case 0x22: /* FADD */
+			    fadd_rr (dreg, sreg);
+			    break;
+			  case 0x23: /* FMUL */
+			    fmul_rr (dreg, sreg);
+			    break;
+			  case 0x24: /* FSGLDIV */
+			    fsgldiv_rr (dreg, sreg);
+			    break;
+			  case 0x60: /* FSDIV */
+			    fdiv_rr (dreg, sreg);
+			    if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				    break;
+			    fcuts_r (dreg);
+			    break;
+			  case 0x25: /* FREM */
+			    frem1_rr (dreg, sreg);
+			    break;
+        case 0x27: /* FSGLMUL */
+			    fsglmul_rr (dreg, sreg);
+			    break;
+			  case 0x63: /* FSMUL */
+			    fmul_rr (dreg, sreg);
+			    if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				    break;
+			    fcuts_r (dreg);
+			    break;
+			  case 0x28: /* FSUB */
+			    fsub_rr (dreg, sreg);
+			    break;
+			  case 0x30: /* FSINCOS */
+			  case 0x31:
+			  case 0x32:
+			  case 0x33:
+			  case 0x34:
+			  case 0x35:
+			  case 0x36:
+			  case 0x37:
+				  FAIL (1);
+				  return;
+			  case 0x38: /* FCMP */
+			    fmov_rr (FP_RESULT, dreg);
+			    fsub_rr (FP_RESULT, sreg);
+			    return;
+			  case 0x3a: /* FTST */
+			    fmov_rr (FP_RESULT, sreg);
+			    return;
+		    case 0x40: /* FSMOVE */
+			    if (prec == 1 || !currprefs.fpu_strict) {
+				    if (sreg != dreg) /* no <EA> */
+					    fmov_rr (dreg, sreg);
+			    }
+			    else {
+			    fmovs_rr (dreg, sreg);
+			    }
+          break;
+			  case 0x44: /* FDMOVE */
+          if (sreg != dreg) /* no <EA> */
+			    fmov_rr (dreg, sreg);
+          break;
+			  case 0x41: /* FSSQRT */
+			    fsqrt_rr (dreg, sreg);
+			    if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				    break;
+			    fcuts_r (dreg);
+			    break;
+			  case 0x45: /* FDSQRT */
+          fsqrt_rr (dreg, sreg);
+          break;
+			  case 0x58: /* FSABS */
+			    fabs_rr (dreg, sreg);
+			    if (prec != 1 && currprefs.fpu_strict)
+			      fcuts_r (dreg);
+			    break;
+			  case 0x5a: /* FSNEG */
+			    fneg_rr (dreg, sreg);
+			    if (prec != 1 && currprefs.fpu_strict)
+			      fcuts_r (dreg);
+			    break;
+			  case 0x5c: /* FDABS */
+			    fabs_rr (dreg, sreg);
+			    break;
+			  case 0x5e: /* FDNEG */
+			    fneg_rr (dreg, sreg);
+			    break;
+			  case 0x62: /* FSADD */
+			    fadd_rr (dreg, sreg);
+			    if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				    break;
+			    fcuts_r (dreg);
+			    break;
+			  case 0x64: /* FDDIV */
+			    fdiv_rr (dreg, sreg);
+			    break;
+			  case 0x66: /* FDADD */
+			    fadd_rr (dreg, sreg);
+			    break;
+			  case 0x67: /* FDMUL */
+			    fmul_rr (dreg, sreg);
+			    break;
+			  case 0x68: /* FSSUB */
+			    fsub_rr (dreg, sreg);
+			    if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				    break;
+			    fcuts_r (dreg);
+			    break;
+			  case 0x6c: /* FDSUB */
+			    fsub_rr (dreg, sreg);
+			    break;
+		    default:
+			    FAIL (1);
+			    return;
+      }
+		  fmov_rr (FP_RESULT, dreg);
+		  return;
+		default:
+		  write_log (_T ("Unsupported JIT-FPU instruction: 0x%04x %04x\n"), opcode, extra);
+		  FAIL (1);
+		  return;
+  }
+}
+#endif
diff --git a/jit/arm/compemu_midfunc_arm.cpp b/jit/arm/compemu_midfunc_arm.cpp
new file mode 100644
index 00000000..891048f0
--- /dev/null
+++ b/jit/arm/compemu_midfunc_arm.cpp
@@ -0,0 +1,1066 @@
+/*
+ * compiler/compemu_midfunc_arm.cpp - Native MIDFUNCS for ARM
+ *
+ * Copyright (c) 2014 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ * Copyright (c) 2019 TomB
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Note:
+ *  	File is included by compemu_support.cpp
+ *
+ */
+
+/********************************************************************
+ * CPU functions exposed to gencomp. Both CREATE and EMIT time      *
+ ********************************************************************/
+
+/*
+ *  RULES FOR HANDLING REGISTERS:
+ *
+ *  * In the function headers, order the parameters
+ *     - 1st registers written to
+ *     - 2nd read/modify/write registers
+ *     - 3rd registers read from
+ *  * Before calling raw_*, you must call readreg, writereg or rmw for
+ *    each register
+ *  * The order for this is
+ *     - 1nd call readreg for all registers read without offset
+ *     - 2rd call rmw for all rmw registers
+ *     - 3th call writereg for all written-to registers
+ *     - 4th call raw_*
+ *     - 5th unlock2 all registers that were locked
+ */
+
+#define INIT_REGS_b(d,s) 					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = rmw(d);											\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_RREGS_b(d,s) 				\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = readreg(d);									\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_REG_b(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = rmw(d);
+
+#define INIT_RREG_b(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = readreg(d);
+
+#define INIT_WREG_b(d) 						\
+	int targetIsReg = (d < 16); 		\
+	if(targetIsReg)									\
+		d = rmw(d); 									\
+	else														\
+		d = writereg(d);
+
+#define INIT_REGS_w(d,s) 					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = rmw(d);											\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_RREGS_w(d,s)					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = readreg(d);									\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_REG_w(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = rmw(d);
+
+#define INIT_RREG_w(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = readreg(d);
+
+#define INIT_WREG_w(d) 						\
+	int targetIsReg = (d < 16); 		\
+	if(targetIsReg)									\
+		d = rmw(d);										\
+	else														\
+		d = writereg(d);
+
+#define INIT_REGS_l(d,s) 					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = rmw(d);											\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_RREGS_l(d,s) 				\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = readreg(d);									\
+	if(s_is_d)											\
+		s = d;
+
+#define EXIT_REGS(d,s)						\
+	unlock2(d);											\
+	if(!s_is_d)											\
+		unlock2(s);
+
+
+MIDFUNC(0,live_flags,(void))
+{
+	live.flags_on_stack = TRASH;
+	live.flags_in_flags = VALID;
+	live.flags_are_important = 1;
+}
+MENDFUNC(0,live_flags,(void))
+
+MIDFUNC(0,dont_care_flags,(void))
+{
+	live.flags_are_important = 0;
+}
+MENDFUNC(0,dont_care_flags,(void))
+
+MIDFUNC(0,make_flags_live,(void))
+{
+	make_flags_live_internal();
+}
+MENDFUNC(0,make_flags_live,(void))
+
+MIDFUNC(2,mov_l_mi,(IMPTR d, IM32 s))
+{
+  /* d points always to memory in regs struct */
+  LOAD_U32(REG_WORK2, s);
+  uintptr idx = d - (uintptr) &regs;
+  STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+}
+MENDFUNC(2,mov_l_mi,(IMPTR d, IM32 s))
+
+MIDFUNC(4,disp_ea20_target_add,(RW4 target, RR4 reg, IM8 shift, IM8 extend))
+{
+	if(isconst(target) && isconst(reg)) {
+		if(extend)
+			set_const(target, live.state[target].val + (((uae_s32)(uae_s16)live.state[reg].val) << (shift & 0x1f)));
+		else
+			set_const(target, live.state[target].val + (live.state[reg].val << (shift & 0x1f)));
+		return;
+	}
+
+	reg = readreg(reg);
+	target = rmw(target);
+
+	if(extend) {
+		SIGNED16_REG_2_REG(REG_WORK1, reg);
+		ADD_rrrLSLi(target, target, REG_WORK1, shift & 0x1f);
+	} else {
+		ADD_rrrLSLi(target, target, reg, shift & 0x1f);
+	}
+
+	unlock2(target);
+	unlock2(reg);
+}
+MENDFUNC(4,disp_ea20_target_add,(RW4 target, RR4 reg, IM8 shift, IM8 extend))
+
+MIDFUNC(4,disp_ea20_target_mov,(W4 target, RR4 reg, IM8 shift, IM8 extend))
+{
+	if(isconst(reg)) {
+		if(extend)
+			set_const(target, ((uae_s32)(uae_s16)live.state[reg].val) << (shift & 0x1f));
+		else
+			set_const(target, live.state[reg].val << (shift & 0x1f));
+		return;
+	}
+
+	reg = readreg(reg);
+	target = writereg(target);
+
+	if(extend) {
+		SIGNED16_REG_2_REG(REG_WORK1, reg);
+		LSL_rri(target, REG_WORK1, shift & 0x1f);
+	} else {
+		LSL_rri(target, reg, shift & 0x1f);
+	}
+
+	unlock2(target);
+	unlock2(reg);
+}
+MENDFUNC(4,disp_ea20_target_mov,(W4 target, RR4 reg, IM8 shift, IM8 extend))
+
+MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
+{
+  // Only used in calc_disp_ea_020() -> flags not relevant and never modified
+	if (isconst(s)) {
+		set_const(d, (uae_s32)(uae_s16)live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if (!s_is_d) {
+		s = readreg(s);
+		d = writereg(d);
+	}	else {
+		s = d = rmw(s);
+	}
+	SIGNED16_REG_2_REG(d, s);
+	if (!s_is_d)
+		unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
+
+MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IM32 offset))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_l_ri)(d, live.state[s].val+offset);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if(s_is_d) {
+		s = d = rmw(d);
+	} else {
+		s = readreg(s);
+		d = writereg(d);
+	}
+
+  if(CHECK32(offset)) {
+    ADD_rri(d, s, offset);
+  } else {
+    LOAD_U32(REG_WORK1, offset);
+	ADD_rrr(d, s, REG_WORK1);
+  }
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IM32 offset))
+
+MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor, IM8 offset))
+{
+	if (!offset) {
+		COMPCALL(lea_l_rr_indexed)(d, s, index, factor);
+		return;
+	}
+	if (isconst(s) && isconst(index)) {
+	  set_const(d, live.state[s].val + (uae_s32)(uae_s8)offset + live.state[index].val * factor);
+	  return;
+	}
+
+	s = readreg(s);
+	if(d == index) {
+	  d = index = rmw(d);
+	} else {
+	  index = readreg(index);
+	  d = writereg(d);
+  }
+
+	int shft;
+	switch(factor) {
+	case 1: shft=0; break;
+	case 2: shft=1; break;
+	case 4: shft=2; break;
+	case 8: shft=3; break;
+	default: abort();
+	}
+
+  if(offset >= 0 && offset <= 127) {
+    ADD_rri(REG_WORK1, s, offset);
+  } else {
+    SUB_rri(REG_WORK1, s, -offset);
+  }
+	ADD_rrrLSLi(d, REG_WORK1, index, shft);
+
+	unlock2(d);
+  if(d != index)
+	  unlock2(index);
+	unlock2(s);
+}
+MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor, IM8 offset))
+
+MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor))
+{
+	if (isconst(s) && isconst(index)) {
+	  set_const(d, live.state[s].val + live.state[index].val * factor);
+	  return;
+	}
+
+	s = readreg(s);
+	if(d == index) {
+	  d = index = rmw(d);
+	} else {
+	  index = readreg(index);
+	  d = writereg(d);
+  }
+
+	int shft;
+	switch(factor) {
+	case 1: shft=0; break;
+	case 2: shft=1; break;
+	case 4: shft=2; break;
+	case 8: shft=3; break;
+	default: abort();
+	}
+
+	ADD_rrrLSLi(d, s, index, shft);
+
+	unlock2(d);
+  if(d != index)
+	  unlock2(index);
+	unlock2(s);
+}
+MENDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor))
+
+MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
+{
+	int olds;
+
+	if (d == s) { /* How pointless! */
+		return;
+	}
+	if (isconst(s)) {
+		COMPCALL(mov_l_ri)(d, live.state[s].val);
+		return;
+	}
+	olds = s;
+	disassociate(d);
+	s = readreg(s);
+	live.state[d].realreg = s;
+	live.state[d].realind = live.nat[s].nholds;
+	live.state[d].val = 0;
+	set_status(d, DIRTY);
+
+	live.nat[s].holds[live.nat[s].nholds] = d;
+	live.nat[s].nholds++;
+	unlock2(s);
+}
+MENDFUNC(2,mov_l_rr,(W4 d, RR4 s))
+
+MIDFUNC(2,mov_l_mr,(IMPTR d, RR4 s))
+{
+  /* d points always to memory in regs struct */
+	if (isconst(s)) {
+		COMPCALL(mov_l_mi)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+
+  uintptr idx = d - (uintptr) &regs;
+  STR_rRI(s, R_REGSTRUCT, idx);
+
+	unlock2(s);
+}
+MENDFUNC(2,mov_l_mr,(IMPTR d, RR4 s))
+
+MIDFUNC(2,mov_l_rm,(W4 d, IMPTR s))
+{
+  /* s points always to memory in regs struct */
+	d = writereg(d);
+
+  uintptr idx = s - (uintptr) &regs;
+  LDR_rRI(d, R_REGSTRUCT, idx);
+
+	unlock2(d);
+}
+MENDFUNC(2,mov_l_rm,(W4 d, IMPTR s))
+
+MIDFUNC(2,mov_l_ri,(W4 d, IM32 s))
+{
+	set_const(d, s);
+}
+MENDFUNC(2,mov_l_ri,(W4 d, IM32 s))
+
+MIDFUNC(2,mov_b_ri,(W1 d, IM8 s))
+{
+  if(d < 16) {
+	  if (isconst(d)) {
+		  set_const(d, (live.state[d].val & 0xffffff00) | (s & 0x000000ff));
+		  return;
+	  }
+	  d = rmw(d);
+
+		BIC_rri(d, d, 0xff);
+		ORR_rri(d, d, (s & 0xff));
+
+	  unlock2(d);
+  } else {
+    set_const(d, s & 0xff);
+  }
+}
+MENDFUNC(2,mov_b_ri,(W1 d, IM8 s))
+
+MIDFUNC(2,sub_l_ri,(RW4 d, IM8 i))
+{
+	if (!i)
+	  return;
+	if (isconst(d)) {
+		live.state[d].val -= i;
+		return;
+	}
+
+	d = rmw(d);
+
+  SUB_rri(d, d, i);
+
+	unlock2(d);
+}
+MENDFUNC(2,sub_l_ri,(RW4 d, IM8 i))
+
+MIDFUNC(2,sub_w_ri,(RW2 d, IM8 i))
+{
+  // This function is only called with i = 1
+	// Caller needs flags...
+	clobber_flags();
+
+	d = rmw(d);
+
+	LSL_rri(REG_WORK2, d, 16);
+
+	SUBS_rri(REG_WORK2, REG_WORK2, (i & 0xff) << 16);
+  PKHTB_rrrASRi(d, d, REG_WORK2, 16);
+
+	unlock2(d);
+}
+MENDFUNC(2,sub_w_ri,(RW2 d, IM8 i))
+
+/* forget_about() takes a mid-layer register */
+MIDFUNC(1,forget_about,(W4 r))
+{
+	if (isinreg(r))
+	  disassociate(r);
+	live.state[r].val = 0;
+	set_status(r, UNDEF);
+}
+MENDFUNC(1,forget_about,(W4 r))
+
+
+MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(arm_ADD_l_ri)(d,live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+	ADD_rrr(d, d, s);
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(arm_ADD_l_ri)(d,(live.state[s].val & ~0x1f) >> 3);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+	ASR_rri(REG_WORK1, s, 5);
+	ADD_rrrLSLi(d, d, REG_WORK1, 2);
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
+
+MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMPTR i))
+{
+	if (!i)
+	  return;
+	if (isconst(d)) {
+		live.state[d].val += i;
+		return;
+	}
+
+	d = rmw(d);
+
+	if(CHECK32(i)) {
+		ADD_rri(d, d, i);
+	} else {
+    LOAD_U32(REG_WORK1, i);
+		ADD_rrr(d, d, REG_WORK1);
+  }
+
+	unlock2(d);
+}
+MENDFUNC(2,arm_ADD_l_ri,(RW4 d, IMPTR i))
+
+MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IM8 i))
+{
+	if (!i)
+	  return;
+	if (isconst(d)) {
+		live.state[d].val += i;
+		return;
+	}
+
+	d = rmw(d);
+	ADD_rri(d, d, i);
+	unlock2(d);
+}
+MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IM8 i))
+
+MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IM8 i))
+{
+	if (!i)
+	  return;
+	if (isconst(d)) {
+		live.state[d].val -= i;
+		return;
+	}
+
+	d = rmw(d);
+	SUB_rri(d, d, i);
+	unlock2(d);
+}
+MENDFUNC(2,arm_SUB_l_ri8,(RW4 d, IM8 i))
+
+
+STATIC_INLINE void flush_cpu_icache(void *start, void *stop)
+{
+	register void *_beg __asm ("a1") = start;
+	register void *_end __asm ("a2") = stop;
+	register void *_flg __asm ("a3") = 0;
+	#ifdef __ARM_EABI__
+	   register unsigned long _scno __asm ("r7") = 0xf0002;
+	   __asm __volatile ("swi 0x0		@ sys_cacheflush"
+                            : "=r" (_beg)
+                            : "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno));
+	#else
+	   __asm __volatile ("swi 0x9f0002		@ sys_cacheflush"
+				    : "=r" (_beg)
+				    : "0" (_beg), "r" (_end), "r" (_flg));
+	#endif
+}
+
+
+STATIC_INLINE void write_jmp_target(uae_u32* jmpaddr, uintptr a)
+{
+	uintptr off = ((uintptr)a - (uintptr)jmpaddr - 8) >> 2;
+	*(jmpaddr) = (*(jmpaddr) & 0xff000000) | (off & 0x00ffffff);
+  flush_cpu_icache((void *)jmpaddr, (void *)&jmpaddr[1]);
+}
+
+
+/*************************************************************************
+* FPU stuff                                                             *
+*************************************************************************/
+
+#ifdef USE_JIT_FPU
+
+MIDFUNC(1,f_forget_about,(FW r))
+{
+	if (f_isinreg(r))
+		f_disassociate(r);
+	live.fate[r].status = UNDEF;
+}
+MENDFUNC(1,f_forget_about,(FW r))
+
+MIDFUNC(0,dont_care_fflags,(void))
+{
+	f_disassociate(FP_RESULT);
+}
+MENDFUNC(0,dont_care_fflags,(void))
+
+MIDFUNC(2,fmov_rr,(FW d, FR s))
+{
+	if (d == s) { /* How pointless! */
+		return;
+	}
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fmov_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmov_rr,(FW d, FR s))
+
+MIDFUNC(2,fmov_l_rr,(FW d, RR4 s))
+{
+	s = readreg(s);
+  d = f_writereg(d);
+  raw_fmov_l_rr(d, s);
+	f_unlock(d);
+  unlock2(s);
+}
+MENDFUNC(2,fmov_l_rr,(FW d, RR4 s))
+
+MIDFUNC(2,fmov_s_rr,(FW d, RR4 s))
+{
+	s = readreg(s);
+  d = f_writereg(d);
+  raw_fmov_s_rr(d, s);
+	f_unlock(d);
+  unlock2(s);
+}
+MENDFUNC(2,fmov_s_rr,(FW d, RR4 s))
+
+MIDFUNC(2,fmov_w_rr,(FW d, RR2 s))
+{
+	s = readreg(s);
+  d = f_writereg(d);
+  raw_fmov_w_rr(d, s);
+	f_unlock(d);
+  unlock2(s);
+}
+MENDFUNC(2,fmov_w_rr,(FW d, RR2 s))
+
+MIDFUNC(2,fmov_b_rr,(FW d, RR1 s))
+{
+	s = readreg(s);
+  d = f_writereg(d);
+  raw_fmov_b_rr(d, s);
+	f_unlock(d);
+  unlock2(s);
+}
+MENDFUNC(2,fmov_b_rr,(FW d, RR1 s))
+
+MIDFUNC(3,fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+{
+	s1 = readreg(s1);
+	s2 = readreg(s2);
+  d = f_writereg(d);
+  raw_fmov_d_rrr(d, s1, s2);
+	f_unlock(d);
+  unlock2(s2);
+  unlock2(s1);
+}
+MENDFUNC(3,fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+
+MIDFUNC(2,fmov_l_ri,(FW d, IM32 i))
+{
+	switch(i) {
+		case 0:
+			fmov_d_ri_0(d);
+			break;
+		case 1:
+			fmov_d_ri_1(d);
+			break;
+		case 10:
+			fmov_d_ri_10(d);
+			break;
+		case 100:
+			fmov_d_ri_100(d);
+			break;
+		default:
+		  d = f_writereg(d);
+		  compemu_raw_mov_l_ri(REG_WORK1, i);
+		  raw_fmov_l_rr(d, REG_WORK1);
+			f_unlock(d);
+	}
+}
+MENDFUNC(2,fmov_l_ri,(FW d, IM32 i))
+
+MIDFUNC(2,fmov_s_ri,(FW d, IM32 i))
+{
+  d = f_writereg(d);
+  compemu_raw_mov_l_ri(REG_WORK1, i);
+  raw_fmov_s_rr(d, REG_WORK1);
+	f_unlock(d);
+}
+MENDFUNC(2,fmov_s_ri,(FW d, IM32 i))
+
+MIDFUNC(2,fmov_to_l_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+  d = writereg(d);
+  raw_fmov_to_l_rr(d, s);
+	unlock2(d);
+  f_unlock(s);
+}
+MENDFUNC(2,fmov_to_l_rr,(W4 d, FR s))
+
+MIDFUNC(2,fmov_to_s_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+  d = writereg(d);
+  raw_fmov_to_s_rr(d, s);
+	unlock2(d);
+  f_unlock(s);
+}
+MENDFUNC(2,fmov_to_s_rr,(W4 d, FR s))
+
+MIDFUNC(2,fmov_to_w_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+	INIT_WREG_w(d);
+
+  raw_fmov_to_w_rr(d, s, targetIsReg);
+	unlock2(d);
+  f_unlock(s);
+}
+MENDFUNC(2,fmov_to_w_rr,(W4 d, FR s))
+
+MIDFUNC(2,fmov_to_b_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+	INIT_WREG_b(d);
+
+  raw_fmov_to_b_rr(d, s, targetIsReg);
+	unlock2(d);
+  f_unlock(s);
+}
+MENDFUNC(2,fmov_to_b_rr,(W4 d, FR s))
+
+MIDFUNC(1,fmov_d_ri_0,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_0(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_0,(FW r))
+
+MIDFUNC(1,fmov_d_ri_1,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_1(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_1,(FW r))
+
+MIDFUNC(1,fmov_d_ri_10,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_10(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_10,(FW r))
+
+MIDFUNC(1,fmov_d_ri_100,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_100(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_100,(FW r))
+
+MIDFUNC(2,fmov_d_rm,(FW r, MEMR m))
+{
+	r = f_writereg(r);
+	raw_fmov_d_rm(r, m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_d_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmovs_rm,(FW r, MEMR m))
+{
+	r = f_writereg(r);
+	raw_fmovs_rm(r, m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmovs_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmov_rm,(FW r, MEMR m))
+{
+	r = f_writereg(r);
+	raw_fmov_d_rm(r, m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_rm,(FW r, MEMR m))
+
+MIDFUNC(3,fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+{
+	s = f_readreg(s);
+  d1 = writereg(d1);
+  d2 = writereg(d2);
+  raw_fmov_to_d_rrr(d1, d2, s);
+	unlock2(d2);
+	unlock2(d1);
+  f_unlock(s);
+}
+MENDFUNC(3,fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+
+MIDFUNC(2,fsqrt_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fsqrt_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsqrt_rr,(FW d, FR s))
+
+MIDFUNC(2,fabs_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fabs_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fabs_rr,(FW d, FR s))
+
+MIDFUNC(2,fneg_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fneg_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fneg_rr,(FW d, FR s))
+
+MIDFUNC(2,fdiv_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fdiv_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fdiv_rr,(FRW d, FR s))
+
+MIDFUNC(2,fadd_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fadd_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fadd_rr,(FRW d, FR s))
+
+MIDFUNC(2,fmul_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fmul_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmul_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsub_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fsub_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsub_rr,(FRW d, FR s))
+
+MIDFUNC(2,frndint_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_frndint_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frndint_rr,(FW d, FR s))
+
+MIDFUNC(2,frndintz_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_frndintz_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frndintz_rr,(FW d, FR s))
+
+MIDFUNC(2,fmod_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fmod_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmod_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsgldiv_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fsgldiv_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsgldiv_rr,(FRW d, FR s))
+
+MIDFUNC(1,fcuts_r,(FRW r))
+{
+	r = f_rmw(r);
+	raw_fcuts_r(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fcuts_r,(FRW r))
+
+MIDFUNC(2,frem1_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_frem1_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frem1_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsglmul_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fsglmul_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsglmul_rr,(FRW d, FR s))
+
+MIDFUNC(2,fmovs_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fmovs_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmovs_rr,(FW d, FR s))
+
+MIDFUNC(3,ffunc_rr,(double (*func)(double), FW d, FR s))
+{
+  clobber_flags();
+
+	s = f_readreg(s);
+	int reald = f_writereg(d);
+
+  prepare_for_call_1();
+
+	f_unlock(s);
+	f_unlock(reald);
+
+  prepare_for_call_2();
+
+	raw_ffunc_rr(func, reald, s);
+
+  live.fat[reald].holds = d;
+  live.fat[reald].nholds = 1;
+
+  live.fate[d].realreg = reald;
+  live.fate[d].status = DIRTY;
+}
+MENDFUNC(3,ffunc_rr,(double (*func)(double), FW d, FR s))
+
+MIDFUNC(3,fpowx_rr,(uae_u32 x, FW d, FR s))
+{
+  clobber_flags();
+
+	s = f_readreg(s);
+	int reald = f_writereg(d);
+
+  prepare_for_call_1();
+
+	f_unlock(s);
+	f_unlock(reald);
+
+  prepare_for_call_2();
+
+	raw_fpowx_rr(x, reald, s);
+
+  live.fat[reald].holds = d;
+  live.fat[reald].nholds = 1;
+
+  live.fate[d].realreg = reald;
+  live.fate[d].status = DIRTY;
+}
+MENDFUNC(3,fpowx_rr,(uae_u32 x, FW d, FR s))
+
+MIDFUNC(1,fflags_into_flags,())
+{
+	clobber_flags();
+	fflags_into_flags_internal();
+}
+MENDFUNC(1,fflags_into_flags,())
+
+MIDFUNC(2,fp_from_exten_mr,(RR4 adr, FR s))
+{
+  clobber_flags();
+
+	adr = readreg(adr);
+	s = f_readreg(s);
+  raw_fp_from_exten_mr(adr, s);
+	f_unlock(s);
+	unlock2(adr);
+}
+MENDFUNC(2,fp_from_exten_mr,(RR4 adr, FR s))
+
+MIDFUNC(2,fp_to_exten_rm,(FW d, RR4 adr))
+{
+  clobber_flags();
+
+	adr = readreg(adr);
+	d = f_writereg(d);
+  raw_fp_to_exten_rm(d, adr);
+	unlock2(adr);
+	f_unlock(d);
+}
+MENDFUNC(2,fp_to_exten_rm,(FW d, RR4 adr))
+
+MIDFUNC(2,fp_from_double_mr,(RR4 adr, FR s))
+{
+	adr = readreg(adr);
+	s = f_readreg(s);
+  raw_fp_from_double_mr(adr, s);
+	f_unlock(s);
+	unlock2(adr);
+}
+MENDFUNC(2,fp_from_double_mr,(RR4 adr, FR s))
+
+MIDFUNC(2,fp_to_double_rm,(FW d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = f_writereg(d);
+  raw_fp_to_double_rm(d, adr);
+	unlock2(adr);
+	f_unlock(d);
+}
+MENDFUNC(2,fp_to_double_rm,(FW d, RR4 adr))
+
+MIDFUNC(2,fp_fscc_ri,(RW4 d, int cc))
+{
+	d = rmw(d);
+	raw_fp_fscc_ri(d, cc);
+	unlock2(d);
+}
+MENDFUNC(2,fp_fscc_ri,(RW4 d, int cc))
+
+
+#endif // USE_JIT_FPU
diff --git a/jit/arm/compemu_midfunc_arm.h b/jit/arm/compemu_midfunc_arm.h
new file mode 100644
index 00000000..f32e7c08
--- /dev/null
+++ b/jit/arm/compemu_midfunc_arm.h
@@ -0,0 +1,110 @@
+/*
+ *  compiler/compemu_midfunc_arm.h - Native MIDFUNCS for ARM
+ *
+ * Copyright (c) 2014 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Note:
+ *  	File is included by compemu.h
+ *
+ */
+
+// Arm optimized midfunc
+DECLARE_MIDFUNC(arm_ADD_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(arm_ADD_ldiv8(RW4 d, RR4 s));
+DECLARE_MIDFUNC(arm_ADD_l_ri(RW4 d, IMPTR i));
+DECLARE_MIDFUNC(arm_ADD_l_ri8(RW4 d, IM8 i));
+DECLARE_MIDFUNC(arm_SUB_l_ri8(RW4 d, IM8 i));
+
+// Emulated midfunc
+DECLARE_MIDFUNC(disp_ea20_target_add(RW4 target, RR4 reg, IM8 shift, IM8 extend));
+DECLARE_MIDFUNC(disp_ea20_target_mov(W4 target, RR4 reg, IM8 shift, IM8 extend));
+
+DECLARE_MIDFUNC(mov_l_mi(IMPTR d, IMPTR s));
+DECLARE_MIDFUNC(pop_l(W4 d));
+DECLARE_MIDFUNC(push_l(RR4 s));
+DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, RR2 s));
+DECLARE_MIDFUNC(lea_l_brr(W4 d, RR4 s, IM32 offset));
+DECLARE_MIDFUNC(lea_l_brr_indexed(W4 d, RR4 s, RR4 index, IM8 factor, IM8 offset));
+DECLARE_MIDFUNC(lea_l_rr_indexed(W4 d, RR4 s, RR4 index, IM8 factor));
+DECLARE_MIDFUNC(mov_l_rr(W4 d, RR4 s));
+DECLARE_MIDFUNC(mov_l_mr(IMPTR d, RR4 s));
+DECLARE_MIDFUNC(mov_l_rm(W4 d, IMPTR s));
+DECLARE_MIDFUNC(mov_l_ri(W4 d, IMPTR s));
+DECLARE_MIDFUNC(mov_b_ri(W1 d, IM8 s));
+DECLARE_MIDFUNC(sub_l_ri(RW4 d, IM8 i));
+DECLARE_MIDFUNC(sub_w_ri(RW2 d, IM8 i));
+DECLARE_MIDFUNC(live_flags(void));
+DECLARE_MIDFUNC(dont_care_flags(void));
+DECLARE_MIDFUNC(make_flags_live(void));
+DECLARE_MIDFUNC(forget_about(W4 r));
+
+DECLARE_MIDFUNC(f_forget_about(FW r));
+DECLARE_MIDFUNC(dont_care_fflags(void));
+DECLARE_MIDFUNC(fmov_rr(FW d, FR s));
+
+DECLARE_MIDFUNC(fmov_l_rr(FW d, RR4 s));
+DECLARE_MIDFUNC(fmov_s_rr(FW d, RR4 s));
+DECLARE_MIDFUNC(fmov_w_rr(FW d, RR2 s));
+DECLARE_MIDFUNC(fmov_b_rr(FW d, RR1 s));
+DECLARE_MIDFUNC(fmov_d_rrr(FW d, RR4 s1, RR4 s2));
+DECLARE_MIDFUNC(fmov_l_ri(FW d, IM32 i));
+DECLARE_MIDFUNC(fmov_s_ri(FW d, IM32 i));
+DECLARE_MIDFUNC(fmov_to_l_rr(W4 d, FR s));
+DECLARE_MIDFUNC(fmov_to_s_rr(W4 d, FR s));
+DECLARE_MIDFUNC(fmov_to_w_rr(W4 d, FR s));
+DECLARE_MIDFUNC(fmov_to_b_rr(W4 d, FR s));
+DECLARE_MIDFUNC(fmov_d_ri_0(FW d));
+DECLARE_MIDFUNC(fmov_d_ri_1(FW d));
+DECLARE_MIDFUNC(fmov_d_ri_10(FW d));
+DECLARE_MIDFUNC(fmov_d_ri_100(FW d));
+DECLARE_MIDFUNC(fmov_d_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmovs_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmov_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmov_to_d_rrr(W4 d1, W4 d2, FR s));
+DECLARE_MIDFUNC(fsqrt_rr(FW d, FR s));
+DECLARE_MIDFUNC(fabs_rr(FW d, FR s));
+DECLARE_MIDFUNC(fneg_rr(FW d, FR s));
+DECLARE_MIDFUNC(fdiv_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fadd_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fmul_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fsub_rr(FRW d, FR s));
+DECLARE_MIDFUNC(frndint_rr(FW d, FR s));
+DECLARE_MIDFUNC(frndintz_rr(FW d, FR s));
+DECLARE_MIDFUNC(fmod_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fsgldiv_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fcuts_r(FRW r));
+DECLARE_MIDFUNC(frem1_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fsglmul_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fmovs_rr(FW d, FR s));
+DECLARE_MIDFUNC(ffunc_rr(double (*func)(double), FW d, FR s));
+DECLARE_MIDFUNC(fsincos_rr(FW d, FW c, FR s));
+DECLARE_MIDFUNC(fpowx_rr(uae_u32 x, FW d, FR s));
+DECLARE_MIDFUNC(fflags_into_flags());
+DECLARE_MIDFUNC(fp_from_exten_mr(RR4 adr, FR s));
+DECLARE_MIDFUNC(fp_to_exten_rm(FW d, RR4 adr));
+DECLARE_MIDFUNC(fp_from_double_mr(RR4 adr, FR s));
+DECLARE_MIDFUNC(fp_to_double_rm(FW d, RR4 adr));
+DECLARE_MIDFUNC(fp_fscc_ri(RW4, int cc));
diff --git a/jit/arm/compemu_midfunc_arm2.cpp b/jit/arm/compemu_midfunc_arm2.cpp
new file mode 100644
index 00000000..4a6c1e5e
--- /dev/null
+++ b/jit/arm/compemu_midfunc_arm2.cpp
@@ -0,0 +1,8145 @@
+/*
+ * compiler/compemu_midfunc_arm.cpp - Native MIDFUNCS for ARM (JIT v2)
+ *
+ * Copyright (c) 2014 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ * Copyright (c) 2019 TomB
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Note:
+ *  	File is included by compemu_support.cpp
+ *
+ */
+
+const uae_u32 ARM_CCR_MAP[] = { 0, ARM_C_FLAG, // 1 C
+	ARM_V_FLAG, // 2 V
+	ARM_C_FLAG | ARM_V_FLAG, // 3 VC
+	ARM_Z_FLAG, // 4 Z
+	ARM_Z_FLAG | ARM_C_FLAG, // 5 ZC
+	ARM_Z_FLAG | ARM_V_FLAG, // 6 ZV
+	ARM_Z_FLAG | ARM_C_FLAG | ARM_V_FLAG, // 7 ZVC
+	ARM_N_FLAG, // 8 N
+	ARM_N_FLAG | ARM_C_FLAG, // 9 NC
+	ARM_N_FLAG | ARM_V_FLAG, // 10 NV
+	ARM_N_FLAG | ARM_C_FLAG | ARM_V_FLAG, // 11 NVC
+	ARM_N_FLAG | ARM_Z_FLAG, // 12 NZ
+	ARM_N_FLAG | ARM_Z_FLAG | ARM_C_FLAG, // 13 NZC
+	ARM_N_FLAG | ARM_Z_FLAG | ARM_V_FLAG, // 14 NZV
+	ARM_N_FLAG | ARM_Z_FLAG | ARM_C_FLAG | ARM_V_FLAG, // 15 NZVC
+};
+
+
+#define DUPLICACTE_CARRY            \
+  if (needed_flags & FLAG_X) {      \
+    int x = writereg(FLAGX);     		\
+    MOV_ri(x, 0);                   \
+    if (flags_carry_inverted) {     \
+		  CC_MOV_ri(NATIVE_CC_CC, x, 1); \
+    } else {                        \
+	    ADC_rri(x, x, 0);             \
+    }                               \
+    unlock2(x);                     \
+  }
+
+/*
+ * ADD
+ * Operand Syntax: 	<ea>, Dn
+ * 					Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ */
+MIDFUNC(3,jnf_ADD_im8,(W4 d, RR4 s, IM8 v))
+{
+	int s_is_d = (s == d);
+	if(s_is_d) {
+		s = d = rmw(d);
+	} else {
+		s = readreg(s);
+		d = writereg(d);
+	}
+
+	ADD_rri(d, s, v & 0xff);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(3,jnf_ADD_im8,(W4 d, RR4 s, IM8 v))
+
+MIDFUNC(2,jnf_ADD_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+	  live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val + v) & 0x000000ff);
+    return;
+  }
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+	  ADD_rri(REG_WORK1, d, v & 0xff);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+	  ADD_rri(d, d, v & 0xff);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADD_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_ADD_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADD_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		ADD_rrr(REG_WORK1, d, s);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		ADD_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADD_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_ADD_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	if(targetIsReg) {
+	  if(CHECK32(v & 0xffff)) {
+	    ADD_rri(REG_WORK1, d, (v & 0xffff));
+	  } else {
+		  LOAD_U16(REG_WORK1, v & 0xffff);
+		  ADD_rrr(REG_WORK1, d, REG_WORK1);
+	  }
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else{
+	  if(CHECK32(v & 0xffff)) {
+	    ADD_rri(d, d, (v & 0xffff));
+	  } else {
+		  LOAD_U16(REG_WORK1, v & 0xffff);
+		  ADD_rrr(d, d, REG_WORK1);
+	  }
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADD_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_ADD_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADD_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		ADD_rrr(REG_WORK1, d, s);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		ADD_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADD_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_ADD_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val + v;
+		return;
+	}
+
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    ADD_rri(d, d, v);
+  } else {
+    // never reached...
+	  LOAD_U32(REG_WORK1, v);
+	  ADD_rrr(d, d, REG_WORK1);
+  }
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADD_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_ADD_l,(RW4 d, RR4 s))
+{
+	if (isconst(d) && isconst(s)) {
+		COMPCALL(jnf_ADD_l_imm)(d, live.state[s].val);
+		return;
+	}
+	if (isconst(s) && CHECK32(live.state[s].val)) {
+		COMPCALL(jnf_ADD_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ADD_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADD_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_ADD_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	MOV_ri8RORi(REG_WORK2, v & 0xff, 8);
+  ADDS_rrrLSLi(REG_WORK1, REG_WORK2, d, 24);
+	if(targetIsReg) {
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+	} else {
+		LSR_rri(d, REG_WORK1, 24);
+	}
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ADD_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_ADD_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_ADD_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	LSL_rri(REG_WORK2, s, 24);
+  ADDS_rrrLSLi(REG_WORK1, REG_WORK2, d, 24);
+	if(targetIsReg) {
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+	} else {
+		LSR_rri(d, REG_WORK1, 24);
+	}
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADD_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_ADD_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+#ifdef ARMV6T2
+  MOVW_ri16(REG_WORK1, v & 0xffff);
+  LSL_rri(REG_WORK1, REG_WORK1, 16);
+#else
+  uae_s32 offs = data_long_offs(v << 16);
+	LDR_rRI(REG_WORK1, RPC_INDEX, offs);
+#endif
+
+  ADDS_rrrLSLi(REG_WORK1, REG_WORK1, d, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ADD_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_ADD_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_ADD_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	LSL_rri(REG_WORK1, s, 16);
+  ADDS_rrrLSLi(REG_WORK1, REG_WORK1, d, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADD_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_ADD_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    ADDS_rri(d, d, v);
+  } else {
+    // never reached...
+	  LOAD_U32(REG_WORK2, v);
+	  ADDS_rrr(d, d, REG_WORK2);
+  }
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ADD_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_ADD_l,(RW4 d, RR4 s))
+{
+	if (isconst(s) && CHECK32(live.state[s].val)) {
+		COMPCALL(jff_ADD_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ADDS_rrr(d, d, s);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADD_l,(RW4 d, RR4 s))
+
+/*
+ * ADDA
+ * Operand Syntax: 	<ea>, An
+ *
+ * Operand Size: 16,32
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_ADDA_w_imm,(RW4 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val + (uae_s32)(uae_s16)v;
+		return;
+	}
+
+  uae_s16 tmp = (uae_s16)v;
+	d = rmw(d);
+	if(CHECK32(tmp)) {
+	  ADD_rri(d, d, tmp);
+  } else if (CHECK32(-tmp)) {
+	  SUB_rri(d, d, -tmp);
+	} else {
+	  SIGNED16_IMM_2_REG(REG_WORK1, tmp);
+	  ADD_rrr(d, d, REG_WORK1);
+	}
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADDA_w_imm,(RW4 d, IM16 v))
+
+MIDFUNC(2,jnf_ADDA_w,(RW4 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADDA_w_imm)(d, live.state[s].val & 0xffff);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SXTAH_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADDA_w,(RW4 d, RR2 s))
+
+MIDFUNC(2,jnf_ADDA_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		set_const(d, live.state[d].val + v);
+		return;
+	}
+
+	d = rmw(d);
+
+	if (CHECK32((uae_s32)v)) {
+    ADD_rri(d, d, v);
+	} else {
+    LOAD_U32(REG_WORK1, v);
+	ADD_rrr(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADDA_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_ADDA_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADDA_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ADD_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADDA_l,(RW4 d, RR4 s))
+
+/*
+ * ADDX
+ * Operand Syntax: 	Dy, Dx
+ * 					-(Ay), -(Ax)
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Cleared if the result is nonzero; unchanged otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ * Attention: Z is cleared only if the result is nonzero. Unchanged otherwise
+ *
+ */
+MIDFUNC(2,jnf_ADDX_b,(RW1 d, RR1 s))
+{
+  int x = readreg(FLAGX);
+
+	INIT_REGS_b(d, s);
+
+	if(s_is_d) {
+		ADD_rrrLSLi(REG_WORK1, x, d, 1);
+	} else {
+		ADD_rrr(REG_WORK1, d, s);
+	  ADD_rrr(REG_WORK1, REG_WORK1, x);
+	}
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_ADDX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_ADDX_w,(RW2 d, RR2 s))
+{
+  int x = readreg(FLAGX);
+
+	INIT_REGS_w(d, s);
+
+	if(s_is_d) {
+		ADD_rrrLSLi(REG_WORK1, x, d, 1);
+	} else {
+		ADD_rrr(REG_WORK1, d, s);
+	  ADD_rrr(REG_WORK1, REG_WORK1, x);
+	}
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_ADDX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_ADDX_l,(RW4 d, RR4 s))
+{
+  int x = readreg(FLAGX);
+
+  if(s != d && isconst(s) && CHECK32(live.state[s].val)) {
+    d = rmw(d);
+    ADD_rri(d, d, live.state[s].val);
+	  ADD_rrr(d, d, x);
+    unlock2(d);
+    unlock2(x);
+    return;
+  }
+
+	INIT_REGS_l(d, s);
+
+	if(s_is_d) {
+	  ADD_rrrLSLi(d, x, d, 1);
+	} else {
+	  ADD_rrr(d, d, s);
+	  ADD_rrr(d, d, x);
+	}
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_ADDX_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_ADDX_b,(RW1 d, RR1 s))
+{
+	INIT_REGS_b(d, s);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore X to carry (don't care about other flags)
+  SUBS_rri(REG_WORK3, x, 1);
+
+	MVN_ri(REG_WORK1, 0);
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK1, s, 24, 31);
+#else
+	BIC_rri(REG_WORK1, REG_WORK1, 0xff000000);
+	ORR_rrrLSLi(REG_WORK1, REG_WORK1, s, 24);
+#endif
+  ADCS_rrrLSLi(REG_WORK1, REG_WORK1, d, 24);
+  BIC_rri(d, d, 0xff);
+  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+
+	MRS_CPSR(REG_WORK1);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+  if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+	MSR_CPSRf_r(REG_WORK1);
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADDX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_ADDX_w,(RW2 d, RR2 s))
+{
+	INIT_REGS_w(d, s);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore X to carry (don't care about other flags)
+  SUBS_rri(REG_WORK3, x, 1);
+
+	MVN_ri(REG_WORK1, 0);
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK1, s, 16, 31);
+#else
+	BIC_rri(REG_WORK1, REG_WORK1, 0xff000000);
+	BIC_rri(REG_WORK1, REG_WORK1, 0x00ff0000);
+	ORR_rrrLSLi(REG_WORK1, REG_WORK1, s, 16);
+#endif
+  ADCS_rrrLSLi(REG_WORK1, REG_WORK1, d, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+	MRS_CPSR(REG_WORK1);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+	MSR_CPSRf_r(REG_WORK1);
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADDX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_ADDX_l,(W4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore X to carry (don't care about other flags)
+  SUBS_rri(REG_WORK3, x, 1);
+
+	ADCS_rrr(d, d, s);
+
+	MRS_CPSR(REG_WORK1);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+	MSR_CPSRf_r(REG_WORK1);
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADDX_l,(W4 d, RR4 s))
+
+/*
+ * ANDSR
+ * Operand Syntax: 	#<data>, CCR
+ *
+ * Operand Size: 8
+ *
+ * X Cleared if bit 4 of immediate operand is zero. Unchanged otherwise.
+ * N Cleared if bit 3 of immediate operand is zero. Unchanged otherwise.
+ * Z Cleared if bit 2 of immediate operand is zero. Unchanged otherwise.
+ * V Cleared if bit 1 of immediate operand is zero. Unchanged otherwise.
+ * C Cleared if bit 0 of immediate operand is zero. Unchanged otherwise.
+ *
+ */
+MIDFUNC(2,jff_ANDSR,(IM32 s, IM8 x))
+{
+	MRS_CPSR(REG_WORK1);
+  if(flags_carry_inverted) {
+    EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+    flags_carry_inverted = false;
+  }
+	AND_rri(REG_WORK1, REG_WORK1, s);
+	MSR_CPSRf_r(REG_WORK1);
+
+	if (!x) {
+		int f = writereg(FLAGX);
+		MOV_ri(f, 0);
+		unlock2(f);
+	}
+}
+MENDFUNC(2,jff_ANDSR,(IM32 s, IM8 x))
+
+/*
+ * AND
+ * Operand Syntax: 	<ea>, Dn
+ * 					Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_AND_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val & v) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	BIC_rri(d, d, (~v) & 0xff);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_AND_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_AND_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_AND_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		AND_rrr(REG_WORK1, d, s);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		AND_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_AND_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_AND_w_imm,(RW2 d, IM16 v))
+{
+	if (isconst(d)) {
+    live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val & v) & 0x0000ffff);
+    return;
+  }
+
+	INIT_REG_w(d);
+
+	if(targetIsReg) {
+	  if(CHECK32(v & 0xffff)) {
+	    AND_rri(REG_WORK1, d, (v & 0xffff));
+	  } else {
+		  LOAD_U16(REG_WORK1, v & 0xffff);
+		  AND_rrr(REG_WORK1, d, REG_WORK1);
+	  }
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else{
+	  if(CHECK32(v & 0xffff)) {
+	    AND_rri(d, d, (v & 0xffff));
+	  } else {
+		  LOAD_U16(REG_WORK1, v & 0xffff);
+		  AND_rrr(d, d, REG_WORK1);
+	  }
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_AND_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_AND_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_AND_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		AND_rrr(REG_WORK1, d, s);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		AND_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_AND_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_AND_l_imm,(RW4 d, IM32 v))
+{
+  if(isconst(d)) {
+    live.state[d].val = live.state[d].val & v;
+    return;
+  }
+
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    AND_rri(d, d, v);
+  } else {
+    LOAD_U32(REG_WORK1, v);
+	AND_rrr(d, d, REG_WORK1);
+  }
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_AND_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_AND_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_AND_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	AND_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_AND_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_AND_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_IMM_2_REG(REG_WORK2, v);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ANDS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		ANDS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_AND_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_AND_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_AND_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_REG_2_REG(REG_WORK2, s);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ANDS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		ANDS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_AND_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_AND_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_IMM_2_REG(REG_WORK2, v);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ANDS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		ANDS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_AND_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_AND_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_AND_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_REG_2_REG(REG_WORK2, s);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ANDS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		ANDS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_AND_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_AND_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	if(CHECK32(v)) {
+	  ANDS_rri(d, d, v);
+	} else {
+	  LOAD_U32(REG_WORK1, v);
+	ANDS_rrr(d, d, REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_AND_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_AND_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_AND_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	MSR_CPSRf_i(0);
+	ANDS_rrr(d, d, s);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_AND_l,(RW4 d, RR4 s))
+
+/*
+ * ASL
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ * imm version only called with 1 <= i <= 8
+ *
+ */
+MIDFUNC(2,jff_ASL_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_rri(REG_WORK3, d, 24);
+	if (i) {
+    if (needed_flags & FLAG_V) {
+		  // Calculate V Flag
+		  MOV_ri8RORi(REG_WORK2, 0x80, 8);
+		  ASR_rri(REG_WORK2, REG_WORK2, i);
+		  ANDS_rrr(REG_WORK1, REG_WORK3, REG_WORK2);
+		  CC_TEQ_rr(NATIVE_CC_NE, REG_WORK1, REG_WORK2);
+		  MOV_ri(REG_WORK1, 0);
+		  CC_MOV_ri(NATIVE_CC_NE, REG_WORK1, ARM_V_FLAG);
+		  MSR_CPSRf_r(REG_WORK1); // store V flag
+    }
+
+		LSLS_rri(REG_WORK3, REG_WORK3, i);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrrLSRi(d, d, REG_WORK3, 24);
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		MSR_CPSRf_i(0);
+		TST_rr(REG_WORK3, REG_WORK3);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ASL_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_rri(REG_WORK3, d, 16);
+	if (i) {
+    if (needed_flags & FLAG_V) {
+		  // Calculate V Flag
+		  MOV_ri8RORi(REG_WORK2, 0x80, 8);
+		  ASR_rri(REG_WORK2, REG_WORK2, i);
+		  ANDS_rrr(REG_WORK1, REG_WORK3, REG_WORK2);
+		  CC_TEQ_rr(NATIVE_CC_NE, REG_WORK1, REG_WORK2);
+		  MOV_ri(REG_WORK1, 0);
+		  CC_MOV_ri(NATIVE_CC_NE, REG_WORK1, ARM_V_FLAG);
+		  MSR_CPSRf_r(REG_WORK1); // store V flag
+    }
+
+		LSLS_rri(REG_WORK3, REG_WORK3, i);
+	  PKHTB_rrrASRi(d, d, REG_WORK3, 16);
+
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		MSR_CPSRf_i(0);
+		TST_rr(REG_WORK3, REG_WORK3);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ASL_l_imm,(RW4 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	if (i) {
+    if (needed_flags & FLAG_V) {
+		  // Calculate V Flag
+		  MOV_ri8RORi(REG_WORK2, 0x80, 8);
+		  ASR_rri(REG_WORK2, REG_WORK2, i);
+		  ANDS_rrr(REG_WORK1, d, REG_WORK2);
+		  CC_TEQ_rr(NATIVE_CC_NE, REG_WORK1, REG_WORK2);
+		  MOV_ri(REG_WORK1, 0);
+		  CC_MOV_ri(NATIVE_CC_NE, REG_WORK1, ARM_V_FLAG);
+		  MSR_CPSRf_r(REG_WORK1); // store V flag
+    }
+
+		LSLS_rri(d, d, i);
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		MSR_CPSRf_i(0);
+		TST_rr(d, d);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_ASL_b_reg,(RW1 d, RR4 i))
+{
+	i = readreg(i);
+	d = rmw(d);
+  int x = writereg(FLAGX);
+
+	LSL_rri(REG_WORK3, d, 24);
+  if (needed_flags & FLAG_V) {
+	  // Calculate V Flag
+	  MOV_ri8RORi(REG_WORK2, 0x80, 8);
+	  ASR_rrr(REG_WORK2, REG_WORK2, i);
+	  ANDS_rrr(REG_WORK1, REG_WORK3, REG_WORK2);
+	  CC_TEQ_rr(NATIVE_CC_NE, REG_WORK1, REG_WORK2);
+	  MOV_ri(REG_WORK1, 0);
+	  CC_MOV_ri(NATIVE_CC_NE, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1); // store V flag
+  }
+
+	ANDS_rri(REG_WORK2, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged
+
+	LSLS_rrr(REG_WORK3, REG_WORK3, REG_WORK2);
+	MOV_ri(x, 1);
+	CC_MOV_ri(NATIVE_CC_CC, x, 0);
+  BIC_rri(d, d, 0xff);
+  ORR_rrrLSRi(d, d, REG_WORK3, 24);
+	B_i(0);
+
+  // no shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(REG_WORK3, REG_WORK3);
+
+  flags_carry_inverted = false;
+  unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASL_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ASL_w_reg,(RW2 d, RR4 i))
+{
+	i = readreg(i);
+	d = rmw(d);
+  int x = writereg(FLAGX);
+
+	LSL_rri(REG_WORK3, d, 16);
+  if (needed_flags & FLAG_V) {
+	  // Calculate V Flag
+	  MOV_ri8RORi(REG_WORK2, 0x80, 8);
+	  ASR_rrr(REG_WORK2, REG_WORK2, i);
+	  ANDS_rrr(REG_WORK1, REG_WORK3, REG_WORK2);
+	  CC_TEQ_rr(NATIVE_CC_NE, REG_WORK1, REG_WORK2);
+	  MOV_ri(REG_WORK1, 0);
+	  CC_MOV_ri(NATIVE_CC_NE, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1); // store V flag
+  }
+
+	ANDS_rri(REG_WORK2, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged
+
+	LSLS_rrr(REG_WORK3, REG_WORK3, REG_WORK2);
+	MOV_ri(x, 1);
+	CC_MOV_ri(NATIVE_CC_CC, x, 0);
+  PKHTB_rrrASRi(d, d, REG_WORK3, 16);
+	B_i(0);
+
+  // no shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(REG_WORK3, REG_WORK3);
+
+  flags_carry_inverted = false;
+  unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASL_w_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ASL_l_reg,(RW4 d, RR4 i))
+{
+	i = readreg(i);
+	d = rmw(d);
+  int x = writereg(FLAGX);
+
+  if (needed_flags & FLAG_V) {
+	  // Calculate V Flag
+	  MOV_ri8RORi(REG_WORK2, 0x80, 8);
+	  ASR_rrr(REG_WORK2, REG_WORK2, i);
+	  ANDS_rrr(REG_WORK1, d, REG_WORK2);
+	  CC_TEQ_rr(NATIVE_CC_NE, REG_WORK1, REG_WORK2);
+	  MOV_ri(REG_WORK1, 0);
+	  CC_MOV_ri(NATIVE_CC_NE, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1); // store V flag
+  }
+
+	ANDS_rri(REG_WORK2, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged
+
+	LSLS_rrr(d, d, REG_WORK2);
+	MOV_ri(x, 1);
+	CC_MOV_ri(NATIVE_CC_CC, x, 0);
+	B_i(0);
+
+  // no shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(d, d);
+
+  flags_carry_inverted = false;
+  unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASL_l_reg,(RW4 d, RR4 i))
+
+/*
+ * ASLW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise.
+ * C Set according to the last bit shifted out of the operand.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_ASLW,(RW2 d))
+{
+	d = rmw(d);
+
+	LSL_rri(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_ASLW,(RW2 d))
+
+MIDFUNC(1,jff_ASLW,(RW2 d))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	LSLS_rri(d, d, 17);
+
+  if (needed_flags & FLAG_V) {
+	  MRS_CPSR(REG_WORK1);
+    // Calculate V flag
+	  CC_ORR_rri(NATIVE_CC_MI, REG_WORK1, REG_WORK1, ARM_V_FLAG);
+	  CC_EOR_rri(NATIVE_CC_CS, REG_WORK1, REG_WORK1, ARM_V_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+  }
+	ASR_rri(d, d, 16);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_ASLW,(RW2 d))
+
+/*
+ * ASR
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise. Shift right -> always 0
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ */
+MIDFUNC(2,jnf_ASR_b_imm,(RW1 d, IM8 i))
+{
+	if(i) {
+		d = rmw(d);
+
+		SIGNED8_REG_2_REG(REG_WORK1, d);
+    if(i > 31)
+      i = 31;
+	ASR_rri(REG_WORK1, REG_WORK1, i);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ASR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_ASR_w_imm,(RW2 d, IM8 i))
+{
+	if(i) {
+		d = rmw(d);
+
+		SIGNED16_REG_2_REG(REG_WORK1, d);
+    if(i > 31)
+      i = 31;
+	  PKHTB_rrrASRi(d, d, REG_WORK1, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ASR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_ASR_l_imm,(RW4 d, IM8 i))
+{
+	if(i) {
+		d = rmw(d);
+
+    if(i > 31)
+      i = 31;
+	ASR_rri(d, d, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ASR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_ASR_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	if (i) {
+    if(i > 31)
+      i = 31;
+		ASRS_rri(REG_WORK1, REG_WORK1, i);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_rr(REG_WORK1, REG_WORK1);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ASR_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	if (i) {
+    if(i > 31)
+      i = 31;
+		ASRS_rri(REG_WORK1, REG_WORK1, i);
+	  PKHTB_rrr(d, d, REG_WORK1);
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_rr(REG_WORK1, REG_WORK1);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ASR_l_imm,(RW4 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	MSR_CPSRf_i(0);
+	if (i) {
+    if (i > 31) {
+      ASR_rri(d, d, 1); // make sure, msb is shifted out at least once
+      i = 31;
+    }
+		ASRS_rri(d, d, i);
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_rr(d, d);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_ASR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+	  COMPCALL(jnf_ASR_b_imm)(d, live.state[i].val & 0x3f);
+	  return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	AND_rri(REG_WORK2, i, 63);
+	ASR_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jnf_ASR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ASR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+	  COMPCALL(jnf_ASR_w_imm)(d, live.state[i].val & 0x3f);
+	  return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	AND_rri(REG_WORK2, i, 63);
+	ASR_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jnf_ASR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ASR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+	  COMPCALL(jnf_ASR_l_imm)(d, live.state[i].val & 0x3f);
+	  return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, i, 63);
+	ASR_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jnf_ASR_l_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ASR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+	  COMPCALL(jff_ASR_b_imm)(d, live.state[i].val & 0x3f);
+	  return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+  int x = writereg(FLAGX);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK2, i, 63);
+	BEQ_i(3);               // No shift -> X flag unchanged
+
+  // shift count > 0
+	ASRS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MOV_ri(x, 1);
+	CC_MOV_ri(NATIVE_CC_CC, x, 0);
+	B_i(0);
+
+	TST_rr(REG_WORK1, REG_WORK1);
+
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+  flags_carry_inverted = false;
+  unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ASR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+	  COMPCALL(jff_ASR_w_imm)(d, live.state[i].val & 0x3f);
+	  return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+  int x = writereg(FLAGX);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK2, i, 63);
+	BEQ_i(4);               // No shift -> X flag unchanged
+
+  // shift count > 0
+	ASRS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MOV_ri(x, 1);
+	CC_MOV_ri(NATIVE_CC_CC, x, 0);
+  PKHTB_rrr(d, d, REG_WORK1);
+	B_i(0);
+
+	TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ASR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+	  COMPCALL(jff_ASR_l_imm)(d, live.state[i].val & 0x3f);
+	  return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+  int x = writereg(FLAGX);
+
+	MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK1, i, 63);
+	BEQ_i(3);               // No shift -> X flag unchanged
+
+  // shift count > 0
+	ASRS_rrr(d, d, REG_WORK1);
+	MOV_ri(x, 1);
+	CC_MOV_ri(NATIVE_CC_CC, x, 0);
+	B_i(0);
+
+	TST_rr(d, d);
+
+  flags_carry_inverted = false;
+  unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASR_l_reg,(RW4 d, RR4 i))
+
+/*
+ * ASRW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise. Shift right -> always 0
+ * C Set according to the last bit shifted out of the operand.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_ASRW,(RW2 d))
+{
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(d, d);
+	ASR_rri(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_ASRW,(RW2 d))
+
+MIDFUNC(1,jff_ASRW,(RW2 d))
+{
+	d = rmw(d);
+
+  SIGNED16_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	ASRS_rri(d, REG_WORK1, 1);
+
+  flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_ASRW,(RW2 d))
+
+/*
+ * BCHG
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ *  Operand Size: 8,32
+ *
+ * X Not affected.
+ * N Not affected.
+ * Z Set if the bit changed was zero. Cleared otherwise.
+ * V Not affected.
+ * C Not affected.
+ *
+ */
+/* BCHG.B: target is never a register */
+/* BCHG.L: target is always a register */
+MIDFUNC(2,jnf_BCHG_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+	EOR_rri(d, d, (1 << (s & 0x7)));
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCHG_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+	EOR_rri(d, d, (1 << (s & 0x1f)));
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jnf_BCHG_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCHG_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+
+	EOR_rrrLSLr(d, d, REG_WORK2, REG_WORK1);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_BCHG_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCHG_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+
+	EOR_rrrLSLr(d, d, REG_WORK2, REG_WORK1);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_BCHG_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+
+	uae_u32 v = (1 << (s & 0x7));
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(d, d, v);
+#ifdef ARMV6T2
+  UBFX_rrii(REG_WORK2, d, s & 0x7, 1);
+  BFI_rrii(REG_WORK1, REG_WORK2, 30, 30);
+#else
+	LSR_rri(REG_WORK2, d, 29);
+	AND_rri(REG_WORK2, REG_WORK2, 1);
+  BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+  ORR_rrrLSLi(REG_WORK1, REG_WORK1, REG_WORK2, 30);
+#endif
+  MSR_CPSRf_r(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCHG_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jff_BCHG_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+
+	uae_u32 v = (1 << (s & 0x1f));
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(d, d, v);
+#ifdef ARMV6T2
+  UBFX_rrii(REG_WORK2, d, s & 0x1f, 1);
+  BFI_rrii(REG_WORK1, REG_WORK2, 30, 30);
+#else
+	LSR_rri(REG_WORK2, d, 29);
+	AND_rri(REG_WORK2, REG_WORK2, 1);
+  BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+  ORR_rrrLSLi(REG_WORK1, REG_WORK1, REG_WORK2, 30);
+#endif
+  MSR_CPSRf_r(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCHG_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jff_BCHG_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCHG_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	EOR_rrr(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BCHG_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCHG_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	EOR_rrr(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s))
+
+/*
+ * BCLR
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ * Operand Size: 8,32
+ *
+ * X Not affected.
+ * N Not affected.
+ * Z Set if the bit cleared was zero. Cleared otherwise.
+ * V Not affected.
+ * C Not affected.
+ *
+ */
+/* BCLR.B: target is never a register */
+/* BCLR.L: target is always a register */
+MIDFUNC(2,jnf_BCLR_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+	BIC_rri(d, d, (1 << (s & 0x7)));
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCLR_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IM8 s))
+{
+	if(isconst(d)) {
+		live.state[d].val = live.state[d].val & ~(1 << (s & 0x1f));
+		return;
+	}
+	d = rmw(d);
+	BIC_rri(d, d, (1 << (s & 0x1f)));
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jnf_BCLR_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCLR_b_imm)(d, live.state[s].val);
+		return;
+	}
+	s = readreg(s);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+
+	BIC_rrrLSLr(d, d, REG_WORK2, REG_WORK1);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_BCLR_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCLR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+
+	BIC_rrrLSLr(d, d, REG_WORK2, REG_WORK1);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_BCLR_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+
+	uae_u32 v = (1 << (s & 0x7));
+	MRS_CPSR(REG_WORK1);
+	TST_ri(d, v);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	BIC_rri(d, d, v);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCLR_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jff_BCLR_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+
+	uae_u32 v = (1 << (s & 0x1f));
+	MRS_CPSR(REG_WORK1);
+	TST_ri(d, v);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	BIC_rri(d, d, v);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCLR_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jff_BCLR_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCLR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d,REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	BIC_rrr(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BCLR_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCLR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	BIC_rrr(d, d ,REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s))
+
+/*
+ * BFINS
+ * Operand Syntax: 	#xxx.w,<ea>
+ *
+ * Operand Size: 32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the bitfield is set. Cleared otherwise.
+ * Z Set if the bitfield is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(4,jnf_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+
+  MOV_ri(REG_WORK3, offs);
+
+  LSL_rri(REG_WORK1, s, 32 - width);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rri(REG_WORK2, REG_WORK2, width);
+  AND_rrrRORr(d, d, REG_WORK2, REG_WORK3);
+  ORR_rrrRORr(d, d, REG_WORK1, REG_WORK3);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+
+MIDFUNC(4,jff_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+
+  MOV_ri(REG_WORK3, offs);
+
+  LSL_rri(REG_WORK1, s, 32 - width);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rri(REG_WORK2, REG_WORK2, width);
+  AND_rrrRORr(d, d, REG_WORK2, REG_WORK3);
+  ORR_rrrRORr(d, d, REG_WORK1, REG_WORK3);
+
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+
+MIDFUNC(5,jnf_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+{
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 64 - width);
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, offs);
+
+  VSHL64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, 64 - width - offs);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+
+MIDFUNC(5,jff_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+{
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 64 - width);
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, offs);
+
+  VSHL64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, 64 - width - offs);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  LSL_rri(REG_WORK1, s, 32 - width);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+
+// Next only called when dest is D0-D7
+MIDFUNC(4,jnf_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rri(REG_WORK2, REG_WORK2, width);
+  ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_2, REG_WORK2, REG_WORK2);
+
+  VMOV64_drr(SCRATCH_F64_1, d, d);
+
+  ROR_rri(REG_WORK1, s, width);
+  ROR_rrr(REG_WORK1, REG_WORK1, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_3, REG_WORK1, REG_WORK1);
+
+  VBIF64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d, REG_WORK2, SCRATCH_F64_1);
+
+  unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(4,jff_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rri(REG_WORK2, REG_WORK2, width);
+  ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_2, REG_WORK2, REG_WORK2);
+
+  VMOV64_drr(SCRATCH_F64_1, d, d);
+
+  ROR_rri(REG_WORK1, s, width);
+  ROR_rrr(REG_WORK1, REG_WORK1, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_3, REG_WORK1, REG_WORK1);
+
+  VBIF64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d, REG_WORK2, SCRATCH_F64_1);
+
+  LSL_rri(REG_WORK1, s, 32 - width);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(4,jnf_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+{
+  clobber_flags();
+
+	INIT_REGS_l(d,s);
+  width = readreg(width);
+
+  ANDS_rri(REG_WORK1, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK1, 0x20);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  ROR_rri(REG_WORK2, REG_WORK2, offs);
+  VMOV64_drr(SCRATCH_F64_2, REG_WORK2, REG_WORK2);
+
+  VMOV64_drr(SCRATCH_F64_1, d, d);
+
+  ROR_rrr(REG_WORK2, s, REG_WORK1);
+  ROR_rri(REG_WORK2, REG_WORK2, offs);
+  VMOV64_drr(SCRATCH_F64_3, REG_WORK2, REG_WORK2);
+
+  VBIF64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d, REG_WORK2, SCRATCH_F64_1);
+
+  unlock2(width);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(4,jff_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+{
+	INIT_REGS_l(d,s);
+  width = readreg(width);
+
+  ANDS_rri(REG_WORK1, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK1, 0x20);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  ROR_rri(REG_WORK2, REG_WORK2, offs);
+  VMOV64_drr(SCRATCH_F64_2, REG_WORK2, REG_WORK2);
+
+  VMOV64_drr(SCRATCH_F64_1, d, d);
+
+  ROR_rrr(REG_WORK2, s, REG_WORK1);
+  ROR_rri(REG_WORK2, REG_WORK2, offs);
+  VMOV64_drr(SCRATCH_F64_3, REG_WORK2, REG_WORK2);
+
+  VBIF64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d, REG_WORK2, SCRATCH_F64_1);
+
+  RSB_rri(REG_WORK1, REG_WORK1, 32);
+  LSL_rrr(REG_WORK1, s, REG_WORK1);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(width);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(4,jnf_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+{
+  clobber_flags();
+
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+  width = readreg(width);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+  ANDS_rri(REG_WORK1, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK1, 0x20);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_2, REG_WORK2, REG_WORK2);
+
+  VMOV64_drr(SCRATCH_F64_1, d, d);
+
+  ROR_rrr(REG_WORK2, s, REG_WORK1);
+  ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_3, REG_WORK2, REG_WORK2);
+
+  VBIF64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d, REG_WORK2, SCRATCH_F64_1);
+
+  unlock2(width);
+  unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+
+MIDFUNC(4,jff_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+{
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+  width = readreg(width);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+  ANDS_rri(REG_WORK1, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK1, 0x20);
+
+  MVN_ri(REG_WORK2, 0);
+  LSR_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_2, REG_WORK2, REG_WORK2);
+
+  VMOV64_drr(SCRATCH_F64_1, d, d);
+
+  ROR_rrr(REG_WORK2, s, REG_WORK1);
+  ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK3);
+  VMOV64_drr(SCRATCH_F64_3, REG_WORK2, REG_WORK2);
+
+  VBIF64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d, REG_WORK2, SCRATCH_F64_1);
+
+  RSB_rri(REG_WORK1, REG_WORK1, 32);
+  LSL_rrr(REG_WORK1, s, REG_WORK1);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(width);
+  unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+
+
+// Next called when dest is <ea>
+MIDFUNC(5,jnf_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+{
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+  RSB_rri(REG_WORK3, REG_WORK3, 32);
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK3, 0);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 64 - width);
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 32);
+  VSHL64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, 32 - width);
+
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  unlock2(offs);
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(5,jff_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+{
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+  RSB_rri(REG_WORK3, REG_WORK3, 32);
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK3, 0);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 64 - width);
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 32);
+  VSHL64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, 32 - width);
+
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  LSL_rri(REG_WORK1, s, 32 - width);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(offs);
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(5,jnf_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+{
+  clobber_flags();
+
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+  width = readreg(width);
+
+  ANDS_rri(REG_WORK2, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK2, 0x20);
+  RSB_rri(REG_WORK2, REG_WORK2, 64);
+
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK2, 0);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, offs);
+  VSHR64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, offs);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  unlock2(width);
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(5,jff_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+{
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+  width = readreg(width);
+
+  ANDS_rri(REG_WORK2, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK2, 0x20);
+  RSB_rri(REG_WORK2, REG_WORK2, 64);
+
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK2, 0);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, offs);
+  VSHR64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, offs);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  SUB_rri(REG_WORK2, REG_WORK2, 32);
+  LSL_rrr(REG_WORK1, s, REG_WORK2);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(width);
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(5,jnf_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+{
+  clobber_flags();
+
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+  width = readreg(width);
+
+  ANDS_rri(REG_WORK2, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK2, 0x20);
+  RSB_rri(REG_WORK2, REG_WORK2, 64);
+
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK2, 0);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+  RSB_rri(REG_WORK3, REG_WORK3, 32);
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK3, 0);
+
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 32);
+  VSHR64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, 32);
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  unlock2(width);
+  unlock2(offs);
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+
+MIDFUNC(5,jff_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+{
+  d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+  offs = readreg(offs);
+  width = readreg(width);
+
+  ANDS_rri(REG_WORK2, width, 0x1f);
+  BNE_i(0);
+  MOV_ri(REG_WORK2, 0x20);
+  RSB_rri(REG_WORK2, REG_WORK2, 64);
+
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK2, 0);
+
+  VMOV64_drr(SCRATCH_F64_1, d2, d);
+  VMOV64_drr(SCRATCH_F64_3, s, s);
+
+  VMOV_I64_dimmI(SCRATCH_F64_2, 0xff);
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  AND_rri(REG_WORK3, offs, 0x1f);
+  RSB_rri(REG_WORK3, REG_WORK3, 32);
+  VMOV_I64_dimmI(SCRATCH_F64_4, 0x00);
+  VMOVi_from_ARM_dr(SCRATCH_F64_4, REG_WORK3, 0);
+
+  VSHR64_ddi(SCRATCH_F64_2, SCRATCH_F64_2, 32);
+  VSHR64_ddi(SCRATCH_F64_3, SCRATCH_F64_3, 32);
+  VSHL64_ddd(SCRATCH_F64_2, SCRATCH_F64_2, SCRATCH_F64_4);
+  VSHL64_ddd(SCRATCH_F64_3, SCRATCH_F64_3, SCRATCH_F64_4);
+
+  VBIT64_ddd(SCRATCH_F64_1, SCRATCH_F64_3, SCRATCH_F64_2);
+
+  VMOV64_rrd(d2, d, SCRATCH_F64_1);
+
+  SUB_rri(REG_WORK2, REG_WORK2, 32);
+  LSL_rrr(REG_WORK1, s, REG_WORK2);
+  TST_rr(REG_WORK1, REG_WORK1);
+
+  flags_carry_inverted = false;
+  unlock2(width);
+  unlock2(offs);
+	EXIT_REGS(d,s);
+  unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+
+/*
+ * BSET
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ *  Operand Size: 8,32
+ *
+ * X Not affected.
+ * N Not affected.
+ * Z Set if the bit set was zero. Cleared otherwise.
+ * V Not affected.
+ * C Not affected.
+ *
+ */
+/* BSET.B: target is never a register */
+/* BSET.L: target is always a register */
+MIDFUNC(2,jnf_BSET_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+	ORR_rri(d, d, (1 << (s & 0x7)));
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BSET_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jnf_BSET_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+	ORR_rri(d, d, (1 << (s & 0x1f)));
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BSET_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jnf_BSET_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BSET_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+
+	ORR_rrrLSLr(d, d, REG_WORK2, REG_WORK1);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_BSET_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BSET_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+
+	ORR_rrrLSLr(d, d, REG_WORK2, REG_WORK1);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_BSET_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+
+	uae_u32 v = (1 << (s & 0x7));
+	MRS_CPSR(REG_WORK1);
+	TST_ri(d, v);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	ORR_rri(d, d, v);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BSET_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jff_BSET_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+
+	uae_u32 v = (1 << (s & 0x1f));
+	MRS_CPSR(REG_WORK1);
+	TST_ri(d, v);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	ORR_rri(d, d, v);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BSET_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jff_BSET_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BSET_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	ORR_rrr(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BSET_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jff_BSET_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BSET_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+	ORR_rrr(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_BSET_l,(RW4 d, RR4 s))
+
+/*
+ * BTST
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ *  Operand Size: 8,32
+ *
+ * X Not affected
+ * N Not affected
+ * Z Set if the bit tested is zero. Cleared otherwise
+ * V Not affected
+ * C Not affected
+ *
+ */
+/* BTST.B: target is never a register */
+/* BTST.L: target is always a register */
+MIDFUNC(2,jff_BTST_b_imm,(RR1 d, IM8 s))
+{
+	d = readreg(d);
+
+	MRS_CPSR(REG_WORK1);
+	TST_ri(d, (1 << (s & 0x7)));
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BTST_b_imm,(RR1 d, IM8 s))
+
+MIDFUNC(2,jff_BTST_l_imm,(RR4 d, IM8 s))
+{
+	d = readreg(d);
+
+	MRS_CPSR(REG_WORK1);
+	TST_ri(d, (1 << (s & 0x1f)));
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BTST_l_imm,(RR4 d, IM8 s))
+
+MIDFUNC(2,jff_BTST_b,(RR1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BTST_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = readreg(d);
+
+	AND_rri(REG_WORK1, s, 7);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BTST_b,(RR1 d, RR4 s))
+
+MIDFUNC(2,jff_BTST_l,(RR4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BTST_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	d = readreg(d);
+	if(!s_is_d)
+		s = readreg(s);
+	else
+		s = d;
+
+	AND_rri(REG_WORK1, s, 31);
+	MOV_ri(REG_WORK2, 1);
+	LSL_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	TST_rr(d, REG_WORK2);
+	BIC_rri(REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	CC_ORR_rri(NATIVE_CC_EQ, REG_WORK1, REG_WORK1, ARM_Z_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+
+	unlock2(d);
+	if(!s_is_d)
+		unlock2(s);
+}
+MENDFUNC(2,jff_BTST_l,(RR4 d, RR4 s))
+
+/*
+ * CLR
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Always cleared.
+ * Z Always set.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_CLR_b,(W1 d))
+{
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_b(d);
+	BIC_rri(d, d, 0xff);
+	unlock2(d);
+}
+MENDFUNC(1,jnf_CLR_b,(W1 d))
+
+MIDFUNC(1,jnf_CLR_w,(W2 d))
+{
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_w(d);
+	BIC_rri(d, d, 0x00ff);
+	BIC_rri(d, d, 0xff00);
+	unlock2(d);
+}
+MENDFUNC(1,jnf_CLR_w,(W2 d))
+
+MIDFUNC(1,jnf_CLR_l,(W4 d))
+{
+	set_const(d, 0);
+}
+MENDFUNC(1,jnf_CLR_l,(W4 d))
+
+MIDFUNC(1,jff_CLR_b,(W1 d))
+{
+	MSR_CPSRf_i(ARM_Z_FLAG);
+  flags_carry_inverted = false;
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_b(d);
+	BIC_rri(d, d, 0xff);
+	unlock2(d);
+}
+MENDFUNC(1,jff_CLR_b,(W1 d))
+
+MIDFUNC(1,jff_CLR_w,(W2 d))
+{
+	MSR_CPSRf_i(ARM_Z_FLAG);
+  flags_carry_inverted = false;
+	if(d >= 16) {
+		set_const(d, 0);
+    return;
+  }
+	INIT_WREG_w(d);
+	BIC_rri(d, d, 0x00ff);
+	BIC_rri(d, d, 0xff00);
+	unlock2(d);
+}
+MENDFUNC(1,jff_CLR_w,(W2 d))
+
+MIDFUNC(1,jff_CLR_l,(W4 d))
+{
+	MSR_CPSRf_i(ARM_Z_FLAG);
+  flags_carry_inverted = false;
+	set_const(d, 0);
+}
+MENDFUNC(1,jff_CLR_l,(W4 d))
+
+/*
+ * CMP
+ * Operand Syntax: <ea>, Dn
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ */
+MIDFUNC(2,jff_CMP_b_imm,(RR1 d, IM8 v))
+{
+  d = readreg(d);
+
+  LSL_rri(REG_WORK1, d, 24);
+  MOV_ri(REG_WORK2, v & 0xff);
+  CMP_rrLSLi(REG_WORK1, REG_WORK2, 24);
+
+  unlock2(d);
+
+  flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_b_imm,(RR1 d, IM8 v))
+
+MIDFUNC(2,jff_CMP_b,(RR1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMP_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+  INIT_RREGS_b(d, s);
+
+  LSL_rri(REG_WORK1, d, 24);
+  CMP_rrLSLi(REG_WORK1, s, 24);
+
+  EXIT_REGS(d,s);
+
+  flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_b,(RR1 d, RR1 s))
+
+MIDFUNC(2,jff_CMP_w_imm,(RR2 d, IM16 v))
+{
+	if (isconst(d)) {
+	  SIGNED16_IMM_2_REG(REG_WORK1, live.state[d].val & 0xffff);
+	  SIGNED16_IMM_2_REG(REG_WORK2, v & 0xffff);
+	  CMP_rr(REG_WORK1, REG_WORK2);
+	} else {
+	  d = readreg(d);
+
+	  LSL_rri(REG_WORK1, d, 16);
+	  LOAD_U16(REG_WORK2, v);
+	  CMP_rrLSLi(REG_WORK1, REG_WORK2, 16);
+
+	  unlock2(d);
+  }
+  flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_w_imm,(RR2 d, IM16 v))
+
+MIDFUNC(2,jff_CMP_w,(RR2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMP_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+  INIT_RREGS_w(d, s);
+
+  LSL_rri(REG_WORK1, d, 16);
+  CMP_rrLSLi(REG_WORK1, s, 16);
+
+  EXIT_REGS(d,s);
+  flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_w,(RR2 d, RR2 s))
+
+MIDFUNC(2,jff_CMP_l_imm,(RR4 d, IM32 v))
+{
+	d = readreg(d);
+
+  LOAD_U32(REG_WORK1, v);
+	CMP_rr(d, REG_WORK1);
+
+  flags_carry_inverted = true;
+	unlock2(d);
+}
+MENDFUNC(2,jff_CMP_l_imm,(RR4 d, IM32 v))
+
+MIDFUNC(2,jff_CMP_l,(RR4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMP_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_RREGS_l(d, s);
+
+	CMP_rr(d, s);
+
+  flags_carry_inverted = true;
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_CMP_l,(RR4 d, RR4 s))
+
+/*
+ * CMPA
+ * Operand Syntax: 	<ea>, An
+ *
+ * Operand Size: 16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ */
+MIDFUNC(2,jff_CMPA_w_imm,(RR2 d, IM16 v))
+{
+  uae_u16 tmp = (uae_u16)(v & 0xffff);
+  d = readreg(d);
+  SIGNED16_IMM_2_REG(REG_WORK1, tmp);
+  CMP_rr(d, REG_WORK1);
+  unlock2(d);
+
+  flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMPA_w_imm,(RR2 d, IM16 v))
+
+MIDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s))
+{
+  if (isconst(s)) {
+		COMPCALL(jff_CMPA_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_RREGS_w(d, s);
+  SIGNED16_REG_2_REG(REG_WORK2, s);
+  CMP_rr(d, REG_WORK2);
+	EXIT_REGS(d,s);
+
+  flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s))
+
+MIDFUNC(2,jff_CMPA_l_imm,(RR4 d, IM32 v))
+{
+  d = readreg(d);
+
+  LOAD_U32(REG_WORK1, v);
+	CMP_rr(d, REG_WORK1);
+
+  flags_carry_inverted = true;
+	unlock2(d);
+}
+MENDFUNC(2,jff_CMPA_l_imm,(RR4 d, IM32 v))
+
+MIDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMPA_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_RREGS_l(d, s);
+
+	CMP_rr(d, s);
+
+  flags_carry_inverted = true;
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s))
+
+/*
+ * DBCC
+ *
+ */
+MIDFUNC(2,jff_DBCC,(RW4 d, IM8 cc))
+{
+  d = rmw(d);
+
+  FIX_INVERTED_CARRY
+
+  // If cc true -> no branch, so we have to clear ARM_C_FLAG
+	MOV_ri(REG_WORK1, ARM_C_FLAG);
+  switch(cc) {
+    case 9: // LS
+      CC_MOV_ri(NATIVE_CC_EQ, REG_WORK1, 0);
+      CC_MOV_ri(NATIVE_CC_CS, REG_WORK1, 0);
+      break;
+
+    case 8: // HI
+      CC_MOV_ri(NATIVE_CC_CC, REG_WORK1, 0);
+      CC_MOV_ri(NATIVE_CC_EQ, REG_WORK1, ARM_C_FLAG);
+      break;
+
+    default:
+	CC_MOV_ri(cc, REG_WORK1, 0);
+	break;
+  }
+  clobber_flags();
+	MSR_CPSRf_r(REG_WORK1);
+
+  BCC_i(2); // If cc true -> no sub
+
+  // sub (d, 1)
+  LSL_rri(REG_WORK2, d, 16);
+	SUBS_rri(REG_WORK2, REG_WORK2, 1 << 16);
+  PKHTB_rrrASRi(d, d, REG_WORK2, 16);
+
+  // caller can now use register_branch(v1, v2, NATIVE_CC_CS);
+
+  unlock2(d);
+}
+MENDFUNC(2,jff_DBCC,(RW4 d, IM8 cc))
+
+/*
+ * DIVU
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set or overflow. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise.
+ * C Always cleared.
+ *
+ */
+#ifdef ARMV6T2
+
+MIDFUNC(2,jnf_DIVU,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+  UNSIGNED16_REG_2_REG(REG_WORK3, s);
+  TST_rr(REG_WORK3, REG_WORK3);
+  BNE_i(2);     // src is not 0
+
+  // Signal exception 5
+  MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	UDIV_rrr(REG_WORK1, d, REG_WORK3);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
+	VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  LSRS_rri(REG_WORK2, REG_WORK1, 16); 							// if result of this is not 0, DIVU overflows -> no result
+  BNE_i(1);
+
+  // Here we have to calc remainder
+  MLS_rrrr(REG_WORK2, REG_WORK1, REG_WORK3, d);
+	PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
+  // end_of_op
+
+  write_jmp_target(branchadd, (uintptr)get_target());
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_DIVU,(RW4 d, R4 s))
+
+MIDFUNC(2,jff_DIVU,(RW4 d, RR4 s))
+{
+	uae_u32* branchadd;
+	INIT_REGS_l(d, s);
+
+  UNSIGNED16_REG_2_REG(REG_WORK3, s);
+  TST_rr(REG_WORK3, REG_WORK3);
+  BNE_i(4);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+
+  // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
+  MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
+  MSR_CPSRf_r(REG_WORK1);
+  branchadd = (uae_u32*)get_target();
+  B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	UDIV_rrr(REG_WORK1, d, REG_WORK3);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
+	VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  LSRS_rri(REG_WORK2, REG_WORK1, 16); 							// if result of this is not 0, DIVU overflows
+  BEQ_i(2);
+  // Here we handle overflow
+  MOV_ri(REG_WORK1, ARM_V_FLAG | ARM_N_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+  B_i(5);
+
+  // Here we have to calc flags and remainder
+  LSLS_rri(REG_WORK2, REG_WORK1, 16);  // N and Z ok
+	MRS_CPSR(REG_WORK2);
+	BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
+	MSR_CPSRf_r(REG_WORK2);
+
+  MLS_rrrr(REG_WORK2, REG_WORK1, REG_WORK3, d);
+  PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
+
+  // end_of_op
+  flags_carry_inverted = false;
+  write_jmp_target(branchadd, (uintptr)get_target());
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_DIVU,(RW4 d, RR4 s))
+
+#endif
+
+/*
+ * DIVS
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set or overflow. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise.
+ * C Always cleared.
+ *
+ */
+#ifdef ARMV6T2
+
+MIDFUNC(2,jnf_DIVS,(RW4 d, RR4 s))
+{
+	uae_u32* branchadd;
+	INIT_REGS_l(d, s);
+
+  SIGNED16_REG_2_REG(REG_WORK3, s);
+  TST_rr(REG_WORK3, REG_WORK3);
+  BNE_i(2);     // src is not 0
+
+  // Signal exception 5
+  MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+  branchadd = (uae_u32*)get_target();
+  B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	SDIV_rrr(REG_WORK1, d, REG_WORK3);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
+	VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // check for overflow
+  MVN_ri(REG_WORK2, 0);
+  LSL_rri(REG_WORK2, REG_WORK2, 15); 		// REG_WORK2 is now 0xffff8000
+  ANDS_rrr(REG_WORK3, REG_WORK1, REG_WORK2);
+  BEQ_i(1); 														// positive result, no overflow
+	CMP_rr(REG_WORK3, REG_WORK2);
+	BNE_i(5);															// overflow -> end_of_op
+
+  // Here we have to calc remainder
+  SIGNED16_REG_2_REG(REG_WORK3, s);
+  MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
+	SUB_rrr(REG_WORK2, d, REG_WORK2);		// REG_WORK2 contains remainder
+
+	EORS_rrr(REG_WORK3, REG_WORK2, d);	// If sign of remainder and first operand differs, change sign of remainder
+	CC_RSB_rri(NATIVE_CC_MI, REG_WORK2, REG_WORK2, 0);
+
+	PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
+
+  // end_of_op
+  write_jmp_target(branchadd, (uintptr)get_target());
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_DIVS,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_DIVS,(RW4 d, RR4 s))
+{
+	uae_u32* branchadd;
+	INIT_REGS_l(d, s);
+
+  SIGNED16_REG_2_REG(REG_WORK3, s);
+  TST_rr(REG_WORK3, REG_WORK3);
+  BNE_i(4);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+
+  // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
+  MOV_ri(REG_WORK1, ARM_Z_FLAG);
+  MSR_CPSRf_r(REG_WORK1);
+  branchadd = (uae_u32*)get_target();
+  B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	SDIV_rrr(REG_WORK1, d, REG_WORK3);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, REG_WORK3, 0);
+	VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // check for overflow
+  MVN_ri(REG_WORK2, 0);
+  LSL_rri(REG_WORK2, REG_WORK2, 15); 		// REG_WORK2 is now 0xffff8000
+  ANDS_rrr(REG_WORK3, REG_WORK1, REG_WORK2);
+  BEQ_i(4); 														// positive result, no overflow
+	CMP_rr(REG_WORK3, REG_WORK2);
+	BEQ_i(2);															// no overflow
+
+  // Here we handle overflow
+  MOV_ri(REG_WORK1, ARM_V_FLAG | ARM_N_FLAG);
+	MSR_CPSRf_r(REG_WORK1);
+  B_i(9);
+
+  // calc flags
+  LSLS_rri(REG_WORK2, REG_WORK1, 16);  // N and Z ok
+	MRS_CPSR(REG_WORK2);
+	BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
+	MSR_CPSRf_r(REG_WORK2);
+
+  // calc remainder
+  SIGNED16_REG_2_REG(REG_WORK3, s);
+  MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
+	SUB_rrr(REG_WORK2, d, REG_WORK2);		// REG_WORK2 contains remainder
+
+	EORS_rrr(REG_WORK3, REG_WORK2, d);	// If sign of remainder and first operand differs, change sign of remainder
+	CC_RSB_rri(NATIVE_CC_MI, REG_WORK2, REG_WORK2, 0);
+
+	PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
+
+  // end_of_op
+  flags_carry_inverted = false;
+	write_jmp_target(branchadd, (uintptr)get_target());
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_DIVS,(RW4 d, RR4 s))
+
+MIDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1);
+  d = rmw(d);
+  rem = writereg(rem);
+
+  TST_rr(s1, s1);
+  BNE_i(2);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	UDIV_rrr(REG_WORK1, d, s1);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc remainder
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+  MOV_rr(d, REG_WORK1);
+
+// end_of_op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1);
+  d = rmw(d);
+  rem = writereg(rem);
+
+  TST_rr(s1, s1);
+  BNE_i(4);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+
+  // simplified flag handling for div0: set Z and V (for signed DIV: Z only)
+  MOV_ri(REG_WORK1, ARM_Z_FLAG);
+  MSR_CPSRf_r(REG_WORK1);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	UDIV_rrr(REG_WORK1, d, s1);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc flags and remainder
+  TST_rr(REG_WORK1, REG_WORK1);
+	MRS_CPSR(REG_WORK2);
+	BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
+	MSR_CPSRf_r(REG_WORK2);
+
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+  MOV_rr(d, REG_WORK1);
+
+  // end_of_op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1);
+  d = rmw(d);
+  rem = writereg(rem);
+
+  TST_rr(s1, s1);
+  BNE_i(2);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	SDIV_rrr(REG_WORK1, d, s1);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc remainder
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+
+	EORS_rrr(REG_WORK3, rem, d);	// If sign of remainder and first operand differs, change sign of remainder
+	CC_RSB_rri(NATIVE_CC_MI, rem, rem, 0);
+  MOV_rr(d, REG_WORK1);
+
+  // end_of_op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+{
+  s1 = readreg(s1);
+  d = rmw(d);
+  rem = writereg(rem);
+
+  TST_rr(s1, s1);
+  BNE_i(2);     // src is not 0
+
+  // Signal exception 5
+	MOV_ri(REG_WORK1, 5);
+  uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+  STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);        // end_of_op
+
+	// src is not 0
+#ifdef ARM_HAS_DIV
+	SDIV_rrr(REG_WORK1, d, s1);
+#else
+	VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
+	VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
+	VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
+	VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
+	VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
+	VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
+	VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
+#endif
+
+  // Here we have to calc remainder
+  MUL_rrr(REG_WORK2, s1, REG_WORK1);
+  SUB_rrr(rem, d, REG_WORK2);
+
+	EORS_rrr(REG_WORK3, rem, d);	// If sign of remainder and first operand differs, change sign of remainder
+	CC_RSB_rri(NATIVE_CC_MI, rem, rem, 0);
+  MOV_rr(d, REG_WORK1);
+
+  // end_of_op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+  unlock2(rem);
+  unlock2(d);
+  unlock2(s1);
+}
+MENDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+
+#endif
+
+/*
+ * EOR
+ * Operand Syntax: 	Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_EOR_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	EOR_rri(d, d, (v & 0xff));
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_EOR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_EOR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_EOR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		EOR_rrr(REG_WORK1, d, s);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		EOR_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_EOR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_EOR_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+  if(CHECK32(v & 0xffff)) {
+    EOR_rri(REG_WORK1, d, (v & 0xffff));
+  } else {
+	  LOAD_U16(REG_WORK1, v & 0xffff);
+	  EOR_rrr(REG_WORK1, d, REG_WORK1);
+  }
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_EOR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_EOR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_EOR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	EOR_rrr(REG_WORK1, d, s);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_EOR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_EOR_l_imm,(RW4 d, IM32 v))
+{
+  if(isconst(d)) {
+    live.state[d].val = live.state[d].val ^ v;
+    return;
+  }
+
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    EOR_rri(d, d, v);
+  } else {
+    LOAD_U32(REG_WORK1, v);
+	EOR_rrr(d, d, REG_WORK1);
+  }
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_EOR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_EOR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_EOR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	EOR_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_EOR_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_EOR_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_IMM_2_REG(REG_WORK2, v);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		EORS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		EORS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_EOR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_EOR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_EOR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_REG_2_REG(REG_WORK2, s);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		EORS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		EORS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_EOR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_EOR_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_IMM_2_REG(REG_WORK2, v);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		EORS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		EORS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_EOR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_EOR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_EOR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_REG_2_REG(REG_WORK2, s);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		EORS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		EORS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_EOR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_EOR_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	if(CHECK32(v)) {
+	  EORS_rri(d, d, v);
+	} else {
+	  LOAD_U32(REG_WORK1, v);
+	EORS_rrr(d, d, REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_EOR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_EOR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_EOR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	MSR_CPSRf_i(0);
+	EORS_rrr(d, d, s);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_EOR_l,(RW4 d, RR4 s))
+
+/*
+ * EORSR
+ * Operand Syntax: 	#<data>, CCR
+ *
+ * Operand Size: 8
+ *
+ * X - Changed if bit 4 of immediate operand is one; unchanged otherwise.
+ * N - Changed if bit 3 of immediate operand is one; unchanged otherwise.
+ * Z - Changed if bit 2 of immediate operand is one; unchanged otherwise.
+ * V - Changed if bit 1 of immediate operand is one; unchanged otherwise.
+ * C - Changed if bit 0 of immediate operand is one; unchanged otherwise.
+ *
+ */
+MIDFUNC(2,jff_EORSR,(IM32 s, IM8 x))
+{
+	MRS_CPSR(REG_WORK1);
+  if(flags_carry_inverted) {
+    EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);;
+    flags_carry_inverted = false;
+  }
+	EOR_rri(REG_WORK1, REG_WORK1, s);
+	MSR_CPSRf_r(REG_WORK1);
+
+	if (x) {
+		int f = rmw(FLAGX);
+		EOR_rri(f, f, 1);
+		unlock2(f);
+	}
+}
+MENDFUNC(2,jff_EORSR,(IM32 s, IM8 x))
+
+/*
+ * EXT
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_EXT_b,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (uae_s32)(uae_s8)live.state[d].val;
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_EXT_b,(RW4 d))
+
+MIDFUNC(1,jnf_EXT_w,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (((uae_s32)(uae_s8)live.state[d].val) & 0x0000ffff);
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	PKHTB_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_EXT_w,(RW4 d))
+
+MIDFUNC(1,jnf_EXT_l,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (uae_s32)(uae_s16)live.state[d].val;
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_EXT_l,(RW4 d))
+
+MIDFUNC(1,jff_EXT_b,(RW4 d))
+{
+	if (isconst(d)) {
+    uae_u8 tmp = (uae_u8)live.state[d].val;
+		d = writereg(d);
+		SIGNED8_IMM_2_REG(d, tmp);
+	} else {
+	  d = rmw(d);
+	  SIGNED8_REG_2_REG(d, d);
+	}
+
+	MSR_CPSRf_i(0);
+	TST_rr(d, d);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_EXT_b,(RW4 d))
+
+MIDFUNC(1,jff_EXT_w,(RW4 d))
+{
+	if (isconst(d)) {
+    uae_u8 tmp = (uae_u8)live.state[d].val;
+	  d = writereg(d);
+		SIGNED8_IMM_2_REG(REG_WORK1, tmp);
+	} else {
+		d = rmw(d);
+	  SIGNED8_REG_2_REG(REG_WORK1, d);
+	}
+
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+	PKHTB_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_EXT_w,(RW4 d))
+
+MIDFUNC(1,jff_EXT_l,(RW4 d))
+{
+	if (isconst(d)) {
+    uae_u16 tmp = (uae_u8)live.state[d].val;
+		d = writereg(d);
+		SIGNED16_IMM_2_REG(d, tmp);
+	} else {
+	  d = rmw(d);
+	  SIGNED16_REG_2_REG(d, d);
+	}
+	MSR_CPSRf_i(0);
+	TST_rr(d, d);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_EXT_l,(RW4 d))
+
+/*
+ * LSL
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ */
+MIDFUNC(2,jnf_LSL_b_imm,(RW1 d, IM8 i))
+{
+  if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val << i) & 0x000000ff);
+			return;
+		}
+
+		INIT_REG_b(d);
+
+    if(i > 31)
+      i = 31;
+	LSL_rri(REG_WORK1, d, i);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_LSL_w_imm,(RW2 d, IM8 i))
+{
+  if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val << i) & 0x0000ffff);
+			return;
+		}
+
+		INIT_REG_w(d);
+
+    if(i > 31)
+      i = 31;
+	LSL_rri(REG_WORK1, d, i);
+	  PKHTB_rrr(d, d, REG_WORK1);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_LSL_l_imm,(RW4 d, IM8 i))
+{
+  if(i) {
+		if (isconst(d)) {
+			live.state[d].val = live.state[d].val << i;
+			return;
+		}
+
+		d = rmw(d);
+
+	  LSL_rri(d, d, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_LSL_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSL_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	AND_rri(REG_WORK1, i, 63);
+	LSL_rrr(REG_WORK1, d, REG_WORK1);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSL_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_LSL_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSL_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	AND_rri(REG_WORK1, i, 63);
+	LSL_rrr(REG_WORK1, d, REG_WORK1);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSL_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_LSL_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		if(i > 31)
+			set_const(d, 0);
+		else
+			COMPCALL(jnf_LSL_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_rri(REG_WORK1, i, 63);
+	LSL_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSL_l_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_LSL_b_imm,(RW1 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+    if(i > 8) {
+	MSR_CPSRf_i(ARM_Z_FLAG);
+      BIC_rri(d, d, 0xff);
+    } else {
+	MSR_CPSRf_i(0);
+      if(i == 8) {
+	      LSL_rri(REG_WORK3, d, i);
+	      LSLS_rri(REG_WORK3, REG_WORK3, 24);
+      } else
+		LSLS_rri(REG_WORK3, d, i + 24);
+
+	    BIC_rri(d, d, 0xff);
+	    ORR_rrrLSRi(d, d, REG_WORK3, 24);
+    }
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+	MSR_CPSRf_i(0);
+		LSL_rri(REG_WORK3, d, 24);
+		TST_rr(REG_WORK3, REG_WORK3);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_LSL_w_imm,(RW2 d, IM8 i))
+{
+	if (i) {
+    if(i > 16) {
+	MSR_CPSRf_i(ARM_Z_FLAG);
+      BIC_rri(d, d, 0x00ff);
+      BIC_rri(d, d, 0xff00);
+    } else {
+	MSR_CPSRf_i(0);
+		  d = rmw(d);
+      if(i == 16) {
+	      LSL_rri(REG_WORK3, d, i);
+	      LSLS_rri(REG_WORK3, REG_WORK3, 16);
+      } else
+		  LSLS_rri(REG_WORK3, d, i + 16);
+	    PKHTB_rrrASRi(d, d, REG_WORK3, 16);
+    }
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+	MSR_CPSRf_i(0);
+		LSL_rri(REG_WORK3, d, 16);
+		TST_rr(REG_WORK3, REG_WORK3);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_LSL_l_imm,(RW4 d, IM8 i))
+{
+	if (i) {
+    if(i > 32) {
+	MSR_CPSRf_i(ARM_Z_FLAG);
+      set_const(d, 0);
+    } else {
+	  d = rmw(d);
+	MSR_CPSRf_i(0);
+      if(i == 32) {
+		  LSL_rri(d, d, 16);
+		  LSLS_rri(d, d, 16);
+      } else
+		  LSLS_rri(d, d, i);
+	unlock2(d);
+    }
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+	MSR_CPSRf_i(0);
+		TST_rr(d, d);
+    flags_carry_inverted = false;
+	unlock2(d);
+	}
+}
+MENDFUNC(2,jff_LSL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_LSL_b_reg,(RW1 d, RR4 i))
+{
+  if (isconst(i)) {
+    COMPCALL(jff_LSL_b_imm)(d, live.state[i].val & 0x3f);
+    return;
+  }
+
+	INIT_REGS_b(d, i);
+
+	MSR_CPSRf_i(0);
+	LSL_rri(REG_WORK3, d, 24);
+	ANDS_rri(REG_WORK1, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged, C cleared
+
+  // shift count > 0
+	LSLS_rrr(REG_WORK3, REG_WORK3, REG_WORK1);
+  BIC_rri(d, d, 0xff);
+  ORR_rrrLSRi(d, d, REG_WORK3, 24);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+	B_i(0);
+
+  // No shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(REG_WORK3, REG_WORK3);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSL_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_LSL_w_reg,(RW2 d, RR4 i))
+{
+  if (isconst(i)) {
+    COMPCALL(jff_LSL_w_imm)(d, live.state[i].val & 0x3f);
+    return;
+  }
+
+	INIT_REGS_w(d, i);
+
+	MSR_CPSRf_i(0);
+	LSL_rri(REG_WORK3, d, 16);
+	ANDS_rri(REG_WORK1, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged, C cleared
+
+	LSLS_rrr(REG_WORK3, REG_WORK3, REG_WORK1);
+  PKHTB_rrrASRi(d, d, REG_WORK3, 16);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+	B_i(0);
+
+  // No shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(REG_WORK3, REG_WORK3);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSL_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_LSL_l_reg,(RW4 d, RR4 i))
+{
+  if (isconst(i)) {
+    COMPCALL(jff_LSL_l_imm)(d, live.state[i].val & 0x3f);
+    return;
+  }
+
+	INIT_REGS_l(d, i);
+
+	MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK1, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged, C cleared
+
+	LSLS_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+	B_i(0);
+
+  // No shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(d, d);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSL_l_reg,(RW4 d, RR4 i))
+
+/*
+ * LSLW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_LSLW,(RW2 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val << 1) & 0xffff;
+		return;
+	}
+
+	d = rmw(d);
+
+	LSL_rri(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_LSLW,(RW2 d))
+
+MIDFUNC(1,jff_LSLW,(RW2 d))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	LSLS_rri(d, d, 17);
+	LSR_rri(d, d, 16);
+
+  flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_LSLW,(RW2 d))
+
+/*
+ * LSR
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ */
+MIDFUNC(2,jnf_LSR_b_imm,(RW1 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val & 0xff) >> i);
+			return;
+		}
+
+		INIT_REG_b(d);
+
+		UNSIGNED8_REG_2_REG(REG_WORK1, d);
+    if(i > 31)
+      i = 31;
+	LSR_rri(REG_WORK1, REG_WORK1, i);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_LSR_w_imm,(RW2 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val & 0x0000ffff) >> i);
+			return;
+		}
+
+		INIT_REG_w(d);
+
+		UNSIGNED16_REG_2_REG(REG_WORK1, d);
+    if(i > 31)
+      i = 31;
+	  PKHTB_rrrASRi(d, d, REG_WORK1, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_LSR_l_imm,(RW4 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = live.state[d].val >> i;
+			return;
+		}
+
+		d = rmw(d);
+
+	LSR_rri(d, d, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_LSR_b_imm,(RW1 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+    if(i > 8) {
+	MSR_CPSRf_i(ARM_Z_FLAG);
+      BIC_rri(d, d, 0xff);
+    } else {
+	MSR_CPSRf_i(0);
+	UNSIGNED8_REG_2_REG(REG_WORK1, d);
+		  LSRS_rri(REG_WORK1, REG_WORK1, i);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	    AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	    BIC_rri(d, d, 0xff);
+	    ORR_rrr(d, d, REG_WORK1);
+#endif
+    }
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+		TST_rr(REG_WORK1, REG_WORK1);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_LSR_w_imm,(RW2 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+    if(i > 16) {
+	MSR_CPSRf_i(ARM_Z_FLAG);
+      BIC_rri(d, d, 0x00ff);
+      BIC_rri(d, d, 0xff00);
+    } else {
+	MSR_CPSRf_i(0);
+	UNSIGNED16_REG_2_REG(REG_WORK1, d);
+		  LSRS_rri(REG_WORK1, REG_WORK1, i);
+	    PKHTB_rrr(d, d, REG_WORK1);
+    }
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+	  SIGNED16_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+		TST_rr(REG_WORK1, REG_WORK1);
+    flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_LSR_l_imm,(RW4 d, IM8 i))
+{
+	if (i) {
+    if(i > 32) {
+	MSR_CPSRf_i(ARM_Z_FLAG);
+      set_const(d, 0);
+    } else {
+	    d = rmw(d);
+	MSR_CPSRf_i(0);
+      if(i == 32) {
+		    LSR_rri(d, d, 16);
+		    LSRS_rri(d, d, 16);
+      } else
+		    LSRS_rri(d, d, i);
+	unlock2(d);
+    }
+    flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+	MSR_CPSRf_i(0);
+		TST_rr(d, d);
+    flags_carry_inverted = false;
+	unlock2(d);
+	}
+}
+MENDFUNC(2,jff_LSR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_LSR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSR_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	UNSIGNED8_REG_2_REG(REG_WORK1, d);
+	AND_rri(REG_WORK2, i, 63);
+	LSR_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_LSR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSR_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	UNSIGNED16_REG_2_REG(REG_WORK1, d);
+	AND_rri(REG_WORK2, i, 63);
+	LSR_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_LSR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		if(i > 31)
+			set_const(d, 0);
+		else
+			COMPCALL(jnf_LSR_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_rri(REG_WORK1, i, 63);
+	LSR_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSR_l_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_LSR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSR_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK1, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);                       // No shift -> X flag unchanged
+
+  AND_rri(REG_WORK2, d, 0xff);            // Shift count is not 0 -> unsigned required
+	LSRS_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+  flags_carry_inverted = false;
+  DUPLICACTE_CARRY
+
+	B_i(1);
+
+  // No shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	SIGNED8_REG_2_REG(REG_WORK2, d);        // Make sure, sign is in MSB if shift count is 0 (to get correct N flag)
+	TST_rr(REG_WORK2, REG_WORK2);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_LSR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSR_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+  MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK1, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);                       // No shift -> X flag unchanged
+
+	UXTH_rr(REG_WORK2, d);                  // Shift count is not 0 -> unsigned required
+	LSRS_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  PKHTB_rrr(d, d, REG_WORK2);
+
+  flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	B_i(1);
+
+  // No shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	SIGNED16_REG_2_REG(REG_WORK2, d);       // Make sure, sign is in MSB if shift count is 0 (to get correct N flag)
+	TST_rr(REG_WORK2, REG_WORK2);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_LSR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSR_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+  MSR_CPSRf_i(0);
+	ANDS_rri(REG_WORK1, i, 63);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);                       // No shift -> X flag unchanged
+
+	LSRS_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	B_i(0);
+
+  // No shift
+  write_jmp_target(branchadd, (uintptr)get_target());
+	TST_rr(d, d);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSR_l_reg,(RW4 d, RR4 i))
+
+/*
+ * LSRW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_LSRW,(RW2 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = ((live.state[d].val & 0xffff) >> 1);
+		return;
+	}
+
+	d = rmw(d);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	LSR_rri(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_LSRW,(RW2 d))
+
+MIDFUNC(1,jff_LSRW,(RW2 d))
+{
+	d = rmw(d);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	MSR_CPSRf_i(0);
+	LSRS_rri(d, d, 1);
+  flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_LSRW,(RW2 d))
+
+/*
+ * MOVE
+ * Operand Syntax: <ea>, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_MOVE_b_imm,(W1 d, IM8 s))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | (s & 0x000000ff);
+		return;
+	}
+
+	d = rmw(d);
+
+	MOV_ri(REG_WORK1, s & 0xff);
+#ifdef ARMV6T2
+	BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MOVE_b_imm,(W1 d, IM8 s))
+
+MIDFUNC(2,jnf_MOVE_w_imm,(W2 d, IM16 s))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (s & 0x0000ffff);
+		return;
+	}
+
+	d = rmw(d);
+
+	LOAD_U16(REG_WORK1, s & 0xffff);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MOVE_w_imm,(W2 d, IM16 s))
+
+MIDFUNC(2,jnf_MOVE_b,(W1 d, RR1 s))
+{
+	if(s == d)
+		return;
+	if (isconst(s)) {
+		COMPCALL(jnf_MOVE_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+#ifdef ARMV6T2
+  BFI_rrii(d, s, 0, 7);
+#else
+  AND_rri(REG_WORK1, s, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MOVE_b,(W1 d, RR1 s))
+
+MIDFUNC(2,jnf_MOVE_w,(W2 d, RR2 s))
+{
+	if(s == d)
+		return;
+	if (isconst(s)) {
+		COMPCALL(jnf_MOVE_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+  PKHTB_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MOVE_w,(W2 d, RR2 s))
+
+MIDFUNC(2,jnf_MOVE_l,(W4 d, RR4 s))
+{
+	mov_l_rr(d, s);
+}
+MENDFUNC(2,jnf_MOVE_l,(W4 d, RR4 s))
+
+MIDFUNC(2,jff_MOVE_b_imm,(W1 d, IM8 s))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	if (s & 0x80) {
+		MVNS_ri(REG_WORK1, (uae_u8) ~s);
+	} else {
+		MOVS_ri(REG_WORK1, (uae_u8) s);
+	}
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_MOVE_b_imm,(W1 d, IM8 s))
+
+MIDFUNC(2,jff_MOVE_w_imm,(W2 d, IM16 s))
+{
+	d = rmw(d);
+
+	SIGNED16_IMM_2_REG(REG_WORK1, (uae_u16)s);
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_MOVE_w_imm,(W2 d, IM16 s))
+
+MIDFUNC(2,jff_MOVE_l_imm,(W4 d, IM32 s))
+{
+	d = writereg(d);
+
+	LOAD_U32(d, s);
+	MSR_CPSRf_i(0);
+	TST_rr(d, d);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_MOVE_l_imm,(W4 d, IM32 s))
+
+MIDFUNC(2,jff_MOVE_b,(W1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_MOVE_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if(!s_is_d) {
+		s = readreg(s);
+	  d = rmw(d);
+  } else {
+		s = d = readreg(d);
+  }
+
+	SIGNED8_REG_2_REG(REG_WORK1, s);
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+	if(!s_is_d) {
+#ifdef ARMV6T2
+    BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+    AND_rri(REG_WORK1, REG_WORK1, 0xff);
+    BIC_rri(d, d, 0xff);
+    ORR_rrr(d, d, REG_WORK2);
+#endif
+  }
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MOVE_b,(W1 d, RR1 s))
+
+MIDFUNC(2,jff_MOVE_w,(W2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_MOVE_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if(!s_is_d) {
+		s = readreg(s);
+	  d = rmw(d);
+  } else {
+		s = d = readreg(d);
+  }
+
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+  if(!s_is_d)
+    PKHTB_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MOVE_w,(W2 d, RR2 s))
+
+MIDFUNC(2,jff_MOVE_l,(W4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_MOVE_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	s = readreg(s);
+
+	MSR_CPSRf_i(0);
+	if(!s_is_d) {
+	  d = writereg(d);
+	  MOVS_rr(d, s);
+  } else {
+    TST_rr(s, s);
+  }
+
+  flags_carry_inverted = false;
+	if(!s_is_d)
+	  unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_MOVE_l,(W4 d, RR4 s))
+
+/*
+ * MVMEL
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(3,jnf_MVMEL_w,(W4 d, RR4 s, IM8 offset))
+{
+	s = readreg(s);
+	d = writereg(d);
+
+	LDRH_rRI(REG_WORK1, s, offset);
+  REVSH_rr(d, REG_WORK1);
+  SXTH_rr(d, d);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(3,jnf_MVMEL_w,(W4 d, RR4 s, IM8 offset))
+
+MIDFUNC(3,jnf_MVMEL_l,(W4 d, RR4 s, IM8 offset))
+{
+	if (s == d || isconst(d) || isinreg(d)) {
+	  s = readreg(s);
+	  d = writereg(d);
+
+	  LDR_rRI(REG_WORK1, s, offset);
+    REV_rr(d, REG_WORK1);
+
+	  unlock2(d);
+	  unlock2(s);
+  } else {
+	s = readreg(s);
+
+	LDR_rRI(REG_WORK1, s, offset);
+    REV_rr(REG_WORK2, REG_WORK1);
+    uintptr idx = (uintptr)(&regs.regs[d]) - (uintptr) &regs;
+    STR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+
+	unlock2(s);
+  }
+}
+MENDFUNC(3,jnf_MVMEL_l,(W4 d, RR4 s, IM8 offset))
+
+/*
+ * MVMLE
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(3,jnf_MVMLE_w,(RR4 d, RR4 s, IM8 offset))
+{
+	s = readreg(s);
+	d = readreg(d);
+
+	REV16_rr(REG_WORK1, s);
+	if (offset >= 0)
+		STRH_rRI(REG_WORK1, d, offset);
+	else
+		STRH_rRi(REG_WORK1, d, -offset);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(3,jnf_MVMLE_w,(RR4 d, RR4 s, IM8 offset))
+
+MIDFUNC(3,jnf_MVMLE_l,(RR4 d, RR4 s, IM8 offset))
+{
+	if (s == d || isconst(s) || isinreg(s)) {
+	  s = readreg(s);
+	  d = readreg(d);
+
+	  REV_rr(REG_WORK1, s);
+	  if (offset >= 0)
+		  STR_rRI(REG_WORK1, d, offset);
+	  else
+		  STR_rRi(REG_WORK1, d, -offset);
+
+	  unlock2(d);
+	  unlock2(s);
+  } else {
+	d = readreg(d);
+
+    uintptr idx = (uintptr)(&regs.regs[s]) - (uintptr) &regs;
+    LDR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+	REV_rr(REG_WORK1, REG_WORK2);
+	  if (offset >= 0)
+		  STR_rRI(REG_WORK1, d, offset);
+	  else
+		  STR_rRi(REG_WORK1, d, -offset);
+
+	unlock2(d);
+  }
+}
+MENDFUNC(3,jnf_MVMLE_l,(RR4 d, RR4 s, IM8 offset))
+
+/*
+ * MOVE16
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s))
+{
+	s = readreg(s);
+	d = readreg(d);
+
+  PUSH_REGS((1 << d));
+
+	BIC_rri(REG_WORK3, s, 0x0000000F);
+	BIC_rri(d, d, 0x0000000F);
+
+	ADD_rrr(REG_WORK3, REG_WORK3, R_MEMSTART);
+	ADD_rrr(d, d, R_MEMSTART);
+
+#ifdef ARMV6T2
+	LDRD_rR(REG_WORK1, REG_WORK3);
+	STRD_rR(REG_WORK1, d);
+
+	LDRD_rRI(REG_WORK1, REG_WORK3, 8);
+	STRD_rRI(REG_WORK1, d, 8);
+#else
+	LDR_rR(REG_WORK1, REG_WORK3);
+	LDR_rRI(REG_WORK2, REG_WORK3, 4);
+	STR_rR(REG_WORK1, d);
+	STR_rRI(REG_WORK2, d, 4);
+
+	LDR_rRI(REG_WORK1, REG_WORK3, 8);
+	LDR_rRI(REG_WORK2, REG_WORK3, 12);
+	STR_rRI(REG_WORK1, d, 8);
+	STR_rRI(REG_WORK2, d, 12);
+#endif
+
+  POP_REGS((1 << d));
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s))
+
+/*
+ * MOVEA
+ * Operand Syntax: 	<ea>, An
+ *
+ * Operand Size: 16,32
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_MOVEA_w_imm,(W4 d, IM16 v))
+{
+  set_const(d, (uae_s32)(uae_s16)v);
+}
+MENDFUNC(2,jnf_MOVEA_w_imm,(W4 d, IM16 v))
+
+MIDFUNC(2,jnf_MOVEA_w,(W4 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_MOVEA_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SIGNED16_REG_2_REG(d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MOVEA_w,(W4 d, RR2 s))
+
+MIDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s))
+{
+	mov_l_rr(d, s);
+}
+MENDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s))
+
+/*
+ * MULS
+ * Operand Syntax: 	<ea>, Dn
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise. (32 Bit multiply only)
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_MULS,(RW4 d, RR4 s))
+{
+  if (isconst(s)) {
+    uae_s16 tmp = (uae_s16)live.state[s].val;
+    d = rmw(d);
+    SIGNED16_IMM_2_REG(REG_WORK1, tmp);
+    SMULxy_rrr(d, d, REG_WORK1, 0, 0);
+    unlock2(d);
+    return;
+  }
+
+	INIT_REGS_l(d, s);
+
+  SMULxy_rrr(d, d, s, 0, 0);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULS,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULS,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	SIGNED16_REG_2_REG(d, d);
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+
+	MSR_CPSRf_i(0);
+	MULS_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULS,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULS32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	MUL_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULS32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULS32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	MSR_CPSRf_i(0);
+	SMULLS_rrrr(d, REG_WORK2, d, s);
+
+  if (needed_flags & FLAG_V) {
+	  MRS_CPSR(REG_WORK1);
+	  TEQ_rrASRi(REG_WORK2, d, 31);
+	  CC_ORR_rri(NATIVE_CC_NE, REG_WORK1, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1);
+  }
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULS32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULS64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	SMULL_rrrr(d, s, d, s);
+
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MULS64,(RW4 d, RW4 s))
+
+MIDFUNC(2,jff_MULS64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	SMULLS_rrrr(d, s, d, s);
+
+  if (needed_flags & FLAG_V) {
+	  MRS_CPSR(REG_WORK1);
+	  TEQ_rrASRi(s, d, 31);
+	  CC_ORR_rri(NATIVE_CC_NE, REG_WORK1, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jff_MULS64,(RW4 d, RW4 s))
+
+/*
+ * MULU
+ * Operand Syntax: 	<ea>, Dn
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise. (32 Bit multiply only)
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_MULU,(RW4 d, RR4 s))
+{
+  if (isconst(s)) {
+    uae_u16 tmp = (uae_u16)live.state[s].val;
+    d = rmw(d);
+    UNSIGNED16_IMM_2_REG(REG_WORK1, tmp);
+    UNSIGNED16_REG_2_REG(d, d);
+    MUL_rrr(d, d, REG_WORK1);
+    unlock2(d);
+    return;
+  }
+
+	INIT_REGS_l(d, s);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	UNSIGNED16_REG_2_REG(REG_WORK1, s);
+	MUL_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULU,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULU,(RW4 d, RR4 s))
+{
+  if (isconst(s)) {
+    uae_u16 tmp = (uae_u16)live.state[s].val;
+    d = rmw(d);
+    UNSIGNED16_IMM_2_REG(REG_WORK1, tmp);
+    UNSIGNED16_REG_2_REG(d, d);
+	MSR_CPSRf_i(0);
+    MULS_rrr(d, d, REG_WORK1);
+    flags_carry_inverted = false;
+    unlock2(d);
+    return;
+  }
+
+	INIT_REGS_l(d, s);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	UNSIGNED16_REG_2_REG(REG_WORK1, s);
+	MSR_CPSRf_i(0);
+	MULS_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULU,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULU32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	MUL_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULU32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULU32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	MSR_CPSRf_i(0);
+	UMULLS_rrrr(d, REG_WORK2, d, s);
+
+  if (needed_flags & FLAG_V) {
+	  MRS_CPSR(REG_WORK1);
+	  TST_rr(REG_WORK2, REG_WORK2);
+	  CC_ORR_rri(NATIVE_CC_NE, REG_WORK1, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULU32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULU64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	UMULL_rrrr(d, s, d, s);
+
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MULU64,(RW4 d, RW4 s))
+
+MIDFUNC(2,jff_MULU64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	UMULLS_rrrr(d, s, d, s);
+
+  if (needed_flags & FLAG_V) {
+	  MRS_CPSR(REG_WORK1);
+	  TST_rr(s, s);
+	  CC_ORR_rri(NATIVE_CC_NE, REG_WORK1, REG_WORK1, ARM_V_FLAG);
+	  MSR_CPSRf_r(REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jff_MULU64,(RW4 d, RW4 s))
+
+/*
+ * NEG
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ */
+MIDFUNC(1,jnf_NEG_b,(RW1 d))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	RSB_rri(REG_WORK1, REG_WORK1, 0);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NEG_b,(RW1 d))
+
+MIDFUNC(1,jnf_NEG_w,(RW2 d))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	RSB_rri(REG_WORK1, REG_WORK1, 0);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NEG_w,(RW2 d))
+
+MIDFUNC(1,jnf_NEG_l,(RW4 d))
+{
+	d = rmw(d);
+
+	RSB_rri(d, d, 0);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NEG_l,(RW4 d))
+
+MIDFUNC(1,jff_NEG_b,(RW1 d))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	RSBS_rri(REG_WORK1, REG_WORK1, 0);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEG_b,(RW1 d))
+
+MIDFUNC(1,jff_NEG_w,(RW2 d))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	RSBS_rri(REG_WORK1, REG_WORK1, 0);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEG_w,(RW2 d))
+
+MIDFUNC(1,jff_NEG_l,(RW4 d))
+{
+	d = rmw(d);
+
+	RSBS_rri(d, d, 0);
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEG_l,(RW4 d))
+
+/*
+ * NEGX
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Cleared if the result is nonzero; unchanged otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ * Attention: Z is cleared only if the result is nonzero. Unchanged otherwise
+ *
+ */
+MIDFUNC(1,jnf_NEGX_b,(RW1 d))
+{
+  int x = readreg(FLAGX);
+	INIT_REG_b(d);
+  clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	RSC_rri(REG_WORK1, REG_WORK1, 0);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	unlock2(d);
+	unlock2(x);
+}
+MENDFUNC(1,jnf_NEGX_b,(RW1 d))
+
+MIDFUNC(1,jnf_NEGX_w,(RW2 d))
+{
+  int x = readreg(FLAGX);
+	INIT_REG_w(d);
+
+  clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	RSC_rri(REG_WORK1, REG_WORK1, 0);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(x);
+}
+MENDFUNC(1,jnf_NEGX_w,(RW2 d))
+
+MIDFUNC(1,jnf_NEGX_l,(RW4 d))
+{
+  int x = readreg(FLAGX);
+	d = rmw(d);
+
+  clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	RSC_rri(d, d, 0);
+
+	unlock2(d);
+	unlock2(x);
+}
+MENDFUNC(1,jnf_NEGX_l,(RW4 d))
+
+MIDFUNC(1,jff_NEGX_b,(RW1 d))
+{
+	INIT_REG_b(d);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	RSCS_rri(REG_WORK1, REG_WORK1, 0);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_CPSRf_r(REG_WORK1);
+  flags_carry_inverted = false;
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+
+	unlock2(x);
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEGX_b,(RW1 d))
+
+MIDFUNC(1,jff_NEGX_w,(RW2 d))
+{
+	INIT_REG_w(d);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	RSCS_rri(REG_WORK1, REG_WORK1, 0);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_CPSRf_r(REG_WORK1);
+  flags_carry_inverted = false;
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+
+	unlock2(x);
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEGX_w,(RW2 d))
+
+MIDFUNC(1,jff_NEGX_l,(RW4 d))
+{
+	d = rmw(d);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	RSCS_rri(d, d, 0);
+
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_CPSRf_r(REG_WORK1);
+  flags_carry_inverted = false;
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+
+	unlock2(x);
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEGX_l,(RW4 d))
+
+/*
+ * NOT
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_NOT_b,(RW1 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((~live.state[d].val) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+		MVN_rr(REG_WORK1, d);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		MVN_rr(d, d);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NOT_b,(RW1 d))
+
+MIDFUNC(1,jnf_NOT_w,(RW2 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | ((~live.state[d].val) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	if(targetIsReg) {
+		MVN_rr(REG_WORK1, d);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		MVN_rr(d, d);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NOT_w,(RW2 d))
+
+MIDFUNC(1,jnf_NOT_l,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = ~live.state[d].val;
+		return;
+	}
+
+	d = rmw(d);
+
+	MVN_rr(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NOT_l,(RW4 d))
+
+MIDFUNC(1,jff_NOT_b,(RW1 d))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		MVNS_rr(REG_WORK1, REG_WORK1);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		MVNS_rr(d, REG_WORK1);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_NOT_b,(RW1 d))
+
+MIDFUNC(1,jff_NOT_w,(RW2 d))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		MVNS_rr(REG_WORK1, REG_WORK1);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		MVNS_rr(d, REG_WORK1);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_NOT_w,(RW2 d))
+
+MIDFUNC(1,jff_NOT_l,(RW4 d))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	MVNS_rr(d, d);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_NOT_l,(RW4 d))
+
+/*
+ * OR
+ * Operand Syntax: 	<ea>, Dn
+ *  				Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_OR_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val | v) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+	  ORR_rri(REG_WORK1, d, v & 0xff);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+	  ORR_rri(d, d, v & 0xff);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_OR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_OR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_OR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		ORR_rrr(REG_WORK1, d, s);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		ORR_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_OR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_OR_w_imm,(RW2 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val | v) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	if(targetIsReg) {
+	  if(CHECK32(v & 0xffff)) {
+	    ORR_rri(REG_WORK1, d, (v & 0xffff));
+	  } else {
+		  LOAD_U16(REG_WORK1, v & 0xffff);
+		  ORR_rrr(REG_WORK1, d, REG_WORK1);
+	  }
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else{
+	  if(CHECK32(v & 0xffff)) {
+	    ORR_rri(d, d, (v & 0xffff));
+	  } else {
+		  LOAD_U16(REG_WORK1, v & 0xffff);
+		  ORR_rrr(d, d, REG_WORK1);
+	  }
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_OR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_OR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_OR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		ORR_rrr(REG_WORK1, d, s);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		ORR_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_OR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_OR_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val | v;
+		return;
+	}
+
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    ORR_rri(d, d, v);
+  } else {
+    LOAD_U32(REG_WORK1, v);
+	ORR_rrr(d, d, REG_WORK1);
+  }
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_OR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_OR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_OR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ORR_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_OR_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_OR_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_IMM_2_REG(REG_WORK2, v);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ORRS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		ORRS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_OR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_OR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_OR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_REG_2_REG(REG_WORK2, s);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ORRS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		ORRS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_OR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_OR_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_IMM_2_REG(REG_WORK2, v);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ORRS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		ORRS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_OR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_OR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_OR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_REG_2_REG(REG_WORK2, s);
+	MSR_CPSRf_i(0);
+	if(targetIsReg) {
+		ORRS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else {
+		ORRS_rrr(d, REG_WORK1, REG_WORK2);
+	}
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_OR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_OR_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	MSR_CPSRf_i(0);
+	if(CHECK32(v)) {
+	  ORRS_rri(d, d, v);
+	} else {
+	  LOAD_U32(REG_WORK1, v);
+	ORRS_rrr(d, d, REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_OR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_OR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_OR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	MSR_CPSRf_i(0);
+	ORRS_rrr(d, d, s);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_OR_l,(RW4 d, RR4 s))
+
+/*
+ * ORSR
+ * Operand Syntax: 	#<data>, CCR
+ *
+ * Operand Size: 8
+ *
+ * X - Set if bit 4 of immediate operand is one; unchanged otherwise.
+ * N - Set if bit 3 of immediate operand is one; unchanged otherwise.
+ * Z - Set if bit 2 of immediate operand is one; unchanged otherwise.
+ * V - Set if bit 1 of immediate operand is one; unchanged otherwise.
+ * C - Set if bit 0 of immediate operand is one; unchanged otherwise.
+ *
+ */
+MIDFUNC(1,jff_ORSR,(IM32 s, IM8 x))
+{
+	MRS_CPSR(REG_WORK1);
+  if (flags_carry_inverted) {
+    EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+    flags_carry_inverted = false;
+  }
+	ORR_rri(REG_WORK1, REG_WORK1, s);
+	MSR_CPSRf_r(REG_WORK1);
+
+	if (x) {
+		int f = writereg(FLAGX);
+		MOV_ri(f, 1);
+		unlock2(f);
+	}
+}
+MENDFUNC(2,jff_ORSR,(IM32 s, IM8 x))
+
+/*
+ * ROL
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROL_b_imm,(RW1 d, IM8 i))
+{
+  if(i & 0x1f) {
+		INIT_REG_b(d);
+
+	LSL_rri(REG_WORK1, d, 24);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	ROR_rri(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+		unlock2(d);
+  }
+}
+MENDFUNC(2,jnf_ROL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_ROL_w_imm,(RW2 d, IM8 i))
+{
+  if(i & 0x1f) {
+		INIT_REG_w(d);
+
+	PKHBT_rrrLSLi(REG_WORK1, d, d, 16);
+	ROR_rri(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+	  PKHTB_rrr(d, d, REG_WORK1);
+
+		unlock2(d);
+  }
+}
+MENDFUNC(2,jnf_ROL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_ROL_l_imm,(RW4 d, IM8 i))
+{
+  if(i & 0x1f) {
+    if (isconst(d)) {
+      i = i & 31;
+      live.state[d].val = (live.state[d].val << i) | (live.state[d].val >> (32-i));
+      return;
+    }
+
+		d = rmw(d);
+
+	ROR_rri(d, d, (32 - (i & 0x1f)));
+
+		unlock2(d);
+  }
+}
+MENDFUNC(2,jnf_ROL_l_imm,(RW4 d, RR4 s, IM8 i))
+
+MIDFUNC(2,jff_ROL_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_rri(REG_WORK1, d, 24);
+	MSR_CPSRf_i(0);
+	if (i) {
+	  ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	  ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+		if(i & 0x1f)
+		  RORS_rri(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+    else
+      TST_rr(REG_WORK1, REG_WORK1);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+
+		MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(REG_WORK2, REG_WORK1, 29, 29); // Handle C flag
+#else
+		TST_ri(REG_WORK1, 1);
+		CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+		CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+		MSR_CPSRf_r(REG_WORK2);
+	} else {
+		TST_rr(REG_WORK1, REG_WORK1);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ROL_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	PKHBT_rrrLSLi(REG_WORK1, d, d, 16);
+	MSR_CPSRf_i(0);
+	if (i) {
+		if(i & 0x1f)
+		RORS_rri(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+    else
+      TST_rr(REG_WORK1, REG_WORK1);
+	  PKHTB_rrr(d, d, REG_WORK1);
+
+		MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(REG_WORK2, REG_WORK1, 29, 29); // Handle C flag
+#else
+		TST_ri(d, 1);
+		CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+		CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+		MSR_CPSRf_r(REG_WORK2);
+	} else {
+		TST_rr(REG_WORK1, REG_WORK1);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ROL_l_imm,(RW4 d, IM8 i))
+{
+	MSR_CPSRf_i(0);
+	if (i) {
+		if(i & 0x1f) {
+	  d = rmw(d);
+		RORS_rri(d, d, (32 - (i & 0x1f)));
+    } else {
+		d = readreg(d);
+      TST_rr(d, d);
+    }
+
+		MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+		BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
+#else
+		TST_ri(d, 1);
+		CC_ORR_rri(NATIVE_CC_NE, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+		CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+		MSR_CPSRf_r(REG_WORK2);
+	} else {
+		d = readreg(d);
+		TST_rr(d, d);
+	}
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_ROL_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROL_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	AND_rri(REG_WORK1, i, 0x1f);
+	RSB_rri(REG_WORK1, REG_WORK1, 32);
+
+	LSL_rri(REG_WORK2, d, 24);
+	ORR_rrrLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 8);
+	ORR_rrrLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 16);
+	ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROL_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROL_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	AND_rri(REG_WORK1, i, 0x1f);
+	RSB_rri(REG_WORK1, REG_WORK1, 32);
+
+	PKHBT_rrrLSLi(REG_WORK2, d, d, 16);
+	ROR_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  PKHTB_rrr(d, d, REG_WORK2);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROL_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROL_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_rri(REG_WORK1, i, 0x1f);
+	RSB_rri(REG_WORK1, REG_WORK1, 32);
+
+	ROR_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROL_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROL_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROL_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	ANDS_rri(REG_WORK1, i, 0x1f);
+  BNE_i(3);
+
+  // shift count is 0
+	LSL_rri(REG_WORK3, d, 24);
+	MSR_CPSRf_i(0);
+  TST_rr(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0); // <end>
+
+	RSB_rri(REG_WORK1, REG_WORK1, 32);
+
+	LSL_rri(REG_WORK2, d, 24);
+	ORR_rrrLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 8);
+	ORR_rrrLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 16);
+	MSR_CPSRf_i(0);
+	RORS_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+	MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
+#else
+	TST_ri(d, 1);
+	ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
+	CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+	MSR_CPSRf_r(REG_WORK2);
+
+  // <end>
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROL_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROL_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	ANDS_rri(REG_WORK1, i, 0x1f);
+  BNE_i(3);
+
+  // shift count is 0
+	LSL_rri(REG_WORK3, d, 16);
+	MSR_CPSRf_i(0);
+  TST_rr(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+  uae_u32* branchadd = (uae_u32*)get_target();
+  B_i(0); // <end>
+
+	RSB_rri(REG_WORK1, REG_WORK1, 32);
+
+	PKHBT_rrrLSLi(REG_WORK2, d, d, 16);
+	MSR_CPSRf_i(0);
+	RORS_rrr(REG_WORK2, REG_WORK2, REG_WORK1);
+  PKHTB_rrr(d, d, REG_WORK2);
+
+	MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
+#else
+	TST_ri(d, 1);
+	ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
+	CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+	MSR_CPSRf_r(REG_WORK2);
+
+  // <end>
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROL_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROL_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_rri(REG_WORK1, i, 0x1f);
+	RSB_rri(REG_WORK1, REG_WORK1, 32);
+
+	MSR_CPSRf_i(0);
+	RORS_rrr(d, d, REG_WORK1);
+
+	MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
+#else
+	TST_ri(d, 1);
+	ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
+	CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+	MSR_CPSRf_r(REG_WORK2);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ROL_l,(RW4 d, RR4 i))
+
+/*
+ * ROLW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_ROLW,(RW2 d))
+{
+	d = rmw(d);
+
+	PKHBT_rrrLSLi(d, d, d, 16);
+	ROR_rri(d, d, (32 - 1));
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_ROLW,(RW2 d))
+
+MIDFUNC(1,jff_ROLW,(RW2 d))
+{
+	d = rmw(d);
+
+	PKHBT_rrrLSLi(d, d, d, 16);
+	MSR_CPSRf_i(0);
+	RORS_rri(d, d, (32 - 1));
+
+	MRS_CPSR(REG_WORK2);
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, d, 29, 29); // Handle C flag
+#else
+	TST_ri(d, 1);
+	ORR_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG);
+	CC_BIC_rri(NATIVE_CC_EQ, REG_WORK2, REG_WORK2, ARM_C_FLAG);
+#endif
+	MSR_CPSRf_r(REG_WORK2);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_ROLW,(RW2 d))
+
+/*
+ * ROXL
+ * Operand Syntax: Dx, Dy
+ * 				   #<data>, Dy
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit rotated out of the operand. Unchanged when the rotate count is zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROXL_b,(RW1 d, RR4 i))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_b(d, i);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 35);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
+	CMP_ri(REG_WORK1, 17);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
+	CMP_ri(REG_WORK1, 8);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 8);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	SUB_rri(REG_WORK3, REG_WORK1, 1);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 9);
+	UNSIGNED8_REG_2_REG(REG_WORK1, d);
+	ORR_rrrLSRr(REG_WORK2, REG_WORK2, REG_WORK1, REG_WORK3);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXL_w,(RW2 d, RR4 i))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_w(d, i);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 33);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
+	CMP_ri(REG_WORK1, 16);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 16);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	SUB_rri(REG_WORK3, REG_WORK1, 1);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 17);
+	UNSIGNED16_REG_2_REG(REG_WORK1, d);
+	ORR_rrrLSRr(REG_WORK2, REG_WORK2, REG_WORK1, REG_WORK3);
+  PKHTB_rrr(d, d, REG_WORK2);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXL_l,(RW4 d, RR4 i))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_l(d, i);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 32);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);			// end of op
+
+// need to rotate
+	CMP_ri(REG_WORK1, 32);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	SUB_rri(REG_WORK3, REG_WORK1, 1);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 33);
+	ORR_rrrLSRr(d, REG_WORK2, d, REG_WORK3);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXL_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROXL_b,(RW1 d, RR4 i))
+{
+	INIT_REGS_b(d, i);
+  int x = rmw(FLAGX);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 35);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
+	CMP_ri(REG_WORK1, 17);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
+	CMP_ri(REG_WORK1, 8);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(3);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	AND_rri(REG_WORK1, d, 0xff); // make sure to clear carry
+	MOVS_rrLSLi(REG_WORK1, REG_WORK1, 24);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+  // need to rotate
+	CMP_ri(REG_WORK1, 8);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	SUB_rri(REG_WORK3, REG_WORK1, 1);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	MSR_CPSRf_i(0);
+	RSB_rri(REG_WORK3, REG_WORK1, 9);
+	UNSIGNED8_REG_2_REG(REG_WORK1, d);
+	ORRS_rrrLSRr(REG_WORK2, REG_WORK2, REG_WORK1, REG_WORK3); // this LSR places correct bit in carry
+
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+	// Calc N and Z
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, x, 8, 8); // Make sure to set carry (last bit shifted out)
+#else
+	BIC_rri(REG_WORK2, REG_WORK2, 0x100);
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8);
+#endif
+	LSLS_rri(REG_WORK1, REG_WORK2, 24);
+
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROXL_w,(RW2 d, RR4 i))
+{
+	INIT_REGS_w(d, i);
+  int x = rmw(FLAGX);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 33);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
+	CMP_ri(REG_WORK1, 16);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(3);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	BIC_rri(REG_WORK1, d, 0x00ff0000); // make sure to clear carry
+	MOVS_rrLSLi(REG_WORK1, REG_WORK1, 16);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+  // need to rotate
+	CMP_ri(REG_WORK1, 16);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	SUB_rri(REG_WORK3, REG_WORK1, 1);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	MSR_CPSRf_i(0);
+	RSB_rri(REG_WORK3, REG_WORK1, 17);
+	UNSIGNED16_REG_2_REG(REG_WORK1, d);
+	ORRS_rrrLSRr(REG_WORK2, REG_WORK2, REG_WORK1, REG_WORK3); // this LSR places correct bit in carry
+
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+	// Calc N and Z
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, x, 16, 16); // Make sure to set carry (last bit shifted out)
+#else
+	BIC_rri(REG_WORK2, REG_WORK2, 0x10000);
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16);
+#endif
+	LSLS_rri(REG_WORK1, REG_WORK2, 16);
+
+  PKHTB_rrr(d, d, REG_WORK2);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROXL_l,(RW4 d, RR4 i))
+{
+	INIT_REGS_l(d, i);
+  int x = rmw(FLAGX);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 32);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(2);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	TST_rr(d, d);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+  // need to rotate
+	CMP_ri(REG_WORK1, 32);
+	CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	SUB_rri(REG_WORK3, REG_WORK1, 1);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	MSR_CPSRf_i(0);
+	RSB_rri(REG_WORK3, REG_WORK1, 33);
+	ORRS_rrrLSRr(d, REG_WORK2, d, REG_WORK3); // this LSR places correct bit in carry
+
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXL_l,(RW4 d, RR4 i))
+
+/*
+ * ROR
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROR_b_imm,(RW1 d, IM8 i))
+{
+	if(i & 0x07) {
+		INIT_REG_b(d);
+
+	LSL_rri(REG_WORK1, d, 24);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	ROR_rri(REG_WORK1, REG_WORK1, i & 0x07);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	BIC_rri(d, d, 0xff);
+	ORR_rrr(d, d, REG_WORK1);
+#endif
+
+		unlock2(d);
+  }
+}
+MENDFUNC(2,jnf_ROR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_ROR_w_imm,(RW2 d, IM8 i))
+{
+	if(i & 0x0f) {
+		INIT_REG_w(d);
+
+	PKHBT_rrrLSLi(REG_WORK1, d, d, 16);
+	ROR_rri(REG_WORK1, REG_WORK1, i & 0x0f);
+	  PKHTB_rrr(d, d, REG_WORK1);
+
+		unlock2(d);
+  }
+}
+MENDFUNC(2,jnf_ROR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_ROR_l_imm,(RW4 d, IM8 i))
+{
+	if(i & 0x1f) {
+	  if (isconst(d)) {
+	    i = i & 31;
+	    live.state[d].val = (live.state[d].val >> i) | (live.state[d].val << (32-i));
+	    return;
+	  }
+
+		d = rmw(d);
+
+		ROR_rri(d, d, i & 31);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_ROR_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_rri(REG_WORK1, d, 24);
+	MSR_CPSRf_i(0);
+	if(i & 0x07) {
+	  ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	  ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	RORS_rri(REG_WORK1, REG_WORK1, i & 0x07);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	BIC_rri(d, d, 0xff);
+	ORR_rrr(d, d, REG_WORK1);
+#endif
+  } else if (i > 0x07) {
+    TST_rr(REG_WORK1, REG_WORK1);
+    // We need to copy MSB to carry
+	MRS_CPSR(REG_WORK1); // carry is cleared
+	  CC_ORR_rri(NATIVE_CC_MI, REG_WORK1, REG_WORK1, ARM_C_FLAG);
+    MSR_CPSRf_r(REG_WORK1);
+  } else {
+    TST_rr(REG_WORK1, REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ROR_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	PKHBT_rrrLSLi(REG_WORK1, d, d, 16);
+	MSR_CPSRf_i(0);
+	if(i & 0x0f) {
+	RORS_rri(REG_WORK1, REG_WORK1, i & 0x0f);
+	  PKHTB_rrr(d, d, REG_WORK1);
+  } else if (i > 0x0f) {
+    TST_rr(REG_WORK1, REG_WORK1);
+    // We need to copy MSB to carry
+	MRS_CPSR(REG_WORK1); // carry is cleared
+	  CC_ORR_rri(NATIVE_CC_MI, REG_WORK1, REG_WORK1, ARM_C_FLAG);
+    MSR_CPSRf_r(REG_WORK1);
+  } else {
+    TST_rr(REG_WORK1, REG_WORK1);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ROR_l_imm,(RW4 d, IM8 i))
+{
+	if(i)
+	  d = rmw(d);
+	else
+		d = readreg(d);
+
+	MSR_CPSRf_i(0);
+	if(i & 0x1f) {
+	  RORS_rri(d, d, i & 0x1f);
+  } else if (i > 0x1f) {
+    TST_rr(d, d);
+    // We need to copy MSB to carry
+	MRS_CPSR(REG_WORK1); // carry is cleared
+	  CC_ORR_rri(NATIVE_CC_MI, REG_WORK1, REG_WORK1, ARM_C_FLAG);
+    MSR_CPSRf_r(REG_WORK1);
+  } else {
+    TST_rr(d, d);
+  }
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_ROR_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROR_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	LSL_rri(REG_WORK1, d, 24);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	ROR_rrr(REG_WORK1, REG_WORK1, i);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	BIC_rri(d, d, 0xff);
+	ORR_rrr(d, d, REG_WORK1);
+#endif
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROR_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROR_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	PKHBT_rrrLSLi(REG_WORK1, d, d, 16);
+	ROR_rrr(REG_WORK1, REG_WORK1, i);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROR_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROR_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	ROR_rrr(d, d, i);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROR_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROR_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROR_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	LSL_rri(REG_WORK1, d, 24);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	ORR_rrrLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	MSR_CPSRf_i(0);
+	AND_rri(REG_WORK2, i, 63);
+	RORS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	BIC_rri(d, d, 0xff);
+	ORR_rrr(d, d, REG_WORK1);
+#endif
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROR_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROR_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	PKHBT_rrrLSLi(REG_WORK1, d, d, 16);
+	MSR_CPSRf_i(0);
+	AND_rri(REG_WORK2, i, 63);
+	RORS_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+  PKHTB_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROR_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROR_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	MSR_CPSRf_i(0);
+	AND_rri(REG_WORK1, i, 63);
+	RORS_rrr(d, d, REG_WORK1);
+
+  flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROR_l,(RW4 d, RR4 i))
+
+/*
+ * RORW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_RORW,(RW2 d))
+{
+	d = rmw(d);
+
+	PKHBT_rrrLSLi(d, d, d, 16);
+	ROR_rri(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_RORW,(RW2 d))
+
+MIDFUNC(1,jff_RORW,(RW2 d))
+{
+	d = rmw(d);
+
+	PKHBT_rrrLSLi(d, d, d, 16);
+	MSR_CPSRf_i(0);
+	RORS_rri(d, d, 1);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_RORW,(RW2 d))
+
+/*
+ * ROXR
+ * Operand Syntax: Dx, Dy
+ * 				   #<data>, Dy
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit rotated out of the operand. Unchanged when the rotate count is zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROXR_b,(RW1 d, RR4 i))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_b(d, i);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 35);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
+	CMP_ri(REG_WORK1, 17);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
+	CMP_ri(REG_WORK1, 8);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);			// end of op
+
+  // need to rotate
+	AND_rri(REG_WORK2, d, 0xff);						 					// val = val & 0xff
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 9);	// val = val | (val << 9)
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8); 					// val = val | (x << 8)
+	MOV_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); 			// val = val >> cnt
+
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXR_w,(RW2 d, RR4 i))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_w(d, i);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 33);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
+	CMP_ri(REG_WORK1, 16);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);			// end of op
+
+  // need to rotate
+	BIC_rri(REG_WORK2, d, 0xff000000);
+	BIC_rri(REG_WORK2, REG_WORK2, 0x00ff0000);				// val = val & 0xffff
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 17);	// val = val | (val << 17)
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16); 				// val = val | (x << 16)
+	MOV_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); 			// val = val >> cnt
+
+  PKHTB_rrr(d, d, REG_WORK2);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXR_l,(RW4 d, RR4 i))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_l(d, i);
+
+	clobber_flags();
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 32);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
+	TST_rr(REG_WORK1, REG_WORK1);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);			// end of op
+
+  // need to rotate
+	CMP_ri(REG_WORK1, 32);
+	CC_MOV_rrLSRr(NATIVE_CC_NE, REG_WORK2, d, REG_WORK1);
+	CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 32);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	ADD_rri(REG_WORK3, REG_WORK3, 1);
+	ORR_rrrLSLr(d, REG_WORK2, d, REG_WORK3);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXR_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROXR_b,(RW1 d, RR4 i))
+{
+	INIT_REGS_b(d, i);
+  int x = rmw(FLAGX);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 35);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
+	CMP_ri(REG_WORK1, 17);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
+	CMP_ri(REG_WORK1, 8);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(3);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	BIC_rri(REG_WORK1, d, 0x0000ff00); // make sure to clear carry
+	MOVS_rrLSLi(REG_WORK1, REG_WORK1, 24);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			  // end of op
+
+  // need to rotate
+	AND_rri(REG_WORK2, d, 0xff);						 					// val = val & 0xff
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 9);	// val = val | (val << 9)
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8); 					// val = val | (x << 8)
+	MSR_CPSRf_i(0);
+	MOVS_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); 		// val = val >> cnt
+
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+	// Calc N and Z
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, x, 8, 8); // Make sure to set carry (last bit shifted out)
+#else
+	BIC_rri(REG_WORK2, REG_WORK2, 0x100);
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 8);
+#endif
+	LSLS_rri(REG_WORK1, REG_WORK2, 24);
+
+#ifdef ARMV6T2
+  BFI_rrii(d, REG_WORK2, 0, 7);
+#else
+  AND_rri(REG_WORK2, REG_WORK2, 0xff);
+  BIC_rri(d, d, 0xff);
+  ORR_rrr(d, d, REG_WORK2);
+#endif
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROXR_w,(RW2 d, RR4 i))
+{
+	INIT_REGS_w(d, i);
+  int x = rmw(FLAGX);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 33);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
+	CMP_ri(REG_WORK1, 16);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(3);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	BIC_rri(REG_WORK1, d, 0x00ff0000); // make sure to clear carry
+	MOVS_rrLSLi(REG_WORK1, REG_WORK1, 16);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+  // need to rotate
+	BIC_rri(REG_WORK2, d, 0xff000000);
+	BIC_rri(REG_WORK2, REG_WORK2, 0x00ff0000);				// val = val & 0xffff
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, REG_WORK2, 17);	// val = val | (val << 17)
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16); 				// val = val | (x << 16)
+	MSR_CPSRf_i(0);
+	MOVS_rrLSRr(REG_WORK2, REG_WORK2, REG_WORK1); 		// val = val >> cnt
+
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+	// Calc N and Z
+#ifdef ARMV6T2
+	BFI_rrii(REG_WORK2, x, 16, 16); // Make sure to set carry (last bit shifted out)
+#else
+	BIC_rri(REG_WORK2, REG_WORK2, 0x10000);
+	ORR_rrrLSLi(REG_WORK2, REG_WORK2, x, 16);
+#endif
+	LSLS_rri(REG_WORK1, REG_WORK2, 16);
+
+  PKHTB_rrr(d, d, REG_WORK2);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROXR_l,(RW4 d, RR4 i))
+{
+	INIT_REGS_l(d, i);
+  int x = rmw(FLAGX);
+
+	AND_rri(REG_WORK1, i, 63);
+	CMP_ri(REG_WORK1, 32);
+	CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
+	TST_rr(REG_WORK1, REG_WORK1);
+	BNE_i(2);			// need to rotate
+
+	MSR_CPSRf_i(0);
+	TST_rr(d, d);
+  uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+  // need to rotate
+	CMP_ri(REG_WORK1, 32);
+	BNE_i(3);			// rotate 1-31
+
+  // rotate 32
+	MSR_CPSRf_i(0);
+	LSLS_rri(d, d, 1);
+	ORRS_rrr(d, d, x);
+	B_i(5);				// duplicate carry
+
+  // rotate 1-31
+	MSR_CPSRf_i(0);
+	MOVS_rrLSRr(REG_WORK2, d, REG_WORK1);
+
+	RSB_rri(REG_WORK3, REG_WORK1, 32);
+	ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
+
+	ADD_rri(REG_WORK3, REG_WORK3, 1);
+	ORR_rrrLSLr(d, REG_WORK2, d, REG_WORK3);
+
+  // Duplicate carry
+	MOV_ri(x, 1);
+  CC_MOV_ri(NATIVE_CC_CC, x, 0);
+
+  // end of op
+  write_jmp_target(branchadd, (uintptr)get_target());
+
+  flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXR_l,(RW4 d, RR4 i))
+
+/*
+ * SCC
+ *
+ */
+MIDFUNC(2,jnf_SCC,(W1 d, IM8 cc))
+{
+  FIX_INVERTED_CARRY
+
+	INIT_WREG_b(d);
+
+	switch (cc) {
+		case 9: // LS
+			BIC_rri(d, d, 0xff);
+			CC_ORR_rri(NATIVE_CC_CS, d, d, 0xff);
+			CC_ORR_rri(NATIVE_CC_EQ, d, d, 0xff);
+			break;
+
+		case 8: // HI
+      BIC_rri(d, d, 0xff);
+      CC_ORR_rri(NATIVE_CC_CC, d, d, 0xff);
+      CC_BIC_rri(NATIVE_CC_EQ, d, d, 0xff);
+			break;
+
+		default:
+			ORR_rri(d, d, 0xff);
+			CC_BIC_rri(cc^1, d, d, 0xff);
+			break;
+	}
+
+  unlock2(d);
+}
+MENDFUNC(2,jnf_SCC,(W1 d, IM8 cc))
+
+/*
+ * SUB
+ * Operand Syntax: 	<ea>, Dn
+ * 					Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ */
+MIDFUNC(2,jnf_SUB_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | (((live.state[d].val & 0xff) - (v & 0xff)) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+	  SUB_rri(REG_WORK1, d, v & 0xff);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		SUB_rri(d, d, v & 0xff);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUB_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_SUB_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUB_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		SUB_rrr(REG_WORK1, d, s);
+#ifdef ARMV6T2
+	  BFI_rrii(d, REG_WORK1, 0, 7);
+#else
+	  AND_rri(REG_WORK1, REG_WORK1, 0xff);
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrr(d, d, REG_WORK1);
+#endif
+	} else {
+		SUB_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUB_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_SUB_w_imm,(RW2 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (((live.state[d].val & 0xffff) - (v & 0xffff)) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	UNSIGNED16_IMM_2_REG(REG_WORK1, (uae_u16)v);
+	if(targetIsReg) {
+		SUB_rrr(REG_WORK1, d, REG_WORK1);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else{
+		SUB_rrr(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUB_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_SUB_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUB_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		SUB_rrr(REG_WORK1, d, s);
+	  PKHTB_rrr(d, d, REG_WORK1);
+	} else{
+		SUB_rrr(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUB_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_SUB_l_imm,(RW2 d, IM32 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val - v;
+		return;
+	}
+
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    SUB_rri(d, d, v);
+  } else {
+    LOAD_U32(REG_WORK1, v);
+		SUB_rrr(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUB_l_imm,(RW2 d, IM32 v))
+
+MIDFUNC(2,jnf_SUB_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUB_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SUB_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUB_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_SUB_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	LSL_rri(REG_WORK1, d, 24);
+	SUBS_rri(REG_WORK1, REG_WORK1, (v << 24));
+	if(targetIsReg) {
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+	} else {
+		LSR_rri(d, REG_WORK1, 24);
+	}
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_SUB_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_SUB_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_SUB_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	LSL_rri(REG_WORK1, d, 24);
+	SUBS_rrrLSLi(REG_WORK1, REG_WORK1, s, 24);
+	if(targetIsReg) {
+	  BIC_rri(d, d, 0xff);
+	  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+	} else {
+		LSR_rri(d, REG_WORK1, 24);
+	}
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUB_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_SUB_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+  if(CHECK32(v)) {
+    MOV_ri(REG_WORK1, v);
+  } else {
+    LOAD_U16(REG_WORK1, v);
+  }
+	LSL_rri(REG_WORK2, d, 16);
+	SUBS_rrrLSLi(REG_WORK1, REG_WORK2, REG_WORK1, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_SUB_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_SUB_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_SUB_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	LSL_rri(REG_WORK1, d, 16);
+  SUBS_rrrLSLi(REG_WORK1, REG_WORK1, s, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUB_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_SUB_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+  if(CHECK32(v)) {
+    SUBS_rri(d, d,v);
+  } else {
+    LOAD_U32(REG_WORK1, v);
+	SUBS_rrr(d, d, REG_WORK1);
+  }
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_SUB_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_SUB_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_SUB_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SUBS_rrr(d, d, s);
+
+  flags_carry_inverted = true;
+  DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUB_l,(RW4 d, RR4 s))
+
+/*
+ * SUBA
+ *
+ * Operand Syntax: 	<ea>, Dn
+ *
+ * Operand Size: 16,32
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_SUBA_w_imm,(RW4 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val - (uae_s32)(uae_s16)v;
+		return;
+	}
+
+	d = rmw(d);
+	if(CHECK32(v)) {
+	  SUB_rri(d, d, v);
+	} else {
+	SIGNED16_IMM_2_REG(REG_WORK1, v);
+	SUB_rrr(d, d, REG_WORK1);
+  }
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUBA_w_imm,(RW4 d, IM16 v))
+
+MIDFUNC(2,jnf_SUBA_w,(RW4 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUBA_w_imm)(d, live.state[s].val & 0xffff);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	SUB_rrr(d, d, REG_WORK1);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBA_w,(RW4 d, RR2 s))
+
+MIDFUNC(2,jnf_SUBA_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		set_const(d, live.state[d].val - v);
+		return;
+	}
+
+	d = rmw(d);
+
+	if(CHECK32(v)) {
+	  SUB_rri(d, d, v);
+	} else {
+	LOAD_U32(REG_WORK1, v);
+	SUB_rrr(d, d, REG_WORK1);
+  }
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUBA_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_SUBA_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUBA_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SUB_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBA_l,(RW4 d, RR4 s))
+
+/*
+ * SUBX
+ * Operand Syntax: 	Dy, Dx
+ * 					-(Ay), -(Ax)
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Cleared if the result is nonzero. Unchanged otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ * Attention: Z is cleared only if the result is nonzero. Unchanged otherwise
+ *
+ */
+MIDFUNC(2,jnf_SUBX_b,(RW1 d, RR1 s))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_b(d, s);
+
+  clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	LSL_rri(REG_WORK1, d, 24);
+	SBC_rrrLSLi(REG_WORK1, REG_WORK1, s, 24);
+  BIC_rri(d, d, 0xff);
+  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_SUBX_w,(RW2 d, RR2 s))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_w(d, s);
+
+  clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	LSL_rri(REG_WORK1, d, 16);
+	SBC_rrrLSLi(REG_WORK1, REG_WORK1, s, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_SUBX_l,(RW4 d, RR4 s))
+{
+  int x = readreg(FLAGX);
+	INIT_REGS_l(d, s);
+
+  clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	SBC_rrr(d, d, s);
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_SUBX_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_SUBX_b,(RW1 d, RR1 s))
+{
+	INIT_REGS_b(d, s);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	LSL_rri(REG_WORK1, d, 24);
+	SBCS_rrrLSLi(REG_WORK1, REG_WORK1, s, 24);
+  BIC_rri(d, d, 0xff);
+  ORR_rrrLSRi(d, d, REG_WORK1, 24);
+
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_CPSRf_r(REG_WORK1);
+  flags_carry_inverted = false;
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUBX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_SUBX_w,(RW2 d, RR2 s))
+{
+	INIT_REGS_w(d, s);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	LSL_rri(REG_WORK1, d, 16);
+	SBCS_rrrLSLi(REG_WORK1, REG_WORK1, s, 16);
+  PKHTB_rrrASRi(d, d, REG_WORK1, 16);
+
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_CPSRf_r(REG_WORK1);
+  flags_carry_inverted = false;
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUBX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_SUBX_l,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+  int x = rmw(FLAGX);
+
+	MVN_ri(REG_WORK2, 0);
+	CC_MVN_ri(NATIVE_CC_NE, REG_WORK2, ARM_Z_FLAG);
+
+	// Restore inverted X to carry (don't care about other flags)
+  RSBS_rri(REG_WORK1, x, 0);
+
+	SBCS_rrr(d, d, s);
+
+	MRS_CPSR(REG_WORK1);
+	EOR_rri(REG_WORK1, REG_WORK1, ARM_C_FLAG);
+	AND_rrr(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_CPSRf_r(REG_WORK1);
+  flags_carry_inverted = false;
+	if (needed_flags & FLAG_X) {
+#ifdef ARMV6T2
+	UBFX_rrii(x, REG_WORK1, 29, 1); // Duplicate carry
+#else
+	  LSR_rri(x, REG_WORK1, 29);
+	  AND_rri(x, x, 1);
+#endif
+  }
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUBX_l,(RW4 d, RR4 s))
+
+/*
+ * SWAP
+ * Operand Syntax: Dn
+ *
+ *  Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the 32-bit result is set. Cleared otherwise.
+ * Z Set if the 32-bit result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_SWAP,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val >> 16) | (live.state[d].val << 16);
+		return;
+	}
+
+	d = rmw(d);
+
+	ROR_rri(d, d, 16);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_SWAP,(RW4 d))
+
+MIDFUNC(1,jff_SWAP,(RW4 d))
+{
+	d = rmw(d);
+
+	ROR_rri(d, d, 16);
+	MSR_CPSRf_i(0);
+	TST_rr(d, d);
+
+  flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_SWAP,(RW4 d))
+
+/*
+ * TST
+ * Operand Syntax: <ea>
+ *
+ *  Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the operand is negative. Cleared otherwise.
+ * Z Set if the operand is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jff_TST_b_imm,(IM8 v))
+{
+	SIGNED8_IMM_2_REG(REG_WORK1, (uae_u8)v);
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+  flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_b_imm,(IM8 v))
+
+MIDFUNC(1,jff_TST_b,(RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_TST_b_imm)(live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	SIGNED8_REG_2_REG(REG_WORK1, s);
+	unlock2(s);
+
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+  flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_b,(RR1 s))
+
+MIDFUNC(1,jff_TST_w_imm,(IM16 v))
+{
+	SIGNED16_IMM_2_REG(REG_WORK1, (uae_u16)v);
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+  flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_w_imm,(IM16 v))
+
+MIDFUNC(1,jff_TST_w,(RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_TST_w_imm)(live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	unlock2(s);
+
+	MSR_CPSRf_i(0);
+	TST_rr(REG_WORK1, REG_WORK1);
+  flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_w,(RR2 s))
+
+MIDFUNC(1,jff_TST_l_imm,(IM32 v))
+{
+	MSR_CPSRf_i(0);
+  LOAD_U32(REG_WORK1, v);
+	TST_rr(REG_WORK1, REG_WORK1);
+  flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_l_imm,(IM32 v))
+
+MIDFUNC(1,jff_TST_l,(RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_TST_l_imm)(live.state[s].val);
+		return;
+	}
+
+	MSR_CPSRf_i(0);
+	s = readreg(s);
+	TST_rr(s, s);
+	unlock2(s);
+  flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_l,(RR4 s))
+
+/*
+ * Memory access functions
+ *
+ * Two versions: full address range and 24 bit address range
+ *
+ */
+MIDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
+{
+  adr = readreg(adr);
+	b = readreg(b);
+
+  STRB_rRR(b, adr, R_MEMSTART);
+
+  unlock2(b);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
+
+MIDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
+{
+  adr = readreg(adr);
+	w = readreg(w);
+
+  REV16_rr(REG_WORK1, w);
+  STRH_rRR(REG_WORK1, adr, R_MEMSTART);
+
+  unlock2(w);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
+
+MIDFUNC(2,jnf_MEM_WRITE_OFF_l,(RR4 adr, RR4 l))
+{
+  adr = readreg(adr);
+  l = readreg(l);
+
+  REV_rr(REG_WORK1, l);
+  STR_rRR(REG_WORK1, adr, R_MEMSTART);
+
+  unlock2(l);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE_OFF_l,(RR4 adr, RR4 l))
+
+
+MIDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  LDRB_rRR(d, adr, R_MEMSTART);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  LDRH_rRR(REG_WORK1, adr, R_MEMSTART);
+  REV16_rr(d, REG_WORK1);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ_OFF_l,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  LDR_rRR(REG_WORK1, adr, R_MEMSTART);
+  REV_rr(d, REG_WORK1);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ_OFF_l,(W4 d, RR4 adr))
+
+
+MIDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
+{
+  adr = readreg(adr);
+  b = readreg(b);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  STRB_rRR(b, REG_WORK1, R_MEMSTART);
+
+  unlock2(b);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
+
+MIDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
+{
+  adr = readreg(adr);
+  w = readreg(w);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  REV16_rr(REG_WORK3, w);
+  STRH_rRR(REG_WORK3, REG_WORK1, R_MEMSTART);
+
+  unlock2(w);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
+
+MIDFUNC(2,jnf_MEM_WRITE24_OFF_l,(RR4 adr, RR4 l))
+{
+  adr = readreg(adr);
+  l = readreg(l);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  REV_rr(REG_WORK3, l);
+  STR_rRR(REG_WORK3, REG_WORK1, R_MEMSTART);
+
+  unlock2(l);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE24_OFF_l,(RR4 adr, RR4 l))
+
+
+MIDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  LDRB_rRR(d, REG_WORK1, R_MEMSTART);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  LDRH_rRR(REG_WORK1, REG_WORK1, R_MEMSTART);
+  REV16_rr(d, REG_WORK1);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ24_OFF_l,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  LDR_rRR(d, REG_WORK1, R_MEMSTART);
+  REV_rr(d, d);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ24_OFF_l,(W4 d, RR4 adr))
+
+
+MIDFUNC(2,jnf_MEM_GETADR_OFF,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  ADD_rrr(d, adr, R_MEMSTART);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_GETADR_OFF,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  BIC_rri(REG_WORK1, adr, 0xff000000);
+  ADD_rrr(d, REG_WORK1, R_MEMSTART);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_GETADR_JMP_OFF,(W4 d, RR4 adr))
+{
+  adr = readreg(adr);
+  d = writereg(d);
+
+  LOAD_U32(REG_WORK2, (uintptr)baseaddr);
+  LSR_rri(REG_WORK1, adr, 16);
+  LDR_rRR_LSLi(REG_WORK3, REG_WORK2, REG_WORK1, 2);
+  ADD_rrr(d, adr, REG_WORK3);
+  BIC_rri(d, d, 1);
+
+  unlock2(d);
+  unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_GETADR_JMP_OFF,(W4 d, RR4 adr))
+
+
+MIDFUNC(3,jnf_MEM_READMEMBANK,(W4 dest, RR4 adr, IM8 offset))
+{
+  clobber_flags();
+  if (dest != adr) {
+    COMPCALL(forget_about)(dest);
+  }
+
+  adr = readreg_specific(adr, REG_PAR1);
+  prepare_for_call_1();
+  unlock2(adr);
+  prepare_for_call_2();
+
+  uintptr idx = (uintptr)(&regs.mem_banks) - (uintptr)(&regs);
+  LDR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+  LSR_rri(REG_WORK1, adr, 16);
+  LDR_rRR_LSLi(REG_WORK3, REG_WORK2, REG_WORK1, 2);
+  LDR_rRI(REG_WORK3, REG_WORK3, offset);
+
+  compemu_raw_call_r(REG_WORK3);
+
+  live.nat[REG_RESULT].holds[0] = dest;
+  live.nat[REG_RESULT].nholds = 1;
+  live.nat[REG_RESULT].touched = touchcnt++;
+
+  live.state[dest].realreg = REG_RESULT;
+  live.state[dest].realind = 0;
+  live.state[dest].val = 0;
+  set_status(dest, DIRTY);
+}
+MENDFUNC(3,jnf_MEM_READMEMBANK,(W4 dest, RR4 adr, IM8 offset))
+
+
+MIDFUNC(3,jnf_MEM_WRITEMEMBANK,(RR4 adr, RR4 source, IM8 offset))
+{
+  clobber_flags();
+
+  adr = readreg_specific(adr, REG_PAR1);
+  source = readreg_specific(source, REG_PAR2);
+  prepare_for_call_1();
+  unlock2(adr);
+  unlock2(source);
+  prepare_for_call_2();
+
+  uintptr idx = (uintptr)(&regs.mem_banks) - (uintptr)(&regs);
+  LDR_rRI(REG_WORK2, R_REGSTRUCT, idx);
+  LSR_rri(REG_WORK1, adr, 16);
+  LDR_rRR_LSLi(REG_WORK3, REG_WORK2, REG_WORK1, 2);
+  LDR_rRI(REG_WORK3, REG_WORK3, offset);
+
+  compemu_raw_call_r(REG_WORK3);
+}
+MENDFUNC(3,jnf_MEM_WRITEMEMBANK,(RR4 adr, RR4 source, IM8 offset))
diff --git a/jit/arm/compemu_midfunc_arm2.h b/jit/arm/compemu_midfunc_arm2.h
new file mode 100644
index 00000000..7d1ee96f
--- /dev/null
+++ b/jit/arm/compemu_midfunc_arm2.h
@@ -0,0 +1,468 @@
+/*
+ *  compiler/compemu_midfunc_arm2.h - Native MIDFUNCS for ARM (JIT v2)
+ *
+ * Copyright (c) 2014 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Note:
+ *  	File is included by compemu.h
+ *
+ */
+
+// Arm optimized midfunc
+extern const uae_u32 ARM_CCR_MAP[];
+
+// ADD
+DECLARE_MIDFUNC(jnf_ADD_im8(W4 d, RR4 s, IM8 v));
+DECLARE_MIDFUNC(jnf_ADD_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jnf_ADD_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jnf_ADD_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jnf_ADD_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_ADD_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_ADD_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_ADD_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jff_ADD_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jff_ADD_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jff_ADD_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_ADD_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_ADD_l(RW4 d, RR4 s));
+
+// ADDA
+DECLARE_MIDFUNC(jnf_ADDA_w(RW4 d, RR2 s));
+DECLARE_MIDFUNC(jnf_ADDA_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jnf_ADDA_w_imm(RW4 d, IM16 v));
+DECLARE_MIDFUNC(jnf_ADDA_l_imm(RW4 d, IM32 v));
+
+// ADDX
+DECLARE_MIDFUNC(jnf_ADDX_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_ADDX_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_ADDX_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_ADDX_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_ADDX_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_ADDX_l(RW4 d, RR4 s));
+
+// ANDSR
+DECLARE_MIDFUNC(jff_ANDSR(IM32 s, IM8 x));
+
+// AND
+DECLARE_MIDFUNC(jnf_AND_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jnf_AND_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jnf_AND_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jnf_AND_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_AND_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_AND_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_AND_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jff_AND_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jff_AND_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jff_AND_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_AND_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_AND_l(RW4 d, RR4 s));
+
+// ASL
+DECLARE_MIDFUNC(jff_ASL_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jff_ASL_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jff_ASL_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jff_ASL_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_ASL_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_ASL_l_reg(RW4 d, RR4 i));
+
+// ASLW
+DECLARE_MIDFUNC(jff_ASLW(RW2 d));
+DECLARE_MIDFUNC(jnf_ASLW(RW2 d));
+
+// ASR
+DECLARE_MIDFUNC(jnf_ASR_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jnf_ASR_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jnf_ASR_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jff_ASR_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jff_ASR_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jff_ASR_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jnf_ASR_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ASR_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ASR_l_reg(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_ASR_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_ASR_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_ASR_l_reg(RW4 d, RR4 i));
+
+// ASRW
+DECLARE_MIDFUNC(jff_ASRW(RW2 d));
+DECLARE_MIDFUNC(jnf_ASRW(RW2 d));
+
+// BCHG
+DECLARE_MIDFUNC(jnf_BCHG_b_imm(RW1 d, IM8 s));
+DECLARE_MIDFUNC(jnf_BCHG_l_imm(RW4 d, IM8 s));
+DECLARE_MIDFUNC(jff_BCHG_b_imm(RW1 d, IM8 s));
+DECLARE_MIDFUNC(jff_BCHG_l_imm(RW4 d, IM8 s));
+DECLARE_MIDFUNC(jnf_BCHG_b(RW1 d, RR4 s));
+DECLARE_MIDFUNC(jnf_BCHG_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_BCHG_b(RW1 d, RR4 s));
+DECLARE_MIDFUNC(jff_BCHG_l(RW4 d, RR4 s));
+
+// BCLR
+DECLARE_MIDFUNC(jnf_BCLR_b_imm(RW1 d, IM8 s));
+DECLARE_MIDFUNC(jnf_BCLR_l_imm(RW4 d, IM8 s));
+DECLARE_MIDFUNC(jnf_BCLR_b(RW1 d, RR4 s));
+DECLARE_MIDFUNC(jnf_BCLR_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_BCLR_b_imm(RW1 d, IM8 s));
+DECLARE_MIDFUNC(jff_BCLR_l_imm(RW4 d, IM8 s));
+DECLARE_MIDFUNC(jff_BCLR_b(RW1 d, RR4 s));
+DECLARE_MIDFUNC(jff_BCLR_l(RW4 d, RR4 s));
+
+// BFINS
+DECLARE_MIDFUNC(jnf_BFINS_ii(RW4 d, RR4 s, IM8 offs, IM8 width));
+DECLARE_MIDFUNC(jff_BFINS_ii(RW4 d, RR4 s, IM8 offs, IM8 width));
+DECLARE_MIDFUNC(jnf_BFINS2_ii(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width));
+DECLARE_MIDFUNC(jff_BFINS2_ii(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width));
+DECLARE_MIDFUNC(jnf_BFINS_di(RW4 d, RR4 s, RR4 offs, IM8 width));
+DECLARE_MIDFUNC(jff_BFINS_di(RW4 d, RR4 s, RR4 offs, IM8 width));
+DECLARE_MIDFUNC(jnf_BFINS2_di(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width));
+DECLARE_MIDFUNC(jff_BFINS2_di(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width));
+DECLARE_MIDFUNC(jnf_BFINS_id(RW4 d, RR4 s, IM8 offs, RR4 width));
+DECLARE_MIDFUNC(jff_BFINS_id(RW4 d, RR4 s, IM8 offs, RR4 width));
+DECLARE_MIDFUNC(jnf_BFINS2_id(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width));
+DECLARE_MIDFUNC(jff_BFINS2_id(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width));
+DECLARE_MIDFUNC(jnf_BFINS_dd(RW4 d, RR4 s, RR4 offs, RR4 width));
+DECLARE_MIDFUNC(jff_BFINS_dd(RW4 d, RR4 s, RR4 offs, RR4 width));
+DECLARE_MIDFUNC(jnf_BFINS2_dd(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width));
+DECLARE_MIDFUNC(jff_BFINS2_dd(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width));
+
+// BSET
+DECLARE_MIDFUNC(jnf_BSET_b_imm(RW1 d, IM8 s));
+DECLARE_MIDFUNC(jnf_BSET_l_imm(RW4 d, IM8 s));
+DECLARE_MIDFUNC(jnf_BSET_b(RW1 d, RR4 s));
+DECLARE_MIDFUNC(jnf_BSET_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_BSET_b_imm(RW1 d, IM8 s));
+DECLARE_MIDFUNC(jff_BSET_l_imm(RW4 d, IM8 s));
+DECLARE_MIDFUNC(jff_BSET_b(RW1 d, RR4 s));
+DECLARE_MIDFUNC(jff_BSET_l(RW4 d, RR4 s));
+
+// BTST
+DECLARE_MIDFUNC(jff_BTST_b_imm(RR1 d, IM8 s));
+DECLARE_MIDFUNC(jff_BTST_l_imm(RR4 d, IM8 s));
+DECLARE_MIDFUNC(jff_BTST_b(RR1 d, RR4 s));
+DECLARE_MIDFUNC(jff_BTST_l(RR4 d, RR4 s));
+
+// CLR
+DECLARE_MIDFUNC (jnf_CLR_b(W1 d));
+DECLARE_MIDFUNC (jnf_CLR_w(W2 d));
+DECLARE_MIDFUNC (jnf_CLR_l(W4 d));
+DECLARE_MIDFUNC (jff_CLR_b(W1 d));
+DECLARE_MIDFUNC (jff_CLR_w(W2 d));
+DECLARE_MIDFUNC (jff_CLR_l(W4 d));
+
+// CMP
+DECLARE_MIDFUNC(jff_CMP_b_imm(RR1 d, IM8 v));
+DECLARE_MIDFUNC(jff_CMP_w_imm(RR2 d, IM16 v));
+DECLARE_MIDFUNC(jff_CMP_l_imm(RR4 d, IM32 v));
+DECLARE_MIDFUNC(jff_CMP_b(RR1 d, RR1 s));
+DECLARE_MIDFUNC(jff_CMP_w(RR2 d, RR2 s));
+DECLARE_MIDFUNC(jff_CMP_l(RR4 d, RR4 s));
+
+// CMPA
+DECLARE_MIDFUNC(jff_CMPA_w_imm(RR2 d, IM16 v));
+DECLARE_MIDFUNC(jff_CMPA_l_imm(RR4 d, IM32 v));
+DECLARE_MIDFUNC(jff_CMPA_w(RR2 d, RR2 s));
+DECLARE_MIDFUNC(jff_CMPA_l(RR4 d, RR4 s));
+
+// DBCC
+DECLARE_MIDFUNC(jff_DBCC(RW4 d, IM8 cc));
+
+// DIVU
+DECLARE_MIDFUNC(jnf_DIVU(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_DIVU(RW4 d, RR4 s));
+
+// DIVS
+DECLARE_MIDFUNC(jnf_DIVS(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_DIVS(RW4 d, RR4 s));
+
+// DIVL
+DECLARE_MIDFUNC(jnf_DIVLU32(RW4 d, RR4 s1, W4 rem));
+DECLARE_MIDFUNC(jff_DIVLU32(RW4 d, RR4 s1, W4 rem));
+DECLARE_MIDFUNC(jnf_DIVLS32(RW4 d, RR4 s1, W4 rem));
+DECLARE_MIDFUNC(jff_DIVLS32(RW4 d, RR4 s1, W4 rem));
+
+// EOR
+DECLARE_MIDFUNC(jnf_EOR_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jnf_EOR_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jnf_EOR_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jnf_EOR_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_EOR_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_EOR_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_EOR_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jff_EOR_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jff_EOR_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jff_EOR_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_EOR_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_EOR_l(RW4 d, RR4 s));
+
+// EORSR
+DECLARE_MIDFUNC(jff_EORSR(IM32 s, IM8 x));
+
+// EXT
+DECLARE_MIDFUNC(jnf_EXT_b(RW4 d));
+DECLARE_MIDFUNC(jnf_EXT_w(RW4 d));
+DECLARE_MIDFUNC(jnf_EXT_l(RW4 d));
+DECLARE_MIDFUNC(jff_EXT_b(RW4 d));
+DECLARE_MIDFUNC(jff_EXT_w(RW4 d));
+DECLARE_MIDFUNC(jff_EXT_l(RW4 d));
+
+// LSL
+DECLARE_MIDFUNC(jnf_LSL_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jnf_LSL_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jnf_LSL_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jnf_LSL_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_LSL_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_LSL_l_reg(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_LSL_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jff_LSL_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jff_LSL_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jff_LSL_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_LSL_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_LSL_l_reg(RW4 d, RR4 i));
+
+// LSLW
+DECLARE_MIDFUNC(jff_LSLW(RW2 d));
+DECLARE_MIDFUNC(jnf_LSLW(RW2 d));
+
+// LSR
+DECLARE_MIDFUNC(jnf_LSR_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jnf_LSR_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jnf_LSR_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jff_LSR_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jff_LSR_w_imm(RW2 d, IM8 i));
+DECLARE_MIDFUNC(jff_LSR_l_imm(RW4 d, IM8 i));
+DECLARE_MIDFUNC(jnf_LSR_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_LSR_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_LSR_l_reg(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_LSR_b_reg(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_LSR_w_reg(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_LSR_l_reg(RW4 d, RR4 i));
+
+// LSRW
+DECLARE_MIDFUNC(jff_LSRW(RW2 d));
+DECLARE_MIDFUNC(jnf_LSRW(RW2 d));
+
+// MOVE
+DECLARE_MIDFUNC(jnf_MOVE_b_imm(W4 d, IM8 i));
+DECLARE_MIDFUNC(jnf_MOVE_w_imm(W4 d, IM16 i));
+DECLARE_MIDFUNC(jnf_MOVE_b(W4 d, RR1 s));
+DECLARE_MIDFUNC(jnf_MOVE_w(W4 d, RR2 s));
+DECLARE_MIDFUNC(jnf_MOVE_l(W4 d, RR4 s));
+DECLARE_MIDFUNC(jff_MOVE_b_imm(W4 d, IM8 i));
+DECLARE_MIDFUNC(jff_MOVE_w_imm(W4 d, IM16 i));
+DECLARE_MIDFUNC(jff_MOVE_l_imm(W4 d, IM32 i));
+DECLARE_MIDFUNC(jff_MOVE_b(W4 d, RR1 s));
+DECLARE_MIDFUNC(jff_MOVE_w(W4 d, RR2 s));
+DECLARE_MIDFUNC(jff_MOVE_l(W4 d, RR4 s));
+
+// MVMEL
+DECLARE_MIDFUNC(jnf_MVMEL_w(W4 d, RR4 s, IM8 offset));
+DECLARE_MIDFUNC(jnf_MVMEL_l(W4 d, RR4 s, IM8 offset));
+
+// MVMLE
+DECLARE_MIDFUNC(jnf_MVMLE_w(RR4 d, RR4 s, IM8 offset));
+DECLARE_MIDFUNC(jnf_MVMLE_l(RR4 d, RR4 s, IM8 offset));
+
+// MOVE16
+DECLARE_MIDFUNC(jnf_MOVE16(RR4 d, RR4 s));
+
+// MOVEA
+DECLARE_MIDFUNC(jnf_MOVEA_w_imm(W4 d, IM16 v));
+DECLARE_MIDFUNC(jnf_MOVEA_w(W4 d, RR2 s));
+DECLARE_MIDFUNC(jnf_MOVEA_l(W4 d, RR4 s));
+
+// MULS
+DECLARE_MIDFUNC (jnf_MULS(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jff_MULS(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jnf_MULS32(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jff_MULS32(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jnf_MULS64(RW4 d, RW4 s));
+DECLARE_MIDFUNC (jff_MULS64(RW4 d, RW4 s));
+
+// MULU
+DECLARE_MIDFUNC (jnf_MULU(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jff_MULU(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jnf_MULU32(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jff_MULU32(RW4 d, RR4 s));
+DECLARE_MIDFUNC (jnf_MULU64(RW4 d, RW4 s));
+DECLARE_MIDFUNC (jff_MULU64(RW4 d, RW4 s));
+
+// NEG
+DECLARE_MIDFUNC(jnf_NEG_b(RW1 d));
+DECLARE_MIDFUNC(jnf_NEG_w(RW2 d));
+DECLARE_MIDFUNC(jnf_NEG_l(RW4 d));
+DECLARE_MIDFUNC(jff_NEG_b(RW1 d));
+DECLARE_MIDFUNC(jff_NEG_w(RW2 d));
+DECLARE_MIDFUNC(jff_NEG_l(RW4 d));
+
+// NEGX
+DECLARE_MIDFUNC(jnf_NEGX_b(RW1 d));
+DECLARE_MIDFUNC(jnf_NEGX_w(RW2 d));
+DECLARE_MIDFUNC(jnf_NEGX_l(RW4 d));
+DECLARE_MIDFUNC(jff_NEGX_b(RW1 d));
+DECLARE_MIDFUNC(jff_NEGX_w(RW2 d));
+DECLARE_MIDFUNC(jff_NEGX_l(RW4 d));
+
+// NOT
+DECLARE_MIDFUNC(jnf_NOT_b(RW1 d));
+DECLARE_MIDFUNC(jnf_NOT_w(RW2 d));
+DECLARE_MIDFUNC(jnf_NOT_l(RW4 d));
+DECLARE_MIDFUNC(jff_NOT_b(RW1 d));
+DECLARE_MIDFUNC(jff_NOT_w(RW2 d));
+DECLARE_MIDFUNC(jff_NOT_l(RW4 d));
+
+// OR
+DECLARE_MIDFUNC(jnf_OR_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jnf_OR_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jnf_OR_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jnf_OR_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_OR_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_OR_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_OR_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jff_OR_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jff_OR_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jff_OR_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_OR_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_OR_l(RW4 d, RR4 s));
+
+// ORSR
+DECLARE_MIDFUNC(jff_ORSR(IM32 s, IM8 x));
+
+// ROL
+DECLARE_MIDFUNC(jnf_ROL_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jnf_ROL_w_imm(RW2 d, IM16 i));
+DECLARE_MIDFUNC(jnf_ROL_l_imm(RW4 d, IM32 i));
+DECLARE_MIDFUNC(jnf_ROL_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROL_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROL_l(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROL_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jff_ROL_w_imm(RW2 d, IM16 i));
+DECLARE_MIDFUNC(jff_ROL_l_imm(RW4 d, IM32 i));
+DECLARE_MIDFUNC(jff_ROL_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROL_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROL_l(RW4 d, RR4 i));
+
+// ROLW
+DECLARE_MIDFUNC(jff_ROLW(RW2 d));
+DECLARE_MIDFUNC(jnf_ROLW(RW2 d));
+
+// RORW
+DECLARE_MIDFUNC(jff_RORW(RW2 d));
+DECLARE_MIDFUNC(jnf_RORW(RW2 d));
+
+// ROXL
+DECLARE_MIDFUNC(jnf_ROXL_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROXL_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROXL_l(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROXL_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROXL_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROXL_l(RW4 d, RR4 i));
+
+// ROR
+DECLARE_MIDFUNC(jnf_ROR_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jnf_ROR_w_imm(RW2 d, IM16 i));
+DECLARE_MIDFUNC(jnf_ROR_l_imm(RW4 d, IM32 i));
+DECLARE_MIDFUNC(jnf_ROR_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROR_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROR_l(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROR_b_imm(RW1 d, IM8 i));
+DECLARE_MIDFUNC(jff_ROR_w_imm(RW2 d, IM16 i));
+DECLARE_MIDFUNC(jff_ROR_l_imm(RW4 d, IM32 i));
+DECLARE_MIDFUNC(jff_ROR_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROR_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROR_l(RW4 d, RR4 i));
+
+// ROXR
+DECLARE_MIDFUNC(jnf_ROXR_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROXR_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jnf_ROXR_l(RW4 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROXR_b(RW1 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROXR_w(RW2 d, RR4 i));
+DECLARE_MIDFUNC(jff_ROXR_l(RW4 d, RR4 i));
+
+// Scc
+DECLARE_MIDFUNC(jnf_SCC(W1 d, IM8 cc));
+
+// SUB
+DECLARE_MIDFUNC(jnf_SUB_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jnf_SUB_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jnf_SUB_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jnf_SUB_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_SUB_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_SUB_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_SUB_b_imm(RW1 d, IM8 v));
+DECLARE_MIDFUNC(jff_SUB_w_imm(RW2 d, IM16 v));
+DECLARE_MIDFUNC(jff_SUB_l_imm(RW4 d, IM32 v));
+DECLARE_MIDFUNC(jff_SUB_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_SUB_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_SUB_l(RW4 d, RR4 s));
+
+// SUBA
+DECLARE_MIDFUNC(jnf_SUBA_w(RW4 d, RR2 s));
+DECLARE_MIDFUNC(jnf_SUBA_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jnf_SUBA_w_imm(RW4 d, IM16 v));
+DECLARE_MIDFUNC(jnf_SUBA_l_imm(RW4 d, IM32 v));
+
+// SUBX
+DECLARE_MIDFUNC(jnf_SUBX_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jnf_SUBX_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jnf_SUBX_l(RW4 d, RR4 s));
+DECLARE_MIDFUNC(jff_SUBX_b(RW1 d, RR1 s));
+DECLARE_MIDFUNC(jff_SUBX_w(RW2 d, RR2 s));
+DECLARE_MIDFUNC(jff_SUBX_l(RW4 d, RR4 s));
+
+// SWAP
+DECLARE_MIDFUNC (jnf_SWAP(RW4 d));
+DECLARE_MIDFUNC (jff_SWAP(RW4 d));
+
+// TST
+DECLARE_MIDFUNC (jff_TST_b_imm(IM8 v));
+DECLARE_MIDFUNC (jff_TST_w_imm(IM16 v));
+DECLARE_MIDFUNC (jff_TST_l_imm(IM32 v));
+DECLARE_MIDFUNC (jff_TST_b(RR1 s));
+DECLARE_MIDFUNC (jff_TST_w(RR2 s));
+DECLARE_MIDFUNC (jff_TST_l(RR4 s));
+
+// Memory access functions
+DECLARE_MIDFUNC(jnf_MEM_WRITE_OFF_b(RR4 adr, RR4 b));
+DECLARE_MIDFUNC(jnf_MEM_WRITE_OFF_w(RR4 adr, RR4 w));
+DECLARE_MIDFUNC(jnf_MEM_WRITE_OFF_l(RR4 adr, RR4 l));
+DECLARE_MIDFUNC(jnf_MEM_WRITE24_OFF_b(RR4 adr, RR4 b));
+DECLARE_MIDFUNC(jnf_MEM_WRITE24_OFF_w(RR4 adr, RR4 w));
+DECLARE_MIDFUNC(jnf_MEM_WRITE24_OFF_l(RR4 adr, RR4 l));
+
+DECLARE_MIDFUNC(jnf_MEM_READ_OFF_b(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_READ_OFF_w(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_READ_OFF_l(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_READ24_OFF_b(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_READ24_OFF_w(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_READ24_OFF_l(W4 d, RR4 adr));
+
+DECLARE_MIDFUNC(jnf_MEM_GETADR_OFF(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_GETADR24_OFF(W4 d, RR4 adr));
+DECLARE_MIDFUNC(jnf_MEM_GETADR_JMP_OFF(W4 d, RR4 adr));
+
+DECLARE_MIDFUNC(jnf_MEM_READMEMBANK(W4 dest, RR4 adr, IM8 offset));
+DECLARE_MIDFUNC(jnf_MEM_WRITEMEMBANK(RR4 adr, RR4 source, IM8 offset));
diff --git a/jit/arm/compemu_midfunc_arm64.cpp b/jit/arm/compemu_midfunc_arm64.cpp
new file mode 100644
index 00000000..7126d473
--- /dev/null
+++ b/jit/arm/compemu_midfunc_arm64.cpp
@@ -0,0 +1,1238 @@
+/*
+ * compiler/compemu_midfunc_armA64.cpp - Native MIDFUNCS for AARCH64
+ *
+ * Copyright (c) 2019 TomB
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Note:
+ *  	File is included by compemu_support.cpp
+ *
+ */
+
+/********************************************************************
+ * CPU functions exposed to gencomp. Both CREATE and EMIT time      *
+ ********************************************************************/
+
+/*
+ *  RULES FOR HANDLING REGISTERS:
+ *
+ *  * In the function headers, order the parameters
+ *     - 1st registers written to
+ *     - 2nd read/modify/write registers
+ *     - 3rd registers read from
+ *  * Before calling raw_*, you must call readreg, writereg or rmw for
+ *    each register
+ *  * The order for this is
+ *     - 1nd call readreg for all registers read without offset
+ *     - 2rd call rmw for all rmw registers
+ *     - 3th call writereg for all written-to registers
+ *     - 4th call raw_*
+ *     - 5th unlock2 all registers that were locked
+ */
+
+#define INIT_REGS_b(d,s) 					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = rmw(d);											\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_RREGS_b(d,s) 				\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = readreg(d);									\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_REG_b(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = rmw(d);
+
+#define INIT_RREG_b(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = readreg(d);
+
+#define INIT_WREG_b(d) 						\
+	int targetIsReg = (d < 16); 		\
+	if(targetIsReg)									\
+		d = rmw(d); 									\
+	else														\
+		d = writereg(d);
+
+#define INIT_REGS_w(d,s) 					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = rmw(d);											\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_RREGS_w(d,s)					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = readreg(d);									\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_REG_w(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = rmw(d);
+
+#define INIT_RREG_w(d) 						\
+	int targetIsReg = (d < 16); 		\
+	d = readreg(d);
+
+#define INIT_WREG_w(d) 						\
+	int targetIsReg = (d < 16); 		\
+	if(targetIsReg)									\
+		d = rmw(d);										\
+	else														\
+		d = writereg(d);
+
+#define INIT_REGS_l(d,s) 					\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = rmw(d);											\
+	if(s_is_d)											\
+		s = d;
+
+#define INIT_RREGS_l(d,s) 				\
+	int targetIsReg = (d < 16); 		\
+	int s_is_d = (s == d);  				\
+	if(!s_is_d) 										\
+		s = readreg(s); 							\
+	d = readreg(d);									\
+	if(s_is_d)											\
+		s = d;
+
+#define EXIT_REGS(d,s)						\
+	unlock2(d);											\
+	if(!s_is_d)											\
+		unlock2(s);
+
+
+MIDFUNC(0,live_flags,(void))
+{
+	live.flags_on_stack = TRASH;
+	live.flags_in_flags = VALID;
+	live.flags_are_important = 1;
+}
+MENDFUNC(0,live_flags,(void))
+
+MIDFUNC(0,dont_care_flags,(void))
+{
+	live.flags_are_important = 0;
+}
+MENDFUNC(0,dont_care_flags,(void))
+
+MIDFUNC(0,make_flags_live,(void))
+{
+	make_flags_live_internal();
+}
+MENDFUNC(0,make_flags_live,(void))
+
+MIDFUNC(2,mov_l_mi,(IMPTR d, IMPTR s))
+{
+	/* d usually points to memory in regs struct, but can also be a global
+	   (e.g. regflags.nzcv). Use absolute address if out of LDR/STR range. */
+	if(d >= (uintptr)&regs && d < (uintptr)&regs + 32760) {
+		uintptr idx = d - (uintptr) &regs;
+		if(d == (uintptr) &(regs.pc_p) || d == (uintptr) &(regs.pc_oldp)) {
+			LOAD_U64(REG_WORK2, s);  // pc_p/pc_oldp are 64-bit host pointers
+			STR_xXi(REG_WORK2, R_REGSTRUCT, idx);
+		} else {
+			LOAD_U32(REG_WORK2, (uae_u32)s);
+			STR_wXi(REG_WORK2, R_REGSTRUCT, idx);
+		}
+	} else {
+		LOAD_U32(REG_WORK2, (uae_u32)s);
+		LOAD_U64(REG_WORK1, d);
+		STR_wXi(REG_WORK2, REG_WORK1, 0);
+	}
+}
+MENDFUNC(2,mov_l_mi,(IMPTR d, IMPTR s))
+
+MIDFUNC(4,disp_ea20_target_add,(RW4 target, RR4 reg, IM8 shift, IM8 extend))
+{
+	if(isconst(target) && isconst(reg)) {
+		if(extend)
+			set_const(target, live.state[target].val + (((uae_s32)(uae_s16)live.state[reg].val) << (shift & 0x1f)));
+		else
+			set_const(target, live.state[target].val + (live.state[reg].val << (shift & 0x1f)));
+		return;
+	}
+
+	reg = readreg(reg);
+	target = rmw(target);
+
+	if(extend) {
+		SIGNED16_REG_2_REG(REG_WORK1, reg);
+		ADD_wwwLSLi(target, target, REG_WORK1, shift & 0x1f);
+	} else {
+		ADD_wwwLSLi(target, target, reg, shift & 0x1f);
+	}
+
+	unlock2(target);
+	unlock2(reg);
+}
+MENDFUNC(4,disp_ea20_target_add,(RW4 target, RR4 reg, IM8 shift, IM8 extend))
+
+MIDFUNC(4,disp_ea20_target_mov,(W4 target, RR4 reg, IM8 shift, IM8 extend))
+{
+	if(isconst(reg)) {
+		if(extend)
+			set_const(target, ((uae_s32)(uae_s16)live.state[reg].val) << (shift & 0x1f));
+		else
+			set_const(target, live.state[reg].val << (shift & 0x1f));
+		return;
+	}
+
+	reg = readreg(reg);
+	target = writereg(target);
+
+	if(extend) {
+		SIGNED16_REG_2_REG(REG_WORK1, reg);
+		LSL_wwi(target, REG_WORK1, shift & 0x1f);
+	} else {
+		LSL_wwi(target, reg, shift & 0x1f);
+	}
+
+	unlock2(target);
+	unlock2(reg);
+}
+MENDFUNC(4,disp_ea20_target_mov,(W4 target, RR4 reg, IM8 shift, IM8 extend))
+
+MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
+{
+	// Only used in calc_disp_ea_020() -> flags not relevant and never modified
+	if (isconst(s)) {
+		set_const(d, (uae_s32)(uae_s16)live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if (!s_is_d) {
+		s = readreg(s);
+		d = writereg(d);
+	}	else {
+		s = d = rmw(s);
+	}
+	SIGNED16_REG_2_REG(d, s);
+	if (!s_is_d)
+		unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
+
+MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IM32 offset))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_l_ri)(d, live.state[s].val+offset);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if(s_is_d) {
+		s = d = rmw(d);
+	} else {
+		s = readreg(s);
+		d = writereg(d);
+	}
+
+	if(offset >= 0 && offset <= 0xfff) {
+		ADD_wwi(d, s, offset);
+	} else if(offset >= -0xfff && offset < 0) {
+		SUB_wwi(d, s, -offset);
+	} else {
+		LOAD_U32(REG_WORK1, offset);
+		ADD_www(d, s, REG_WORK1);
+	}
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IM32 offset))
+
+MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor, IM8 offset))
+{
+	if (!offset) {
+		COMPCALL(lea_l_rr_indexed)(d, s, index, factor);
+		return;
+	}
+	if (isconst(s) && isconst(index)) {
+		set_const(d, live.state[s].val + (uae_s32)(uae_s8)offset + live.state[index].val * factor);
+		return;
+	}
+
+	s = readreg(s);
+	if(d == index) {
+		d = index = rmw(d);
+	} else {
+		index = readreg(index);
+		d = writereg(d);
+	}
+
+	int shft;
+	switch(factor) {
+		case 1: shft=0; break;
+		case 2: shft=1; break;
+		case 4: shft=2; break;
+		case 8: shft=3; break;
+		default: abort();
+	}
+
+	if(offset >= 0 && offset <= 127) {
+		ADD_wwi(REG_WORK1, s, offset);
+	} else {
+		SUB_wwi(REG_WORK1, s, -offset);
+	}
+	ADD_wwwLSLi(d, REG_WORK1, index, shft);
+
+	unlock2(d);
+	if(d != index)
+		unlock2(index);
+	unlock2(s);
+}
+MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor, IM8 offset))
+
+MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor))
+{
+	if (isconst(s) && isconst(index)) {
+		set_const(d, live.state[s].val + live.state[index].val * factor);
+		return;
+	}
+
+	s = readreg(s);
+	if(d == index) {
+		d = index = rmw(d);
+	} else {
+		index = readreg(index);
+		d = writereg(d);
+	}
+
+	int shft;
+	switch(factor) {
+		case 1: shft=0; break;
+		case 2: shft=1; break;
+		case 4: shft=2; break;
+		case 8: shft=3; break;
+		default: abort();
+	}
+
+	ADD_wwwLSLi(d, s, index, shft);
+
+	unlock2(d);
+	if(d != index)
+		unlock2(index);
+	unlock2(s);
+}
+MENDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IM8 factor))
+
+MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
+{
+	int olds;
+
+	if (d == s) { /* How pointless! */
+		return;
+	}
+	if (isconst(s)) {
+		COMPCALL(mov_l_ri)(d, live.state[s].val);
+		return;
+	}
+	olds = s;
+	disassociate(d);
+	s = readreg(s);
+	live.state[d].realreg = s;
+	live.state[d].realind = live.nat[s].nholds;
+	live.state[d].val = 0;
+	set_status(d, DIRTY);
+
+	live.nat[s].holds[live.nat[s].nholds] = d;
+	live.nat[s].nholds++;
+	unlock2(s);
+}
+MENDFUNC(2,mov_l_rr,(W4 d, RR4 s))
+
+MIDFUNC(2,mov_l_mr,(IMPTR d, RR4 s))
+{
+	/* d usually points to memory in regs struct, but can also be a global
+	   (e.g. regflags.nzcv). Use absolute address if out of LDR/STR range. */
+	if (isconst(s)) {
+		COMPCALL(mov_l_mi)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+
+	if(d >= (uintptr)&regs && d < (uintptr)&regs + 32760) {
+		uintptr idx = d - (uintptr) &regs;
+		if(d == (uintptr)&regs.pc_oldp || d == (uintptr)&regs.pc_p)
+			STR_xXi(s, R_REGSTRUCT, idx);
+		else
+			STR_wXi(s, R_REGSTRUCT, idx);
+	} else {
+		LOAD_U64(REG_WORK1, d);
+		STR_wXi(s, REG_WORK1, 0);
+	}
+
+	unlock2(s);
+}
+MENDFUNC(2,mov_l_mr,(IMPTR d, RR4 s))
+
+MIDFUNC(2,mov_l_rm,(W4 d, IMPTR s))
+{
+	/* s usually points to memory in regs struct, but can also be a global
+	   (e.g. regflags.nzcv). Use absolute address if out of LDR/STR range. */
+	d = writereg(d);
+
+	if(s >= (uintptr)&regs && s < (uintptr)&regs + 32760) {
+		uintptr idx = s - (uintptr) &regs;
+		if (s == (uintptr)&regs.pc_p || s == (uintptr)&regs.pc_oldp)
+			LDR_xXi(d, R_REGSTRUCT, idx);
+		else
+			LDR_wXi(d, R_REGSTRUCT, idx);
+	} else {
+		LOAD_U64(REG_WORK1, s);
+		LDR_wXi(d, REG_WORK1, 0);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,mov_l_rm,(W4 d, IMPTR s))
+
+MIDFUNC(2,mov_l_ri,(W4 d, IMPTR s))
+{
+	set_const(d, s);
+}
+MENDFUNC(2,mov_l_ri,(W4 d, IMPTR s))
+
+MIDFUNC(2,mov_b_ri,(W1 d, IM8 s))
+{
+	if(d < 16) {
+		if (isconst(d)) {
+			set_const(d, (live.state[d].val & 0xffffff00) | (s & 0x000000ff));
+			return;
+		}
+		d = rmw(d);
+
+		MOV_wi(REG_WORK1, (s & 0xff));
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		unlock2(d);
+	} else {
+		set_const(d, s & 0xff);
+	}
+}
+MENDFUNC(2,mov_b_ri,(W1 d, IM8 s))
+
+MIDFUNC(2,sub_l_ri,(RW4 d, IM8 i))
+{
+	if (!i)
+		return;
+	if (isconst(d)) {
+		// Preserve full 64-bit if the current value already exceeds 32 bits
+		// (e.g. scratch register holding a host pointer for branch target).
+		if (live.state[d].val > (uintptr)0xFFFFFFFFULL)
+			live.state[d].val = live.state[d].val - i;
+		else
+			live.state[d].val = (uae_u32)(live.state[d].val - i);
+		return;
+	}
+
+	d = rmw(d);
+
+	SUB_wwi(d, d, i);
+
+	unlock2(d);
+}
+MENDFUNC(2,sub_l_ri,(RW4 d, IM8 i))
+
+MIDFUNC(2,sub_w_ri,(RW2 d, IM8 i))
+{
+	// This function is only called with i = 1
+	// Caller needs flags...
+	clobber_flags();
+
+	d = rmw(d);
+
+	LSL_wwi(REG_WORK2, d, 16);
+
+	SUBS_wwish(REG_WORK2, REG_WORK2, (i & 0xff) << 4, 1);
+	BFXIL_xxii(d, REG_WORK2, 16, 16);
+
+	unlock2(d);
+}
+MENDFUNC(2,sub_w_ri,(RW2 d, IM8 i))
+
+/* forget_about() takes a mid-layer register */
+MIDFUNC(1,forget_about,(W4 r))
+{
+	if (isinreg(r))
+		disassociate(r);
+	live.state[r].val = 0;
+	set_status(r, UNDEF);
+}
+MENDFUNC(1,forget_about,(W4 r))
+
+
+MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		uintptr val = live.state[s].val;
+		#ifdef CPU_AARCH64
+		// When adding a 32-bit M68K displacement to PC_P (a 64-bit host
+		// pointer), sign-extend the displacement first.  M68K branch
+		// offsets are signed, but stored as unsigned uintptr in
+		// live.state[].val.  Adding an unsigned 0xFFFFFE42 (i.e. -0x1BE)
+		// to a 64-bit pointer causes carry into bit 32, producing 0x4...
+		// instead of the correct 0x3...
+		if (d == PC_P && val <= (uintptr)0xFFFFFFFFULL)
+			val = (uintptr)(uae_s64)(uae_s32)val;
+#endif
+		COMPCALL(arm_ADD_l_ri)(d, val);
+		return;
+	}
+
+#ifdef CPU_AARCH64
+	bool is_pcp = (d == PC_P);
+#endif
+	s = readreg(s);
+	d = rmw(d);
+#ifdef CPU_AARCH64
+	if (is_pcp) {
+		/* PC_P holds a 64-bit host pointer. src is a signed 32-bit
+		   displacement in a W register.  Use ADD Xd, Xd, Ws, SXTW
+		   to sign-extend the 32-bit displacement to 64-bit before
+		   adding, preserving the upper bits of the host pointer. */
+		ADD_xxwEX(d, d, s, 6); // extend option 6 = SXTW
+	} else
+#endif
+	{
+		ADD_www(d, d, s);
+	}
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(arm_ADD_l_ri)(d,(live.state[s].val & ~0x1f) >> 3);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+	ASR_wwi(REG_WORK1, s, 5);
+	ADD_wwwLSLi(d, d, REG_WORK1, 2);
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,arm_ADD_ldiv8,(RW4 d, RR4 s))
+
+MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMPTR i))
+{
+	if (!i)
+		return;
+	if (isconst(d)) {
+		// Preserve full 64-bit result when d is PC_P, when i is a 64-bit
+		// host pointer, OR when val already exceeds 32 bits (e.g. scratch
+		// register that received comp_pc_p in a previous arm_ADD_l_ri).
+		if (d == PC_P || i > (IMPTR)0xFFFFFFFFULL || live.state[d].val > (uintptr)0xFFFFFFFFULL) {
+			uintptr val = live.state[d].val;
+			// When adding a 64-bit host pointer (i) to a 32-bit M68K value
+			// (val), sign-extend val first.  M68K branch displacements are
+			// signed, so a backward branch like -0x100 is stored as
+			// 0xFFFFFF00.  Without sign extension, adding 0xFFFFFF00 to a
+			// 64-bit pointer produces carry into bit 32 (0x4... instead of
+			// 0x3...).
+			if (val <= (uintptr)0xFFFFFFFFULL && i > (IMPTR)0xFFFFFFFFULL)
+				val = (uintptr)(uae_s64)(uae_s32)val;
+			live.state[d].val = val + i;
+		} else {
+			live.state[d].val = (uae_u32)(live.state[d].val + i);
+		}
+		return;
+	}
+
+	// Use 64-bit ADD when d is PC_P (always a host pointer) or when
+	// the immediate itself exceeds 32 bits (e.g. branch target scratch
+	// registers that hold natmem_offset + M68k_addr).
+	bool is_ptr = (d == PC_P) || (i > (IMPTR)0xFFFFFFFFULL);
+	bool is_pcp = (d == PC_P);
+	d = rmw(d);
+
+	if (is_ptr) {
+		// 64-bit ADD to preserve upper bits (e.g. 0x300000000 on macOS).
+		if (is_pcp) {
+			// PC_P already holds a 64-bit host pointer; just add.
+			if(i <= 0xfff) {
+				ADD_xxi(d, d, i);
+			} else {
+				LOAD_U64(REG_WORK1, (uintptr)i);
+				ADD_xxx(d, d, REG_WORK1);
+			}
+		} else {
+			// d is a scratch holding a 32-bit M68K displacement in Wd.
+			// Sign-extend Wd to Xd before adding the 64-bit pointer,
+			// because M68K branch displacements are signed.
+			LOAD_U64(REG_WORK1, (uintptr)i);
+			ADD_xxwEX(d, REG_WORK1, d, 6); // ADD Xd, Ximm, Wd, SXTW
+		}
+	} else {
+		// Use 32-bit ADD (ADD_www/ADD_wwi) to keep upper 32 bits of the X
+		// register zeroed.  The result may later be used as an Amiga memory
+		// address in [Xn, X27] indexed loads, which read the full 64-bit
+		// register.  64-bit ADD_xxx could leave upper bits set on wrap.
+		uae_u32 i32 = (uae_u32)i;
+		if(i32 <= 0xfff) {
+			ADD_wwi(d, d, i32);
+		} else {
+			LOAD_U32(REG_WORK1, i32);
+			ADD_www(d, d, REG_WORK1);
+		}
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,arm_ADD_l_ri,(RW4 d, IMPTR i))
+
+MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IM8 i))
+{
+	if (!i)
+		return;
+	if (isconst(d)) {
+		// Preserve full 64-bit if d is PC_P or already holds a 64-bit value
+		if (d == PC_P || live.state[d].val > (uintptr)0xFFFFFFFFULL)
+			live.state[d].val = live.state[d].val + i;
+		else
+			live.state[d].val = (uae_u32)(live.state[d].val + i);
+		return;
+	}
+
+	bool is_ptr = (d == PC_P);
+	d = rmw(d);
+	if (is_ptr)
+		ADD_xxi(d, d, i);  // 64-bit ADD for host pointer
+	else
+		ADD_wwi(d, d, i);  // 32-bit ADD for M68k values
+	unlock2(d);
+}
+MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IM8 i))
+
+MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IM8 i))
+{
+	if (!i)
+		return;
+	if (isconst(d)) {
+		// Preserve full 64-bit if d is PC_P or already holds a 64-bit value
+		if (d == PC_P || live.state[d].val > (uintptr)0xFFFFFFFFULL)
+			live.state[d].val = live.state[d].val - i;
+		else
+			live.state[d].val = (uae_u32)(live.state[d].val - i);
+		return;
+	}
+
+	bool is_ptr = (d == PC_P);
+	d = rmw(d);
+	if (is_ptr)
+		SUB_xxi(d, d, i);  // 64-bit SUB for host pointer
+	else
+		SUB_wwi(d, d, i);  // 32-bit SUB for M68k values
+	unlock2(d);
+}
+MENDFUNC(2,arm_SUB_l_ri8,(RW4 d, IM8 i))
+
+
+#ifdef JIT_DEBUG
+#include "aarch64.h"
+
+void disam_range(void *start, void *stop)
+{
+  char disbuf[256];
+  uint64_t disptr = (uint64_t)start;
+  while(disptr < (uint64_t)stop) {
+    disasm(disptr, disbuf);
+    write_log("%016llx  %s\n", disptr, disbuf);
+    disptr += 4;
+  }
+}
+
+#endif
+
+STATIC_INLINE void flush_cpu_icache(void *start, void *stop)
+{
+#ifdef JIT_DEBUG
+	if((uae_u64)stop - (uae_u64)start > 4) {
+    if(disasm_this) {
+      char disbuf[256];
+      uint64_t disptr = (uint64_t)start;
+      while(disptr < (uint64_t)stop) {
+        disasm(disptr, disbuf);
+        write_log("%016llx  %s\n", disptr, disbuf);
+        disptr += 4;
+      }
+      disasm_this = false;
+    }
+  }
+#endif
+
+#if defined(_WIN32) && defined(CPU_AARCH64)
+	FlushInstructionCache(GetCurrentProcess(), start, (SIZE_T)((char *)stop - (char *)start));
+#elif defined(__APPLE__) && defined(CPU_AARCH64)
+	sys_icache_invalidate(start, (char *)stop - (char *)start);
+#else
+	__builtin___clear_cache((char *)start, (char *)stop);
+#endif
+}
+
+
+STATIC_INLINE void write_jmp_target(uae_u32* jmpaddr, uintptr a)
+{
+	jit_begin_write_window();
+	uintptr off = (a - (uintptr)jmpaddr) >> 2;
+	if((*(jmpaddr) & 0xfc000000) == 0x14000000) {
+		/* branch always */
+		off = off & 0x3ffffff;
+		*(jmpaddr) = (*(jmpaddr) & 0xfc000000) | off;
+	} else if((*(jmpaddr) & 0x7c000000) == 0x34000000) {
+		/* TBZ/TBNZ/CBZ/CBNZ */
+		if((a > (uintptr)jmpaddr && off > 0x1fff) || (a < (uintptr)jmpaddr && (~off) > 0x1fff))
+			write_log("JIT: TBZ/TBNZ branch to target too long.\n");
+		off = off & 0x3fff;
+		*(jmpaddr) = (*(jmpaddr) & 0xfffc001f) | (off << 5);
+	} else {
+		/* conditional branch */
+		if((a > (uintptr)jmpaddr && off > 0x3ffff) || (a < (uintptr)jmpaddr && (~off) > 0x3ffff))
+			write_log("JIT: Branch to target too long.\n");
+		off = off & 0x7ffff;
+		*(jmpaddr) = (*(jmpaddr) & 0xff00001f) | (off << 5);
+	}
+
+	flush_cpu_icache((void *)jmpaddr, (void *)&jmpaddr[1]);
+	jit_end_write_window();
+}
+
+static inline void emit_jmp_target(uae_u32 a) {
+	emit_long(a - (JITPTR target + 4));
+}
+
+/*************************************************************************
+* FPU stuff                                                             *
+*************************************************************************/
+
+#ifdef USE_JIT_FPU
+
+MIDFUNC(1,f_forget_about,(FW r))
+{
+	if (f_isinreg(r))
+		f_disassociate(r);
+	live.fate[r].status = UNDEF;
+}
+MENDFUNC(1,f_forget_about,(FW r))
+
+MIDFUNC(0,dont_care_fflags,(void))
+{
+	f_disassociate(FP_RESULT);
+}
+MENDFUNC(0,dont_care_fflags,(void))
+
+MIDFUNC(2,fmov_rr,(FW d, FR s))
+{
+	if (d == s) { /* How pointless! */
+		return;
+	}
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fmov_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmov_rr,(FW d, FR s))
+
+MIDFUNC(2,fmov_l_rr,(FW d, RR4 s))
+{
+	s = readreg(s);
+	d = f_writereg(d);
+	raw_fmov_l_rr(d, s);
+	f_unlock(d);
+	unlock2(s);
+}
+MENDFUNC(2,fmov_l_rr,(FW d, RR4 s))
+
+MIDFUNC(2,fmov_s_rr,(FW d, RR4 s))
+{
+	s = readreg(s);
+	d = f_writereg(d);
+	raw_fmov_s_rr(d, s);
+	f_unlock(d);
+	unlock2(s);
+}
+MENDFUNC(2,fmov_s_rr,(FW d, RR4 s))
+
+MIDFUNC(2,fmov_w_rr,(FW d, RR2 s))
+{
+	s = readreg(s);
+	d = f_writereg(d);
+	raw_fmov_w_rr(d, s);
+	f_unlock(d);
+	unlock2(s);
+}
+MENDFUNC(2,fmov_w_rr,(FW d, RR2 s))
+
+MIDFUNC(2,fmov_b_rr,(FW d, RR1 s))
+{
+	s = readreg(s);
+	d = f_writereg(d);
+	raw_fmov_b_rr(d, s);
+	f_unlock(d);
+	unlock2(s);
+}
+MENDFUNC(2,fmov_b_rr,(FW d, RR1 s))
+
+MIDFUNC(3,fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+{
+	s1 = readreg(s1);
+	s2 = readreg(s2);
+	d = f_writereg(d);
+	raw_fmov_d_rrr(d, s1, s2);
+	f_unlock(d);
+	unlock2(s2);
+	unlock2(s1);
+}
+MENDFUNC(3,fmov_d_rrr,(FW d, RR4 s1, RR4 s2))
+
+MIDFUNC(2,fmov_l_ri,(FW d, IM32 i))
+{
+	switch(i) {
+		case 0:
+			fmov_d_ri_0(d);
+			break;
+		case 1:
+			fmov_d_ri_1(d);
+			break;
+		case 10:
+			fmov_d_ri_10(d);
+			break;
+		case 100:
+			fmov_d_ri_100(d);
+			break;
+		default:
+			d = f_writereg(d);
+			compemu_raw_mov_l_ri(REG_WORK1, i);
+			raw_fmov_l_rr(d, REG_WORK1);
+			f_unlock(d);
+	}
+}
+MENDFUNC(2,fmov_l_ri,(FW d, IM32 i))
+
+MIDFUNC(2,fmov_s_ri,(FW d, IM32 i))
+{
+	d = f_writereg(d);
+	compemu_raw_mov_l_ri(REG_WORK1, i);
+	raw_fmov_s_rr(d, REG_WORK1);
+	f_unlock(d);
+}
+MENDFUNC(2,fmov_s_ri,(FW d, IM32 i))
+
+MIDFUNC(2,fmov_to_l_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+	d = writereg(d);
+	raw_fmov_to_l_rr(d, s);
+	unlock2(d);
+	f_unlock(s);
+}
+MENDFUNC(2,fmov_to_l_rr,(W4 d, FR s))
+
+MIDFUNC(2,fmov_to_s_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+	d = writereg(d);
+	raw_fmov_to_s_rr(d, s);
+	unlock2(d);
+	f_unlock(s);
+}
+MENDFUNC(2,fmov_to_s_rr,(W4 d, FR s))
+
+MIDFUNC(2,fmov_to_w_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+	INIT_WREG_w(d);
+
+	raw_fmov_to_w_rr(d, s, targetIsReg);
+	unlock2(d);
+	f_unlock(s);
+}
+MENDFUNC(2,fmov_to_w_rr,(W4 d, FR s))
+
+MIDFUNC(2,fmov_to_b_rr,(W4 d, FR s))
+{
+	s = f_readreg(s);
+	INIT_WREG_b(d);
+
+	raw_fmov_to_b_rr(d, s, targetIsReg);
+	unlock2(d);
+	f_unlock(s);
+}
+MENDFUNC(2,fmov_to_b_rr,(W4 d, FR s))
+
+MIDFUNC(1,fmov_d_ri_0,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_0(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_0,(FW r))
+
+MIDFUNC(1,fmov_d_ri_1,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_1(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_1,(FW r))
+
+MIDFUNC(1,fmov_d_ri_10,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_10(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_10,(FW r))
+
+MIDFUNC(1,fmov_d_ri_100,(FW r))
+{
+	r = f_writereg(r);
+	raw_fmov_d_ri_100(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_d_ri_100,(FW r))
+
+MIDFUNC(2,fmov_d_rm,(FW r, MEMR m))
+{
+	r = f_writereg(r);
+	raw_fmov_d_rm(r, m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_d_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmovs_rm,(FW r, MEMR m))
+{
+	r = f_writereg(r);
+	raw_fmovs_rm(r, m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmovs_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmov_rm,(FW r, MEMR m))
+{
+	r = f_writereg(r);
+	raw_fmov_d_rm(r, m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_rm,(FW r, MEMR m))
+
+MIDFUNC(3,fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+{
+	s = f_readreg(s);
+	d1 = writereg(d1);
+	d2 = writereg(d2);
+	raw_fmov_to_d_rrr(d1, d2, s);
+	unlock2(d2);
+	unlock2(d1);
+	f_unlock(s);
+}
+MENDFUNC(3,fmov_to_d_rrr,(W4 d1, W4 d2, FR s))
+
+MIDFUNC(2,fsqrt_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fsqrt_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsqrt_rr,(FW d, FR s))
+
+MIDFUNC(2,fabs_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fabs_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fabs_rr,(FW d, FR s))
+
+MIDFUNC(2,fneg_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fneg_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fneg_rr,(FW d, FR s))
+
+MIDFUNC(2,fdiv_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fdiv_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fdiv_rr,(FRW d, FR s))
+
+MIDFUNC(2,fadd_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fadd_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fadd_rr,(FRW d, FR s))
+
+MIDFUNC(2,fmul_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fmul_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmul_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsub_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fsub_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsub_rr,(FRW d, FR s))
+
+MIDFUNC(2,frndint_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_frndint_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frndint_rr,(FW d, FR s))
+
+MIDFUNC(2,frndintz_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_frndintz_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frndintz_rr,(FW d, FR s))
+
+MIDFUNC(2,fmod_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fmod_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmod_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsgldiv_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fsgldiv_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsgldiv_rr,(FRW d, FR s))
+
+MIDFUNC(1,fcuts_r,(FRW r))
+{
+	r = f_rmw(r);
+	raw_fcuts_r(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fcuts_r,(FRW r))
+
+MIDFUNC(2,frem1_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_frem1_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frem1_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsglmul_rr,(FRW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_rmw(d);
+	raw_fsglmul_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsglmul_rr,(FRW d, FR s))
+
+MIDFUNC(2,fmovs_rr,(FW d, FR s))
+{
+	s = f_readreg(s);
+	d = f_writereg(d);
+	raw_fmovs_rr(d, s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmovs_rr,(FW d, FR s))
+
+MIDFUNC(3,ffunc_rr,(double (*func)(double), FW d, FR s))
+{
+	clobber_flags();
+
+	s = f_readreg(s);
+	int reald = f_writereg(d);
+
+	prepare_for_call_1();
+
+	f_unlock(s);
+	f_unlock(reald);
+
+	prepare_for_call_2();
+
+	raw_ffunc_rr(func, reald, s);
+
+	live.fat[reald].holds = d;
+	live.fat[reald].nholds = 1;
+
+	live.fate[d].realreg = reald;
+	live.fate[d].status = DIRTY;
+}
+MENDFUNC(3,ffunc_rr,(double (*func)(double), FW d, FR s))
+
+MIDFUNC(3,fpowx_rr,(uae_u32 x, FW d, FR s))
+{
+	clobber_flags();
+
+	s = f_readreg(s);
+	int reald = f_writereg(d);
+
+	prepare_for_call_1();
+
+	f_unlock(s);
+	f_unlock(reald);
+
+	prepare_for_call_2();
+
+	raw_fpowx_rr(x, reald, s);
+
+	live.fat[reald].holds = d;
+	live.fat[reald].nholds = 1;
+
+	live.fate[d].realreg = reald;
+	live.fate[d].status = DIRTY;
+}
+MENDFUNC(3,fpowx_rr,(uae_u32 x, FW d, FR s))
+
+MIDFUNC(1,fflags_into_flags,())
+{
+	clobber_flags();
+	fflags_into_flags_internal();
+}
+MENDFUNC(1,fflags_into_flags,())
+
+MIDFUNC(2,fp_from_exten_mr,(RR4 adr, FR s))
+{
+	clobber_flags();
+
+	adr = readreg(adr);
+	s = f_readreg(s);
+	raw_fp_from_exten_mr(adr, s);
+	f_unlock(s);
+	unlock2(adr);
+}
+MENDFUNC(2,fp_from_exten_mr,(RR4 adr, FR s))
+
+MIDFUNC(2,fp_to_exten_rm,(FW d, RR4 adr))
+{
+	clobber_flags();
+
+	adr = readreg(adr);
+	d = f_writereg(d);
+	raw_fp_to_exten_rm(d, adr);
+	unlock2(adr);
+	f_unlock(d);
+}
+MENDFUNC(2,fp_to_exten_rm,(FW d, RR4 adr))
+
+MIDFUNC(2,fp_from_double_mr,(RR4 adr, FR s))
+{
+	adr = readreg(adr);
+	s = f_readreg(s);
+	raw_fp_from_double_mr(adr, s);
+	f_unlock(s);
+	unlock2(adr);
+}
+MENDFUNC(2,fp_from_double_mr,(RR4 adr, FR s))
+
+MIDFUNC(2,fp_to_double_rm,(FW d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = f_writereg(d);
+	raw_fp_to_double_rm(d, adr);
+	unlock2(adr);
+	f_unlock(d);
+}
+MENDFUNC(2,fp_to_double_rm,(FW d, RR4 adr))
+
+MIDFUNC(2,fp_fscc_ri,(RW4 d, int cc))
+{
+	d = rmw(d);
+	raw_fp_fscc_ri(d, cc);
+	// Fix 20: raw_fp_fscc_ri uses CLEAR_LOW8_xx, SET_LOW8_xx, and BFXIL_xxii
+	// which are all 64-bit ops that preserve dirty upper 32 bits.
+	MOV_ww(d, d);
+	unlock2(d);
+}
+MENDFUNC(2,fp_fscc_ri,(RW4 d, int cc))
+
+
+#endif // USE_JIT_FPU
diff --git a/jit/arm/compemu_midfunc_arm64_2.cpp b/jit/arm/compemu_midfunc_arm64_2.cpp
new file mode 100644
index 00000000..421d9dde
--- /dev/null
+++ b/jit/arm/compemu_midfunc_arm64_2.cpp
@@ -0,0 +1,8027 @@
+/*
+ * compiler/compemu_midfunc_arm.cpp - Native MIDFUNCS for AARCH64 (JIT v2)
+ *
+ * Copyright (c) 2019 TomB
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Note:
+ *  	File is included by compemu_support.cpp
+ *
+ */
+
+const uae_u32 ARM_CCR_MAP[] = { 0, ARM_C_FLAG, // 1 C
+                                ARM_V_FLAG, // 2 V
+                                ARM_C_FLAG | ARM_V_FLAG, // 3 VC
+                                ARM_Z_FLAG, // 4 Z
+                                ARM_Z_FLAG | ARM_C_FLAG, // 5 ZC
+                                ARM_Z_FLAG | ARM_V_FLAG, // 6 ZV
+                                ARM_Z_FLAG | ARM_C_FLAG | ARM_V_FLAG, // 7 ZVC
+                                ARM_N_FLAG, // 8 N
+                                ARM_N_FLAG | ARM_C_FLAG, // 9 NC
+                                ARM_N_FLAG | ARM_V_FLAG, // 10 NV
+                                ARM_N_FLAG | ARM_C_FLAG | ARM_V_FLAG, // 11 NVC
+                                ARM_N_FLAG | ARM_Z_FLAG, // 12 NZ
+                                ARM_N_FLAG | ARM_Z_FLAG | ARM_C_FLAG, // 13 NZC
+                                ARM_N_FLAG | ARM_Z_FLAG | ARM_V_FLAG, // 14 NZV
+                                ARM_N_FLAG | ARM_Z_FLAG | ARM_C_FLAG | ARM_V_FLAG, // 15 NZVC
+};
+
+
+#define DUPLICACTE_CARRY            \
+  if (needed_flags & FLAG_X) {      \
+    int x = writereg(FLAGX);     		\
+    if (flags_carry_inverted)       \
+      CSET_xc(x, NATIVE_CC_CC);     \
+    else                            \
+      CSET_xc(x, NATIVE_CC_CS);     \
+    unlock2(x);                     \
+  }
+
+/*
+ * ADD
+ * Operand Syntax: 	<ea>, Dn
+ * 					Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ */
+MIDFUNC(3,jnf_ADD_im8,(W4 d, RR4 s, IM8 v))
+{
+	int s_is_d = (s == d);
+	if(s_is_d) {
+		s = d = rmw(d);
+	} else {
+		s = readreg(s);
+		d = writereg(d);
+	}
+
+	ADD_wwi(d, s, v & 0xff);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(3,jnf_ADD_im8,(W4 d, RR4 s, IM8 v))
+
+MIDFUNC(2,jnf_ADD_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val + v) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+		ADD_wwi(REG_WORK1, d, v & 0xff);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ADD_wwi(d, d, v & 0xff);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADD_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_ADD_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADD_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		ADD_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ADD_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADD_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_ADD_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	if(targetIsReg) {
+		if(v >= 0 && v <= 0xfff) {
+			ADD_wwi(REG_WORK1, d, v);
+		} else {
+			MOV_xi(REG_WORK1, v & 0xffff);
+			ADD_www(REG_WORK1, d, REG_WORK1);
+		}
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else{
+		if(v >= 0 && v <= 0xfff) {
+			ADD_wwi(d, d, v);
+		} else {
+			MOV_xi(REG_WORK1, v & 0xffff);
+			ADD_www(d, d, REG_WORK1);
+		}
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADD_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_ADD_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADD_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		ADD_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		ADD_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADD_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_ADD_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val + v;
+		return;
+	}
+
+	d = rmw(d);
+
+	if(v >= 0 && v <= 0xfff) {
+		ADD_wwi(d, d, v);
+	} else {
+		// never reached...
+		LOAD_U32(REG_WORK1, v);
+		ADD_www(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADD_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_ADD_l,(RW4 d, RR4 s))
+{
+	if (isconst(d) && isconst(s)) {
+		COMPCALL(jnf_ADD_l_imm)(d, live.state[s].val);
+		return;
+	}
+	if (isconst(s) && (uae_s32)live.state[s].val >= 0 && (uae_s32)live.state[s].val <= 0xfff) {
+		COMPCALL(jnf_ADD_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ADD_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADD_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_ADD_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	MOV_xish(REG_WORK2, (v & 0xff) << 8, 16);
+	ADDS_wwwLSLi(REG_WORK1, REG_WORK2, d, 24);
+	BFXIL_xxii(d, REG_WORK1, 24, 8);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ADD_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_ADD_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_ADD_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	LSL_wwi(REG_WORK2, s, 24);
+	ADDS_wwwLSLi(REG_WORK1, REG_WORK2, d, 24);
+	BFXIL_xxii(d, REG_WORK1, 24, 8);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADD_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_ADD_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	MOV_xish(REG_WORK1, v & 0xffff, 16);
+	ADDS_wwwLSLi(REG_WORK1, REG_WORK1, d, 16);
+	BFXIL_xxii(d, REG_WORK1, 16, 16);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ADD_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_ADD_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_ADD_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	LSL_wwi(REG_WORK1, s, 16);
+	ADDS_wwwLSLi(REG_WORK1, REG_WORK1, d, 16);
+	BFXIL_xxii(d, REG_WORK1, 16, 16);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADD_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_ADD_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	if(v >= 0 && v <= 0xfff) {
+		ADDS_wwi(d, d, v);
+	} else {
+		// never reached...
+		LOAD_U32(REG_WORK2, v);
+		ADDS_www(d, d, REG_WORK2);
+	}
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ADD_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_ADD_l,(RW4 d, RR4 s))
+{
+	if (isconst(s) && (uae_s32)live.state[s].val >= 0 && (uae_s32)live.state[s].val <= 0xfff) {
+		COMPCALL(jff_ADD_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ADDS_www(d, d, s);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADD_l,(RW4 d, RR4 s))
+
+/*
+ * ADDA
+ * Operand Syntax: 	<ea>, An
+ *
+ * Operand Size: 16,32
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_ADDA_w_imm,(RW4 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val + (uae_s32)(uae_s16)v;
+		return;
+	}
+
+	uae_s16 tmp = (uae_s16)v;
+	d = rmw(d);
+	if(tmp >= 0 && tmp <= 0xfff) {
+		ADD_wwi(d, d, tmp);
+	} else if (tmp >= -0xfff && tmp < 0) {
+		SUB_wwi(d, d, -tmp);
+	} else {
+		SIGNED16_IMM_2_REG(REG_WORK1, tmp);
+		ADD_www(d, d, REG_WORK1);
+	}
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADDA_w_imm,(RW4 d, IM16 v))
+
+MIDFUNC(2,jnf_ADDA_w,(RW4 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADDA_w_imm)(d, live.state[s].val & 0xffff);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	ADD_wwwEX(d, d, s, EX_SXTH);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADDA_w,(RW4 d, RR2 s))
+
+MIDFUNC(2,jnf_ADDA_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		set_const(d, live.state[d].val + v);
+		return;
+	}
+
+	d = rmw(d);
+
+	if(v >= 0 && v <= 0xfff) {
+		ADD_wwi(d, d, v);
+	} else if (v >= -0xfff && v < 0) {
+		SUB_wwi(d, d, -v);
+	} else {
+		LOAD_U32(REG_WORK1, v);
+		ADD_www(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_ADDA_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_ADDA_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_ADDA_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ADD_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_ADDA_l,(RW4 d, RR4 s))
+
+/*
+ * ADDX
+ * Operand Syntax: 	Dy, Dx
+ * 					-(Ay), -(Ax)
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Cleared if the result is nonzero; unchanged otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ * Attention: Z is cleared only if the result is nonzero. Unchanged otherwise
+ *
+ */
+MIDFUNC(2,jnf_ADDX_b,(RW1 d, RR1 s))
+{
+	int x = readreg(FLAGX);
+
+	INIT_REGS_b(d, s);
+
+	if(s_is_d) {
+		ADD_wwwLSLi(REG_WORK1, x, d, 1);
+	} else {
+		ADD_www(REG_WORK1, d, s);
+		ADD_www(REG_WORK1, REG_WORK1, x);
+	}
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_ADDX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_ADDX_w,(RW2 d, RR2 s))
+{
+	int x = readreg(FLAGX);
+
+	INIT_REGS_w(d, s);
+
+	if(s_is_d) {
+		ADD_wwwLSLi(REG_WORK1, x, d, 1);
+	} else {
+		ADD_www(REG_WORK1, d, s);
+		ADD_www(REG_WORK1, REG_WORK1, x);
+	}
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_ADDX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_ADDX_l,(RW4 d, RR4 s))
+{
+	int x = readreg(FLAGX);
+
+	if(s != d && isconst(s) && live.state[s].val >= 0 && live.state[s].val <= 0xfff) {
+		d = rmw(d);
+		ADD_wwi(d, d, live.state[s].val);
+		ADD_www(d, d, x);
+		unlock2(d);
+		unlock2(x);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	if(s_is_d) {
+		ADD_wwwLSLi(d, x, d, 1);
+	} else {
+		ADD_www(d, d, s);
+		ADD_www(d, d, x);
+	}
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_ADDX_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_ADDX_b,(RW1 d, RR1 s))
+{
+	INIT_REGS_b(d, s);
+	int x = rmw(FLAGX);
+
+	// REG_WORK1 must be all-ones: bits 0-23 are padding for the byte BFI+ADCS
+	// carry chain, and also serves as the all-ones value for sticky-Z CSEL.
+	MOVN_xi(REG_WORK1, 0);
+	if (needed_flags & FLAG_Z) {
+		MOVN_xish(REG_WORK2, 0x4000, 16); // inverse Z flag
+		CSEL_xxxc(REG_WORK2, REG_WORK2, REG_WORK1, NATIVE_CC_NE);
+	}
+
+	// Restore X to carry (don't care about other flags)
+	SUBS_wwi(REG_WORK3, x, 1);
+
+	BFI_xxii(REG_WORK1, s, 24, 8);
+	LSL_wwi(REG_WORK3, d, 24);
+	ADCS_www(REG_WORK1, REG_WORK1, REG_WORK3);
+	BFXIL_xxii(d, REG_WORK1, 24, 8);
+
+	MRS_NZCV_x(REG_WORK1);
+
+	if (needed_flags & FLAG_Z) {
+		// Fix Z flag: ADCS Z is always 0 due to all-ones padding in lower bits.
+		UBFX_wwii(REG_WORK3, d, 0, 8);
+		CMP_wi(REG_WORK3, 0);
+		SET_xxZflag(REG_WORK3, REG_WORK1);
+		CSEL_xxxc(REG_WORK1, REG_WORK3, REG_WORK1, NATIVE_CC_EQ);
+		AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2); // apply ADDX sticky-Z
+	}
+	if (needed_flags & FLAG_X)
+		UBFX_xxii(x, REG_WORK1, 29, 1); // Duplicate carry
+	MSR_NZCV_x(REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADDX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_ADDX_w,(RW2 d, RR2 s))
+{
+	INIT_REGS_w(d, s);
+	int x = rmw(FLAGX);
+
+	// REG_WORK1 must be all-ones: bits 0-15 are padding for the word BFI+ADCS
+	// carry chain, and also serves as the all-ones value for sticky-Z CSEL.
+	MOVN_xi(REG_WORK1, 0);
+	if (needed_flags & FLAG_Z) {
+		MOVN_xish(REG_WORK2, 0x4000, 16); // inverse Z flag
+		CSEL_xxxc(REG_WORK2, REG_WORK2, REG_WORK1, NATIVE_CC_NE);
+	}
+
+	// Restore X to carry (don't care about other flags)
+	SUBS_wwi(REG_WORK3, x, 1);
+
+	BFI_xxii(REG_WORK1, s, 16, 16);
+	LSL_wwi(REG_WORK3, d, 16);
+	ADCS_www(REG_WORK1, REG_WORK1, REG_WORK3);
+	BFXIL_xxii(d, REG_WORK1, 16, 16);
+
+	MRS_NZCV_x(REG_WORK1);
+
+	if (needed_flags & FLAG_Z) {
+		// Fix Z flag: ADCS Z is always 0 due to all-ones padding in lower bits.
+		UBFX_wwii(REG_WORK3, d, 0, 16);
+		CMP_wi(REG_WORK3, 0);
+		SET_xxZflag(REG_WORK3, REG_WORK1);
+		CSEL_xxxc(REG_WORK1, REG_WORK3, REG_WORK1, NATIVE_CC_EQ);
+		AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2); // apply ADDX sticky-Z
+	}
+	if (needed_flags & FLAG_X)
+		UBFX_xxii(x, REG_WORK1, 29, 1); // Duplicate carry
+	MSR_NZCV_x(REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADDX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_ADDX_l,(W4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+	int x = rmw(FLAGX);
+
+	if (needed_flags & FLAG_Z) {
+		MOVN_xi(REG_WORK1, 0);
+		MOVN_xish(REG_WORK2, 0x4000, 16); // inverse Z flag
+		CSEL_xxxc(REG_WORK2, REG_WORK2, REG_WORK1, NATIVE_CC_NE);
+	}
+
+	// Restore X to carry (don't care about other flags)
+	SUBS_wwi(REG_WORK3, x, 1);
+
+	ADCS_www(d, d, s);
+
+	MRS_NZCV_x(REG_WORK1);
+	if (needed_flags & FLAG_Z)
+		AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+	if (needed_flags & FLAG_X)
+		UBFX_xxii(x, REG_WORK1, 29, 1); // Duplicate carry
+	MSR_NZCV_x(REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_ADDX_l,(W4 d, RR4 s))
+
+/*
+ * ANDSR
+ * Operand Syntax: 	#<data>, CCR
+ *
+ * Operand Size: 8
+ *
+ * X Cleared if bit 4 of immediate operand is zero. Unchanged otherwise.
+ * N Cleared if bit 3 of immediate operand is zero. Unchanged otherwise.
+ * Z Cleared if bit 2 of immediate operand is zero. Unchanged otherwise.
+ * V Cleared if bit 1 of immediate operand is zero. Unchanged otherwise.
+ * C Cleared if bit 0 of immediate operand is zero. Unchanged otherwise.
+ *
+ */
+MIDFUNC(2,jff_ANDSR,(IM32 s, IM8 x))
+{
+	MRS_NZCV_x(REG_WORK1);
+	if(flags_carry_inverted) {
+		EOR_xxCflag(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+	MOV_xish(REG_WORK2, (s >> 16), 16);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_NZCV_x(REG_WORK1);
+
+	if (!x) {
+		int f = writereg(FLAGX);
+		// Use 32-bit MOV for consistency (MOV_xi with 0 is safe, but MOV_wi is preferred).
+		MOV_wi(f, 0);
+		unlock2(f);
+	}
+}
+MENDFUNC(2,jff_ANDSR,(IM32 s, IM8 x))
+
+/*
+ * AND
+ * Operand Syntax: 	<ea>, Dn
+ * 					Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_AND_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val & v) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	MOVN_xi(REG_WORK1, (~v) & 0xff);
+	AND_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_AND_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_AND_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_AND_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		AND_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		AND_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_AND_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_AND_w_imm,(RW2 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val & v) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	MOVN_xi(REG_WORK1, (~v));
+	AND_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_AND_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_AND_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_AND_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		AND_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		AND_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_AND_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_AND_l_imm,(RW4 d, IM32 v))
+{
+	if(isconst(d)) {
+		live.state[d].val = live.state[d].val & v;
+		return;
+	}
+
+	d = rmw(d);
+
+	LOAD_U32(REG_WORK1, v);
+	AND_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_AND_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_AND_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_AND_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	AND_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_AND_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_AND_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_IMM_2_REG(REG_WORK2, v);
+	if(targetIsReg) {
+		ANDS_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ANDS_www(d, REG_WORK1, REG_WORK2);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_AND_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_AND_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_AND_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_REG_2_REG(REG_WORK2, s);
+	if(targetIsReg) {
+		ANDS_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ANDS_www(d, REG_WORK1, REG_WORK2);
+	}
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_AND_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_AND_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_IMM_2_REG(REG_WORK2, v);
+	if(targetIsReg) {
+		ANDS_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		ANDS_www(d, REG_WORK1, REG_WORK2);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_AND_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_AND_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_AND_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_REG_2_REG(REG_WORK2, s);
+	if(targetIsReg) {
+		ANDS_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		ANDS_www(d, REG_WORK1, REG_WORK2);
+	}
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_AND_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_AND_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	LOAD_U32(REG_WORK1, v);
+	ANDS_www(d, d, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_AND_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_AND_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_AND_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ANDS_www(d, d, s);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_AND_l,(RW4 d, RR4 s))
+
+/*
+ * ASL
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ * imm version only called with 1 <= i <= 8
+ *
+ */
+MIDFUNC(2,jff_ASL_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_wwi(REG_WORK3, d, 24);
+	if (i) {
+		LSL_xxi(REG_WORK2, REG_WORK3, i);
+		BFXIL_xxii(d, REG_WORK2, 24, 8);  // result is ready
+		TST_ww(REG_WORK2, REG_WORK2);     // NZ correct, VC cleared
+
+		if (needed_flags & FLAG_V) {
+			// Calculate C Flag
+			MRS_NZCV_x(REG_WORK4);
+			TBZ_xii(REG_WORK2, 32, 2);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+
+			// Calculate V Flag
+			CLS_ww(REG_WORK1, REG_WORK3);
+			CMP_wi(REG_WORK1, i);
+			BGE_i(2);
+			SET_xxVflag(REG_WORK4, REG_WORK4);
+
+			MSR_NZCV_x(REG_WORK4);
+		} else {
+			// Calculate C Flag
+			TBZ_xii(REG_WORK2, 32, 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_ww(REG_WORK3, REG_WORK3);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ASL_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_wwi(REG_WORK3, d, 16);
+	if (i) {
+		LSL_xxi(REG_WORK2, REG_WORK3, i);
+		BFXIL_xxii(d, REG_WORK2, 16, 16); // result is ready
+		TST_ww(REG_WORK2, REG_WORK2);     // NZ correct, VC cleared
+
+		if (needed_flags & FLAG_V) {
+			// Calculate C Flag
+			MRS_NZCV_x(REG_WORK4);
+			TBZ_xii(REG_WORK2, 32, 2);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+
+			// Calculate V Flag
+			CLS_ww(REG_WORK1, REG_WORK3);
+			CMP_wi(REG_WORK1, i);
+			BGE_i(2);
+			SET_xxVflag(REG_WORK4, REG_WORK4);
+
+			MSR_NZCV_x(REG_WORK4);
+		} else {
+			// Calculate C Flag
+			TBZ_xii(REG_WORK2, 32, 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_ww(REG_WORK3, REG_WORK3);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ASL_l_imm,(RW4 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	if (i) {
+		if (needed_flags & FLAG_V)
+			MOV_ww(REG_WORK3, d);
+		LSL_xxi(d, d, i);
+		TST_ww(d, d);               // NZ correct, VC cleared
+
+		if (needed_flags & FLAG_V) {
+			// Calculate C Flag
+			MRS_NZCV_x(REG_WORK4);
+			TBZ_xii(d, 32, 2);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+
+			// Calculate V Flag
+			CLS_ww(REG_WORK1, REG_WORK3);
+			CMP_wi(REG_WORK1, i);
+			BGE_i(2);
+			SET_xxVflag(REG_WORK4, REG_WORK4);
+
+			MSR_NZCV_x(REG_WORK4);
+		} else {
+			// Calculate C Flag
+			TBZ_xii(d, 32, 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+
+		// Clean upper 32 bits of d after 64-bit LSL_xxi used for carry extraction
+		MOV_ww(d, d);
+	} else {
+		TST_ww(d, d);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_ASL_b_reg,(RW1 d, RR4 i))
+{
+	i = readreg(i);
+	d = rmw(d);
+	int x = writereg(FLAGX);
+
+	LSL_wwi(REG_WORK3, d, 24);
+	ANDS_ww3f(REG_WORK1, i);
+	BNE_i(3);
+
+	// shift count is 0
+	TST_ww(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	// shift count > 0
+	LSL_xxx(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFXIL_xxii(d, REG_WORK2, 24, 8);  // result is ready
+	TST_ww(REG_WORK2, REG_WORK2);     // NZ correct, VC cleared
+
+	if (needed_flags & FLAG_V) {
+		// Calculate C Flag
+		MRS_NZCV_x(REG_WORK4);
+		TBZ_xii(REG_WORK2, 32, 2);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+
+		// Calculate V Flag
+		CLS_ww(REG_WORK2, REG_WORK3);
+		CMP_ww(REG_WORK2, REG_WORK1);
+		BGE_i(2);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		// Calculate C Flag
+		TBZ_xii(REG_WORK2, 32, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASL_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ASL_w_reg,(RW2 d, RR4 i))
+{
+	if(isconst(i)) {
+		COMPCALL(jff_ASL_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+	int x = writereg(FLAGX);
+
+	LSL_wwi(REG_WORK3, d, 16);
+	ANDS_ww3f(REG_WORK1, i);
+	BNE_i(3);
+
+	// shift count is 0
+	TST_ww(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	// shift count > 0
+	LSL_xxx(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFXIL_xxii(d, REG_WORK2, 16, 16); // result is ready
+	TST_ww(REG_WORK2, REG_WORK2);     // NZ correct, VC cleared
+
+	if (needed_flags & FLAG_V) {
+		// Calculate C Flag
+		MRS_NZCV_x(REG_WORK4);
+		TBZ_xii(REG_WORK2, 32, 2);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+
+		// Calculate V Flag
+		CLS_ww(REG_WORK2, REG_WORK3);
+		CMP_ww(REG_WORK2, REG_WORK1);
+		BGE_i(2);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		// Calculate C Flag
+		TBZ_xii(REG_WORK2, 32, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASL_w_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ASL_l_reg,(RW4 d, RR4 i))
+{
+	if(isconst(i)) {
+		COMPCALL(jff_ASL_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+	int x = writereg(FLAGX);
+
+	ANDS_ww3f(REG_WORK1, i);
+	BNE_i(3);
+
+	// shift count is 0
+	TST_ww(d, d);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	// shift count > 0
+	if (needed_flags & FLAG_V)
+		MOV_ww(REG_WORK3, d);
+	LSL_xxx(d, d, REG_WORK1);
+	TST_ww(d, d);                     // NZ correct, VC cleared
+
+	if (needed_flags & FLAG_V) {
+		// Calculate C Flag
+		MRS_NZCV_x(REG_WORK4);
+		TBZ_xii(d, 32, 2);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+
+		// Calculate V Flag
+		CLS_ww(REG_WORK2, REG_WORK3);
+		CMP_ww(REG_WORK2, REG_WORK1);
+		BGE_i(2);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		// Calculate C Flag
+		TBZ_xii(d, 32, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// Clean upper 32 bits of d after 64-bit LSL_xxx used for carry extraction
+	MOV_ww(d, d);
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASL_l_reg,(RW4 d, RR4 i))
+
+/*
+ * ASLW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise.
+ * C Set according to the last bit shifted out of the operand.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_ASLW,(RW2 d))
+{
+	d = rmw(d);
+
+	LSL_wwi(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_ASLW,(RW2 d))
+
+MIDFUNC(1,jff_ASLW,(RW2 d))
+{
+	d = rmw(d);
+
+	LSL_wwi(REG_WORK1, d, 17);
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	if (needed_flags & FLAG_V) {
+		// Calculate C flag
+		MRS_NZCV_x(REG_WORK4);
+		TBZ_wii(d, 15, 2);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+
+		// Calculate V flag
+		EOR_wwwLSLi(REG_WORK1, d, d, 1); // eor bit15 and bit14 of source
+		TBZ_wii(REG_WORK1, 15, 2);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		// Calculate C flag
+		TBZ_wii(d, 15, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+	LSL_wwi(d, d, 1);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_ASLW,(RW2 d))
+
+/*
+ * ASR
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise. Shift right -> always 0
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ */
+MIDFUNC(2,jnf_ASR_b_imm,(RW1 d, IM8 i))
+{
+	if(i) {
+		d = rmw(d);
+
+		SIGNED8_REG_2_REG(REG_WORK1, d);
+		if(i > 31)
+			i = 31;
+		ASR_wwi(REG_WORK1, REG_WORK1, i);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ASR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_ASR_w_imm,(RW2 d, IM8 i))
+{
+	if(i) {
+		d = rmw(d);
+
+		SIGNED16_REG_2_REG(REG_WORK1, d);
+		if(i > 31)
+			i = 31;
+		ASR_wwi(REG_WORK1, REG_WORK1, i);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ASR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_ASR_l_imm,(RW4 d, IM8 i))
+{
+	if(i) {
+		d = rmw(d);
+
+		if(i > 31)
+			i = 31;
+		ASR_wwi(d, d, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ASR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_ASR_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	if (i) {
+		if(i > 31)
+			i = 31;
+		ASR_wwi(REG_WORK2, REG_WORK1, i);
+		BFI_wwii(d, REG_WORK2, 0, 8);
+		TST_ww(REG_WORK2, REG_WORK2);
+
+		// Calculate C flag
+		TBZ_wii(REG_WORK1, i-1, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_ww(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ASR_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	if (i) {
+		if(i > 31)
+			i = 31;
+		ASR_wwi(REG_WORK2, REG_WORK1, i);
+		BFI_wwii(d, REG_WORK2, 0, 16);
+		TST_ww(REG_WORK2, REG_WORK2);
+
+		// Calculate C flag
+		TBZ_wii(REG_WORK1, i-1, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		TST_ww(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ASR_l_imm,(RW4 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	if (i) {
+		SXTW_xw(REG_WORK1, d);
+		if(i > 32)
+			i = 32;
+		ASR_xxi(d, REG_WORK1, i);
+		TST_ww(d, d);
+
+		// Calculate C flag
+		TBZ_wii(REG_WORK1, i-1, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+
+		// Clean upper 32 bits after 64-bit ASR_xxi
+		MOV_ww(d, d);
+	} else {
+		TST_ww(d, d);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_ASR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_ASR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ASR_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	AND_ww3f(REG_WORK2, i);
+	ASR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jnf_ASR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ASR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ASR_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	AND_ww3f(REG_WORK2, i);
+	ASR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jnf_ASR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ASR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ASR_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	AND_ww3f(REG_WORK1, i);
+	ASR_www(d, d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jnf_ASR_l_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ASR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ASR_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(REG_WORK3, d);
+	ANDS_ww3f(REG_WORK1, i);
+	BNE_i(3);               // No shift -> X flag unchanged
+
+	// shift count is 0
+	TST_ww(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	// shift count > 0
+	ASR_www(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 8);
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	// Calculate C Flag
+	SUB_wwi(REG_WORK2, REG_WORK1, 1);
+	ASR_www(REG_WORK2, REG_WORK3, REG_WORK2);
+	TBZ_wii(REG_WORK2, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ASR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ASR_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(REG_WORK3, d);
+	ANDS_ww3f(REG_WORK1, i);
+	BNE_i(3);               // No shift -> X flag unchanged
+
+	// shift count is 0
+	TST_ww(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	// shift count > 0
+	ASR_www(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 16);
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	// Calculate C Flag
+	SUB_wwi(REG_WORK2, REG_WORK1, 1);
+	ASR_www(REG_WORK2, REG_WORK3, REG_WORK2);
+	TBZ_wii(REG_WORK2, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ASR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ASR_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	i = readreg(i);
+	d = rmw(d);
+
+	ANDS_ww3f(REG_WORK1, i);
+	BNE_i(3);               // No shift -> X flag unchanged
+
+	// shift count is 0
+	TST_ww(d, d);           // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	// shift count > 0
+	MOV_ww(REG_WORK3, d);
+	ASR_www(d, d, REG_WORK1);
+	TST_ww(d, d);
+
+	// Calculate C Flag
+	SUB_wwi(REG_WORK2, REG_WORK1, 1);
+	ASR_www(REG_WORK2, REG_WORK3, REG_WORK2);
+	TBZ_wii(REG_WORK2, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ASR_l_reg,(RW4 d, RR4 i))
+
+/*
+ * ASRW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise. Shift right -> always 0
+ * C Set according to the last bit shifted out of the operand.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_ASRW,(RW2 d))
+{
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(d, d);
+	ASR_wwi(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_ASRW,(RW2 d))
+
+MIDFUNC(1,jff_ASRW,(RW2 d))
+{
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	ASR_wwi(d, REG_WORK1, 1);
+	TST_ww(d, d);
+
+	// Calculate C flag
+	TBZ_wii(REG_WORK1, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_ASRW,(RW2 d))
+
+/*
+ * BCHG
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ *  Operand Size: 8,32
+ *
+ * X Not affected.
+ * N Not affected.
+ * Z Set if the bit changed was zero. Cleared otherwise.
+ * V Not affected.
+ * C Not affected.
+ *
+ */
+/* BCHG.B: target is never a register */
+/* BCHG.L: target is always a register */
+MIDFUNC(2,jnf_BCHG_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+	EOR_xxbit(d, d, s & 0x7);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCHG_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+	EOR_xxbit(d, d, s & 0x1f);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCHG_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jnf_BCHG_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCHG_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	EOR_www(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_BCHG_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCHG_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	EOR_www(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jnf_BCHG_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_BCHG_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	EOR_xxbit(d, d, s & 0x7);
+	UBFX_xxii(REG_WORK2, d, s & 0x7, 1);
+	BFI_xxii(REG_WORK1, REG_WORK2, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCHG_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jff_BCHG_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	EOR_xxbit(d, d, s & 0x1f);
+	UBFX_xxii(REG_WORK2, d, s & 0x1f, 1);
+	BFI_xxii(REG_WORK1, REG_WORK2, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCHG_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jff_BCHG_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCHG_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d, REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+	EOR_www(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BCHG_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCHG_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d, REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+	EOR_www(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_BCHG_l,(RW4 d, RR4 s))
+
+/*
+ * BCLR
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ * Operand Size: 8,32
+ *
+ * X Not affected.
+ * N Not affected.
+ * Z Set if the bit cleared was zero. Cleared otherwise.
+ * V Not affected.
+ * C Not affected.
+ *
+ */
+/* BCLR.B: target is never a register */
+/* BCLR.L: target is always a register */
+MIDFUNC(2,jnf_BCLR_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+	CLEAR_xxbit(d, d, s & 0x7);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCLR_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IM8 s))
+{
+	if(isconst(d)) {
+		live.state[d].val = live.state[d].val & ~(1 << (s & 0x1f));
+		return;
+	}
+	d = rmw(d);
+	CLEAR_xxbit(d, d, s & 0x1f);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BCLR_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jnf_BCLR_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCLR_b_imm)(d, live.state[s].val);
+		return;
+	}
+	s = readreg(s);
+	d = rmw(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	BIC_www(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_BCLR_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BCLR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	BIC_www(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jnf_BCLR_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_BCLR_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	CLEAR_xxZflag(REG_WORK1, REG_WORK1);
+	TBNZ_wii(d, s & 0x7, 2);
+	SET_xxZflag(REG_WORK1, REG_WORK1);
+	MSR_NZCV_x(REG_WORK1);
+	CLEAR_xxbit(d, d, s & 0x7);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCLR_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jff_BCLR_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	CLEAR_xxZflag(REG_WORK1, REG_WORK1);
+	TBNZ_wii(d, s & 0x1f, 2);
+	SET_xxZflag(REG_WORK1, REG_WORK1);
+	MSR_NZCV_x(REG_WORK1);
+	CLEAR_xxbit(d, d, s & 0x1f);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BCLR_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jff_BCLR_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCLR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d,REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+	BIC_www(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BCLR_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BCLR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d,REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+	BIC_www(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_BCLR_l,(RW4 d, RR4 s))
+
+/*
+ * BFINS
+ * Operand Syntax: 	#xxx.w,<ea>
+ *
+ * Operand Size: 32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the bitfield is set. Cleared otherwise.
+ * Z Set if the bitfield is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(4,jnf_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+
+	BFI_wwii(d, s, (32 - offs - width), width);
+	if(32 - offs - width < 0) {
+		BFI_xxii(d, s, (64 - offs - width), width);
+		MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFI for wrap-around case
+	}
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+
+MIDFUNC(4,jff_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+
+	SBFX_wwii(REG_WORK1, s, 0, width);
+	BFI_wwii(d, REG_WORK1, (32 - offs - width), width);
+	if(32 - offs - width < 0) {
+		BFI_xxii(d, REG_WORK1, (64 - offs - width), width);
+		MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFI for wrap-around case
+	}
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_ii,(RW4 d, RR4 s, IM8 offs, IM8 width))
+
+MIDFUNC(5,jnf_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+{
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+
+	SBFX_wwii(REG_WORK1, s, 0, width);
+	BFI_xxii(d2, d, 32, 32);
+	BFI_xxii(d2, REG_WORK1, (64 - offs - width), width);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+
+MIDFUNC(5,jff_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+{
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+
+	SBFX_wwii(REG_WORK1, s, 0, width);
+	BFI_xxii(d2, d, 32, 32);
+	BFI_xxii(d2, REG_WORK1, (64 - offs - width), width);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_ii,(RW4 d, RW4 d2, RR4 s, IM8 offs, IM8 width))
+
+// Next only called when dest is D0-D7
+MIDFUNC(4,jnf_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+
+	AND_xx1f(REG_WORK3, offs);
+	MOV_xi(REG_WORK4, width);
+
+	BFI_xxii(d, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK4);
+	BFI_xxii(REG_WORK2, REG_WORK2, 32, 32);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d, d, REG_WORK2);
+
+	ROR_www(REG_WORK1, s, REG_WORK4);
+	BFI_xxii(REG_WORK1, REG_WORK1, 32, 32);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d, d, REG_WORK1);
+	ROR_xxi(d, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFINS operations
+
+	unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(4,jff_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+{
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+
+	AND_xx1f(REG_WORK3, offs);
+	MOV_xi(REG_WORK4, width);
+
+	BFI_xxii(d, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK4);
+	BFI_xxii(REG_WORK2, REG_WORK2, 32, 32);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d, d, REG_WORK2);
+
+	ROR_www(REG_WORK1, s, REG_WORK4);
+	BFI_xxii(REG_WORK1, REG_WORK1, 32, 32);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d, d, REG_WORK1);
+	ROR_xxi(d, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFINS operations
+
+	LSL_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	TST_xx(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_di,(RW4 d, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(4,jnf_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+{
+	clobber_flags();
+
+	INIT_REGS_l(d,s);
+	width = readreg(width);
+
+	MOV_xi(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK4);
+	BFI_xxii(REG_WORK2, REG_WORK2, 32, 32);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d, d, REG_WORK2);
+
+	ROR_www(REG_WORK1, s, REG_WORK4);
+	BFI_xxii(REG_WORK1, REG_WORK1, 32, 32);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d, d, REG_WORK1);
+	ROR_xxi(d, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFINS operations
+
+	unlock2(width);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(4,jff_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+{
+	INIT_REGS_l(d,s);
+	width = readreg(width);
+
+	MOV_xi(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK4);
+	BFI_xxii(REG_WORK2, REG_WORK2, 32, 32);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d, d, REG_WORK2);
+
+	ROR_www(REG_WORK1, s, REG_WORK4);
+	BFI_xxii(REG_WORK1, REG_WORK1, 32, 32);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d, d, REG_WORK1);
+	ROR_xxi(d, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFINS operations
+
+	LSL_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	TST_xx(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(width);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_id,(RW4 d, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(4,jnf_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+{
+	clobber_flags();
+
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+	width = readreg(width);
+
+	AND_xx1f(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK4);
+	BFI_xxii(REG_WORK2, REG_WORK2, 32, 32);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d, d, REG_WORK2);
+
+	ROR_www(REG_WORK1, s, REG_WORK4);
+	BFI_xxii(REG_WORK1, REG_WORK1, 32, 32);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d, d, REG_WORK1);
+	ROR_xxi(d, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFINS operations
+
+	unlock2(width);
+	unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jnf_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+
+MIDFUNC(4,jff_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+{
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+	width = readreg(width);
+
+	AND_xx1f(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK4);
+	BFI_xxii(REG_WORK2, REG_WORK2, 32, 32);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d, d, REG_WORK2);
+
+	ROR_www(REG_WORK1, s, REG_WORK4);
+	BFI_xxii(REG_WORK1, REG_WORK1, 32, 32);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d, d, REG_WORK1);
+	ROR_xxi(d, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit BFINS operations
+
+	LSL_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	TST_xx(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(width);
+	unlock2(offs);
+	EXIT_REGS(d,s);
+}
+MENDFUNC(4,jff_BFINS_dd,(RW4 d, RR4 s, RR4 offs, RR4 width))
+
+
+// Next called when dest is <ea>
+MIDFUNC(5,jnf_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+{
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+
+	AND_xx1f(REG_WORK3, offs);
+	MOV_xi(REG_WORK4, width);
+
+	BFI_xxii(d2, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK4);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d2, d2, REG_WORK2);
+
+	ROR_xxx(REG_WORK1, s, REG_WORK4);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d2, d2, REG_WORK1);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	unlock2(offs);
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(5,jff_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+{
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+
+	AND_xx1f(REG_WORK3, offs);
+	MOV_xi(REG_WORK4, width);
+
+	BFI_xxii(d2, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK4);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d2, d2, REG_WORK2);
+
+	ROR_xxx(REG_WORK1, s, REG_WORK4);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d2, d2, REG_WORK1);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	LSL_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	TST_xx(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(offs);
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_di,(RW4 d, RW4 d2, RR4 s, RR4 offs, IM8 width))
+
+MIDFUNC(5,jnf_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+{
+	clobber_flags();
+
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+	width = readreg(width);
+
+	MOV_xi(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d2, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK4);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d2, d2, REG_WORK2);
+
+	ROR_xxx(REG_WORK1, s, REG_WORK4);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d2, d2, REG_WORK1);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	unlock2(width);
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(5,jff_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+{
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+	width = readreg(width);
+
+	MOV_xi(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d2, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK4);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d2, d2, REG_WORK2);
+
+	ROR_xxx(REG_WORK1, s, REG_WORK4);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d2, d2, REG_WORK1);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	LSL_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	TST_xx(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(width);
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_id,(RW4 d, RW4 d2, RR4 s, IM8 offs, RR4 width))
+
+MIDFUNC(5,jnf_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+{
+	clobber_flags();
+
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+	width = readreg(width);
+
+	AND_xx1f(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d2, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK4);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d2, d2, REG_WORK2);
+
+	ROR_xxx(REG_WORK1, s, REG_WORK4);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d2, d2, REG_WORK1);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	unlock2(width);
+	unlock2(offs);
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jnf_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+
+MIDFUNC(5,jff_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+{
+	d2 = rmw(d2);
+	INIT_REGS_l(d,s);
+	offs = readreg(offs);
+	width = readreg(width);
+
+	AND_xx1f(REG_WORK3, offs);
+	ANDS_xx1f(REG_WORK4, width);
+	BNE_i(2);
+	MOV_xi(REG_WORK4, 0x20);
+
+	BFI_xxii(d2, d, 32, 32);
+
+	MOVN_xi(REG_WORK2, 0);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK4);
+	ROR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	AND_xxx(d2, d2, REG_WORK2);
+
+	ROR_xxx(REG_WORK1, s, REG_WORK4);
+	ROR_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	MVN_xx(REG_WORK2, REG_WORK2);
+	AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+
+	ORR_xxx(d2, d2, REG_WORK1);
+	LSR_xxi(d, d2, 32);
+	MOV_ww(d2, d2); // Clean upper 32 bits of d2 after 64-bit BFINS2 operations
+
+	LSL_xxx(REG_WORK1, REG_WORK1, REG_WORK3);
+	TST_xx(REG_WORK1, REG_WORK1);
+
+	flags_carry_inverted = false;
+	unlock2(width);
+	unlock2(offs);
+	EXIT_REGS(d,s);
+	unlock2(d2);
+}
+MENDFUNC(5,jff_BFINS2_dd,(RW4 d, RW4 d2, RR4 s, RR4 offs, RR4 width))
+
+/*
+ * BSET
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ *  Operand Size: 8,32
+ *
+ * X Not affected.
+ * N Not affected.
+ * Z Set if the bit set was zero. Cleared otherwise.
+ * V Not affected.
+ * C Not affected.
+ *
+ */
+/* BSET.B: target is never a register */
+/* BSET.L: target is always a register */
+MIDFUNC(2,jnf_BSET_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+	SET_xxbit(d, d, s & 0x7);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BSET_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jnf_BSET_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+	SET_xxbit(d, d, s & 0x1f);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_BSET_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jnf_BSET_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BSET_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	ORR_www(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_BSET_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_BSET_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	ORR_www(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jnf_BSET_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_BSET_b_imm,(RW1 d, IM8 s))
+{
+	d = rmw(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	CLEAR_xxZflag(REG_WORK1, REG_WORK1);
+	TBNZ_wii(d, s & 0x7, 2);
+	SET_xxZflag(REG_WORK1, REG_WORK1);
+	MSR_NZCV_x(REG_WORK1);
+	SET_xxbit(d, d, s & 0x7);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BSET_b_imm,(RW1 d, IM8 s))
+
+MIDFUNC(2,jff_BSET_l_imm,(RW4 d, IM8 s))
+{
+	d = rmw(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	CLEAR_xxZflag(REG_WORK1, REG_WORK1);
+	TBNZ_wii(d, s & 0x1f, 2);
+	SET_xxZflag(REG_WORK1, REG_WORK1);
+	MSR_NZCV_x(REG_WORK1);
+	SET_xxbit(d, d, s & 0x1f);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BSET_l_imm,(RW4 d, IM8 s))
+
+MIDFUNC(2,jff_BSET_b,(RW1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BSET_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = rmw(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d,REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+	ORR_www(d, d, REG_WORK2);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BSET_b,(RW1 d, RR4 s))
+
+MIDFUNC(2,jff_BSET_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BSET_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d,s);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d,REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+	ORR_www(d, d, REG_WORK2);
+
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_BSET_l,(RW4 d, RR4 s))
+
+/*
+ * BTST
+ * Operand Syntax: 	Dn,<ea>
+ *					#<data>,<ea>
+ *
+ *  Operand Size: 8,32
+ *
+ * X Not affected
+ * N Not affected
+ * Z Set if the bit tested is zero. Cleared otherwise
+ * V Not affected
+ * C Not affected
+ *
+ */
+/* BTST.B: target is never a register */
+/* BTST.L: target is always a register */
+MIDFUNC(2,jff_BTST_b_imm,(RR1 d, IM8 s))
+{
+	d = readreg(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	CLEAR_xxZflag(REG_WORK1, REG_WORK1);
+	TBNZ_wii(d, s & 0x7, 2); // skip next if bit is set
+	SET_xxZflag(REG_WORK1, REG_WORK1);
+	MSR_NZCV_x(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BTST_b_imm,(RR1 d, IM8 s))
+
+MIDFUNC(2,jff_BTST_l_imm,(RR4 d, IM8 s))
+{
+	d = readreg(d);
+
+	MRS_NZCV_x(REG_WORK1);
+	CLEAR_xxZflag(REG_WORK1, REG_WORK1);
+	TBNZ_wii(d, s & 0x1f, 2); // skip next if bit is set
+	SET_xxZflag(REG_WORK1, REG_WORK1);
+	MSR_NZCV_x(REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_BTST_l_imm,(RR4 d, IM8 s))
+
+MIDFUNC(2,jff_BTST_b,(RR1 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BTST_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	d = readreg(d);
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 3); // REG_WORK1 = s & 7
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d, REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_BTST_b,(RR1 d, RR4 s))
+
+MIDFUNC(2,jff_BTST_l,(RR4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_BTST_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	d = readreg(d);
+	if(!s_is_d)
+		s = readreg(s);
+	else
+		s = d;
+
+	UBFIZ_xxii(REG_WORK1, s, 0, 5); // REG_WORK1 = s & 31
+	MOV_xi(REG_WORK2, 1);
+	LSL_www(REG_WORK2, REG_WORK2, REG_WORK1);
+
+	MRS_NZCV_x(REG_WORK1);
+	TST_ww(d, REG_WORK2);
+	CSET_xc(REG_WORK3, NATIVE_CC_EQ);
+	BFI_xxii(REG_WORK1, REG_WORK3, 30, 1);
+	MSR_NZCV_x(REG_WORK1);
+
+	unlock2(d);
+	if(!s_is_d)
+		unlock2(s);
+}
+MENDFUNC(2,jff_BTST_l,(RR4 d, RR4 s))
+
+/*
+ * CLR
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Always cleared.
+ * Z Always set.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_CLR_b,(W1 d))
+{
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_b(d);
+	CLEAR_LOW8_xx(d, d);
+	// Fix 19: CLEAR_LOW8_xx uses 64-bit AND, preserving dirty upper 32 bits.
+	MOV_ww(d, d);
+	unlock2(d);
+}
+MENDFUNC(1,jnf_CLR_b,(W1 d))
+
+MIDFUNC(1,jnf_CLR_w,(W2 d))
+{
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_w(d);
+	CLEAR_LOW16_xx(d, d);
+	// Fix 19: CLEAR_LOW16_xx uses 64-bit AND, preserving dirty upper 32 bits.
+	MOV_ww(d, d);
+	unlock2(d);
+}
+MENDFUNC(1,jnf_CLR_w,(W2 d))
+
+MIDFUNC(1,jnf_CLR_l,(W4 d))
+{
+	set_const(d, 0);
+}
+MENDFUNC(1,jnf_CLR_l,(W4 d))
+
+MIDFUNC(1,jff_CLR_b,(W1 d))
+{
+	MOV_xish(REG_WORK1, 0x4000, 16); // set Z flag
+	MSR_NZCV_x(REG_WORK1);
+	flags_carry_inverted = false;
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_b(d);
+	CLEAR_LOW8_xx(d, d);
+	// Fix 19: CLEAR_LOW8_xx uses 64-bit AND, preserving dirty upper 32 bits.
+	MOV_ww(d, d);
+	unlock2(d);
+}
+MENDFUNC(1,jff_CLR_b,(W1 d))
+
+MIDFUNC(1,jff_CLR_w,(W2 d))
+{
+	MOV_xish(REG_WORK1, 0x4000, 16); // set Z flag
+	MSR_NZCV_x(REG_WORK1);
+	flags_carry_inverted = false;
+	if(d >= 16) {
+		set_const(d, 0);
+		return;
+	}
+	INIT_WREG_w(d);
+	CLEAR_LOW16_xx(d, d);
+	// Fix 19: CLEAR_LOW16_xx uses 64-bit AND, preserving dirty upper 32 bits.
+	MOV_ww(d, d);
+	unlock2(d);
+}
+MENDFUNC(1,jff_CLR_w,(W2 d))
+
+MIDFUNC(1,jff_CLR_l,(W4 d))
+{
+	MOV_xish(REG_WORK1, 0x4000, 16); // set Z flag
+	MSR_NZCV_x(REG_WORK1);
+	flags_carry_inverted = false;
+	set_const(d, 0);
+}
+MENDFUNC(1,jff_CLR_l,(W4 d))
+
+/*
+ * CMP
+ * Operand Syntax: <ea>, Dn
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ */
+MIDFUNC(2,jff_CMP_b_imm,(RR1 d, IM8 v))
+{
+	if (isconst(d)) {
+		uae_u8 tmp = (uae_u8)(live.state[d].val & 0xff);
+		MOV_wish(REG_WORK1, tmp << 8, 16);
+	} else {
+		d = readreg(d);
+		LSL_wwi(REG_WORK1, d, 24);
+		unlock2(d);
+	}
+
+	MOV_wi(REG_WORK2, v & 0xff);
+	CMP_wwLSLi(REG_WORK1, REG_WORK2, 24);
+
+	flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_b_imm,(RR1 d, IM8 v))
+
+MIDFUNC(2,jff_CMP_b,(RR1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMP_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	if (isconst(d)) {
+		uae_u8 tmp = (uae_u8)(live.state[d].val & 0xff);
+		s = readreg(s);
+		MOV_wish(REG_WORK1, tmp << 8, 16);
+		CMP_wwLSLi(REG_WORK1, s, 24);
+		unlock2(s);
+	} else {
+		INIT_RREGS_b(d, s);
+
+		LSL_wwi(REG_WORK1, d, 24);
+		CMP_wwLSLi(REG_WORK1, s, 24);
+
+		EXIT_REGS(d,s);
+	}
+	flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_b,(RR1 d, RR1 s))
+
+MIDFUNC(2,jff_CMP_w_imm,(RR2 d, IM16 v))
+{
+	if (isconst(d)) {
+		MOV_wish(REG_WORK1, (live.state[d].val & 0xffff), 16);
+		MOV_wish(REG_WORK2, (v & 0xffff), 16);
+		CMP_ww(REG_WORK1, REG_WORK2);
+	} else {
+		d = readreg(d);
+
+		LSL_wwi(REG_WORK1, d, 16);
+		MOV_xi(REG_WORK2, v);
+		CMP_wwLSLi(REG_WORK1, REG_WORK2, 16);
+
+		unlock2(d);
+	}
+	flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_w_imm,(RR2 d, IM16 v))
+
+MIDFUNC(2,jff_CMP_w,(RR2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMP_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	if (isconst(d)) {
+		uae_u16 tmp = (uae_u16)(live.state[d].val & 0xffff);
+		s = readreg(s);
+		MOV_wish(REG_WORK1, tmp, 16);
+		CMP_wwLSLi(REG_WORK1, s, 16);
+		unlock2(s);
+	} else {
+		INIT_RREGS_w(d, s);
+
+		LSL_wwi(REG_WORK1, d, 16);
+		CMP_wwLSLi(REG_WORK1, s, 16);
+
+		EXIT_REGS(d,s);
+	}
+	flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMP_w,(RR2 d, RR2 s))
+
+MIDFUNC(2,jff_CMP_l_imm,(RR4 d, IM32 v))
+{
+	if(isconst(d)) {
+		uae_u32 newv = ((uae_u32)live.state[d].val) - ((uae_u32)v);
+		int flgs = ((uae_s32)v) < 0;
+		int flgo = ((uae_s32)live.state[d].val) < 0;
+		int flgn = ((uae_s32)newv) < 0;
+		uae_u32 f = 0;
+		if(((uae_s32)newv) == 0)
+			f |= (ARM_Z_FLAG >> 16);
+		if((flgs != flgo) && (flgn != flgo))
+			f |= (ARM_V_FLAG >> 16);
+		if(((uae_u32)v) > ((uae_u32)live.state[d].val))
+			f |= (ARM_C_FLAG >> 16);
+		if(flgn != 0)
+			f |= (ARM_N_FLAG >> 16);
+		MOV_xish(REG_WORK1, f, 16);
+		MSR_NZCV_x(REG_WORK1);
+
+		flags_carry_inverted = false;
+		return;
+	}
+
+	d = readreg(d);
+
+	LOAD_U32(REG_WORK1, v);
+	CMP_ww(d, REG_WORK1);
+
+	flags_carry_inverted = true;
+	unlock2(d);
+}
+MENDFUNC(2,jff_CMP_l_imm,(RR4 d, IM32 v))
+
+MIDFUNC(2,jff_CMP_l,(RR4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMP_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_RREGS_l(d, s);
+
+	CMP_ww(d, s);
+
+	flags_carry_inverted = true;
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_CMP_l,(RR4 d, RR4 s))
+
+/*
+ * CMPA
+ * Operand Syntax: 	<ea>, An
+ *
+ * Operand Size: 16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ */
+MIDFUNC(2,jff_CMPA_w_imm,(RR2 d, IM16 v))
+{
+	uae_u16 tmp = (uae_u16)(v & 0xffff);
+	d = readreg(d);
+	SIGNED16_IMM_2_REG(REG_WORK1, tmp);
+	CMP_ww(d, REG_WORK1);
+	unlock2(d);
+
+	flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMPA_w_imm,(RR2 d, IM16 v))
+
+MIDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMPA_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_RREGS_w(d, s);
+	CMP_wwEX(d, s, EX_SXTH);
+	EXIT_REGS(d,s);
+
+	flags_carry_inverted = true;
+}
+MENDFUNC(2,jff_CMPA_w,(RR2 d, RR2 s))
+
+MIDFUNC(2,jff_CMPA_l_imm,(RR4 d, IM32 v))
+{
+	d = readreg(d);
+
+	LOAD_U32(REG_WORK1, v);
+	CMP_ww(d, REG_WORK1);
+
+	flags_carry_inverted = true;
+	unlock2(d);
+}
+MENDFUNC(2,jff_CMPA_l_imm,(RR4 d, IM32 v))
+
+MIDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_CMPA_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_RREGS_l(d, s);
+
+	CMP_ww(d, s);
+
+	flags_carry_inverted = true;
+	EXIT_REGS(d,s);
+}
+MENDFUNC(2,jff_CMPA_l,(RR4 d, RR4 s))
+
+/*
+ * DBCC
+ *
+ */
+MIDFUNC(2,jff_DBCC,(RW4 d, IM8 cc))
+{
+	d = rmw(d);
+
+	FIX_INVERTED_CARRY
+
+	// If cc true -> no branch, so we have to clear ARM_C_FLAG
+	MOV_xish(REG_WORK1, 0x2000, 16); // set C flag
+	MOV_xi(REG_WORK2, 0);
+	switch(cc) {
+		case 9: // LS
+			CSEL_xxxc(REG_WORK1, REG_WORK2, REG_WORK1, NATIVE_CC_EQ);
+			CSEL_xxxc(REG_WORK1, REG_WORK2, REG_WORK1, NATIVE_CC_CS);
+			break;
+
+		case 8: // HI
+			MOV_xish(REG_WORK3, 0x2000, 16);
+			CSEL_xxxc(REG_WORK1, REG_WORK2, REG_WORK1, NATIVE_CC_CC);
+			CSEL_xxxc(REG_WORK1, REG_WORK3, REG_WORK1, NATIVE_CC_EQ);
+			break;
+
+		default:
+			CSEL_xxxc(REG_WORK1, REG_WORK2, REG_WORK1, cc);
+			break;
+	}
+	clobber_flags();
+	MSR_NZCV_x(REG_WORK1);
+
+	BCC_i(4); // If cc true -> no sub
+
+	// sub (d, 1)
+	LSL_wwi(REG_WORK2, d, 16);
+	SUBS_wwish(REG_WORK2, REG_WORK2, 0x10, 1);
+	BFXIL_xxii(d, REG_WORK2, 16, 16);
+
+	// caller can now use register_branch(v1, v2, NATIVE_CC_CS);
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_DBCC,(RW4 d, IM8 cc))
+
+/*
+ * DIVU
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set or overflow. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_DIVU,(RW4 d, RR4 s))
+{
+	int init_regs_used = 0;
+	int targetIsReg;
+	int s_is_d;
+	if (isconst(s) && (uae_u16)live.state[s].val != 0) {
+		uae_u16 tmp = (uae_u16)live.state[s].val;
+		d = rmw(d);
+		UNSIGNED16_IMM_2_REG(REG_WORK3, tmp);
+	} else {
+		targetIsReg = (d < 16);
+		s_is_d = (s == d);
+		if(!s_is_d)
+			s = readreg(s);
+		d = rmw(d);
+		if(s_is_d)
+			s = d;
+		init_regs_used = 1;
+
+		UNSIGNED16_REG_2_REG(REG_WORK3, s);
+		CBNZ_wi(REG_WORK3, 4);    // src is not 0
+
+		// Signal exception 5
+		MOV_wi(REG_WORK1, 5);
+		uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+		STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+		B_i(7);        // end_of_op
+	}
+
+	// src is not 0
+	UDIV_www(REG_WORK1, d, REG_WORK3);
+
+	LSR_wwi(REG_WORK2, REG_WORK1, 16); 							// if result of this is not 0, DIVU overflows -> no result
+	CBNZ_wi(REG_WORK2, 4);
+
+	// Here we have to calc remainder
+	MSUB_wwww(REG_WORK2, REG_WORK1, REG_WORK3, d);
+	LSL_wwi(d, REG_WORK2, 16);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+	// end_of_op
+
+	if (init_regs_used) {
+		EXIT_REGS(d, s);
+	} else {
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_DIVU,(RW4 d, R4 s))
+
+MIDFUNC(2,jff_DIVU,(RW4 d, RR4 s))
+{
+	uae_u32* branchadd;
+	int init_regs_used = 0;
+	int targetIsReg;
+	int s_is_d;
+	if (isconst(s) && (uae_u16)live.state[s].val != 0) {
+		uae_u16 tmp = (uae_u16)live.state[s].val;
+		d = rmw(d);
+		UNSIGNED16_IMM_2_REG(REG_WORK3, tmp);
+	} else {
+		targetIsReg = (d < 16);
+		s_is_d = (s == d);
+		if(!s_is_d)
+			s = readreg(s);
+		d = rmw(d);
+		if(s_is_d)
+			s = d;
+		init_regs_used = 1;
+
+		UNSIGNED16_REG_2_REG(REG_WORK3, s);
+		uae_u32* branchadd_not0 = (uae_u32*)get_target();
+		CBNZ_wi(REG_WORK3, 0);     // src is not 0
+
+		// Signal exception 5
+		MOV_wi(REG_WORK1, 5);
+		uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+		STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+
+		// flag handling like divbyzero_special()
+		if (currprefs.cpu_model == 68020 || currprefs.cpu_model == 68030) {
+			MOV_wish(REG_WORK1, 0x5000, 16); // Set V and Z (if d >=0)
+			TBZ_wii(d, 31, 2);
+			MOV_wish(REG_WORK1, 0x9000, 16); // Set V and N (if d < 0)
+		} else if (currprefs.cpu_model >= 68040) {
+			MRS_NZCV_x(REG_WORK1);
+			CLEAR_xxCflag(REG_WORK1, REG_WORK1);
+		} else {
+			// 68000/010
+			MOV_wish(REG_WORK1, 0x0000, 16);
+		}
+		MSR_NZCV_x(REG_WORK1);
+		branchadd = (uae_u32*)get_target();
+		B_i(0);        // end_of_op
+		write_jmp_target(branchadd_not0, (uintptr)get_target());
+	}
+
+	// src is not 0
+	UDIV_www(REG_WORK1, d, REG_WORK3);
+
+	LSR_wwi(REG_WORK2, REG_WORK1, 16); 							// if result of this is not 0, DIVU overflows
+	CBZ_wi(REG_WORK2, 4);
+	// Here we handle overflow
+	MOV_wish(REG_WORK1, 0x9000, 16); // set V and N
+	MSR_NZCV_x(REG_WORK1);
+	B_i(6);
+
+	// Here we have to calc flags and remainder
+	LSL_wwi(REG_WORK2, REG_WORK1, 16);
+	TST_ww(REG_WORK2, REG_WORK2);    // N and Z ok, C and V cleared
+
+	MSUB_wwww(REG_WORK2, REG_WORK1, REG_WORK3, d);
+	LSL_wwi(d, REG_WORK2, 16);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	// end_of_op
+	flags_carry_inverted = false;
+	if (init_regs_used) {
+		write_jmp_target(branchadd, (uintptr)get_target());
+		EXIT_REGS(d, s);
+	} else {
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jff_DIVU,(RW4 d, RR4 s))
+
+/*
+ * DIVS
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set or overflow. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_DIVS,(RW4 d, RR4 s))
+{
+	uae_u32* branchadd;
+	int init_regs_used = 0;
+	int targetIsReg;
+	int s_is_d;
+	uae_s16 tmp;
+	if (isconst(s) && (uae_s16)live.state[s].val != 0) {
+		tmp = (uae_s16)live.state[s].val;
+		d = rmw(d);
+		SIGNED16_IMM_2_REG(REG_WORK3, tmp);
+	} else {
+		targetIsReg = (d < 16);
+		s_is_d = (s == d);
+		if(!s_is_d)
+			s = readreg(s);
+		d = rmw(d);
+		if(s_is_d)
+			s = d;
+		init_regs_used = 1;
+
+		SIGNED16_REG_2_REG(REG_WORK3, s);
+		CBNZ_wi(REG_WORK3, 4);     // src is not 0
+
+		// Signal exception 5
+		MOV_wi(REG_WORK1, 5);
+		uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+		STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+		branchadd = (uae_u32*)get_target();
+		B_i(0);        // end_of_op
+	}
+
+	// src is not 0
+	SDIV_www(REG_WORK1, d, REG_WORK3);
+
+	// check for overflow
+	MOVN_wi(REG_WORK2, 0x7fff);           // REG_WORK2 is now 0xffff8000
+	ANDS_www(REG_WORK3, REG_WORK1, REG_WORK2);
+	BEQ_i(3); 														// positive result, no overflow
+	CMP_ww(REG_WORK3, REG_WORK2);
+	BNE_i(8);															// overflow -> end_of_op
+
+	// Here we have to calc remainder
+	if (init_regs_used)
+		SIGNED16_REG_2_REG(REG_WORK3, s);
+	else
+		SIGNED16_IMM_2_REG(REG_WORK3, tmp);
+	MSUB_wwww(REG_WORK2, REG_WORK1, REG_WORK3, d);		// REG_WORK2 contains remainder
+
+	EOR_www(REG_WORK3, REG_WORK2, d);	  // If sign of remainder and first operand differs, change sign of remainder
+	TBZ_wii(REG_WORK3, 31, 2);
+	NEG_ww(REG_WORK2, REG_WORK2);
+
+	LSL_wwi(d, REG_WORK2, 16);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	// end_of_op
+	if (init_regs_used) {
+		write_jmp_target(branchadd, (uintptr)get_target());
+		EXIT_REGS(d, s);
+	} else {
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_DIVS,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_DIVS,(RW4 d, RR4 s))
+{
+	uae_u32* branchadd;
+	int init_regs_used = 0;
+	int targetIsReg;
+	int s_is_d;
+	uae_s16 tmp;
+	if (isconst(s) && (uae_s16)live.state[s].val != 0) {
+		tmp = (uae_s16)live.state[s].val;
+		d = rmw(d);
+		SIGNED16_IMM_2_REG(REG_WORK3, tmp);
+	} else {
+		targetIsReg = (d < 16);
+		s_is_d = (s == d);
+		if(!s_is_d)
+			s = readreg(s);
+		d = rmw(d);
+		if(s_is_d)
+			s = d;
+		init_regs_used = 1;
+
+		SIGNED16_REG_2_REG(REG_WORK3, s);
+		uae_u32* branchadd_not0 = (uae_u32*)get_target();
+		CBNZ_wi(REG_WORK3, 0);     // src is not 0
+
+		// Signal exception 5
+		MOV_wi(REG_WORK1, 5);
+		uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+		STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+
+		// flag handling like divbyzero_special()
+		if (currprefs.cpu_model == 68020 || currprefs.cpu_model == 68030) {
+			MOV_wish(REG_WORK1, 0x4000, 16); // Set Z
+		} else if (currprefs.cpu_model >= 68040) {
+			MRS_NZCV_x(REG_WORK1);
+			CLEAR_xxCflag(REG_WORK1, REG_WORK1);
+		} else {
+			// 68000/010
+			MOV_wish(REG_WORK1, 0x0000, 16);
+		}
+
+		MSR_NZCV_x(REG_WORK1);
+		branchadd = (uae_u32*)get_target();
+		B_i(0);        // end_of_op
+		write_jmp_target(branchadd_not0, (uintptr)get_target());
+	}
+
+	// src is not 0
+	SDIV_www(REG_WORK1, d, REG_WORK3);
+
+	// check for overflow
+	MOVN_wi(REG_WORK2, 0x7fff);           // REG_WORK2 is now 0xffff8000
+	ANDS_www(REG_WORK3, REG_WORK1, REG_WORK2);
+	BEQ_i(6); 														// positive result, no overflow
+	CMP_ww(REG_WORK3, REG_WORK2);
+	BEQ_i(4);															// no overflow
+
+	// Here we handle overflow
+	MOV_wish(REG_WORK1, 0x9000, 16); // set V and N
+	MSR_NZCV_x(REG_WORK1);
+	B_i(10);
+
+	// calc flags
+	LSL_wwi(REG_WORK2, REG_WORK1, 16);
+	TST_ww(REG_WORK2, REG_WORK2);         // N and Z ok, C and V cleared
+
+	// calc remainder
+	if (init_regs_used)
+		SIGNED16_REG_2_REG(REG_WORK3, s);
+	else
+		SIGNED16_IMM_2_REG(REG_WORK3, tmp);
+	MSUB_wwww(REG_WORK2, REG_WORK1, REG_WORK3, d);		// REG_WORK2 contains remainder
+
+	EOR_www(REG_WORK3, REG_WORK2, d);	  // If sign of remainder and first operand differs, change sign of remainder
+	TBZ_wii(REG_WORK3, 31, 2);
+	NEG_ww(REG_WORK2, REG_WORK2);
+
+	LSL_wwi(d, REG_WORK2, 16);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	// end_of_op
+	flags_carry_inverted = false;
+	if (init_regs_used) {
+		write_jmp_target(branchadd, (uintptr)get_target());
+		EXIT_REGS(d, s);
+	} else {
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jff_DIVS,(RW4 d, RR4 s))
+
+MIDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+{
+	s1 = readreg(s1);
+	d = rmw(d);
+	rem = writereg(rem);
+
+	CBNZ_wi(s1, 4);     // src is not 0
+
+	// Signal exception 5
+	MOV_wi(REG_WORK1, 5);
+	uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+	STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+	B_i(4);        // end_of_op
+
+	// src is not 0
+	UDIV_www(REG_WORK1, d, s1);
+
+	// Here we have to calc remainder
+	MSUB_wwww(rem, s1, REG_WORK1, d);
+	MOV_ww(d, REG_WORK1);
+
+// end_of_op
+
+	unlock2(rem);
+	unlock2(d);
+	unlock2(s1);
+}
+MENDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+{
+	s1 = readreg(s1);
+	d = rmw(d);
+	rem = writereg(rem);
+
+	CBNZ_wi(s1, 4);     // src is not 0
+
+	// Signal exception 5
+	MOV_wi(REG_WORK1, 5);
+	uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+	STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+
+	B_i(5);        // end_of_op
+
+	// src is not 0
+	UDIV_www(REG_WORK1, d, s1);
+
+	// Here we have to calc flags and remainder
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	MSUB_wwww(rem, s1, REG_WORK1, d);
+	MOV_ww(d, REG_WORK1);
+
+	// end_of_op
+
+	flags_carry_inverted = false;
+	unlock2(rem);
+	unlock2(d);
+	unlock2(s1);
+}
+MENDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+{
+	s1 = readreg(s1);
+	d = rmw(d);
+	rem = writereg(rem);
+
+	CBNZ_wi(s1, 4);     // src is not 0
+
+	// Signal exception 5
+	MOV_wi(REG_WORK1, 5);
+	uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+	STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+	B_i(7);        // end_of_op
+
+	// src is not 0
+	SDIV_www(REG_WORK1, d, s1);
+
+	// Here we have to calc remainder
+	MSUB_wwww(rem, s1, REG_WORK1, d);
+
+	EOR_www(REG_WORK3, rem, d);	// If sign of remainder and first operand differs, change sign of remainder
+	TBZ_wii(REG_WORK3, 31, 2);
+	NEG_ww(rem, rem);
+
+	MOV_ww(d, REG_WORK1);
+
+	// end_of_op
+
+	unlock2(rem);
+	unlock2(d);
+	unlock2(s1);
+}
+MENDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+
+MIDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+{
+	s1 = readreg(s1);
+	d = rmw(d);
+	rem = writereg(rem);
+
+	CBNZ_wi(s1, 4);     // src is not 0
+
+	// Signal exception 5
+	MOV_wi(REG_WORK1, 5);
+	uintptr idx = (uintptr)(&regs.jit_exception) - (uintptr)(&regs);
+	STR_wXi(REG_WORK1, R_REGSTRUCT, idx);
+	B_i(8);        // end_of_op
+
+	// src is not 0
+	SDIV_www(REG_WORK1, d, s1);
+
+	// Here we have to calc remainder
+	MSUB_wwww(rem, s1, REG_WORK1, d);
+
+	EOR_www(REG_WORK3, rem, d);	// If sign of remainder and first operand differs, change sign of remainder
+	TBZ_wii(REG_WORK3, 31, 2);
+	NEG_ww(REG_WORK2, REG_WORK2);
+
+	MOV_ww(d, REG_WORK1);
+	TST_ww(d, d);
+
+	// end_of_op
+
+	flags_carry_inverted = false;
+	unlock2(rem);
+	unlock2(d);
+	unlock2(s1);
+}
+MENDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
+
+/*
+ * EOR
+ * Operand Syntax: 	Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_EOR_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	MOV_xi(REG_WORK1, (v & 0xff));
+	EOR_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_EOR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_EOR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_EOR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		EOR_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		EOR_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_EOR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_EOR_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	MOV_xi(REG_WORK1, v & 0xffff);
+	EOR_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_EOR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_EOR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_EOR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	EOR_www(REG_WORK1, d, s);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_EOR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_EOR_l_imm,(RW4 d, IM32 v))
+{
+	if(isconst(d)) {
+		live.state[d].val = live.state[d].val ^ v;
+		return;
+	}
+
+	d = rmw(d);
+
+	LOAD_U32(REG_WORK1, v);
+	EOR_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_EOR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_EOR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_EOR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	EOR_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_EOR_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_EOR_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_IMM_2_REG(REG_WORK2, v);
+	if(targetIsReg) {
+		EOR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+		TST_ww(REG_WORK1, REG_WORK1);
+	} else {
+		EOR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_EOR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_EOR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_EOR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_REG_2_REG(REG_WORK2, s);
+	if(targetIsReg) {
+		EOR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+		TST_ww(REG_WORK1, REG_WORK1);
+	} else {
+		EOR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_EOR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_EOR_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_IMM_2_REG(REG_WORK2, v);
+	if(targetIsReg) {
+		EOR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+		TST_ww(REG_WORK1, REG_WORK1);
+	} else {
+		EOR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_EOR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_EOR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_EOR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_REG_2_REG(REG_WORK2, s);
+	if(targetIsReg) {
+		EOR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+		TST_ww(REG_WORK1, REG_WORK1);
+	} else {
+		EOR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_EOR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_EOR_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	LOAD_U32(REG_WORK1, v);
+	EOR_www(d, d, REG_WORK1);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_EOR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_EOR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_EOR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	EOR_www(d, d, s);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_EOR_l,(RW4 d, RR4 s))
+
+/*
+ * EORSR
+ * Operand Syntax: 	#<data>, CCR
+ *
+ * Operand Size: 8
+ *
+ * X - Changed if bit 4 of immediate operand is one; unchanged otherwise.
+ * N - Changed if bit 3 of immediate operand is one; unchanged otherwise.
+ * Z - Changed if bit 2 of immediate operand is one; unchanged otherwise.
+ * V - Changed if bit 1 of immediate operand is one; unchanged otherwise.
+ * C - Changed if bit 0 of immediate operand is one; unchanged otherwise.
+ *
+ */
+MIDFUNC(2,jff_EORSR,(IM32 s, IM8 x))
+{
+	MRS_NZCV_x(REG_WORK1);
+	if(flags_carry_inverted) {
+		EOR_xxCflag(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+	MOV_xish(REG_WORK2, (s >> 16), 16);
+	EOR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_NZCV_x(REG_WORK1);
+
+	if (x) {
+		int f = rmw(FLAGX);
+		EOR_xxbit(f, f, 0);
+		unlock2(f);
+	}
+}
+MENDFUNC(2,jff_EORSR,(IM32 s, IM8 x))
+
+/*
+ * EXT
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_EXT_b,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (uae_s32)(uae_s8)live.state[d].val;
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_EXT_b,(RW4 d))
+
+MIDFUNC(1,jnf_EXT_w,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (((uae_s32)(uae_s8)live.state[d].val) & 0x0000ffff);
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_EXT_w,(RW4 d))
+
+MIDFUNC(1,jnf_EXT_l,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (uae_s32)(uae_s16)live.state[d].val;
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED16_REG_2_REG(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_EXT_l,(RW4 d))
+
+MIDFUNC(1,jff_EXT_b,(RW4 d))
+{
+	if (isconst(d)) {
+		uae_u8 tmp = (uae_u8)live.state[d].val;
+		d = writereg(d);
+		SIGNED8_IMM_2_REG(d, tmp);
+	} else {
+		d = rmw(d);
+		SIGNED8_REG_2_REG(d, d);
+	}
+
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_EXT_b,(RW4 d))
+
+MIDFUNC(1,jff_EXT_w,(RW4 d))
+{
+	if (isconst(d)) {
+		uae_u8 tmp = (uae_u8)live.state[d].val;
+		d = writereg(d);
+		SIGNED8_IMM_2_REG(REG_WORK1, tmp);
+	} else {
+		d = rmw(d);
+		SIGNED8_REG_2_REG(REG_WORK1, d);
+	}
+
+	TST_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_EXT_w,(RW4 d))
+
+MIDFUNC(1,jff_EXT_l,(RW4 d))
+{
+	if(isconst(d)) {
+		live.state[d].val = (uae_s32)(uae_s16)live.state[d].val;
+		uae_u32 f = 0;
+		if(((uae_s32)live.state[d].val) == 0)
+			f |= (ARM_Z_FLAG >> 16);
+		if(((uae_s32)live.state[d].val) < 0)
+			f |= (ARM_N_FLAG >> 16);
+		MOV_xish(REG_WORK1, f, 16);
+		MSR_NZCV_x(REG_WORK1);
+
+		flags_carry_inverted = false;
+		return;
+	}
+
+	d = rmw(d);
+	SIGNED16_REG_2_REG(d, d);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_EXT_l,(RW4 d))
+
+/*
+ * LSL
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ */
+MIDFUNC(2,jnf_LSL_b_imm,(RW1 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val << i) & 0x000000ff);
+			return;
+		}
+
+		INIT_REG_b(d);
+
+		if(i > 31)
+			i = 31;
+		LSL_wwi(REG_WORK1, d, i);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_LSL_w_imm,(RW2 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val << i) & 0x0000ffff);
+			return;
+		}
+
+		INIT_REG_w(d);
+
+		if(i > 31)
+			i = 31;
+		LSL_wwi(REG_WORK1, d, i);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_LSL_l_imm,(RW4 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = live.state[d].val << i;
+			return;
+		}
+
+		d = rmw(d);
+
+		LSL_wwi(d, d, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_LSL_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSL_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	AND_ww3f(REG_WORK1, i);
+	LSL_www(REG_WORK1, d, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSL_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_LSL_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSL_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	AND_ww3f(REG_WORK1, i);
+	LSL_www(REG_WORK1, d, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSL_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_LSL_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		if(i > 31)
+			set_const(d, 0);
+		else
+			COMPCALL(jnf_LSL_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_ww3f(REG_WORK1, i);
+	LSL_www(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSL_l_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_LSL_b_imm,(RW1 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+		if(i >= 8)
+			MOV_wi(REG_WORK3, 0);
+		else
+			LSL_wwi(REG_WORK3, d, i + 24);
+		TST_ww(REG_WORK3, REG_WORK3);
+
+		if(i <= 8) {
+			TBZ_wii(d, (8 - i), 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+
+		BFXIL_xxii(d, REG_WORK3, 24, 8);
+	} else {
+		d = readreg(d);
+		LSL_wwi(REG_WORK3, d, 24);
+		TST_ww(REG_WORK3, REG_WORK3);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_LSL_w_imm,(RW2 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+		if(i >= 16)
+			MOV_wi(REG_WORK3, 0);
+		else
+			LSL_wwi(REG_WORK3, d, i + 16);
+		TST_ww(REG_WORK3, REG_WORK3);
+
+		if(i <= 16) {
+			TBZ_wii(d, (16 - i), 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+
+		BFXIL_xxii(d, REG_WORK3, 16, 16);
+	} else {
+		d = readreg(d);
+		LSL_wwi(REG_WORK3, d, 16);
+		TST_ww(REG_WORK3, REG_WORK3);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_LSL_l_imm,(RW4 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+		if(i >= 32)
+			MOV_wi(REG_WORK3, 0);
+		else
+			LSL_wwi(REG_WORK3, d, i);
+		TST_ww(REG_WORK3, REG_WORK3);
+
+		if(i <= 32) {
+			TBZ_wii(d, (32 - i), 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+		MOV_ww(d, REG_WORK3);
+	} else {
+		d = readreg(d);
+		TST_ww(d, d);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_LSL_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSL_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	LSL_wwi(REG_WORK3, d, 24);
+	ANDS_ww3f(REG_WORK1, i);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged, C cleared
+
+	// shift count > 0
+	LSL_xxx(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFXIL_xxii(d, REG_WORK2, 24, 8);  // result is ready
+	TST_ww(REG_WORK2, REG_WORK2);     // NZ correct, VC cleared
+
+	// Calculate C Flag
+	TBZ_xii(REG_WORK2, 32, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+	B_i(2);
+
+	// No shift
+	write_jmp_target(branchadd, (uintptr)get_target());
+	TST_ww(REG_WORK3, REG_WORK3);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSL_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_LSL_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSL_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	LSL_wwi(REG_WORK3, d, 16);
+	ANDS_ww3f(REG_WORK1, i);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged, C cleared
+
+	LSL_xxx(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFXIL_xxii(d, REG_WORK2, 16, 16); // result is ready
+	TST_ww(REG_WORK2, REG_WORK2);     // NZ correct, VC cleared
+
+	// Calculate C Flag
+	TBZ_xii(REG_WORK2, 32, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+	B_i(2);
+
+	// No shift
+	write_jmp_target(branchadd, (uintptr)get_target());
+	TST_ww(REG_WORK3, REG_WORK3);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSL_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_LSL_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSL_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	ANDS_ww3f(REG_WORK1, i);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);               // No shift -> X flag unchanged, C cleared
+
+	LSL_xxx(d, d, REG_WORK1);
+	TST_ww(d, d);     // NZ correct, VC cleared
+
+	// Calculate C Flag
+	TBZ_xii(d, 32, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	// Clean upper 32 bits of d after 64-bit LSL_xxx used for carry extraction
+	MOV_ww(d, d);
+
+	B_i(2);
+
+	// No shift
+	write_jmp_target(branchadd, (uintptr)get_target());
+	TST_ww(d, d);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSL_l_reg,(RW4 d, RR4 i))
+
+/*
+ * LSLW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_LSLW,(RW2 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val << 1) & 0xffff;
+		return;
+	}
+
+	d = rmw(d);
+
+	LSL_wwi(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_LSLW,(RW2 d))
+
+MIDFUNC(1,jff_LSLW,(RW2 d))
+{
+	d = rmw(d);
+
+	LSL_wwi(REG_WORK1, d, 17);
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	// Calculate C flag
+	TBZ_wii(d, 15, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	LSL_wwi(d, d, 1);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_LSLW,(RW2 d))
+
+/*
+ * LSR
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ */
+MIDFUNC(2,jnf_LSR_b_imm,(RW1 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val & 0xff) >> i);
+			return;
+		}
+
+		INIT_REG_b(d);
+
+		UNSIGNED8_REG_2_REG(REG_WORK1, d);
+		if(i > 31)
+			i = 31;
+		LSR_wwi(REG_WORK1, REG_WORK1, i);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_LSR_w_imm,(RW2 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val & 0x0000ffff) >> i);
+			return;
+		}
+
+		INIT_REG_w(d);
+
+		UNSIGNED16_REG_2_REG(REG_WORK1, d);
+		if(i > 31)
+			i = 31;
+		LSR_wwi(REG_WORK1, REG_WORK1, i);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_LSR_l_imm,(RW4 d, IM8 i))
+{
+	if(i) {
+		if (isconst(d)) {
+			live.state[d].val = live.state[d].val >> i;
+			return;
+		}
+
+		d = rmw(d);
+
+		LSR_wwi(d, d, i);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_LSR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_LSR_b_imm,(RW1 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+		if(i >= 8)
+			MOV_wi(REG_WORK1, 0);
+		else {
+			UNSIGNED8_REG_2_REG(REG_WORK1, d);
+			LSR_wwi(REG_WORK1, REG_WORK1, i);
+		}
+		TST_ww(REG_WORK1, REG_WORK1);
+
+		if(i <= 8) {
+			TBZ_wii(d, i-1, 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+		BFI_wwii(d, REG_WORK1, 0, 8);
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+		SIGNED8_REG_2_REG(REG_WORK1, d);
+		TST_ww(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_LSR_w_imm,(RW2 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+		if(i >= 16)
+			MOV_wi(REG_WORK1, 0);
+		else {
+			UNSIGNED16_REG_2_REG(REG_WORK1, d);
+			LSR_wwi(REG_WORK1, REG_WORK1, i);
+		}
+		TST_ww(REG_WORK1, REG_WORK1);
+
+		if(i <= 16) {
+			TBZ_wii(d, i-1, 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+		BFI_wwii(d, REG_WORK1, 0, 16);
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+		SIGNED16_REG_2_REG(REG_WORK1, d);
+		TST_ww(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_LSR_l_imm,(RW4 d, IM8 i))
+{
+	if (i) {
+		d = rmw(d);
+		MOV_ww(REG_WORK1, d);
+		LSR_wwi(d, d, i);
+		TST_ww(d, d);
+
+		if(i <= 32) {
+			TBZ_wii(REG_WORK1, i-1, 4);
+			MRS_NZCV_x(REG_WORK4);
+			SET_xxCflag(REG_WORK4, REG_WORK4);
+			MSR_NZCV_x(REG_WORK4);
+		}
+		flags_carry_inverted = false;
+		DUPLICACTE_CARRY
+	} else {
+		d = readreg(d);
+		TST_ww(d, d);
+		flags_carry_inverted = false;
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_LSR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_LSR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSR_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	UNSIGNED8_REG_2_REG(REG_WORK1, d);
+	AND_ww3f(REG_WORK2, i);
+	LSR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_LSR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_LSR_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	UNSIGNED16_REG_2_REG(REG_WORK1, d);
+	AND_ww3f(REG_WORK2, i);
+	LSR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_LSR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		if(i > 31)
+			set_const(d, 0);
+		else
+			COMPCALL(jnf_LSR_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_ww3f(REG_WORK1, i);
+	LSR_www(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_LSR_l_reg,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_LSR_b_reg,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSR_b_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	ANDS_ww3f(REG_WORK1, i);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);                       // No shift -> X flag unchanged
+
+	UNSIGNED8_REG_2_REG(REG_WORK3, d);
+	LSR_www(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 8);
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	// Calculate C Flag
+	SUB_wwi(REG_WORK2, REG_WORK1, 1);
+	LSR_www(REG_WORK2, REG_WORK3, REG_WORK2);
+	TBZ_wii(REG_WORK2, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	B_i(3);
+
+	// No shift
+	write_jmp_target(branchadd, (uintptr)get_target());
+	SIGNED8_REG_2_REG(REG_WORK2, d);        // Make sure, sign is in MSB if shift count is 0 (to get correct N flag)
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSR_b_reg,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_LSR_w_reg,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSR_w_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	ANDS_ww3f(REG_WORK1, i);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);                       // No shift -> X flag unchanged
+
+	UXTH_ww(REG_WORK3, d);                  // Shift count is not 0 -> unsigned required
+	LSR_www(REG_WORK2, REG_WORK3, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 16);
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	// Calculate C Flag
+	SUB_wwi(REG_WORK2, REG_WORK1, 1);
+	LSR_www(REG_WORK2, REG_WORK3, REG_WORK2);
+	TBZ_wii(REG_WORK2, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	B_i(3);
+
+	// No shift
+	write_jmp_target(branchadd, (uintptr)get_target());
+	SIGNED16_REG_2_REG(REG_WORK2, d);       // Make sure, sign is in MSB if shift count is 0 (to get correct N flag)
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSR_w_reg,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_LSR_l_reg,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_LSR_l_imm)(d, live.state[i].val & 0x3f);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	ANDS_ww3f(REG_WORK1, i);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	BEQ_i(0);                       // No shift -> X flag unchanged
+
+	MOV_ww(REG_WORK3, d);
+	LSR_www(d, d, REG_WORK1);
+	TST_ww(d, d);
+
+	// Calculate C Flag
+	SUB_wwi(REG_WORK2, REG_WORK1, 1);
+	LSR_www(REG_WORK2, REG_WORK3, REG_WORK2);
+	TBZ_wii(REG_WORK2, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	B_i(2);
+
+	// No shift
+	write_jmp_target(branchadd, (uintptr)get_target());
+	TST_ww(d, d);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_LSR_l_reg,(RW4 d, RR4 i))
+
+/*
+ * LSRW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit shifted out of the operand. Cleared for a shift count of zero.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_LSRW,(RW2 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = ((live.state[d].val & 0xffff) >> 1);
+		return;
+	}
+
+	d = rmw(d);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	LSR_wwi(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_LSRW,(RW2 d))
+
+MIDFUNC(1,jff_LSRW,(RW2 d))
+{
+	d = rmw(d);
+
+	UNSIGNED16_REG_2_REG(REG_WORK3, d);
+	LSR_wwi(d, REG_WORK3, 1);
+	TST_ww(d, d);
+
+	// Calculate C Flag
+	TBZ_wii(REG_WORK3, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_LSRW,(RW2 d))
+
+/*
+ * MOVE
+ * Operand Syntax: <ea>, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_MOVE_b_imm,(W1 d, IM8 s))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | (s & 0x000000ff);
+		return;
+	}
+
+	d = rmw(d);
+
+	MOV_xi(REG_WORK1, s & 0xff);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MOVE_b_imm,(W1 d, IM8 s))
+
+MIDFUNC(2,jnf_MOVE_w_imm,(W2 d, IM16 s))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (s & 0x0000ffff);
+		return;
+	}
+
+	d = rmw(d);
+
+	// Fix 21: MOVK_xi preserves dirty bits in [63:32]. Use MOVK_wi which
+	// writes to W register, zeroing [63:32] while preserving [31:16].
+	MOVK_wi(d, s & 0xffff);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MOVE_w_imm,(W2 d, IM16 s))
+
+MIDFUNC(2,jnf_MOVE_b,(W1 d, RR1 s))
+{
+	if(s == d)
+		return;
+	if (isconst(s)) {
+		COMPCALL(jnf_MOVE_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	BFI_wwii(d, s, 0, 8);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MOVE_b,(W1 d, RR1 s))
+
+MIDFUNC(2,jnf_MOVE_w,(W2 d, RR2 s))
+{
+	if(s == d)
+		return;
+	if (isconst(s)) {
+		COMPCALL(jnf_MOVE_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	BFI_wwii(d, s, 0, 16);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MOVE_w,(W2 d, RR2 s))
+
+MIDFUNC(2,jnf_MOVE_l,(W4 d, RR4 s))
+{
+	mov_l_rr(d, s);
+}
+MENDFUNC(2,jnf_MOVE_l,(W4 d, RR4 s))
+
+MIDFUNC(2,jff_MOVE_b_imm,(W1 d, IM8 s))
+{
+	d = rmw(d);
+
+	if (s & 0x80) {
+		MOVN_wi(REG_WORK1, (uae_u8) ~s);
+	} else {
+		MOV_xi(REG_WORK1, (uae_u8) s);
+	}
+	TST_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_MOVE_b_imm,(W1 d, IM8 s))
+
+MIDFUNC(2,jff_MOVE_w_imm,(W2 d, IM16 s))
+{
+	if(isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (s & 0x0000ffff);
+		uae_u32 f = 0;
+		if((uae_s16)s == 0)
+			f |= (ARM_Z_FLAG >> 16);
+		if((uae_s16)s < 0)
+			f |= (ARM_N_FLAG >> 16);
+		MOV_xish(REG_WORK1, f, 16);
+		MSR_NZCV_x(REG_WORK1);
+		flags_carry_inverted = false;
+		return;
+	}
+
+	d = rmw(d);
+
+	SIGNED16_IMM_2_REG(REG_WORK1, (uae_u16)s);
+	TST_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_MOVE_w_imm,(W2 d, IM16 s))
+
+MIDFUNC(2,jff_MOVE_l_imm,(W4 d, IM32 s))
+{
+	set_const(d, s);
+	uae_u32 f = 0;
+	if(s == 0)
+		f |= (ARM_Z_FLAG >> 16);
+	if((uae_s32)s < 0)
+		f |= (ARM_N_FLAG >> 16);
+	MOV_xish(REG_WORK1, f, 16);
+	MSR_NZCV_x(REG_WORK1);
+
+	flags_carry_inverted = false;
+}
+MENDFUNC(2,jff_MOVE_l_imm,(W4 d, IM32 s))
+
+MIDFUNC(2,jff_MOVE_b,(W1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_MOVE_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if(!s_is_d) {
+		s = readreg(s);
+		d = rmw(d);
+	} else {
+		s = d = readreg(d);
+	}
+
+	SIGNED8_REG_2_REG(REG_WORK1, s);
+	TST_ww(REG_WORK1, REG_WORK1);
+	if(!s_is_d)
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MOVE_b,(W1 d, RR1 s))
+
+MIDFUNC(2,jff_MOVE_w,(W2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_MOVE_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	if(!s_is_d) {
+		s = readreg(s);
+		d = rmw(d);
+	} else {
+		s = d = readreg(d);
+	}
+
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	TST_ww(REG_WORK1, REG_WORK1);
+	if(!s_is_d)
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MOVE_w,(W2 d, RR2 s))
+
+MIDFUNC(2,jff_MOVE_l,(W4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_MOVE_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	int s_is_d = (s == d);
+	s = readreg(s);
+
+	if(!s_is_d) {
+		d = writereg(d);
+		MOV_ww(d, s);
+	}
+	TST_ww(s, s);
+
+	flags_carry_inverted = false;
+	if(!s_is_d)
+		unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jff_MOVE_l,(W4 d, RR4 s))
+
+/*
+ * MVMEL
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(3,jnf_MVMEL_w,(W4 d, RR4 s, IM8 offset))
+{
+	s = readreg(s);
+	d = writereg(d);
+
+	LDRH_wXi(REG_WORK1, s, offset);
+	REV16_ww(d, REG_WORK1);
+	SXTH_ww(d, d);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(3,jnf_MVMEL_w,(W4 d, RR4 s, IM8 offset))
+
+MIDFUNC(3,jnf_MVMEL_l,(W4 d, RR4 s, IM8 offset))
+{
+	if (s == d || isconst(d) || isinreg(d)) {
+		s = readreg(s);
+		d = writereg(d);
+
+		LDR_wXi(REG_WORK1, s, offset);
+		REV_ww(d, REG_WORK1);
+
+		unlock2(d);
+		unlock2(s);
+	} else {
+		s = readreg(s);
+
+		LDR_wXi(REG_WORK1, s, offset);
+		REV_ww(REG_WORK2, REG_WORK1);
+		uintptr idx = (uintptr)(&regs.regs[d]) - (uintptr) &regs;
+		STR_wXi(REG_WORK2, R_REGSTRUCT, idx);
+
+		unlock2(s);
+	}
+}
+MENDFUNC(3,jnf_MVMEL_l,(W4 d, RR4 s, IM8 offset))
+
+/*
+ * MVMLE
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(3,jnf_MVMLE_w,(RR4 d, RR4 s, IM8 offset))
+{
+	s = readreg(s);
+	d = readreg(d);
+
+	REV16_ww(REG_WORK1, s);
+	STURH_wXi(REG_WORK1, d, offset);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(3,jnf_MVMLE_w,(RR4 d, RR4 s, IM8 offset))
+
+MIDFUNC(3,jnf_MVMLE_l,(RR4 d, RR4 s, IM8 offset))
+{
+	if (s == d || isconst(s) || isinreg(s)) {
+		s = readreg(s);
+		d = readreg(d);
+
+		REV_ww(REG_WORK1, s);
+		STUR_wXi(REG_WORK1, d, offset);
+
+		unlock2(d);
+		unlock2(s);
+	} else {
+		d = readreg(d);
+
+		uintptr idx = (uintptr)(&regs.regs[s]) - (uintptr) &regs;
+		LDR_wXi(REG_WORK2, R_REGSTRUCT, idx);
+		REV_ww(REG_WORK1, REG_WORK2);
+		STUR_wXi(REG_WORK1, d, offset);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(3,jnf_MVMLE_l,(RR4 d, RR4 s, IM8 offset))
+
+/*
+ * MOVE16
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s))
+{
+	s = readreg(s);
+	d = readreg(d);
+
+	CLEAR_LOW4_xx(REG_WORK3, s);
+	CLEAR_LOW4_xx(REG_WORK4, d);
+
+	ADD_xxx(REG_WORK3, REG_WORK3, R_MEMSTART);
+	ADD_xxx(REG_WORK4, REG_WORK4, R_MEMSTART);
+
+	LDP_xxXi(REG_WORK1, REG_WORK2, REG_WORK3, 0);
+	STP_xxXi(REG_WORK1, REG_WORK2, REG_WORK4, 0);
+
+	unlock2(d);
+	unlock2(s);
+}
+MENDFUNC(2,jnf_MOVE16,(RR4 d, RR4 s))
+
+/*
+ * MOVEA
+ * Operand Syntax: 	<ea>, An
+ *
+ * Operand Size: 16,32
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_MOVEA_w_imm,(W4 d, IM16 v))
+{
+	set_const(d, (uae_s32)(uae_s16)v);
+}
+MENDFUNC(2,jnf_MOVEA_w_imm,(W4 d, IM16 v))
+
+MIDFUNC(2,jnf_MOVEA_w,(W4 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_MOVEA_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SIGNED16_REG_2_REG(d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MOVEA_w,(W4 d, RR2 s))
+
+MIDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s))
+{
+	mov_l_rr(d, s);
+}
+MENDFUNC(2,jnf_MOVEA_l,(W4 d, RR4 s))
+
+/*
+ * MULS
+ * Operand Syntax: 	<ea>, Dn
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise. (32 Bit multiply only)
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_MULS,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		uae_s16 tmp = (uae_s16)live.state[s].val;
+		d = rmw(d);
+		SIGNED16_IMM_2_REG(REG_WORK1, tmp);
+		SIGNED16_REG_2_REG(d, d);
+		SMULL_xww(d, d, REG_WORK1);
+		MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+		unlock2(d);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SIGNED16_REG_2_REG(d, d);
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	SMULL_xww(d, d, REG_WORK1);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULS,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULS,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	SIGNED16_REG_2_REG(d, d);
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	SMULL_xww(d, d, REG_WORK1);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULS,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULS32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	SMULL_xww(d, d, s);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULS32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULS32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	SMULL_xww(d, d, s);
+	TST_ww(d, d);
+
+	if (needed_flags & FLAG_V) {
+		LSR_xxi(REG_WORK1, d, 32);
+		CBZ_wi(REG_WORK1, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply (after overflow check reads upper bits)
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULS32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULS64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	SMULL_xww(d, d, s);
+	LSR_xxi(s, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits of d after 64-bit multiply
+
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MULS64,(RW4 d, RW4 s))
+
+MIDFUNC(2,jff_MULS64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	SXTW_xw(REG_WORK1, d);
+	SXTW_xw(REG_WORK2, s);
+	SMULL_xww(d, REG_WORK1, REG_WORK2);
+	TST_xx(d, d);
+	LSR_xxi(s, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits of d after 64-bit multiply
+
+	if (needed_flags & FLAG_V) {
+		// check overflow: no overflow if high part is 0 or 0xffffffff
+		SMULH_xxx(REG_WORK3, REG_WORK1, REG_WORK2);
+		CBZ_xi(REG_WORK3, 6);
+		ADD_wwi(REG_WORK3, REG_WORK3, 1);
+		CBZ_xi(REG_WORK3, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jff_MULS64,(RW4 d, RW4 s))
+
+/*
+ * MULU
+ * Operand Syntax: 	<ea>, Dn
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if overflow. Cleared otherwise. (32 Bit multiply only)
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_MULU,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		uae_u16 tmp = (uae_u16)live.state[s].val;
+		d = rmw(d);
+		UNSIGNED16_IMM_2_REG(REG_WORK1, tmp);
+		UNSIGNED16_REG_2_REG(d, d);
+		UMULL_xww(d, d, REG_WORK1);
+		MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+		unlock2(d);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	UNSIGNED16_REG_2_REG(REG_WORK1, s);
+	UMULL_xww(d, d, REG_WORK1);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULU,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULU,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		uae_u16 tmp = (uae_u16)live.state[s].val;
+		d = rmw(d);
+		UNSIGNED16_IMM_2_REG(REG_WORK1, tmp);
+		UNSIGNED16_REG_2_REG(d, d);
+		UMULL_xww(d, d, REG_WORK1);
+		MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+		TST_ww(d, d);
+		flags_carry_inverted = false;
+		unlock2(d);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	UNSIGNED16_REG_2_REG(d, d);
+	UNSIGNED16_REG_2_REG(REG_WORK1, s);
+	UMULL_xww(d, d, REG_WORK1);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULU,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULU32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	UMULL_xww(d, d, s);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_MULU32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_MULU32,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+
+	UMULL_xww(d, d, s);
+	TST_ww(d, d);
+
+	if (needed_flags & FLAG_V) {
+		LSR_xxi(REG_WORK1, d, 32);
+		CBZ_wi(REG_WORK1, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit multiply (after overflow check reads upper bits)
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_MULU32,(RW4 d, RR4 s))
+
+MIDFUNC(2,jnf_MULU64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	UMULL_xww(d, d, s);
+	LSR_xxi(s, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits of d after 64-bit multiply
+
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jnf_MULU64,(RW4 d, RW4 s))
+
+MIDFUNC(2,jff_MULU64,(RW4 d, RW4 s))
+{
+	s = rmw(s);
+	d = rmw(d);
+
+	if (needed_flags & FLAG_V) {
+		MOV_ww(REG_WORK1, d);
+		MOV_ww(REG_WORK2, s);
+		UMULL_xww(d, REG_WORK1, REG_WORK2);
+	} else {
+		UMULL_xww(d, d, s);
+	}
+	TST_xx(d, d);
+	LSR_xxi(s, d, 32);
+	MOV_ww(d, d); // Clean upper 32 bits of d after 64-bit multiply
+
+	if (needed_flags & FLAG_V) {
+		// check overflow: no overflow if high part is 0
+		UMULH_xxx(REG_WORK3, REG_WORK1, REG_WORK2);
+		CBZ_xi(REG_WORK3, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxVflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(s);
+	unlock2(d);
+}
+MENDFUNC(2,jff_MULU64,(RW4 d, RW4 s))
+
+/*
+ * NEG
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ */
+MIDFUNC(1,jnf_NEG_b,(RW1 d))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	NEG_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NEG_b,(RW1 d))
+
+MIDFUNC(1,jnf_NEG_w,(RW2 d))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	NEG_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NEG_w,(RW2 d))
+
+MIDFUNC(1,jnf_NEG_l,(RW4 d))
+{
+	d = rmw(d);
+
+	NEG_ww(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NEG_l,(RW4 d))
+
+MIDFUNC(1,jff_NEG_b,(RW1 d))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	NEGS_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEG_b,(RW1 d))
+
+MIDFUNC(1,jff_NEG_w,(RW2 d))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	NEGS_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEG_w,(RW2 d))
+
+MIDFUNC(1,jff_NEG_l,(RW4 d))
+{
+	d = rmw(d);
+
+	NEGS_ww(d, d);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEG_l,(RW4 d))
+
+/*
+ * NEGX
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Cleared if the result is nonzero; unchanged otherwise.
+ * V Set if an overflow occurs. Cleared otherwise.
+ * C Set if a borrow occurs. Cleared otherwise.
+ *
+ * Attention: Z is cleared only if the result is nonzero. Unchanged otherwise
+ *
+ */
+MIDFUNC(1,jnf_NEGX_b,(RW1 d))
+{
+	int x = readreg(FLAGX);
+	INIT_REG_b(d);
+	clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	NGC_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	unlock2(d);
+	unlock2(x);
+}
+MENDFUNC(1,jnf_NEGX_b,(RW1 d))
+
+MIDFUNC(1,jnf_NEGX_w,(RW2 d))
+{
+	int x = readreg(FLAGX);
+	INIT_REG_w(d);
+
+	clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	NGC_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	unlock2(d);
+	unlock2(x);
+}
+MENDFUNC(1,jnf_NEGX_w,(RW2 d))
+
+MIDFUNC(1,jnf_NEGX_l,(RW4 d))
+{
+	int x = readreg(FLAGX);
+	d = rmw(d);
+
+	clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	NGC_ww(d, d);
+
+	unlock2(d);
+	unlock2(x);
+}
+MENDFUNC(1,jnf_NEGX_l,(RW4 d))
+
+MIDFUNC(1,jff_NEGX_b,(RW1 d))
+{
+	INIT_REG_b(d);
+	int x = rmw(FLAGX);
+
+	MOVN_xi(REG_WORK2, 0);
+	MOVN_xish(REG_WORK1, 0x4000, 16); // inverse Z flag
+	CSEL_xxxc(REG_WORK2, REG_WORK1, REG_WORK2, NATIVE_CC_NE);
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	NGCS_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	MRS_NZCV_x(REG_WORK4);
+	EOR_xxCflag(REG_WORK4, REG_WORK4);
+	AND_www(REG_WORK4, REG_WORK4, REG_WORK2);
+	MSR_NZCV_x(REG_WORK4);
+	flags_carry_inverted = false;
+	if (needed_flags & FLAG_X)
+		UBFX_wwii(x, REG_WORK4, 29, 1); // Duplicate carry
+
+	unlock2(x);
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEGX_b,(RW1 d))
+
+MIDFUNC(1,jff_NEGX_w,(RW2 d))
+{
+	INIT_REG_w(d);
+	int x = rmw(FLAGX);
+
+	MOVN_xi(REG_WORK2, 0);
+	MOVN_xish(REG_WORK1, 0x4000, 16); // inverse Z flag
+	CSEL_xxxc(REG_WORK2, REG_WORK1, REG_WORK2, NATIVE_CC_NE);
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	NGCS_ww(REG_WORK1, REG_WORK1);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	MRS_NZCV_x(REG_WORK4);
+	EOR_xxCflag(REG_WORK4, REG_WORK4);
+	AND_www(REG_WORK4, REG_WORK4, REG_WORK2);
+	MSR_NZCV_x(REG_WORK4);
+	flags_carry_inverted = false;
+	if (needed_flags & FLAG_X)
+		UBFX_wwii(x, REG_WORK4, 29, 1); // Duplicate carry
+
+	unlock2(x);
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEGX_w,(RW2 d))
+
+MIDFUNC(1,jff_NEGX_l,(RW4 d))
+{
+	d = rmw(d);
+	int x = rmw(FLAGX);
+
+	MOVN_xi(REG_WORK2, 0);
+	MOVN_xish(REG_WORK1, 0x4000, 16); // inverse Z flag
+	CSEL_xxxc(REG_WORK2, REG_WORK1, REG_WORK2, NATIVE_CC_NE);
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	NGCS_ww(d, d);
+
+	MRS_NZCV_x(REG_WORK4);
+	EOR_xxCflag(REG_WORK4, REG_WORK4);
+	AND_www(REG_WORK4, REG_WORK4, REG_WORK2);
+	MSR_NZCV_x(REG_WORK4);
+	flags_carry_inverted = false;
+	if (needed_flags & FLAG_X)
+		UBFX_wwii(x, REG_WORK4, 29, 1); // Duplicate carry
+
+	unlock2(x);
+	unlock2(d);
+}
+MENDFUNC(1,jff_NEGX_l,(RW4 d))
+
+/*
+ * NOT
+ * Operand Syntax: <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_NOT_b,(RW1 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((~live.state[d].val) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+		MVN_ww(REG_WORK1, d);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		MVN_ww(d, d);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NOT_b,(RW1 d))
+
+MIDFUNC(1,jnf_NOT_w,(RW2 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | ((~live.state[d].val) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	if(targetIsReg) {
+		MVN_ww(REG_WORK1, d);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		MVN_ww(d, d);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NOT_w,(RW2 d))
+
+MIDFUNC(1,jnf_NOT_l,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = ~live.state[d].val;
+		return;
+	}
+
+	d = rmw(d);
+
+	MVN_ww(d, d);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_NOT_l,(RW4 d))
+
+MIDFUNC(1,jff_NOT_b,(RW1 d))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	if(targetIsReg) {
+		MVN_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+		TST_ww(REG_WORK1, REG_WORK1);
+	} else {
+		MVN_ww(d, REG_WORK1);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_NOT_b,(RW1 d))
+
+MIDFUNC(1,jff_NOT_w,(RW2 d))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	if(targetIsReg) {
+		MVN_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+		TST_ww(REG_WORK1, REG_WORK1);
+	} else {
+		MVN_ww(d, REG_WORK1);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_NOT_w,(RW2 d))
+
+MIDFUNC(1,jff_NOT_l,(RW4 d))
+{
+	d = rmw(d);
+
+	MVN_ww(d, d);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_NOT_l,(RW4 d))
+
+/*
+ * OR
+ * Operand Syntax: 	<ea>, Dn
+ *  				Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(2,jnf_OR_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | ((live.state[d].val | v) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	MOV_xi(REG_WORK2, v & 0xff);
+	ORR_www(d, d, REG_WORK2);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_OR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_OR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_OR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		ORR_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ORR_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_OR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_OR_w_imm,(RW2 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | ((live.state[d].val | v) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	MOV_xi(REG_WORK1, v & 0xffff);
+	ORR_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_OR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_OR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_OR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		ORR_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		ORR_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_OR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_OR_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val | v;
+		return;
+	}
+
+	d = rmw(d);
+
+	LOAD_U32(REG_WORK1, v);
+	ORR_www(d, d, REG_WORK1);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_OR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_OR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_OR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ORR_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_OR_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_OR_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_IMM_2_REG(REG_WORK2, v);
+	if(targetIsReg) {
+		ORR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		TST_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ORR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_OR_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_OR_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_OR_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	SIGNED8_REG_2_REG(REG_WORK1, d);
+	SIGNED8_REG_2_REG(REG_WORK2, s);
+	if(targetIsReg) {
+		ORR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		TST_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		ORR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_OR_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_OR_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_IMM_2_REG(REG_WORK2, v);
+	if(targetIsReg) {
+		ORR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		TST_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		ORR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_OR_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_OR_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_OR_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SIGNED16_REG_2_REG(REG_WORK1, d);
+	SIGNED16_REG_2_REG(REG_WORK2, s);
+	if(targetIsReg) {
+		ORR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+		TST_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else {
+		ORR_www(d, REG_WORK1, REG_WORK2);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_OR_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_OR_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	LOAD_U32(REG_WORK1, v);
+	ORR_www(d, d, REG_WORK1);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_OR_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_OR_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_OR_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	ORR_www(d, d, s);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_OR_l,(RW4 d, RR4 s))
+
+/*
+ * ORSR
+ * Operand Syntax: 	#<data>, CCR
+ *
+ * Operand Size: 8
+ *
+ * X - Set if bit 4 of immediate operand is one; unchanged otherwise.
+ * N - Set if bit 3 of immediate operand is one; unchanged otherwise.
+ * Z - Set if bit 2 of immediate operand is one; unchanged otherwise.
+ * V - Set if bit 1 of immediate operand is one; unchanged otherwise.
+ * C - Set if bit 0 of immediate operand is one; unchanged otherwise.
+ *
+ */
+MIDFUNC(1,jff_ORSR,(IM32 s, IM8 x))
+{
+	MRS_NZCV_x(REG_WORK1);
+	if (flags_carry_inverted) {
+		EOR_xxCflag(REG_WORK1, REG_WORK1);
+		flags_carry_inverted = false;
+	}
+	MOV_xish(REG_WORK2, (s >> 16), 16);
+	ORR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_NZCV_x(REG_WORK1);
+
+	if (x) {
+		int f = writereg(FLAGX);
+		MOV_wi(f, 1);
+		unlock2(f);
+	}
+}
+MENDFUNC(2,jff_ORSR,(IM32 s, IM8 x))
+
+/*
+ * ROL
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROL_b_imm,(RW1 d, IM8 i))
+{
+	if(i & 0x1f) {
+		INIT_REG_b(d);
+
+		LSL_wwi(REG_WORK1, d, 24);
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+		ROR_wwi(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_ROL_w_imm,(RW2 d, IM8 i))
+{
+	if(i & 0x1f) {
+		INIT_REG_w(d);
+
+		MOV_ww(REG_WORK1, d);
+		BFI_wwii(REG_WORK1, REG_WORK1, 16, 16);
+		ROR_wwi(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_ROL_l_imm,(RW4 d, IM8 i))
+{
+	if(i & 0x1f) {
+		if (isconst(d)) {
+			i = i & 31;
+			live.state[d].val = (live.state[d].val << i) | (live.state[d].val >> (32-i));
+			return;
+		}
+
+		d = rmw(d);
+
+		ROR_wwi(d, d, (32 - (i & 0x1f)));
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROL_l_imm,(RW4 d, RR4 s, IM8 i))
+
+MIDFUNC(2,jff_ROL_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	if (i) {
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+		if(i & 0x1f) {
+			ROR_wwi(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+		}
+		TST_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		MRS_NZCV_x(REG_WORK4);
+		BFI_wwii(REG_WORK4, REG_WORK1, 29, 1); // Handle C flag
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		TST_ww(REG_WORK1, REG_WORK1);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROL_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ROL_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	MOV_ww(REG_WORK1, d);
+	BFI_wwii(REG_WORK1, REG_WORK1, 16, 16);
+	if (i) {
+		if(i & 0x1f)
+			ROR_wwi(REG_WORK1, REG_WORK1, (32 - (i & 0x1f)));
+		TST_ww(REG_WORK1, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+		MRS_NZCV_x(REG_WORK4);
+		BFI_wwii(REG_WORK4, REG_WORK1, 29, 1); // Handle C flag
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		TST_ww(REG_WORK1, REG_WORK1);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROL_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ROL_l_imm,(RW4 d, IM8 i))
+{
+	if (i) {
+		if(i & 0x1f) {
+			d = rmw(d);
+			ROR_wwi(d, d, (32 - (i & 0x1f)));
+		} else {
+			d = readreg(d);
+		}
+		TST_ww(d, d);
+
+		MRS_NZCV_x(REG_WORK4);
+		BFI_wwii(REG_WORK4, d, 29, 1); // Handle C flag
+		MSR_NZCV_x(REG_WORK4);
+	} else {
+		d = readreg(d);
+		TST_ww(d, d);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROL_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_ROL_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROL_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	UBFIZ_xxii(REG_WORK1, i, 0, 5); // AND_rri(REG_WORK1, i, 0x1f);
+	MOV_wi(REG_WORK2, 32);
+	SUB_www(REG_WORK1, REG_WORK2, REG_WORK1);
+
+	LSL_wwi(REG_WORK2, d, 24);
+	ORR_wwwLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 8);
+	ORR_wwwLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 16);
+	ROR_www(REG_WORK2, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 8);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROL_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROL_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	UBFIZ_xxii(REG_WORK1, i, 0, 5); // AND_rri(REG_WORK1, i, 0x1f);
+	MOV_wi(REG_WORK2, 32);
+	SUB_www(REG_WORK1, REG_WORK2, REG_WORK1);
+
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, REG_WORK2, 16, 16);
+	ROR_www(REG_WORK2, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 16);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROL_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROL_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	UBFIZ_xxii(REG_WORK1, i, 0, 5); // AND_rri(REG_WORK1, i, 0x1f);
+	MOV_wi(REG_WORK2, 32);
+	SUB_www(REG_WORK1, REG_WORK2, REG_WORK1);
+
+	ROR_www(d, d, REG_WORK1);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROL_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROL_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROL_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	UBFIZ_xxii(REG_WORK1, i, 0, 5); // AND_rri(REG_WORK1, i, 0x1f);
+	CBNZ_wi(REG_WORK1, 4);
+
+	// shift count is 0
+	LSL_wwi(REG_WORK3, d, 24);
+	TST_ww(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	MOV_wi(REG_WORK2, 32);
+	SUB_www(REG_WORK1, REG_WORK2, REG_WORK1);
+
+	LSL_wwi(REG_WORK2, d, 24);
+	ORR_wwwLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 8);
+	ORR_wwwLSRi(REG_WORK2, REG_WORK2, REG_WORK2, 16);
+	ROR_www(REG_WORK2, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 8);
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	MRS_NZCV_x(REG_WORK4);
+	BFI_wwii(REG_WORK4, d, 29, 1); // Handle C flag
+	MSR_NZCV_x(REG_WORK4);
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROL_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROL_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	UBFIZ_xxii(REG_WORK1, i, 0, 5); // AND_rri(REG_WORK1, i, 0x1f);
+	CBNZ_wi(REG_WORK1, 4);
+
+	// shift count is 0
+	LSL_wwi(REG_WORK3, d, 16);
+	TST_ww(REG_WORK3, REG_WORK3);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	MOV_wi(REG_WORK2, 32);
+	SUB_www(REG_WORK1, REG_WORK2, REG_WORK1);
+
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, REG_WORK2, 16, 16);
+	ROR_www(REG_WORK2, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 16);
+	TST_ww(REG_WORK2, REG_WORK2);
+
+	MRS_NZCV_x(REG_WORK4);
+	BFI_wwii(REG_WORK4, d, 29, 1); // Handle C flag
+	MSR_NZCV_x(REG_WORK4);
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROL_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROL_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	UBFIZ_xxii(REG_WORK1, i, 0, 5); // AND_rri(REG_WORK1, i, 0x1f);
+	CBNZ_wi(REG_WORK1, 3);
+
+	// shift count is 0
+	TST_ww(d, d);     // NZ correct, VC cleared
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0); // <end>
+
+	MOV_wi(REG_WORK2, 32);
+	SUB_www(REG_WORK1, REG_WORK2, REG_WORK1);
+
+	ROR_www(d, d, REG_WORK1);
+	TST_ww(d, d);
+
+	MRS_NZCV_x(REG_WORK4);
+	BFI_wwii(REG_WORK4, d, 29, 1); // Handle C flag
+	MSR_NZCV_x(REG_WORK4);
+
+	// <end>
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(d);
+	unlock2(i);
+}
+MENDFUNC(2,jff_ROL_l,(RW4 d, RR4 i))
+
+/*
+ * ROLW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_ROLW,(RW2 d))
+{
+	d = rmw(d);
+
+	BFI_wwii(d, d, 16, 16);
+	ROR_wwi(d, d, (32 - 1));
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_ROLW,(RW2 d))
+
+MIDFUNC(1,jff_ROLW,(RW2 d))
+{
+	d = rmw(d);
+
+	BFI_wwii(d, d, 16, 16);
+	ROR_wwi(d, d, (32 - 1));
+	TST_ww(d, d);
+
+	MRS_NZCV_x(REG_WORK4);
+	BFI_wwii(REG_WORK4, d, 29, 1); // Handle C flag
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_ROLW,(RW2 d))
+
+/*
+ * ROXL
+ * Operand Syntax: Dx, Dy
+ * 				   #<data>, Dy
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit rotated out of the operand. Unchanged when the rotate count is zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROXL_b,(RW1 d, RR4 i))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_b(d, i);
+
+	clobber_flags();
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 35);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 36);
+	CMP_wi(REG_WORK1, 17);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 18);
+	CMP_wi(REG_WORK1, 8);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 9);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 8, 1);         // move x to left side of d
+	BFI_wwii(REG_WORK2, REG_WORK2, 9, 9); // duplicate 9 bits
+
+	MOV_wi(REG_WORK3, 9);
+	SUB_www(REG_WORK3, REG_WORK3, REG_WORK1);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK3);
+
+	BFI_wwii(d, REG_WORK2, 0, 8);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXL_w,(RW2 d, RR4 i))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_w(d, i);
+
+	clobber_flags();
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 33);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 34);
+	CMP_wi(REG_WORK1, 16);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 17);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 16, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 17, 17); // duplicate 17 bits
+
+	MOV_wi(REG_WORK3, 17);
+	SUB_www(REG_WORK3, REG_WORK3, REG_WORK1);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+
+	BFI_wwii(d, REG_WORK2, 0, 16);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXL_l,(RW4 d, RR4 i))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_l(d, i);
+
+	clobber_flags();
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 32);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 33);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_xxii(REG_WORK2, x, 32, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 33, 31); // duplicate 31 bits
+
+	MOV_wi(REG_WORK3, 33);
+	SUB_www(REG_WORK3, REG_WORK3, REG_WORK1);
+	LSR_xxx(d, REG_WORK2, REG_WORK3);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit LSR_xxx
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXL_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROXL_b,(RW1 d, RR4 i))
+{
+	INIT_REGS_b(d, i);
+	int x = rmw(FLAGX);
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 35);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 36);
+	CMP_wi(REG_WORK1, 17);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 18);
+	CMP_wi(REG_WORK1, 8);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 9);
+	CBNZ_wi(REG_WORK1, 4);			// need to rotate
+
+	LSL_wwi(REG_WORK1, d, 24);
+	TST_ww(REG_WORK1, REG_WORK1);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 8, 1);         // move x to left side of d
+	BFI_wwii(REG_WORK2, REG_WORK2, 9, 9); // duplicate 9 bits
+
+	MOV_wi(REG_WORK3, 9);
+	SUB_www(REG_WORK3, REG_WORK3, REG_WORK1);
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK3);
+	BFI_wwii(d, REG_WORK2, 0, 8);
+
+	// Calculate NZ
+	LSL_wwi(REG_WORK1, REG_WORK2, 24);
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	// Calculate C: bit left of result
+	MRS_NZCV_x(REG_WORK4);
+	UBFX_wwii(x, REG_WORK2, 8, 1);
+	BFI_wwii(REG_WORK4, x, 29, 1);
+	MSR_NZCV_x(REG_WORK4);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXL_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROXL_w,(RW2 d, RR4 i))
+{
+	INIT_REGS_w(d, i);
+	int x = rmw(FLAGX);
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 33);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 34);
+	CMP_wi(REG_WORK1, 16);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 17);
+	CBNZ_wi(REG_WORK1, 4);			// need to rotate
+
+	LSL_wwi(REG_WORK1, d, 16);
+	TST_ww(REG_WORK1, REG_WORK1);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 16, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 17, 17); // duplicate 17 bits
+
+	MOV_wi(REG_WORK3, 17);
+	SUB_www(REG_WORK3, REG_WORK3, REG_WORK1);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+
+	BFI_wwii(d, REG_WORK2, 0, 16);
+
+	// Calculate NZ
+	LSL_wwi(REG_WORK1, REG_WORK2, 16);
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	// Calculate C: bit left of result
+	MRS_NZCV_x(REG_WORK4);
+	UBFX_wwii(x, REG_WORK2, 16, 1);
+	BFI_wwii(REG_WORK4, x, 29, 1);
+	MSR_NZCV_x(REG_WORK4);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXL_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROXL_l,(RW4 d, RR4 i))
+{
+	INIT_REGS_l(d, i);
+	int x = rmw(FLAGX);
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 32);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 33);
+	CBNZ_wi(REG_WORK1, 3);			// need to rotate
+
+	TST_ww(d, d);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_xxii(REG_WORK2, x, 32, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 33, 31); // duplicate 31 bits
+
+	MOV_wi(REG_WORK3, 33);
+	SUB_www(REG_WORK3, REG_WORK3, REG_WORK1);
+	LSR_xxx(d, REG_WORK2, REG_WORK3);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit LSR_xxx
+
+	// Calculate NZ
+	TST_ww(d, d);
+
+	// Calculate C
+	MRS_NZCV_x(REG_WORK4);
+	SUB_wwi(REG_WORK3, REG_WORK3, 1);
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK3);
+	UBFX_wwii(x, REG_WORK2, 0, 1);
+	BFI_wwii(REG_WORK4, x, 29, 1);
+	MSR_NZCV_x(REG_WORK4);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXL_l,(RW4 d, RR4 i))
+
+/*
+ * ROR
+ * Operand Syntax: 	Dx, Dy
+ * 					#<data>, Dy
+ *					<ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROR_b_imm,(RW1 d, IM8 i))
+{
+	if(i & 0x07) {
+		INIT_REG_b(d);
+
+		MOV_ww(REG_WORK1, d);
+		BFI_wwii(REG_WORK1, REG_WORK1, 8, 8);
+		ROR_wwi(REG_WORK1, REG_WORK1, i & 0x07);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jnf_ROR_w_imm,(RW2 d, IM8 i))
+{
+	if(i & 0x0f) {
+		INIT_REG_w(d);
+
+		MOV_ww(REG_WORK1, d);
+		BFI_wwii(REG_WORK1, REG_WORK1, 16, 16);
+		ROR_wwi(REG_WORK1, REG_WORK1, i & 0x0f);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jnf_ROR_l_imm,(RW4 d, IM8 i))
+{
+	if(i & 0x1f) {
+		if (isconst(d)) {
+			i = i & 31;
+			live.state[d].val = (live.state[d].val >> i) | (live.state[d].val << (32-i));
+			return;
+		}
+
+		d = rmw(d);
+
+		ROR_wwi(d, d, i & 31);
+
+		unlock2(d);
+	}
+}
+MENDFUNC(2,jnf_ROR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jff_ROR_b_imm,(RW1 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	if(i & 0x07) {
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+		ROR_wwi(REG_WORK1, REG_WORK1, i & 0x07);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	}
+	TST_ww(REG_WORK1, REG_WORK1);
+	if(i) {
+		TBZ_wii(REG_WORK1, 31, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROR_b_imm,(RW1 d, IM8 i))
+
+MIDFUNC(2,jff_ROR_w_imm,(RW2 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	LSL_wwi(REG_WORK1, d, 16);
+	if(i & 0x0f) {
+		ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+		ROR_wwi(REG_WORK1, REG_WORK1, i & 0x0f);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	}
+	TST_ww(REG_WORK1, REG_WORK1);
+	if (i) {
+		TBZ_wii(REG_WORK1, 31, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROR_w_imm,(RW2 d, IM8 i))
+
+MIDFUNC(2,jff_ROR_l_imm,(RW4 d, IM8 i))
+{
+	if(i)
+		d = rmw(d);
+	else
+		d = readreg(d);
+
+	if(i & 0x1f) {
+		ROR_wwi(d, d, i & 0x1f);
+	}
+	TST_ww(d, d);
+	if (i) {
+		TBZ_wii(d, 31, 4);
+		MRS_NZCV_x(REG_WORK4);
+		SET_xxCflag(REG_WORK4, REG_WORK4);
+		MSR_NZCV_x(REG_WORK4);
+	}
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(2,jff_ROR_l_imm,(RW4 d, IM8 i))
+
+MIDFUNC(2,jnf_ROR_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROR_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	ROR_www(REG_WORK1, REG_WORK1, i);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROR_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROR_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	LSL_wwi(REG_WORK1, d, 16);
+	ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	ROR_www(REG_WORK1, REG_WORK1, i);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROR_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jnf_ROR_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	ROR_www(d, d, i);
+
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROR_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROR_b,(RW1 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROR_b_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_b(d, i);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 8);
+	ORR_wwwLSRi(REG_WORK1, REG_WORK1, REG_WORK1, 16);
+	AND_ww3f(REG_WORK2, i);
+	ROR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFI_wwii(d, REG_WORK1, 0, 8);
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	CBZ_wi(REG_WORK2, 5); // C cleared if no shift
+	TBZ_wii(REG_WORK1, 31, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROR_w,(RW2 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROR_w_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_w(d, i);
+
+	LSL_wwi(REG_WORK1, d, 16);
+	BFXIL_wwii(REG_WORK1, REG_WORK1, 16, 16);
+	AND_ww3f(REG_WORK2, i);
+	ROR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFI_wwii(d, REG_WORK1, 0, 16);
+	TST_ww(REG_WORK1, REG_WORK1);
+
+	CBZ_wi(REG_WORK2, 5); // C cleared if no shift
+	TBZ_wii(REG_WORK1, 31, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROR_l,(RW4 d, RR4 i))
+{
+	if (isconst(i)) {
+		COMPCALL(jff_ROR_l_imm)(d, (uae_u8)live.state[i].val);
+		return;
+	}
+
+	INIT_REGS_l(d, i);
+
+	AND_ww3f(REG_WORK1, i);
+	ROR_www(d, d, REG_WORK1);
+	TST_ww(d, d);
+
+	CBZ_wi(REG_WORK1, 5); // C cleared if no shift
+	TBZ_wii(d, 31, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROR_l,(RW4 d, RR4 i))
+
+/*
+ * RORW
+ * Operand Syntax: 	<ea>
+ *
+ * Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand.
+ *
+ * Target is never a register.
+ */
+MIDFUNC(1,jnf_RORW,(RW2 d))
+{
+	d = rmw(d);
+
+	BFI_wwii(d, d, 16, 16);
+	ROR_wwi(d, d, 1);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_RORW,(RW2 d))
+
+MIDFUNC(1,jff_RORW,(RW2 d))
+{
+	d = rmw(d);
+
+	BFI_wwii(d, d, 16, 16);
+	ROR_wwi(d, d, 1);
+	TST_ww(d, d);
+
+	TBZ_wii(d, 31, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_RORW,(RW2 d))
+
+/*
+ * ROXR
+ * Operand Syntax: Dx, Dy
+ * 				   #<data>, Dy
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set according to the last bit rotated out of the operand. Unchanged when the rotate count is zero.
+ * N Set if the most significant bit of the result is set. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
+ *
+ */
+MIDFUNC(2,jnf_ROXR_b,(RW1 d, RR4 i))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_b(d, i);
+
+	clobber_flags();
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 35);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 36);
+	CMP_wi(REG_WORK1, 17);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 18);
+	CMP_wi(REG_WORK1, 8);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 9);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 8, 1);         // move x to left side of d
+	BFI_wwii(REG_WORK2, REG_WORK2, 9, 9); // duplicate 9 bits
+
+	LSR_www(REG_WORK2, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 8);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXR_w,(RW2 d, RR4 i))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_w(d, i);
+
+	clobber_flags();
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 33);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 34);
+	CMP_wi(REG_WORK1, 16);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 17);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 16, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 17, 17); // duplicate 17 bits
+
+	LSR_xxx(REG_WORK2, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK2, 0, 16);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jnf_ROXR_l,(RW4 d, RR4 i))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_l(d, i);
+
+	clobber_flags();
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 32);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 33);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	CBZ_wi(REG_WORK1, 0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_xxii(REG_WORK2, x, 32, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 33, 31); // duplicate 31 bits
+
+	LSR_xxx(d, REG_WORK2, REG_WORK1);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit LSR_xxx
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jnf_ROXR_l,(RW4 d, RR4 i))
+
+MIDFUNC(2,jff_ROXR_b,(RW1 d, RR4 i))
+{
+	INIT_REGS_b(d, i);
+	int x = rmw(FLAGX);
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 35);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 36);
+	CMP_wi(REG_WORK1, 17);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 18);
+	CMP_wi(REG_WORK1, 8);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 9);
+	CBNZ_wi(REG_WORK1, 4);			// need to rotate
+
+	LSL_wwi(REG_WORK1, d, 24);
+	TST_ww(REG_WORK1, REG_WORK1);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 8, 1);         // move x to left side of d
+	BFI_wwii(REG_WORK2, REG_WORK2, 9, 9); // duplicate 9 bits
+
+	LSR_www(REG_WORK3, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK3, 0, 8);
+
+	// calc N and Z
+	LSL_wwi(REG_WORK3, REG_WORK3, 24);
+	TST_ww(REG_WORK3, REG_WORK3);
+
+	// calc C and X
+	SUB_wwi(REG_WORK1, REG_WORK1, 1);
+	LSR_www(REG_WORK3, REG_WORK2, REG_WORK1);
+	UBFIZ_wwii(x, REG_WORK3, 0, 1);
+	TBZ_wii(x, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXR_b,(RW1 d, RR4 i))
+
+MIDFUNC(2,jff_ROXR_w,(RW2 d, RR4 i))
+{
+	INIT_REGS_w(d, i);
+	int x = rmw(FLAGX);
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 33);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 34);
+	CMP_wi(REG_WORK1, 16);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 17);
+	CBNZ_wi(REG_WORK1, 4);			// need to rotate
+
+	LSL_wwi(REG_WORK1, d, 16);
+	TST_ww(REG_WORK1, REG_WORK1);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_wwii(REG_WORK2, x, 16, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 17, 17); // duplicate 17 bits
+
+	LSR_xxx(REG_WORK3, REG_WORK2, REG_WORK1);
+	BFI_wwii(d, REG_WORK3, 0, 16);
+
+	// calc N and Z
+	LSL_wwi(REG_WORK3, REG_WORK3, 16);
+	TST_ww(REG_WORK3, REG_WORK3);
+
+	// calc C and X
+	SUB_wwi(REG_WORK1, REG_WORK1, 1);
+	LSR_www(REG_WORK3, REG_WORK2, REG_WORK1);
+	UBFIZ_wwii(x, REG_WORK3, 0, 1);
+	TBZ_wii(x, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXR_w,(RW2 d, RR4 i))
+
+MIDFUNC(2,jff_ROXR_l,(RW4 d, RR4 i))
+{
+	INIT_REGS_l(d, i);
+	int x = rmw(FLAGX);
+
+	AND_ww3f(REG_WORK1, i);
+	CMP_wi(REG_WORK1, 32);
+	BLE_i(2);
+	SUB_wwi(REG_WORK1, REG_WORK1, 33);
+	CBNZ_wi(REG_WORK1, 3);			// need to rotate
+
+	TST_ww(d, d);
+	uae_u32* branchadd = (uae_u32*)get_target();
+	B_i(0);			// end of op
+
+	// need to rotate
+	MOV_ww(REG_WORK2, d);
+	BFI_xxii(REG_WORK2, x, 32, 1);          // move x to left side of d
+	BFI_xxii(REG_WORK2, REG_WORK2, 33, 31); // duplicate 31 bits
+
+	LSR_xxx(d, REG_WORK2, REG_WORK1);
+	MOV_ww(d, d); // Clean upper 32 bits after 64-bit LSR_xxx
+
+	// Calculate NZ
+	TST_ww(d, d);
+
+	// Calculate C
+	SUB_wwi(REG_WORK1, REG_WORK1, 1);
+	LSR_xxx(REG_WORK3, REG_WORK2, REG_WORK1);
+	UBFIZ_wwii(x, REG_WORK3, 0, 1);
+	TBZ_wii(x, 0, 4);
+	MRS_NZCV_x(REG_WORK4);
+	SET_xxCflag(REG_WORK4, REG_WORK4);
+	MSR_NZCV_x(REG_WORK4);
+
+	// end of op
+	write_jmp_target(branchadd, (uintptr)get_target());
+
+	flags_carry_inverted = false;
+	unlock2(x);
+	EXIT_REGS(d, i);
+}
+MENDFUNC(2,jff_ROXR_l,(RW4 d, RR4 i))
+
+/*
+ * SCC
+ *
+ */
+MIDFUNC(2,jnf_SCC,(W1 d, IM8 cc))
+{
+	FIX_INVERTED_CARRY
+
+	INIT_WREG_b(d);
+
+	switch (cc) {
+		case 9: // LS
+			CSETM_wc(REG_WORK1, NATIVE_CC_CS);
+			CSETM_wc(REG_WORK2, NATIVE_CC_EQ);
+			ORR_www(REG_WORK1, REG_WORK1, REG_WORK2);
+			break;
+
+		case 8: // HI
+			CSETM_wc(REG_WORK1, NATIVE_CC_CC);
+			CSETM_wc(REG_WORK2, NATIVE_CC_NE);
+			AND_www(REG_WORK1, REG_WORK1, REG_WORK2);
+			break;
+
+		default:
+			CSETM_wc(REG_WORK1, cc);
+			break;
+	}
+	BFI_wwii(d, REG_WORK1, 0, 8);
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SCC,(W1 d, IM8 cc))
+
+/*
+ * SUB
+ * Operand Syntax: 	<ea>, Dn
+ * 					Dn, <ea>
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Set if the result is zero. Cleared otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ */
+MIDFUNC(2,jnf_SUB_b_imm,(RW1 d, IM8 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffffff00) | (((live.state[d].val & 0xff) - (v & 0xff)) & 0x000000ff);
+		return;
+	}
+
+	INIT_REG_b(d);
+
+	if(targetIsReg) {
+		SUB_wwi(REG_WORK1, d, v & 0xff);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		SUB_wwi(d, d, v & 0xff);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUB_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jnf_SUB_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUB_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	if(targetIsReg) {
+		SUB_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 8);
+	} else {
+		SUB_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUB_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_SUB_w_imm,(RW2 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val & 0xffff0000) | (((live.state[d].val & 0xffff) - (v & 0xffff)) & 0x0000ffff);
+		return;
+	}
+
+	INIT_REG_w(d);
+
+	UNSIGNED16_IMM_2_REG(REG_WORK1, (uae_u16)v);
+	if(targetIsReg) {
+		SUB_www(REG_WORK1, d, REG_WORK1);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else{
+		SUB_www(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUB_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jnf_SUB_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUB_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	if(targetIsReg) {
+		SUB_www(REG_WORK1, d, s);
+		BFI_wwii(d, REG_WORK1, 0, 16);
+	} else{
+		SUB_www(d, d, s);
+	}
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUB_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_SUB_l_imm,(RW2 d, IM32 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val - v;
+		return;
+	}
+
+	d = rmw(d);
+
+	if(v >= 0 && v < 4096) {
+		SUB_wwi(d, d, v);
+	} else {
+		LOAD_U32(REG_WORK1, v);
+		SUB_www(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUB_l_imm,(RW2 d, IM32 v))
+
+MIDFUNC(2,jnf_SUB_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUB_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SUB_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUB_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_SUB_b_imm,(RW1 d, IM8 v))
+{
+	INIT_REG_b(d);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	MOV_wish(REG_WORK2, (v & 0xff) << 8, 16);
+	SUBS_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFXIL_xxii(d, REG_WORK1, 24, 8);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_SUB_b_imm,(RW1 d, IM8 v))
+
+MIDFUNC(2,jff_SUB_b,(RW1 d, RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_SUB_b_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_b(d, s);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	SUBS_wwwLSLi(REG_WORK1, REG_WORK1, s, 24);
+	BFXIL_xxii(d, REG_WORK1, 24, 8);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUB_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_SUB_w_imm,(RW2 d, IM16 v))
+{
+	INIT_REG_w(d);
+
+	MOV_xi(REG_WORK1, v);
+	LSL_wwi(REG_WORK2, d, 16);
+	SUBS_wwwLSLi(REG_WORK1, REG_WORK2, REG_WORK1, 16);
+	BFXIL_xxii(d, REG_WORK1, 16, 16);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_SUB_w_imm,(RW2 d, IM16 v))
+
+MIDFUNC(2,jff_SUB_w,(RW2 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_SUB_w_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	LSL_wwi(REG_WORK1, d, 16);
+	SUBS_wwwLSLi(REG_WORK1, REG_WORK1, s, 16);
+	BFXIL_xxii(d, REG_WORK1, 16, 16);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUB_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_SUB_l_imm,(RW4 d, IM32 v))
+{
+	d = rmw(d);
+
+	if(v >= 0 && v < 4096) {
+		SUBS_wwi(d, d, v);
+	} else {
+		LOAD_U32(REG_WORK1, v);
+		SUBS_www(d, d, REG_WORK1);
+	}
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	unlock2(d);
+}
+MENDFUNC(2,jff_SUB_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jff_SUB_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_SUB_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SUBS_www(d, d, s);
+
+	flags_carry_inverted = true;
+	DUPLICACTE_CARRY
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUB_l,(RW4 d, RR4 s))
+
+/*
+ * SUBA
+ *
+ * Operand Syntax: 	<ea>, Dn
+ *
+ * Operand Size: 16,32
+ *
+ * Flags: Not affected.
+ *
+ */
+MIDFUNC(2,jnf_SUBA_w_imm,(RW4 d, IM16 v))
+{
+	if (isconst(d)) {
+		live.state[d].val = live.state[d].val - (uae_s32)(uae_s16)v;
+		return;
+	}
+
+	d = rmw(d);
+	if(v >= 0 && v < 4096) {
+		SUB_wwi(d, d, v);
+	} else {
+		SIGNED16_IMM_2_REG(REG_WORK1, v);
+		SUB_www(d, d, REG_WORK1);
+	}
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUBA_w_imm,(RW4 d, IM16 v))
+
+MIDFUNC(2,jnf_SUBA_w,(RW4 d, RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUBA_w_imm)(d, live.state[s].val & 0xffff);
+		return;
+	}
+
+	INIT_REGS_w(d, s);
+
+	SUB_wwwEX(d, d, s, EX_SXTH);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBA_w,(RW4 d, RR2 s))
+
+MIDFUNC(2,jnf_SUBA_l_imm,(RW4 d, IM32 v))
+{
+	if (isconst(d)) {
+		set_const(d, live.state[d].val - v);
+		return;
+	}
+
+	d = rmw(d);
+
+	if(v >= 0 && v < 4096) {
+		SUB_wwi(d, d, v);
+	} else {
+		LOAD_U32(REG_WORK1, v);
+		SUB_www(d, d, REG_WORK1);
+	}
+
+	unlock2(d);
+}
+MENDFUNC(2,jnf_SUBA_l_imm,(RW4 d, IM32 v))
+
+MIDFUNC(2,jnf_SUBA_l,(RW4 d, RR4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jnf_SUBA_l_imm)(d, live.state[s].val);
+		return;
+	}
+
+	INIT_REGS_l(d, s);
+
+	SUB_www(d, d, s);
+
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBA_l,(RW4 d, RR4 s))
+
+/*
+ * SUBX
+ * Operand Syntax: 	Dy, Dx
+ * 					-(Ay), -(Ax)
+ *
+ * Operand Size: 8,16,32
+ *
+ * X Set the same as the carry bit.
+ * N Set if the result is negative. Cleared otherwise.
+ * Z Cleared if the result is nonzero. Unchanged otherwise.
+ * V Set if an overflow is generated. Cleared otherwise.
+ * C Set if a carry is generated. Cleared otherwise.
+ *
+ * Attention: Z is cleared only if the result is nonzero. Unchanged otherwise
+ *
+ */
+MIDFUNC(2,jnf_SUBX_b,(RW1 d, RR1 s))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_b(d, s);
+
+	clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	LSL_wwi(REG_WORK2, s, 24);
+	SBC_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFXIL_wwii(d, REG_WORK1, 24, 8);
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jnf_SUBX_w,(RW2 d, RR2 s))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_w(d, s);
+
+	clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	LSL_wwi(REG_WORK1, d, 16);
+	LSL_wwi(REG_WORK2, s, 16);
+	SBC_www(REG_WORK1, REG_WORK1, REG_WORK2);
+	BFXIL_wwii(d, REG_WORK1, 16, 16);
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jnf_SUBX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jnf_SUBX_l,(RW4 d, RR4 s))
+{
+	int x = readreg(FLAGX);
+	INIT_REGS_l(d, s);
+
+	clobber_flags();
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	SBC_www(d, d, s);
+
+	EXIT_REGS(d, s);
+	unlock2(x);
+}
+MENDFUNC(2,jnf_SUBX_l,(RW4 d, RR4 s))
+
+MIDFUNC(2,jff_SUBX_b,(RW1 d, RR1 s))
+{
+	INIT_REGS_b(d, s);
+	int x = rmw(FLAGX);
+
+	if (needed_flags & FLAG_Z) {
+		MOVN_xi(REG_WORK2, 0);
+		MOVN_xish(REG_WORK1, 0x4000, 16); // inverse Z flag
+		CSEL_xxxc(REG_WORK2, REG_WORK1, REG_WORK2, NATIVE_CC_NE);
+	}
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	LSL_wwi(REG_WORK1, d, 24);
+	LSL_wwi(REG_WORK3, s, 24);
+	SBCS_www(REG_WORK1, REG_WORK1, REG_WORK3);
+	BFXIL_wwii(d, REG_WORK1, 24, 8);
+
+	MRS_NZCV_x(REG_WORK1);
+	EOR_xxCflag(REG_WORK1, REG_WORK1);
+
+	if (needed_flags & FLAG_Z) {
+		// Fix Z flag: SBCS Z may be wrong when borrow propagates through lower zero bits.
+		UBFX_wwii(REG_WORK3, d, 0, 8);
+		CMP_wi(REG_WORK3, 0);
+		SET_xxZflag(REG_WORK3, REG_WORK1);
+		CSEL_xxxc(REG_WORK1, REG_WORK3, REG_WORK1, NATIVE_CC_EQ);
+		AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2); // apply SUBX sticky-Z
+	}
+	MSR_NZCV_x(REG_WORK1);
+	flags_carry_inverted = false;
+	if (needed_flags & FLAG_X)
+		UBFX_xxii(x, REG_WORK1, 29, 1); // Duplicate carry
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUBX_b,(RW1 d, RR1 s))
+
+MIDFUNC(2,jff_SUBX_w,(RW2 d, RR2 s))
+{
+	INIT_REGS_w(d, s);
+	int x = rmw(FLAGX);
+
+	if (needed_flags & FLAG_Z) {
+		MOVN_xi(REG_WORK2, 0);
+		MOVN_xish(REG_WORK1, 0x4000, 16); // inverse Z flag
+		CSEL_xxxc(REG_WORK2, REG_WORK1, REG_WORK2, NATIVE_CC_NE);
+	}
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	LSL_wwi(REG_WORK1, d, 16);
+	LSL_wwi(REG_WORK3, s, 16);
+	SBCS_www(REG_WORK1, REG_WORK1, REG_WORK3);
+	BFXIL_wwii(d, REG_WORK1, 16, 16);
+
+	MRS_NZCV_x(REG_WORK1);
+	EOR_xxCflag(REG_WORK1, REG_WORK1);
+
+	if (needed_flags & FLAG_Z) {
+		// Fix Z flag: SBCS Z may be wrong when borrow propagates through lower zero bits.
+		UBFX_wwii(REG_WORK3, d, 0, 16);
+		CMP_wi(REG_WORK3, 0);
+		SET_xxZflag(REG_WORK3, REG_WORK1);
+		CSEL_xxxc(REG_WORK1, REG_WORK3, REG_WORK1, NATIVE_CC_EQ);
+		AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2); // apply SUBX sticky-Z
+	}
+	MSR_NZCV_x(REG_WORK1);
+	flags_carry_inverted = false;
+	if (needed_flags & FLAG_X)
+		UBFX_xxii(x, REG_WORK1, 29, 1); // Duplicate carry
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUBX_w,(RW2 d, RR2 s))
+
+MIDFUNC(2,jff_SUBX_l,(RW4 d, RR4 s))
+{
+	INIT_REGS_l(d, s);
+	int x = rmw(FLAGX);
+
+	if (needed_flags & FLAG_Z) {
+		MOVN_xi(REG_WORK2, 0);
+		MOVN_xish(REG_WORK1, 0x4000, 16); // inverse Z flag
+		CSEL_xxxc(REG_WORK2, REG_WORK1, REG_WORK2, NATIVE_CC_NE);
+	}
+
+	// Restore inverted X to carry (don't care about other flags)
+	NEGS_ww(REG_WORK1, x);
+
+	SBCS_www(d, d, s);
+
+	MRS_NZCV_x(REG_WORK1);
+	EOR_xxCflag(REG_WORK1, REG_WORK1);
+	if (needed_flags & FLAG_Z)
+		AND_xxx(REG_WORK1, REG_WORK1, REG_WORK2);
+	MSR_NZCV_x(REG_WORK1);
+	flags_carry_inverted = false;
+	if (needed_flags & FLAG_X)
+		UBFX_xxii(x, REG_WORK1, 29, 1); // Duplicate carry
+
+	unlock2(x);
+	EXIT_REGS(d, s);
+}
+MENDFUNC(2,jff_SUBX_l,(RW4 d, RR4 s))
+
+/*
+ * SWAP
+ * Operand Syntax: Dn
+ *
+ *  Operand Size: 16
+ *
+ * X Not affected.
+ * N Set if the most significant bit of the 32-bit result is set. Cleared otherwise.
+ * Z Set if the 32-bit result is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jnf_SWAP,(RW4 d))
+{
+	if (isconst(d)) {
+		live.state[d].val = (live.state[d].val >> 16) | (live.state[d].val << 16);
+		return;
+	}
+
+	d = rmw(d);
+
+	ROR_wwi(d, d, 16);
+
+	unlock2(d);
+}
+MENDFUNC(1,jnf_SWAP,(RW4 d))
+
+MIDFUNC(1,jff_SWAP,(RW4 d))
+{
+	if(isconst(d)) {
+		live.state[d].val = (live.state[d].val >> 16) | (live.state[d].val << 16);
+		uae_u32 f = 0;
+		if((uae_s32)live.state[d].val == 0)
+			f |= (ARM_Z_FLAG >> 16);
+		if((uae_s32)live.state[d].val < 0)
+			f |= (ARM_N_FLAG >> 16);
+		MOV_xish(REG_WORK1, f, 16);
+		MSR_NZCV_x(REG_WORK1);
+		flags_carry_inverted = false;
+		return;
+	}
+
+	d = rmw(d);
+
+	ROR_wwi(d, d, 16);
+	TST_ww(d, d);
+
+	flags_carry_inverted = false;
+	unlock2(d);
+}
+MENDFUNC(1,jff_SWAP,(RW4 d))
+
+/*
+ * TST
+ * Operand Syntax: <ea>
+ *
+ *  Operand Size: 8,16,32
+ *
+ * X Not affected.
+ * N Set if the operand is negative. Cleared otherwise.
+ * Z Set if the operand is zero. Cleared otherwise.
+ * V Always cleared.
+ * C Always cleared.
+ *
+ */
+MIDFUNC(1,jff_TST_b_imm,(IM8 v))
+{
+	SIGNED8_IMM_2_REG(REG_WORK1, (uae_u8)v);
+	TST_ww(REG_WORK1, REG_WORK1);
+	flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_b_imm,(IM8 v))
+
+MIDFUNC(1,jff_TST_b,(RR1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_TST_b_imm)(live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	SIGNED8_REG_2_REG(REG_WORK1, s);
+	unlock2(s);
+
+	TST_ww(REG_WORK1, REG_WORK1);
+	flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_b,(RR1 s))
+
+MIDFUNC(1,jff_TST_w_imm,(IM16 v))
+{
+	SIGNED16_IMM_2_REG(REG_WORK1, (uae_u16)v);
+	TST_ww(REG_WORK1, REG_WORK1);
+	flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_w_imm,(IM16 v))
+
+MIDFUNC(1,jff_TST_w,(RR2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(jff_TST_w_imm)(live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	SIGNED16_REG_2_REG(REG_WORK1, s);
+	unlock2(s);
+
+	TST_ww(REG_WORK1, REG_WORK1);
+	flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_w,(RR2 s))
+
+MIDFUNC(1,jff_TST_l_imm,(IM32 v))
+{
+	LOAD_U32(REG_WORK1, v);
+	TST_ww(REG_WORK1, REG_WORK1);
+	flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_l_imm,(IM32 v))
+
+MIDFUNC(1,jff_TST_l,(RR4 s))
+{
+	if(isconst(s)) {
+		COMPCALL(jff_TST_l_imm)(live.state[s].val);
+		return;
+	}
+
+	s = readreg(s);
+	TST_ww(s, s);
+	unlock2(s);
+	flags_carry_inverted = false;
+}
+MENDFUNC(1,jff_TST_l,(RR4 s))
+
+/*
+ * Memory access functions
+ *
+ * Two versions: full address range and 24 bit address range
+ *
+ */
+MIDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
+{
+	adr = readreg(adr);
+	b = readreg(b);
+
+	STRB_wXx(b, adr, R_MEMSTART);
+
+	unlock2(b);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE_OFF_b,(RR4 adr, RR4 b))
+
+MIDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
+{
+	adr = readreg(adr);
+	w = readreg(w);
+
+	REV16_ww(REG_WORK1, w);
+	STRH_wXx(REG_WORK1, adr, R_MEMSTART);
+
+	unlock2(w);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE_OFF_w,(RR4 adr, RR4 w))
+
+MIDFUNC(2,jnf_MEM_WRITE_OFF_l,(RR4 adr, RR4 l))
+{
+	adr = readreg(adr);
+	l = readreg(l);
+
+	REV_ww(REG_WORK1, l);
+	STR_wXx(REG_WORK1, adr, R_MEMSTART);
+
+	unlock2(l);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE_OFF_l,(RR4 adr, RR4 l))
+
+
+MIDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	LDRB_wXx(d, adr, R_MEMSTART);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ_OFF_b,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	LDRH_wXx(REG_WORK1, adr, R_MEMSTART);
+	REV16_ww(d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ_OFF_w,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ_OFF_l,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	LDR_wXx(REG_WORK1, adr, R_MEMSTART);
+	REV_ww(d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ_OFF_l,(W4 d, RR4 adr))
+
+
+MIDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
+{
+	adr = readreg(adr);
+	b = readreg(b);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	STRB_wXx(b, REG_WORK1, R_MEMSTART);
+
+	unlock2(b);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE24_OFF_b,(RR4 adr, RR4 b))
+
+MIDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
+{
+	adr = readreg(adr);
+	w = readreg(w);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	REV16_ww(REG_WORK3, w);
+	STRH_wXx(REG_WORK3, REG_WORK1, R_MEMSTART);
+
+	unlock2(w);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE24_OFF_w,(RR4 adr, RR4 w))
+
+MIDFUNC(2,jnf_MEM_WRITE24_OFF_l,(RR4 adr, RR4 l))
+{
+	adr = readreg(adr);
+	l = readreg(l);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	REV_ww(REG_WORK3, l);
+	STR_wXx(REG_WORK3, REG_WORK1, R_MEMSTART);
+
+	unlock2(l);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_WRITE24_OFF_l,(RR4 adr, RR4 l))
+
+
+MIDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	LDRB_wXx(d, REG_WORK1, R_MEMSTART);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ24_OFF_b,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	LDRH_wXx(REG_WORK1, REG_WORK1, R_MEMSTART);
+	REV16_ww(d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ24_OFF_w,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_READ24_OFF_l,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	LDR_wXx(d, REG_WORK1, R_MEMSTART);
+	REV_ww(d, d);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_READ24_OFF_l,(W4 d, RR4 adr))
+
+
+MIDFUNC(2,jnf_MEM_GETADR_OFF,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	ADD_xxwEX(d, R_MEMSTART, adr, EX_UXTW);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_GETADR_OFF,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	UBFIZ_xxii(REG_WORK1, adr, 0, 24);
+	ADD_xxwEX(d, R_MEMSTART, REG_WORK1, EX_UXTW);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_GETADR24_OFF,(W4 d, RR4 adr))
+
+MIDFUNC(2,jnf_MEM_GETADR_JMP_OFF,(W4 d, RR4 adr))
+{
+	adr = readreg(adr);
+	d = writereg(d);
+
+	LOAD_U64(REG_WORK2, (uintptr)baseaddr);
+	LSR_wwi(REG_WORK1, adr, 16);
+	LDR_xXxLSLi(REG_WORK3, REG_WORK2, REG_WORK1, 1); // 1 means shift by 3
+	ADD_xxwEX(d, REG_WORK3, adr, EX_UXTW);
+	LOAD_U64(REG_WORK1, ~1ULL);
+	AND_xxx(d, d, REG_WORK1);
+
+	unlock2(d);
+	unlock2(adr);
+}
+MENDFUNC(2,jnf_MEM_GETADR_JMP_OFF,(W4 d, RR4 adr))
+
+
+MIDFUNC(3,jnf_MEM_READMEMBANK,(W4 dest, RR4 adr, IM8 offset))
+{
+	clobber_flags();
+	if (dest != adr) {
+		COMPCALL(forget_about)(dest);
+	}
+
+	adr = readreg_specific(adr, REG_PAR1);
+	prepare_for_call_1();
+	unlock2(adr);
+	prepare_for_call_2();
+
+	uintptr idx = (uintptr)(&regs.mem_banks) - (uintptr)(&regs);
+	LDR_xXi(REG_WORK2, R_REGSTRUCT, idx);
+	LSR_wwi(REG_WORK1, adr, 16);
+	LDR_xXxLSLi(REG_WORK3, REG_WORK2, REG_WORK1, 1); // 1 means shift by 3
+	LDR_xXi(REG_WORK3, REG_WORK3, offset);
+
+	compemu_raw_call_r(REG_WORK3);
+	// Most bank callbacks return 32-bit values and need upper-bit cleanup.
+	// xlateaddr callback (offset=6*sizeof(void*)) returns a host pointer.
+	if (offset != SIZEOF_VOID_P * 6)
+		MOV_ww(REG_RESULT, REG_RESULT);
+
+	live.nat[REG_RESULT].holds[0] = dest;
+	live.nat[REG_RESULT].nholds = 1;
+	live.nat[REG_RESULT].touched = touchcnt++;
+
+	live.state[dest].realreg = REG_RESULT;
+	live.state[dest].realind = 0;
+	live.state[dest].val = 0;
+	set_status(dest, DIRTY);
+}
+MENDFUNC(3,jnf_MEM_READMEMBANK,(W4 dest, RR4 adr, IM8 offset))
+
+
+MIDFUNC(3,jnf_MEM_WRITEMEMBANK,(RR4 adr, RR4 source, IM8 offset))
+{
+	clobber_flags();
+
+	adr = readreg_specific(adr, REG_PAR1);
+	source = readreg_specific(source, REG_PAR2);
+	prepare_for_call_1();
+	unlock2(adr);
+	unlock2(source);
+	prepare_for_call_2();
+
+	uintptr idx = (uintptr)(&regs.mem_banks) - (uintptr)(&regs);
+	LDR_xXi(REG_WORK2, R_REGSTRUCT, idx);
+	LSR_wwi(REG_WORK1, adr, 16);
+	LDR_xXxLSLi(REG_WORK3, REG_WORK2, REG_WORK1, 1); // 1 means shift by 3
+	LDR_xXi(REG_WORK3, REG_WORK3, offset);
+
+	compemu_raw_call_r(REG_WORK3);
+}
+MENDFUNC(3,jnf_MEM_WRITEMEMBANK,(RR4 adr, RR4 source, IM8 offset))
diff --git a/jit/arm/compemu_support_arm.cpp b/jit/arm/compemu_support_arm.cpp
new file mode 100644
index 00000000..099d0107
--- /dev/null
+++ b/jit/arm/compemu_support_arm.cpp
@@ -0,0 +1,3843 @@
+/*
+ * compiler/compemu_support.cpp - Core dynamic translation engine
+ *
+ * Copyright (c) 2001-2009 Milan Jurik of ARAnyM dev team (see AUTHORS)
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ * This file is part of the ARAnyM project which builds a new and powerful
+ * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
+ *
+ * JIT compiler m68k -> ARM
+ *
+ * Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ * Adaptation for Basilisk II and improvements, copyright 2000-2004 Gwenole Beauchesne
+ * Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
+ *
+ * ARAnyM is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * ARAnyM is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with ARAnyM; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include "sysdeps.h"
+
+#include <math.h>
+#if defined(CPU_AARCH64) && !defined(_WIN32)
+#include <sys/mman.h>
+#endif
+#if defined(CPU_AARCH64) && defined(_WIN32)
+#ifndef WIN32_LEAN_AND_MEAN
+#define WIN32_LEAN_AND_MEAN
+#endif
+#include <windows.h>
+#endif
+
+#if defined(JIT_DEBUG_MEM_CORRUPTION) && !defined(_WIN32)
+#include <signal.h>
+#include <sys/mman.h>
+#include <ucontext.h>
+#include <errno.h>
+#include <dlfcn.h>
+#endif
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#if defined(JIT)
+
+#include "options.h"
+#include "events.h"
+#include "include/memory.h"
+#include "newcpu.h"
+#include "comptbl_arm.h"
+#include "compemu_arm.h"
+
+/* ARM64 JIT is PIE-compatible: it uses register-indirect addressing
+ * (R_MEMSTART/R15) rather than PC-relative globals, so code placement
+ * relative to .data does not matter. */
+
+#ifdef __MACH__
+// Needed for sys_cache_invalidate to on the JIT space region, Mac OS X specific
+#include <libkern/OSCacheControl.h>
+#endif
+
+#include "uae/vm.h"
+#define VM_PAGE_READ UAE_VM_READ
+#define VM_PAGE_WRITE UAE_VM_WRITE
+#define VM_PAGE_EXECUTE UAE_VM_EXECUTE
+#define VM_MAP_FAILED UAE_VM_ALLOC_FAILED
+#define VM_MAP_DEFAULT 1
+#define VM_MAP_32BIT 1
+#define vm_protect(address, size, protect) uae_vm_protect(address, size, protect)
+#define vm_release(address, size) uae_vm_free(address, size)
+
+static inline void *vm_acquire(uae_u32 size, int options = VM_MAP_DEFAULT)
+{
+	assert(options == (VM_MAP_DEFAULT | VM_MAP_32BIT));
+	int flags = UAE_VM_32BIT;
+#if defined(CPU_AARCH64)
+	/* ARM64 JIT is 64-bit clean: metadata pools don't need low 4GB. */
+	flags = 0;
+#endif
+	return uae_vm_alloc(size, flags, UAE_VM_READ_WRITE);
+}
+
+static inline void* vm_acquire_code(uae_u32 size, int options = VM_MAP_DEFAULT)
+{
+	assert(options == (VM_MAP_DEFAULT | VM_MAP_32BIT));
+	int flags = UAE_VM_32BIT;
+	int protect = UAE_VM_READ_WRITE;
+#if defined(CPU_AARCH64)
+#if defined(__APPLE__)
+	/* On macOS ARM64, MAP_JIT mappings may not be placeable below 4GB.
+	 * Allow normal placement and rely on ARM64 codegen's 64-bit pointers. */
+	flags = UAE_VM_JIT;
+#else
+	/* ARM64 JIT is 64-bit pointer clean - no need for 32-bit constraint.
+	 * On Android, the 32-bit scan loop would iterate ~460K times because
+	 * natmem is placed well above 4GB by the kernel. */
+	flags = 0;
+#endif
+	/* All ARM64: code memory must be executable from allocation time.
+	 * On Android, SELinux may deny mprotect(PROT_EXEC) on non-exec pages. */
+	protect = UAE_VM_READ_WRITE_EXECUTE;
+#endif
+	return uae_vm_alloc(size, flags, protect);
+}
+
+#define UNUSED(x)
+#if defined(CPU_AARCH64)
+#define PRINT_PTR "%016llx"
+#else
+#define PRINT_PTR "%08x"
+#endif
+
+#define jit_log(format, ...) \
+  write_log("JIT: " format "\n", ##__VA_ARGS__);
+#define jit_log2(format, ...)
+
+#if defined(CPU_AARCH64)
+/* Not used on ARM64; R_MEMSTART (x27) holds full 64-bit natmem_offset */
+#define MEMBaseDiff ((uae_u32)0)
+#else
+#define MEMBaseDiff uae_p32(NATMEM_OFFSET)
+#endif
+
+#ifdef NATMEM_OFFSET
+#define FIXED_ADDRESSING 1
+#endif
+
+// %%% BRIAN KING WAS HERE %%%
+extern bool canbang;
+
+#include "../compemu_prefs.cpp"
+
+#define uint32 uae_u32
+#define uint8 uae_u8
+
+
+static inline int distrust_check(int value)
+{
+#ifdef JIT_ALWAYS_DISTRUST
+    return 1;
+#else
+    int distrust = value;
+#ifdef FSUAE
+    switch (value) {
+    case 0: distrust = 0; break;
+    case 1: distrust = 1; break;
+    case 2: distrust = ((start_pc & 0xF80000) == 0xF80000); break;
+    case 3: distrust = !have_done_picasso; break;
+    default: abort();
+    }
+#endif
+    return distrust;
+#endif
+}
+
+static inline int distrust_byte(void)
+{
+    return distrust_check(currprefs.comptrustbyte);
+}
+
+static inline int distrust_word(void)
+{
+    return distrust_check(currprefs.comptrustword);
+}
+
+static inline int distrust_long(void)
+{
+    return distrust_check(currprefs.comptrustlong);
+}
+
+static inline int distrust_addr(void)
+{
+    return distrust_check(currprefs.comptrustnaddr);
+}
+
+//#if DEBUG
+//#define PROFILE_COMPILE_TIME        1
+//#endif
+//#define PROFILE_UNTRANSLATED_INSNS    1
+
+#ifdef JIT_DEBUG
+#undef abort
+#define abort() do { \
+  fprintf(stderr, "Abort in file %s at line %d\n", __FILE__, __LINE__); \
+  exit(EXIT_FAILURE); \
+} while (0)
+#endif
+
+#ifdef RECORD_REGISTER_USAGE
+static uint64 reg_count[16];
+static uint64 reg_count_local[16];
+
+static int reg_count_compare(const void* ap, const void* bp)
+{
+    const int a = *((int*)ap);
+    const int b = *((int*)bp);
+    return reg_count[b] - reg_count[a];
+}
+#endif
+
+#ifdef PROFILE_COMPILE_TIME
+#include <time.h>
+static uae_u32 compile_count    = 0;
+static clock_t compile_time     = 0;
+static clock_t emul_start_time  = 0;
+static clock_t emul_end_time    = 0;
+#endif
+
+#ifdef PROFILE_UNTRANSLATED_INSNS
+static const int untranslated_top_ten = 50;
+static uae_u32 raw_cputbl_count[65536] = { 0, };
+static uae_u16 opcode_nums[65536];
+
+
+static int __cdecl untranslated_compfn(const void* e1, const void* e2)
+{
+    int v1 = *(const uae_u16*)e1;
+    int v2 = *(const uae_u16*)e2;
+    return (int)raw_cputbl_count[v2] - (int)raw_cputbl_count[v1];
+}
+#endif
+
+static compop_func *compfunctbl[65536];
+static compop_func *nfcompfunctbl[65536];
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+static cpuop_func* nfcpufunctbl[65536];
+#endif
+
+uae_u8* comp_pc_p;
+
+// gb-- Extra data for Basilisk II/JIT
+#define follow_const_jumps (currprefs.comp_constjump != 0)
+
+static uae_u32 cache_size = 0;            // Size of total cache allocated for compiled blocks
+static uae_u32 current_cache_size   = 0;  // Cache grows upwards: how much has been consumed already
+#ifdef USE_JIT_FPU
+#define avoid_fpu (!currprefs.compfpu)
+#define lazy_flush (!currprefs.comp_hardflush)
+#else
+#define avoid_fpu (true)
+#define lazy_flush (true)
+#endif
+static bool		have_cmov = false;	// target has CMOV instructions ?
+static bool		have_rat_stall = true;	// target has partial register stalls ?
+const bool		tune_alignment = true;	// Tune code alignments for running CPU ?
+const bool		tune_nop_fillers = true;	// Tune no-op fillers for architecture
+static bool		setzflg_uses_bsf = false;	// setzflg virtual instruction can use native BSF instruction correctly?
+static int		align_loops = 32;	// Align the start of loops
+static int		align_jumps = 32;	// Align the start of jumps
+static int		optcount[10] = {
+#ifdef UAE
+    4,		// How often a block has to be executed before it is translated
+#else
+    10,		// How often a block has to be executed before it is translated
+#endif
+    0,		// How often to use naive translation
+    0, 0, 0, 0,
+    -1, -1, -1, -1
+};
+
+op_properties prop[65536];
+
+bool may_raise_exception = false;
+static bool flags_carry_inverted = false;
+static bool disasm_this = false;
+
+static inline bool is_const_jump(uae_u32 opcode)
+{
+    return (prop[opcode].cflow == fl_const_jump);
+}
+
+static inline unsigned int cft_map(unsigned int f)
+{
+#ifdef UAE
+#if !defined(HAVE_GET_WORD_UNSWAPPED)
+    return f;
+#else
+    return do_byteswap_16(f);
+#endif
+#else
+#if !defined(HAVE_GET_WORD_UNSWAPPED) || defined(FULLMMU)
+    return f;
+#else
+    return ((f >> 8) & 255) | ((f & 255) << 8);
+#endif
+#endif
+}
+
+uae_u8* start_pc_p;
+uae_u32 start_pc;
+uintptr current_block_pc_p;
+static uintptr current_block_start_target;
+uae_u32 needed_flags;
+static uintptr next_pc_p;
+static uintptr taken_pc_p;
+static int     branch_cc;
+static int redo_current_block;
+
+#ifdef UAE
+int segvcount = 0;
+#endif
+uae_u8* current_compile_p = NULL;
+static uae_u8* max_compile_start;
+uae_u8* compiled_code = NULL;
+static uae_s32 reg_alloc_run;
+const int POPALLSPACE_SIZE = 2048; /* That should be enough space */
+uae_u8* popallspace = NULL;
+
+#if defined(CPU_AARCH64)
+/* On ARM64, popallspace and JIT cache are allocated as one contiguous
+ * block to guarantee the cache is within ARM64 B/BL branch range
+ * (+-128 MB) of popallspace. Separate allocations may be scattered
+ * too far apart by the kernel's mmap placement. */
+static size_t popall_combined_alloc_size = 0;
+static uint8 *popall_combined_cache_start = NULL;
+static uint32 popall_combined_cache_kb = 0;
+#endif
+
+void* pushall_call_handler = NULL;
+static void* popall_do_nothing = NULL;
+static void* popall_exec_nostats = NULL;
+static void* popall_execute_normal = NULL;
+static void* popall_cache_miss = NULL;
+static void* popall_recompile_block = NULL;
+static void* popall_check_checksum = NULL;
+
+static void* popall_exec_nostats_setpc = NULL;
+static void* popall_execute_normal_setpc = NULL;
+static void* popall_check_checksum_setpc = NULL;
+static void* popall_execute_exception = NULL;
+
+/* The 68k only ever executes from even addresses. So right now, we
+ * waste half the entries in this array
+ * UPDATE: We now use those entries to store the start of the linked
+ * lists that we maintain for each hash result.
+ */
+static cacheline cache_tags[TAGSIZE];
+static int cache_enabled = 0;
+static blockinfo* hold_bi[MAX_HOLD_BI];
+blockinfo* active;
+blockinfo* dormant;
+
+static void disable_jit_runtime(const char* reason)
+{
+	jit_log("JIT disabled: %s", reason);
+	currprefs.cachesize = 0;
+	changed_prefs.cachesize = 0;
+	cache_size = 0;
+	cache_enabled = 0;
+}
+
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+/* 68040 */
+extern const struct cputbl op_smalltbl_0[];
+#endif
+extern const struct comptbl op_smalltbl_0_comp_nf[];
+extern const struct comptbl op_smalltbl_0_comp_ff[];
+
+static void flush_icache_hard(int);
+static void flush_icache_lazy(int);
+static void flush_icache_none(int);
+
+#if defined(JIT_DEBUG_MEM_CORRUPTION) && !defined(_WIN32)
+// JIT Page 0 DMA Guard
+// Protects the first 4KB of Amiga memory (natmem page 0) from corruption
+// caused by blitter DMA during Kickstart initialization.
+//
+// Root cause: Kickstart ROM programs the blitter to clear M68k addresses
+// 0x004-0x01B (exception vectors 1-6) during init. With JIT's asynchronous
+// blitter, this DMA fires BETWEEN JIT blocks, creating a window where
+// exception vectors are zeroed. If an exception fires during this window,
+// the CPU jumps to address 0, causing illegal instruction cascades.
+//
+// Fix: After the first vec2 (Bus Error vector) change - which signals that
+// exec library init is replacing ROM handlers - we snapshot the entire first
+// page and protect it with mprotect(PROT_READ). All writes trigger SIGSEGV,
+// which uses BRK single-step to allow each write through individually.
+// After each write completes (SIGTRAP from BRK):
+//   - DMA writes (from blitter C code): restored from shadow
+//   - CPU writes (from JIT compiled code): shadow updated with new value
+// Exception_normal() also has a safety net guard using vector shadows.
+
+// Vec2 tracking - detect when exec library init changes vectors, to arm protection
+static uae_u32 jit_dbg_vec2_last = 0;
+
+// Signal handler saved state
+static struct sigaction jit_dbg_old_sigaction;
+static struct sigaction jit_dbg_old_sigtrap_action;
+static volatile int jit_dbg_vec2_page_protected = 0;
+static volatile int jit_dbg_vec2_trap_armed = 0;
+
+// BRK single-step state
+static volatile uint32_t jit_dbg_saved_next_insn = 0;
+static volatile uint32_t *jit_dbg_saved_next_insn_addr = NULL;
+static volatile int jit_dbg_brk_step_count = 0;
+#define JIT_DBG_BRK_IMM 0xD42EEEE0  // BRK #0x7777
+
+// SIGSEGV->SIGTRAP communication
+static volatile uae_u32 jit_dbg_last_write_m68k_addr = 0xFFFFFFFF;
+static volatile uae_u64 jit_dbg_last_write_arm64_pc = 0;
+static volatile int jit_dbg_vec2_sigsegv_count = 0;
+
+// Full-page shadow (4KB) - initialized when protection is armed
+static uae_u8 jit_page0_shadow[4096];
+static int jit_page0_shadow_valid = 0;
+static int jit_dbg_page0_restore_count = 0;
+static int jit_dbg_vec_restore_count = 0;
+static int jit_dbg_vec2_write_count = 0;
+
+// Vector shadow for Exception_normal() safety net (M68k big-endian format)
+#define JIT_VEC_SHADOW_COUNT 7
+uae_u32 jit_vec_shadow[JIT_VEC_SHADOW_COUNT] = {0};
+
+
+// v36: SIGTRAP handler for BRK single-step.
+// When a non-vec2 store to the protected natmem page triggers SIGSEGV, the
+// SIGSEGV handler inserts a BRK at the next instruction (PC+4) and unprotects
+// the page. The faulting store executes, then hits BRK which fires SIGTRAP.
+// This handler restores the original instruction and immediately re-protects
+// the natmem page, eliminating the gap where vec2 corruption could slip through.
+static void jit_dbg_vec2_sigtrap_handler(int sig, siginfo_t *si, void *ctx_raw)
+{
+    ucontext_t *uc = (ucontext_t*)ctx_raw;
+    unsigned long long trap_pc = uc->uc_mcontext.pc;
+
+    // Check if this is our BRK - the PC should point to our saved address
+    if (jit_dbg_saved_next_insn_addr != NULL &&
+        trap_pc == (unsigned long long)(uintptr_t)jit_dbg_saved_next_insn_addr)
+    {
+        jit_dbg_brk_step_count++;
+
+        // Restore the original instruction that was replaced by BRK
+        // First ensure the code page is writable
+        uintptr_t code_page = (uintptr_t)jit_dbg_saved_next_insn_addr & ~0xFFFUL;
+        mprotect((void*)code_page, 4096, PROT_READ | PROT_WRITE | PROT_EXEC);
+
+        *(volatile uint32_t*)jit_dbg_saved_next_insn_addr = jit_dbg_saved_next_insn;
+        __builtin___clear_cache(
+            (char*)jit_dbg_saved_next_insn_addr,
+            (char*)(jit_dbg_saved_next_insn_addr + 1));
+
+        jit_dbg_saved_next_insn_addr = NULL;
+
+        // v43: Full-page shadow restore/update after writes to page 0.
+        // v42 only protected vectors 1-6 (0x004-0x01B). v43 protects the
+        // entire 4KB page, catching DMA writes to FPU vectors (0x0c0-0x0d8),
+        // OS data (0x5d0+), and any other low-memory locations.
+        //   - DMA writes (ARM64 PC outside JIT cache): restore from shadow
+        //   - CPU writes (ARM64 PC inside JIT cache): update shadow
+        // The page is still unprotected here, so we can read/write natmem freely.
+        {
+            uae_u32 wr_addr = jit_dbg_last_write_m68k_addr;
+            if (wr_addr < 4096 && jit_page0_shadow_valid) {
+                uae_u64 wr_pc = jit_dbg_last_write_arm64_pc;
+                // JIT code cache: compiled_code .. current_compile_p
+                // If the write came from outside this range, it's DMA -> restore
+                int from_jit = (compiled_code != NULL &&
+                    wr_pc >= (uae_u64)(uintptr_t)compiled_code &&
+                    wr_pc < (uae_u64)(uintptr_t)current_compile_p);
+
+                // Align to 4-byte boundary for the restore/update
+                uae_u32 aligned_addr = wr_addr & ~3u;
+
+                if (!from_jit) {
+                    // DMA write - restore from shadow (undo the corruption)
+                    uae_u32 shadow_val = *(uae_u32*)(jit_page0_shadow + aligned_addr);
+                    *(volatile uae_u32*)(natmem_offset + aligned_addr) = shadow_val;
+                    jit_dbg_page0_restore_count++;
+
+                    // Also update jit_vec_shadow if this was a vector address (safety net)
+                    int vec_nr = aligned_addr / 4;
+                    if (vec_nr >= 1 && vec_nr <= 6) {
+                        jit_dbg_vec_restore_count++;
+                    }
+
+                    if (jit_dbg_page0_restore_count <= 30 ||
+                        (jit_dbg_page0_restore_count <= 300 && jit_dbg_page0_restore_count % 10 == 0) ||
+                        (jit_dbg_page0_restore_count % 500 == 0)) {
+                        write_log("JIT_VEC v43: page0 M68k 0x%03x restored from shadow "
+                            "after DMA write #%d (ARM64 PC=0x%016llx)\n",
+                            aligned_addr, jit_dbg_page0_restore_count,
+                            (unsigned long long)wr_pc);
+                    }
+                } else {
+                    // CPU write (from JIT cache) - update shadow with new value
+                    uae_u32 new_val = *(volatile uae_u32*)(natmem_offset + aligned_addr);
+                    *(uae_u32*)(jit_page0_shadow + aligned_addr) = new_val;
+
+                    // Also update jit_vec_shadow for vectors (Exception_normal safety net)
+                    int vec_nr = aligned_addr / 4;
+                    if (vec_nr >= 1 && vec_nr <= 6) {
+                        uae_u32 m68k_val = do_byteswap_32(new_val);
+                        if (m68k_val != 0) {
+                            jit_vec_shadow[vec_nr] = m68k_val;
+                        }
+                    }
+                }
+            }
+            jit_dbg_last_write_m68k_addr = 0xFFFFFFFF;  // Reset for next write
+        }
+
+        // Re-protect the natmem page IMMEDIATELY - this is the key improvement.
+        // The page was only unprotected for exactly ONE instruction (the faulting store).
+        unsigned long page_base = (unsigned long)natmem_offset & ~0xFFFUL;
+        mprotect((void*)page_base, 4096, PROT_READ);
+        jit_dbg_vec2_page_protected = 1;
+
+        // Log periodic stats
+        if (jit_dbg_brk_step_count <= 10 ||
+            (jit_dbg_brk_step_count <= 100 && jit_dbg_brk_step_count % 10 == 0) ||
+            (jit_dbg_brk_step_count % 500 == 0)) {
+            write_log("JIT_VEC v36:BRK step #%d completed, page re-protected.\n",
+                jit_dbg_brk_step_count);
+        }
+
+        // Return - CPU re-executes at PC, which now has the restored original instruction
+        return;
+    }
+
+    // Not our BRK - chain to original SIGTRAP handler
+    if (jit_dbg_old_sigtrap_action.sa_flags & SA_SIGINFO) {
+        jit_dbg_old_sigtrap_action.sa_sigaction(sig, si, ctx_raw);
+    } else if (jit_dbg_old_sigtrap_action.sa_handler != SIG_DFL &&
+               jit_dbg_old_sigtrap_action.sa_handler != SIG_IGN) {
+        jit_dbg_old_sigtrap_action.sa_handler(sig);
+    } else {
+        // Default action for SIGTRAP is to terminate - but only if not ours
+        write_log("JIT_VEC v36:WARNING: unexpected SIGTRAP at PC=0x%016llx (not our BRK)\n",
+            trap_pc);
+        // Don't terminate - just return and hope for the best
+    }
+}
+
+// v36: SIGSEGV handler for mprotect-based vec2 write trap.
+// When the first page of natmem is read-only, any write triggers this handler.
+// If the write targets the vec2 area (M68k 0x008-0x00b), we dump the ARM64 PC
+// and all registers - this identifies the EXACT JIT-compiled instruction responsible.
+// For non-vec2 writes: uses BRK single-step to keep the page protected.
+static void jit_dbg_vec2_sigsegv_handler(int sig, siginfo_t *si, void *ctx_raw)
+{
+    uae_u8 *fault_addr = (uae_u8*)si->si_addr;
+
+    // Check if fault is in our protected page
+    unsigned long page_base = (unsigned long)natmem_offset & ~0xFFFUL;
+    if ((unsigned long)fault_addr < page_base ||
+        (unsigned long)fault_addr >= page_base + 4096) {
+        // Not our fault - chain to original handler
+        if (jit_dbg_old_sigaction.sa_flags & SA_SIGINFO) {
+            jit_dbg_old_sigaction.sa_sigaction(sig, si, ctx_raw);
+        } else if (jit_dbg_old_sigaction.sa_handler != SIG_DFL &&
+                   jit_dbg_old_sigaction.sa_handler != SIG_IGN) {
+            jit_dbg_old_sigaction.sa_handler(sig);
+        } else {
+            signal(SIGSEGV, SIG_DFL);
+            raise(SIGSEGV);
+        }
+        return;
+    }
+
+    ucontext_t *uc = (ucontext_t*)ctx_raw;
+    unsigned long long arm64_pc = uc->uc_mcontext.pc;
+    uae_u32 m68k_addr = (uae_u32)(fault_addr - natmem_offset);
+
+    jit_dbg_vec2_sigsegv_count++;
+
+    // v42: Save write info for SIGTRAP handler (immediate vector restore)
+    jit_dbg_last_write_m68k_addr = m68k_addr;
+    jit_dbg_last_write_arm64_pc = arm64_pc;
+
+    // Unprotect the page so the write can complete and we can log
+    mprotect((void*)page_base, 4096, PROT_READ | PROT_WRITE);
+    jit_dbg_vec2_page_protected = 0;
+
+    // Check if this write targets the vector table area (M68k 0x004-0x01b)
+    // v41: expanded from vec2-only (0x008-0x00b) to full blitter-cleared range.
+    // Vectors 1-6 all get corrupted by blitter DMA during Kickstart init.
+    if (m68k_addr >= 0x004 && m68k_addr <= 0x01b) {
+        jit_dbg_vec2_write_count++;
+        if (jit_dbg_vec2_write_count <= 20 ||
+            (jit_dbg_vec2_write_count <= 200 && jit_dbg_vec2_write_count % 10 == 0) ||
+            (jit_dbg_vec2_write_count % 100 == 0)) {
+            int vec_nr = m68k_addr / 4;
+            write_log("JIT_VEC v41: vector DMA write #%d: vec%d M68k 0x%03x, "
+                "ARM64 PC=0x%016llx, val=0x%04llx (BRK step)\n",
+                jit_dbg_vec2_write_count, vec_nr, m68k_addr, arm64_pc,
+                (unsigned long long)uc->uc_mcontext.regs[1]);
+        }
+        // Fall through to BRK single-step below (same path as non-vector writes)
+    }
+
+    // BRK single-step for ALL writes (vec2 and non-vec2).
+    // Strategy: insert BRK at next instruction (PC+4), return.
+    // Faulting store re-executes (succeeds), then hits BRK -> SIGTRAP handler
+    // immediately re-protects the page. Page is unprotected for exactly ONE insn.
+
+    if (jit_dbg_vec2_sigsegv_count <= 30 ||
+        (jit_dbg_vec2_sigsegv_count <= 300 && jit_dbg_vec2_sigsegv_count % 10 == 0) ||
+        (jit_dbg_vec2_sigsegv_count % 500 == 0)) {
+        write_log("JIT_VEC v36:page write #%d: M68k 0x%03x ARM64_PC=0x%016llx (BRK step)\n",
+            jit_dbg_vec2_sigsegv_count, m68k_addr, arm64_pc);
+    }
+
+    // Safety check: if a previous BRK is still pending, something went wrong.
+    // Fall back to unprotect-and-return (v35 behavior) for safety.
+    if (jit_dbg_saved_next_insn_addr != NULL) {
+        write_log("JIT_VEC v36:WARNING: previous BRK still pending at %p! "
+            "Falling back to unprotect-and-return.\n",
+            (void*)jit_dbg_saved_next_insn_addr);
+        // Page is already unprotected (we did it at line 684 above)
+        jit_dbg_vec2_page_protected = 0;
+        return;
+    }
+
+    // Insert BRK #0x7777 at the instruction AFTER the faulting store (PC+4).
+    // When the store re-executes (page is unprotected), control flows to PC+4
+    // which now has BRK. This fires SIGTRAP, and our handler re-protects the page.
+    uint32_t *next_insn_addr = (uint32_t*)((uintptr_t)arm64_pc + 4);
+
+    // Ensure the code page containing PC+4 is writable (JIT cache may be RX)
+    uintptr_t code_page = (uintptr_t)next_insn_addr & ~0xFFFUL;
+    mprotect((void*)code_page, 4096, PROT_READ | PROT_WRITE | PROT_EXEC);
+
+    // Save the original instruction and insert BRK
+    jit_dbg_saved_next_insn = *next_insn_addr;
+    jit_dbg_saved_next_insn_addr = next_insn_addr;
+    *next_insn_addr = JIT_DBG_BRK_IMM;
+
+    // Flush instruction cache so CPU sees the BRK
+    __builtin___clear_cache((char*)next_insn_addr, (char*)(next_insn_addr + 1));
+
+    // Page is already unprotected (we did it above for logging).
+    // The faulting store will re-execute successfully, then hit BRK -> SIGTRAP.
+    jit_dbg_vec2_page_protected = 0;
+    // Return - store executes, then BRK fires SIGTRAP -> handler re-protects page
+}
+
+// v34: Vec2 check function callable from ALL C dispatch functions.
+// This covers the "dark zone" where compiled blocks chain via hash table
+// dispatch without any vec2 monitoring. Called from:
+//   do_nothing(), exec_nostats(), execute_normal() [in newcpu.cpp]
+//   cache_miss(), recompile_block(), compile_block end [in this file]
+// Called from C dispatch functions to detect vec2 changes and arm page protection.
+// Once armed, signal handlers take over - this function stops being called.
+void jit_dbg_check_vec2_dispatch(const char* func_name)
+{
+    if (jit_dbg_vec2_trap_armed || !natmem_offset)
+        return;
+
+    // Read vec2 (Bus Error vector at M68k 0x008)
+    uae_u32 cur_vec2 = *(volatile uae_u32*)(natmem_offset + 0x008);
+    if (cur_vec2 == 0)
+        return;  // ROM hasn't initialized vectors yet
+
+    // Track first non-zero value
+    if (jit_dbg_vec2_last == 0) {
+        jit_dbg_vec2_last = cur_vec2;
+        return;
+    }
+
+    // No change - nothing to do
+    if (cur_vec2 == jit_dbg_vec2_last)
+        return;
+
+    // Vec2 changed - exec library is replacing ROM handlers.
+    // Time to arm the page 0 DMA guard.
+    write_log("JIT: Page 0 DMA guard: vec2 changed in %s, arming protection.\n", func_name);
+    jit_dbg_vec2_last = cur_vec2;
+
+    // Initialize vector shadows (M68k big-endian format)
+    for (int vi = 1; vi <= 6; vi++) {
+        uae_u32 raw_val = *(volatile uae_u32*)(natmem_offset + vi * 4);
+        uae_u32 m68k_val = do_byteswap_32(raw_val);
+        if (m68k_val != 0)
+            jit_vec_shadow[vi] = m68k_val;
+    }
+
+    // Install SIGTRAP handler (for BRK single-step)
+    struct sigaction sa_trap;
+    memset(&sa_trap, 0, sizeof(sa_trap));
+    sa_trap.sa_sigaction = jit_dbg_vec2_sigtrap_handler;
+    sa_trap.sa_flags = SA_SIGINFO | SA_RESTART;
+    sigemptyset(&sa_trap.sa_mask);
+    if (sigaction(SIGTRAP, &sa_trap, &jit_dbg_old_sigtrap_action) != 0) {
+        write_log("JIT: WARNING: SIGTRAP handler install failed, errno=%d\n", errno);
+        return;
+    }
+
+    // Install SIGSEGV handler (for page fault interception)
+    struct sigaction sa;
+    memset(&sa, 0, sizeof(sa));
+    sa.sa_sigaction = jit_dbg_vec2_sigsegv_handler;
+    sa.sa_flags = SA_SIGINFO | SA_RESTART;
+    sigemptyset(&sa.sa_mask);
+    if (sigaction(SIGSEGV, &sa, &jit_dbg_old_sigaction) != 0) {
+        write_log("JIT: WARNING: SIGSEGV handler install failed, errno=%d\n", errno);
+        return;
+    }
+
+    // Snapshot the entire first page BEFORE protecting it
+    memcpy(jit_page0_shadow, (void*)natmem_offset, 4096);
+    jit_page0_shadow_valid = 1;
+    write_log("JIT: Page 0 shadow initialized (4096 bytes).\n");
+
+    // Protect the first page of natmem (M68k 0x000-0xFFF)
+    unsigned long page_base = (unsigned long)natmem_offset & ~0xFFFUL;
+    if (mprotect((void*)page_base, 4096, PROT_READ) == 0) {
+        jit_dbg_vec2_page_protected = 1;
+        jit_dbg_vec2_trap_armed = 1;
+        write_log("JIT: Page 0 DMA guard active at %p.\n", (void*)page_base);
+    } else {
+        write_log("JIT: WARNING: mprotect failed, errno=%d\n", errno);
+    }
+}
+#endif
+
+static bigstate live;
+static smallstate empty_ss;
+static smallstate default_ss;
+static int optlev;
+
+static int writereg(int r);
+static void unlock2(int r);
+static void setlock(int r);
+static int readreg_specific(int r, int size, int spec);
+static int writereg_specific(int r, int size, int spec);
+
+static int readreg(int r);
+static void prepare_for_call_1(void);
+static void prepare_for_call_2(void);
+
+STATIC_INLINE void flush_cpu_icache(void *from, void *to);
+STATIC_INLINE void jit_begin_write_window(void);
+STATIC_INLINE void jit_end_write_window(void);
+STATIC_INLINE void write_jmp_target(uae_u32 *jmpaddr, uintptr a);
+
+static int jit_write_window_depth = 0;
+
+STATIC_INLINE void jit_begin_write_window(void)
+{
+	jit_write_window_depth++;
+#if defined(__APPLE__) && defined(CPU_AARCH64)
+	if (jit_write_window_depth == 1) {
+		uae_vm_jit_write_protect(false);
+	}
+#endif
+}
+
+STATIC_INLINE void jit_end_write_window(void)
+{
+	if (jit_write_window_depth <= 0) {
+		write_log("JIT: write window underflow\n");
+		jit_write_window_depth = 0;
+		return;
+	}
+	jit_write_window_depth--;
+#if defined(__APPLE__) && defined(CPU_AARCH64)
+	if (jit_write_window_depth == 0) {
+		uae_vm_jit_write_protect(true);
+	}
+#endif
+}
+
+uae_u32 m68k_pc_offset;
+
+/* Some arithmetic operations can be optimized away if the operands
+ * are known to be constant. But that's only a good idea when the
+ * side effects they would have on the flags are not important. This
+ * variable indicates whether we need the side effects or not
+ */
+static uae_u32 needflags = 0;
+
+/* Flag handling is complicated.
+ *
+ * ARM instructions create flags, which quite often are exactly what we
+ * want. So at times, the "68k" flags are actually in the ARM flags.
+ * Exception: carry is often inverted.
+ *
+ * Then again, sometimes we do ARM instructions that clobber the ARM
+ * flags, but don't represent a corresponding m68k instruction. In that
+ * case, we have to save them.
+ *
+ * We used to save them to the stack, but now store them back directly
+ * into the regflags.nzcv of the traditional emulation. Thus some odd
+ * names.
+ *
+ * So flags can be in either of two places (used to be three; boy were
+ * things complicated back then!); And either place can contain either
+ * valid flags or invalid trash (and on the stack, there was also the
+ * option of "nothing at all", now gone). A couple of variables keep
+ * track of the respective states.
+ *
+ * To make things worse, we might or might not be interested in the flags.
+ * by default, we are, but a call to dont_care_flags can change that
+ * until the next call to live_flags. If we are not, pretty much whatever
+ * is in the register and/or the native flags is seen as valid.
+*/
+
+static inline blockinfo* get_blockinfo(uae_u32 cl)
+{
+    return cache_tags[cl + 1].bi;
+}
+
+static inline blockinfo* get_blockinfo_addr(void* addr)
+{
+    blockinfo* bi = get_blockinfo(cacheline(addr));
+
+    while (bi) {
+        if (bi->pc_p == addr)
+            return bi;
+        bi = bi->next_same_cl;
+    }
+    return NULL;
+}
+
+
+/*******************************************************************
+ * All sorts of list related functions for all of the lists        *
+ *******************************************************************/
+
+static inline void remove_from_cl_list(blockinfo* bi)
+{
+    uae_u32 cl = cacheline(bi->pc_p);
+
+    if (bi->prev_same_cl_p)
+        *(bi->prev_same_cl_p) = bi->next_same_cl;
+    if (bi->next_same_cl)
+        bi->next_same_cl->prev_same_cl_p = bi->prev_same_cl_p;
+    if (cache_tags[cl + 1].bi)
+        cache_tags[cl].handler = cache_tags[cl + 1].bi->handler_to_use;
+    else
+        cache_tags[cl].handler = (cpuop_func*)popall_execute_normal;
+}
+
+static inline void remove_from_list(blockinfo* bi)
+{
+    if (bi->prev_p)
+        *(bi->prev_p) = bi->next;
+    if (bi->next)
+        bi->next->prev_p = bi->prev_p;
+}
+
+static inline void add_to_cl_list(blockinfo* bi)
+{
+    uae_u32 cl = cacheline(bi->pc_p);
+
+    if (cache_tags[cl + 1].bi)
+        cache_tags[cl + 1].bi->prev_same_cl_p = &(bi->next_same_cl);
+    bi->next_same_cl = cache_tags[cl + 1].bi;
+
+    cache_tags[cl + 1].bi = bi;
+    bi->prev_same_cl_p = &(cache_tags[cl + 1].bi);
+
+    cache_tags[cl].handler = bi->handler_to_use;
+}
+
+void raise_in_cl_list(blockinfo* bi)
+{
+    remove_from_cl_list(bi);
+    add_to_cl_list(bi);
+}
+
+static inline void add_to_active(blockinfo* bi)
+{
+    if (active)
+        active->prev_p = &(bi->next);
+    bi->next = active;
+
+    active = bi;
+    bi->prev_p = &active;
+}
+
+static inline void add_to_dormant(blockinfo* bi)
+{
+    if (dormant)
+        dormant->prev_p = &(bi->next);
+    bi->next = dormant;
+
+    dormant = bi;
+    bi->prev_p = &dormant;
+}
+
+static inline void remove_dep(dependency* d)
+{
+    if (d->prev_p)
+        *(d->prev_p) = d->next;
+    if (d->next)
+        d->next->prev_p = d->prev_p;
+    d->prev_p = NULL;
+    d->next = NULL;
+}
+
+/* This block's code is about to be thrown away, so it no longer
+   depends on anything else */
+static inline void remove_deps(blockinfo* bi)
+{
+    remove_dep(&(bi->dep[0]));
+    remove_dep(&(bi->dep[1]));
+}
+
+static inline void adjust_jmpdep(dependency* d, cpuop_func* a)
+{
+    write_jmp_target(d->jmp_off, (uintptr)a);
+}
+
+/********************************************************************
+ * Soft flush handling support functions                            *
+ ********************************************************************/
+
+static inline void set_dhtu(blockinfo* bi, cpuop_func* dh)
+{
+    jit_log2("bi is %p", bi);
+    if (dh != bi->direct_handler_to_use) {
+        dependency* x = bi->deplist;
+        jit_log2("bi->deplist=%p", bi->deplist);
+        while (x) {
+            jit_log2("x is %p", x);
+            jit_log2("x->next is %p", x->next);
+            jit_log2("x->prev_p is %p", x->prev_p);
+
+            if (x->jmp_off) {
+                adjust_jmpdep(x, dh);
+            }
+            x = x->next;
+        }
+        bi->direct_handler_to_use = (cpuop_func*)dh;
+    }
+}
+
+void invalidate_block(blockinfo* bi)
+{
+    int i;
+
+    bi->optlevel = 0;
+    bi->count = optcount[0] - 1;
+    bi->handler = NULL;
+    bi->handler_to_use = (cpuop_func*)popall_execute_normal;
+    bi->direct_handler = NULL;
+    set_dhtu(bi, bi->direct_pen);
+    bi->needed_flags = 0xff;
+    bi->status = BI_INVALID;
+    for (i = 0; i < 2; i++) {
+        bi->dep[i].jmp_off = NULL;
+        bi->dep[i].target = NULL;
+    }
+    remove_deps(bi);
+}
+
+static inline void create_jmpdep(blockinfo* bi, int i, uae_u32* jmpaddr, uintptr target)
+{
+    blockinfo* tbi = get_blockinfo_addr((void*)target);
+
+    Dif(!tbi) {
+        jit_abort("Could not create jmpdep!");
+    }
+    bi->dep[i].jmp_off = jmpaddr;
+    bi->dep[i].source = bi;
+    bi->dep[i].target = tbi;
+    bi->dep[i].next = tbi->deplist;
+    if (bi->dep[i].next)
+        bi->dep[i].next->prev_p = &(bi->dep[i].next);
+    bi->dep[i].prev_p = &(tbi->deplist);
+    tbi->deplist = &(bi->dep[i]);
+}
+
+static inline void block_need_recompile(blockinfo* bi)
+{
+    uae_u32 cl = cacheline(bi->pc_p);
+
+    set_dhtu(bi, bi->direct_pen);
+    bi->direct_handler = bi->direct_pen;
+
+    bi->handler_to_use = (cpuop_func*)popall_execute_normal;
+    bi->handler = (cpuop_func*)popall_execute_normal;
+    if (bi == cache_tags[cl + 1].bi)
+        cache_tags[cl].handler = (cpuop_func*)popall_execute_normal;
+    bi->status = BI_NEED_RECOMP;
+}
+
+static inline blockinfo* get_blockinfo_addr_new(void* addr)
+{
+    blockinfo* bi = get_blockinfo_addr(addr);
+    int i;
+
+    if (!bi) {
+        for (i = 0; i < MAX_HOLD_BI && !bi; i++) {
+            if (hold_bi[i]) {
+                (void)cacheline(addr);
+
+                bi = hold_bi[i];
+                hold_bi[i] = NULL;
+                bi->pc_p = (uae_u8*)addr;
+                invalidate_block(bi);
+                add_to_active(bi);
+                add_to_cl_list(bi);
+            }
+        }
+    }
+    if (!bi) {
+        jit_abort(_T("JIT: Looking for blockinfo, can't find free one\n"));
+    }
+    return bi;
+}
+
+static void prepare_block(blockinfo* bi);
+
+/* Management of blockinfos.
+
+   A blockinfo struct is allocated whenever a new block has to be
+   compiled. If the list of free blockinfos is empty, we allocate a new
+   pool of blockinfos and link the newly created blockinfos altogether
+   into the list of free blockinfos. Otherwise, we simply pop a structure
+   of the free list.
+
+   Blockinfo are lazily deallocated, i.e. chained altogether in the
+   list of free blockinfos whenvever a translation cache flush (hard or
+   soft) request occurs.
+*/
+
+template< class T >
+class LazyBlockAllocator
+{
+    enum {
+        kPoolSize = 1 + (16384 - sizeof(T) - sizeof(void*)) / sizeof(T)
+    };
+    struct Pool {
+        T chunk[kPoolSize];
+        Pool* next;
+    };
+    Pool* mPools;
+    T* mChunks;
+public:
+    LazyBlockAllocator() : mPools(0), mChunks(0) { }
+#ifdef UAE
+#else
+    ~LazyBlockAllocator();
+#endif
+    T* acquire();
+    void release(T* const);
+};
+
+#ifdef UAE
+/* uae_vm_release may do logging, which isn't safe to do when the application
+ * is shutting down. Better to release memory manually with a function call
+ * to a release_all method on shutdown, or even simpler, just let the OS
+ * handle it (we're shutting down anyway). */
+#else
+template< class T >
+LazyBlockAllocator<T>::~LazyBlockAllocator()
+{
+    Pool* currentPool = mPools;
+    while (currentPool) {
+        Pool* deadPool = currentPool;
+        currentPool = currentPool->next;
+        vm_release(deadPool, sizeof(Pool));
+    }
+}
+#endif
+
+template< class T >
+T* LazyBlockAllocator<T>::acquire()
+{
+    if (!mChunks) {
+        // There is no chunk left, allocate a new pool and link the
+        // chunks into the free list
+		Pool * newPool = (Pool *)vm_acquire(sizeof(Pool), VM_MAP_DEFAULT | VM_MAP_32BIT);
+		if (newPool == VM_MAP_FAILED) {
+			jit_abort("Could not allocate block pool!\n");
+        }
+        for (T* chunk = &newPool->chunk[0]; chunk < &newPool->chunk[kPoolSize]; chunk++) {
+            chunk->next = mChunks;
+            mChunks = chunk;
+        }
+        newPool->next = mPools;
+        mPools = newPool;
+    }
+    T* chunk = mChunks;
+    mChunks = chunk->next;
+    return chunk;
+}
+
+template< class T >
+void LazyBlockAllocator<T>::release(T* const chunk)
+{
+    chunk->next = mChunks;
+    mChunks = chunk;
+}
+
+template< class T >
+class HardBlockAllocator
+{
+public:
+    T* acquire() {
+        T* data = (T*)current_compile_p;
+        current_compile_p += sizeof(T);
+        return data;
+    }
+
+    void release(T* const) {
+        // Deallocated on invalidation
+    }
+};
+
+static LazyBlockAllocator<blockinfo> BlockInfoAllocator;
+static LazyBlockAllocator<checksum_info> ChecksumInfoAllocator;
+
+static inline checksum_info* alloc_checksum_info(void)
+{
+    checksum_info* csi = ChecksumInfoAllocator.acquire();
+    csi->next = NULL;
+    return csi;
+}
+
+static inline void free_checksum_info(checksum_info* csi)
+{
+    csi->next = NULL;
+    ChecksumInfoAllocator.release(csi);
+}
+
+static inline void free_checksum_info_chain(checksum_info* csi)
+{
+    while (csi != NULL) {
+        checksum_info* csi2 = csi->next;
+        free_checksum_info(csi);
+        csi = csi2;
+    }
+}
+
+static inline blockinfo* alloc_blockinfo(void)
+{
+    blockinfo* bi = BlockInfoAllocator.acquire();
+    bi->csi = NULL;
+    return bi;
+}
+
+static inline void free_blockinfo(blockinfo* bi)
+{
+    free_checksum_info_chain(bi->csi);
+    bi->csi = NULL;
+    BlockInfoAllocator.release(bi);
+}
+
+static inline void alloc_blockinfos(void)
+{
+    int i;
+    blockinfo* bi;
+
+    for (i = 0; i < MAX_HOLD_BI; i++) {
+        if (hold_bi[i])
+            return;
+        bi = hold_bi[i] = alloc_blockinfo();
+        prepare_block(bi);
+    }
+}
+
+/********************************************************************
+ * Functions to emit data into memory, and other general support    *
+ ********************************************************************/
+
+static uae_u8* target;
+
+static inline void emit_byte(uae_u8 x)
+{
+    *target++ = x;
+}
+
+static inline void skip_n_bytes(int n) {
+    target += n;
+}
+
+static inline void skip_byte()
+{
+    skip_n_bytes(1);
+}
+
+static inline void skip_word()
+{
+    skip_n_bytes(2);
+}
+
+static inline void skip_long()
+{
+    skip_n_bytes(4);
+}
+
+static inline void skip_quad()
+{
+    skip_n_bytes(8);
+}
+
+static inline void emit_word(uae_u16 x)
+{
+    *((uae_u16*)target) = x;
+    skip_word();
+}
+
+static inline void emit_long(uae_u32 x)
+{
+    *((uae_u32*)target) = x;
+    skip_long();
+}
+
+static inline void emit_quad(uae_u64 x)
+{
+    *((uae_u64*)target) = x;
+    skip_quad();
+}
+
+static inline void emit_block(const uae_u8* block, uae_u32 blocklen)
+{
+    memcpy((uae_u8*)target, block, blocklen);
+    target += blocklen;
+}
+
+#define MAX_COMPILE_PTR max_compile_start
+
+static inline uae_u32 reverse32(uae_u32 v)
+{
+    return uae_bswap_32(v);
+}
+
+static void set_target(uae_u8* t)
+{
+    target = t;
+}
+
+static inline uae_u8* get_target_noopt(void)
+{
+    return target;
+}
+
+inline uae_u8* get_target(void)
+{
+    return get_target_noopt();
+}
+
+/********************************************************************
+ * New version of data buffer: interleave data and code             *
+ ********************************************************************/
+#if defined(USE_DATA_BUFFER)
+
+#define DATA_BUFFER_SIZE 768             // Enlarge POPALLSPACE_SIZE if this value is greater than 768
+#define DATA_BUFFER_MAXOFFSET 4096 - 32  // max range between emit of data and use of data
+static uae_u8* data_writepos = 0;
+static uae_u8* data_endpos = 0;
+#ifdef DEBUG_DATA_BUFFER
+static uae_u32 data_wasted = 0;
+static uae_u32 data_buffers_used = 0;
+#endif
+
+STATIC_INLINE void compemu_raw_branch(IM32 d);
+
+STATIC_INLINE void data_check_end(uae_s32 n, uae_s32 codesize)
+{
+    if (data_writepos + n > data_endpos || get_target() + codesize - data_writepos > DATA_BUFFER_MAXOFFSET) {
+        // Start new buffer
+#ifdef DEBUG_DATA_BUFFER
+        if (data_writepos < data_endpos)
+            data_wasted += data_endpos - data_writepos;
+        data_buffers_used++;
+#endif
+        compemu_raw_branch(DATA_BUFFER_SIZE);
+        data_writepos = get_target();
+        data_endpos = data_writepos + DATA_BUFFER_SIZE;
+        set_target(get_target() + DATA_BUFFER_SIZE);
+    }
+}
+
+STATIC_INLINE uae_s32 data_word_offs(uae_u16 x)
+{
+    data_check_end(4, 4);
+    *((uae_u16*)data_writepos) = x;
+    data_writepos += 2;
+    *((uae_u16*)data_writepos) = 0;
+    data_writepos += 2;
+    return (uae_s32)data_writepos - (uae_s32)get_target() - 12;
+}
+
+STATIC_INLINE uae_s32 data_long(uae_u32 x, uae_s32 codesize)
+{
+    data_check_end(4, codesize);
+    *((uae_u32*)data_writepos) = x;
+    data_writepos += 4;
+    return (uae_s32)data_writepos - 4;
+}
+
+STATIC_INLINE uae_s32 data_long_offs(uae_u32 x)
+{
+    data_check_end(4, 4);
+    *((uae_u32*)data_writepos) = x;
+    data_writepos += 4;
+    return (uae_s32)data_writepos - (uae_s32)get_target() - 12;
+}
+
+STATIC_INLINE uae_s32 get_data_offset(uae_s32 t)
+{
+    return t - (uae_s32)get_target() - 8;
+}
+
+STATIC_INLINE void reset_data_buffer(void)
+{
+    data_writepos = 0;
+    data_endpos = 0;
+}
+
+#endif
+
+/********************************************************************
+ * Getting the information about the target CPU                     *
+ ********************************************************************/
+STATIC_INLINE void clobber_flags(void);
+
+#if defined(CPU_AARCH64)
+#include "codegen_arm64.cpp"
+#elif defined(CPU_arm)
+#include "codegen_arm.cpp"
+#endif
+
+/********************************************************************
+ * Flags status handling. EMIT TIME!                                *
+ ********************************************************************/
+
+static void bt_l_ri_noclobber(RR4 r, IM8 i);
+
+static void make_flags_live_internal(void)
+{
+    if (live.flags_in_flags == VALID)
+        return;
+    Dif(live.flags_on_stack == TRASH) {
+        jit_abort("Want flags, got something on stack, but it is TRASH");
+    }
+    if (live.flags_on_stack == VALID) {
+        int tmp;
+        tmp = readreg(FLAGTMP);
+        raw_reg_to_flags(tmp);
+        unlock2(tmp);
+        flags_carry_inverted = false;
+
+        live.flags_in_flags = VALID;
+        return;
+    }
+    jit_abort("Huh? live.flags_in_flags=%d, live.flags_on_stack=%d, but need to make live",
+        live.flags_in_flags, live.flags_on_stack);
+}
+
+static void flags_to_stack(void)
+{
+    if (live.flags_on_stack == VALID) {
+        flags_carry_inverted = false;
+        return;
+    }
+    if (!live.flags_are_important) {
+        live.flags_on_stack = VALID;
+        flags_carry_inverted = false;
+        return;
+    }
+    Dif(live.flags_in_flags != VALID)
+        jit_abort("flags_to_stack != VALID");
+    else {
+        int tmp = writereg(FLAGTMP);
+        raw_flags_to_reg(tmp);
+        unlock2(tmp);
+    }
+    live.flags_on_stack = VALID;
+}
+
+STATIC_INLINE void clobber_flags(void)
+{
+    if (live.flags_in_flags == VALID && live.flags_on_stack != VALID)
+        flags_to_stack();
+    live.flags_in_flags = TRASH;
+}
+
+/* Prepare for leaving the compiled stuff */
+static inline void flush_flags(void)
+{
+    flags_to_stack();
+}
+
+static int touchcnt;
+
+/********************************************************************
+ * Partial register flushing for optimized calls                    *
+ ********************************************************************/
+
+struct regusage {
+    uae_u16 rmask;
+    uae_u16 wmask;
+};
+
+/********************************************************************
+ * register allocation per block logging                            *
+ ********************************************************************/
+
+static uae_s8 vstate[VREGS];
+static uae_s8 vwritten[VREGS];
+static uae_s8 nstate[N_REGS];
+
+#define L_UNKNOWN -127
+#define L_UNAVAIL -1
+#define L_NEEDED -2
+#define L_UNNEEDED -3
+
+static inline void log_startblock(void)
+{
+    int i;
+
+    for (i = 0; i < VREGS; i++) {
+        vstate[i] = L_UNKNOWN;
+        vwritten[i] = 0;
+    }
+    for (i = 0; i < N_REGS; i++)
+        nstate[i] = L_UNKNOWN;
+}
+
+/* Using an n-reg for a temp variable */
+static inline void log_isused(int n)
+{
+    if (nstate[n] == L_UNKNOWN)
+        nstate[n] = L_UNAVAIL;
+}
+
+static inline void log_visused(int r)
+{
+    if (vstate[r] == L_UNKNOWN)
+        vstate[r] = L_NEEDED;
+}
+
+STATIC_INLINE void do_load_reg(int n, int r)
+{
+    compemu_raw_mov_l_rm(n, (uintptr)live.state[r].mem);
+}
+
+static inline void log_vwrite(int r)
+{
+    vwritten[r] = 1;
+}
+
+/* Using an n-reg to hold a v-reg */
+static inline void log_isreg(int n, int r)
+{
+    if (nstate[n] == L_UNKNOWN && r < 16 && !vwritten[r] && 0)
+        nstate[n] = r;
+    else {
+        do_load_reg(n, r);
+        if (nstate[n] == L_UNKNOWN)
+            nstate[n] = L_UNAVAIL;
+    }
+    if (vstate[r] == L_UNKNOWN)
+        vstate[r] = L_NEEDED;
+}
+
+static inline void log_clobberreg(int r)
+{
+    if (vstate[r] == L_UNKNOWN)
+        vstate[r] = L_UNNEEDED;
+}
+
+/* This ends all possibility of clever register allocation */
+
+static inline void log_flush(void)
+{
+    int i;
+
+    for (i = 0; i < VREGS; i++)
+        if (vstate[i] == L_UNKNOWN)
+            vstate[i] = L_NEEDED;
+    for (i = 0; i < N_REGS; i++)
+        if (nstate[i] == L_UNKNOWN)
+            nstate[i] = L_UNAVAIL;
+}
+
+static inline void log_dump(void)
+{
+    return;
+}
+
+/********************************************************************
+ * register status handling. EMIT TIME!                             *
+ ********************************************************************/
+
+static inline void set_status(int r, int status)
+{
+    if (status == ISCONST)
+        log_clobberreg(r);
+    live.state[r].status = status;
+}
+
+static inline int isinreg(int r)
+{
+    return live.state[r].status == CLEAN || live.state[r].status == DIRTY;
+}
+
+static void tomem(int r)
+{
+    int rr = live.state[r].realreg;
+
+    if (live.state[r].status == DIRTY) {
+        compemu_raw_mov_l_mr((uintptr)live.state[r].mem, live.state[r].realreg);
+        set_status(r, CLEAN);
+    }
+}
+
+static inline int isconst(int r)
+{
+    return live.state[r].status == ISCONST;
+}
+
+int is_const(int r)
+{
+    return isconst(r);
+}
+
+static inline void writeback_const(int r)
+{
+    if (!isconst(r))
+        return;
+    Dif(live.state[r].needflush == NF_HANDLER) {
+        jit_abort("Trying to write back constant NF_HANDLER!");
+    }
+
+    if (r == PC_P) {
+        /* PC_P holds a 64-bit host pointer - use the dedicated 64-bit
+           store path (LOAD_U64 + STR_xXi) instead of compemu_raw_mov_l_mi
+           which truncates to 32 bits via its IM32 parameter. */
+        compemu_raw_set_pc_i(live.state[r].val);
+    } else {
+        compemu_raw_mov_l_mi((uintptr)live.state[r].mem, live.state[r].val);
+    }
+    log_vwrite(r);
+    live.state[r].val = 0;
+    set_status(r, INMEM);
+}
+
+static inline void tomem_c(int r)
+{
+    if (isconst(r)) {
+        writeback_const(r);
+    }
+    else
+        tomem(r);
+}
+
+static void evict(int r)
+{
+    if (!isinreg(r))
+        return;
+    tomem(r);
+    int rr = live.state[r].realreg;
+
+    Dif(live.nat[rr].locked &&
+        live.nat[rr].nholds == 1) {
+        jit_abort("register %d in nreg %d is locked!", r, live.state[r].realreg);
+    }
+
+    live.nat[rr].nholds--;
+    if (live.nat[rr].nholds != live.state[r].realind) { /* Was not last */
+        int topreg = live.nat[rr].holds[live.nat[rr].nholds];
+        int thisind = live.state[r].realind;
+
+        live.nat[rr].holds[thisind] = topreg;
+        live.state[topreg].realind = thisind;
+    }
+    live.state[r].realreg = -1;
+    set_status(r, INMEM);
+}
+
+static inline void free_nreg(int r)
+{
+    int i = live.nat[r].nholds;
+
+    while (i) {
+        int vr;
+
+        --i;
+        vr = live.nat[r].holds[i];
+        evict(vr);
+    }
+    Dif(live.nat[r].nholds != 0) {
+        jit_abort("Failed to free nreg %d, nholds is %d", r, live.nat[r].nholds);
+    }
+}
+
+/* Use with care! */
+static inline void isclean(int r)
+{
+    if (!isinreg(r))
+        return;
+    live.state[r].val = 0;
+    set_status(r, CLEAN);
+}
+
+static inline void disassociate(int r)
+{
+    isclean(r);
+    evict(r);
+}
+
+static inline void set_const(int r, uintptr val)
+{
+    disassociate(r);
+#ifdef CPU_AARCH64
+    // On ARM64, guest registers (Dn, An, flags) are 32-bit values.
+    // Only PC_P holds a 64-bit host pointer.  Mask val to 32-bit for
+    // all other registers to prevent 64-bit arithmetic leaking into
+    // constant-propagation paths (sub_l_ri underflow, etc.).
+    if (r != PC_P)
+        val = (uae_u32)val;
+#endif
+    live.state[r].val = val;
+    set_status(r, ISCONST);
+}
+
+static inline uae_u32 get_offset(int r)
+{
+    return live.state[r].val;
+}
+
+bool has_free_reg(void)
+{
+    for (int i = N_REGS - 1; i >= 0; i--) {
+        if (!live.nat[i].locked) {
+            if (live.nat[i].nholds == 0)
+                return true;
+        }
+    }
+    return false;
+}
+
+static int alloc_reg_hinted(int r, int willclobber, int hint)
+{
+    int bestreg = -1;
+    uae_s32 when = 2000000000;
+    int i;
+
+    for (i = N_REGS - 1; i >= 0; i--) {
+        if (!live.nat[i].locked) {
+            uae_s32 badness = live.nat[i].touched;
+            if (live.nat[i].nholds == 0)
+                badness = 0;
+            if (i == hint)
+                badness -= 200000000;
+            if (badness < when) {
+                bestreg = i;
+                when = badness;
+                if (live.nat[i].nholds == 0 && hint < 0)
+                    break;
+                if (i == hint)
+                    break;
+            }
+        }
+    }
+    Dif(bestreg == -1)
+        jit_abort("alloc_reg_hinted bestreg=-1");
+
+    if (live.nat[bestreg].nholds > 0) {
+        free_nreg(bestreg);
+    }
+
+    if (!willclobber) {
+        if (live.state[r].status != UNDEF) {
+            if (isconst(r)) {
+                if (r == PC_P) {
+                    /* PC_P holds a 64-bit host pointer - use LOAD_U64.
+                       compemu_raw_mov_l_ri uses LOAD_U32 which truncates. */
+                    LOAD_U64(bestreg, live.state[r].val);
+                } else {
+                    compemu_raw_mov_l_ri(bestreg, live.state[r].val);
+                }
+                live.state[r].val = 0;
+                set_status(r, DIRTY);
+                log_isused(bestreg);
+            } else {
+                do_load_reg(bestreg, r);
+                set_status(r, CLEAN);
+            }
+        } else {
+            live.state[r].val = 0;
+            set_status(r, CLEAN);
+            log_isused(bestreg);
+        }
+    } else { /* this is the easiest way, but not optimal. */
+        live.state[r].val = 0;
+        set_status(r, DIRTY);
+    }
+    live.state[r].realreg = bestreg;
+    live.state[r].realind = 0;
+    live.nat[bestreg].touched = touchcnt++;
+    live.nat[bestreg].holds[0] = r;
+    live.nat[bestreg].nholds = 1;
+
+    return bestreg;
+}
+
+
+static void unlock2(int r)
+{
+    Dif(!live.nat[r].locked)
+        jit_abort("unlock2 %d not locked", r);
+    live.nat[r].locked--;
+}
+
+static void setlock(int r)
+{
+    live.nat[r].locked++;
+}
+
+
+static void mov_nregs(int d, int s)
+{
+    if (s == d)
+        return;
+
+    if (live.nat[d].nholds > 0)
+        free_nreg(d);
+
+    log_isused(d);
+    compemu_raw_mov_l_rr(d, s);
+
+    for (int i = 0; i < live.nat[s].nholds; i++) {
+        int vs = live.nat[s].holds[i];
+
+        live.state[vs].realreg = d;
+        live.state[vs].realind = i;
+        live.nat[d].holds[i] = vs;
+    }
+    live.nat[d].nholds = live.nat[s].nholds;
+
+    live.nat[s].nholds = 0;
+}
+
+
+static inline void make_exclusive(int r, int needcopy)
+{
+    reg_status oldstate;
+    int rr = live.state[r].realreg;
+    int nr;
+    int nind;
+
+    if (!isinreg(r))
+        return;
+    if (live.nat[rr].nholds == 1)
+        return;
+
+    /* We have to split the register */
+    oldstate = live.state[r];
+
+    setlock(rr); /* Make sure this doesn't go away */
+    /* Forget about r being in the register rr */
+    disassociate(r);
+    /* Get a new register, that we will clobber completely */
+    nr = alloc_reg_hinted(r, 1, -1);
+    nind = live.state[r].realind;
+    live.state[r] = oldstate;   /* Keep all the old state info */
+    live.state[r].realreg = nr;
+    live.state[r].realind = nind;
+
+    if (needcopy) {
+        compemu_raw_mov_l_rr(nr, rr);  /* Make another copy */
+    }
+    unlock2(rr);
+}
+
+static inline int readreg_general(int r, int spec)
+{
+    int answer = -1;
+
+    if (live.state[r].status == UNDEF) {
+        jit_log("WARNING: Unexpected read of undefined register %d", r);
+    }
+
+    if (isinreg(r)) {
+        answer = live.state[r].realreg;
+    } else {
+        /* the value is in memory to start with */
+        answer = alloc_reg_hinted(r, 0, spec);
+    }
+
+    if (spec >= 0 && spec != answer) {
+        /* Too bad */
+        mov_nregs(spec, answer);
+        answer = spec;
+    }
+    live.nat[answer].locked++;
+    live.nat[answer].touched = touchcnt++;
+    return answer;
+}
+
+
+static int readreg(int r)
+{
+    return readreg_general(r, -1);
+}
+
+static int readreg_specific(int r, int spec)
+{
+    return readreg_general(r, spec);
+}
+
+/* writereg(r)
+ *
+ * INPUT
+ * - r    : mid-layer register
+ *
+ * OUTPUT
+ * - hard (physical, x86 here) register allocated to virtual register r
+ */
+static int writereg(int r)
+{
+    int answer = -1;
+
+    make_exclusive(r, 0);
+    if (isinreg(r)) {
+        answer = live.state[r].realreg;
+    } else {
+        /* the value is in memory to start with */
+        answer = alloc_reg_hinted(r, 1, -1);
+    }
+
+    live.nat[answer].locked++;
+    live.nat[answer].touched = touchcnt++;
+    live.state[r].val = 0;
+    set_status(r, DIRTY);
+    return answer;
+}
+
+static int rmw(int r)
+{
+    int answer = -1;
+
+    if (live.state[r].status == UNDEF) {
+        jit_log("WARNING: Unexpected read of undefined register %d", r);
+    }
+    make_exclusive(r, 1);
+
+    if (isinreg(r)) {
+        answer = live.state[r].realreg;
+    } else {
+        /* the value is in memory to start with */
+        answer = alloc_reg_hinted(r, 0, -1);
+    }
+
+    set_status(r, DIRTY);
+
+    live.nat[answer].locked++;
+    live.nat[answer].touched = touchcnt++;
+
+    return answer;
+}
+
+/********************************************************************
+ * FPU register status handling. EMIT TIME!                         *
+ ********************************************************************/
+
+static void f_tomem_drop(int r)
+{
+    if (live.fate[r].status == DIRTY) {
+        compemu_raw_fmov_mr_drop((uintptr)live.fate[r].mem, live.fate[r].realreg);
+        live.fate[r].status = INMEM;
+    }
+}
+
+
+static int f_isinreg(int r)
+{
+    return live.fate[r].status == CLEAN || live.fate[r].status == DIRTY;
+}
+
+static void f_evict(int r)
+{
+    int rr;
+
+    if (!f_isinreg(r))
+        return;
+    rr = live.fate[r].realreg;
+    f_tomem_drop(r);
+
+    live.fat[rr].nholds = 0;
+    live.fate[r].status = INMEM;
+    live.fate[r].realreg = -1;
+}
+
+static inline void f_free_nreg(int r)
+{
+    int vr = live.fat[r].holds;
+    f_evict(vr);
+}
+
+
+/* Use with care! */
+static inline void f_isclean(int r)
+{
+    if (!f_isinreg(r))
+        return;
+    live.fate[r].status = CLEAN;
+}
+
+static inline void f_disassociate(int r)
+{
+    f_isclean(r);
+    f_evict(r);
+}
+
+static int f_alloc_reg(int r, int willclobber)
+{
+    int bestreg;
+
+    if (r < 8)
+        bestreg = r + 8;   // map real Amiga reg to ARM VFP reg 8-15 (call save)
+    else if (r == FP_RESULT)
+        bestreg = 6;         // map FP_RESULT to ARM VFP reg 6
+    else // FS1
+        bestreg = 7;         // map FS1 to ARM VFP reg 7
+
+    if (!willclobber) {
+        if (live.fate[r].status == INMEM) {
+            compemu_raw_fmov_rm(bestreg, (uintptr)live.fate[r].mem);
+            live.fate[r].status = CLEAN;
+        }
+    } else {
+        live.fate[r].status = DIRTY;
+    }
+    live.fate[r].realreg = bestreg;
+    live.fat[bestreg].holds = r;
+    live.fat[bestreg].nholds = 1;
+
+    return bestreg;
+}
+
+static void f_unlock(int r)
+{
+}
+
+static inline int f_readreg(int r)
+{
+    int answer;
+
+    if (f_isinreg(r)) {
+        answer = live.fate[r].realreg;
+    } else {
+        /* the value is in memory to start with */
+        answer = f_alloc_reg(r, 0);
+    }
+
+    return answer;
+}
+
+static inline int f_writereg(int r)
+{
+    int answer;
+
+    if (f_isinreg(r)) {
+        answer = live.fate[r].realreg;
+    }  else {
+        answer = f_alloc_reg(r, 1);
+    }
+    live.fate[r].status = DIRTY;
+    return answer;
+}
+
+STATIC_INLINE int f_rmw(int r)
+{
+    int n;
+
+    if (f_isinreg(r)) {
+        n = live.fate[r].realreg;
+    } else {
+        n = f_alloc_reg(r, 0);
+    }
+    live.fate[r].status = DIRTY;
+    return n;
+}
+
+static void fflags_into_flags_internal(void)
+{
+    int r = f_readreg(FP_RESULT);
+    raw_fflags_into_flags(r);
+    f_unlock(r);
+    live_flags();
+}
+
+/********************************************************************
+ * Support functions, internal                                      *
+ ********************************************************************/
+
+static inline int isinrom(uintptr addr)
+{
+#ifdef UAE
+    if (addr >= (uintptr)kickmem_bank.baseaddr &&
+        addr < (uintptr)kickmem_bank.baseaddr + 8 * 65536) {
+        return 1;
+    }
+    /* Treat UAE Boot ROM (rtarea) as ROM too for ARM64 JIT safety guards. */
+    if (rtarea_bank.baseaddr &&
+        addr >= (uintptr)rtarea_bank.baseaddr &&
+        addr < (uintptr)rtarea_bank.baseaddr + 65536) {
+        return 1;
+    }
+    return 0;
+#else
+    return ((addr >= (uintptr)ROMBaseHost) && (addr < (uintptr)ROMBaseHost + ROMSize));
+#endif
+}
+
+#if defined(UAE) || defined(FLIGHT_RECORDER)
+static void flush_all(void)
+{
+    int i;
+
+    for (i = 0; i < VREGS; i++) {
+        if (live.state[i].status == DIRTY) {
+            if (!call_saved[live.state[i].realreg]) {
+                tomem(i);
+            }
+        }
+    }
+
+    if (f_isinreg(FP_RESULT))
+        f_evict(FP_RESULT);
+    if (f_isinreg(FS1))
+        f_evict(FS1);
+}
+
+
+/* Make sure all registers that will get clobbered by a call are
+   save and sound in memory */
+static void prepare_for_call_1(void)
+{
+    flush_all();  /* If there are registers that don't get clobbered,
+                   * we should be a bit more selective here */
+}
+
+/* We will call a C routine in a moment. That will clobber all registers,
+   so we need to disassociate everything */
+static void prepare_for_call_2(void)
+{
+    int i;
+    for (i = 0; i < N_REGS; i++) {
+#if defined(CPU_AARCH64)
+        if (live.nat[i].nholds > 0) // in aarch64: first 18 regs not call saved
+#else
+        if (!call_saved[i] && live.nat[i].nholds > 0)
+#endif
+            free_nreg(i);
+    }
+
+#ifdef USE_JIT_FPU
+    for (i = 6; i <= 7; i++) // only FP_RESULT and FS1, FP0-FP7 are call save
+        if (live.fat[i].nholds > 0)
+            f_free_nreg(i);
+#endif
+    live.flags_in_flags = TRASH;  /* Note: We assume we already rescued the
+                                     flags at the very start of the call_r functions! */
+}
+#endif
+
+#if defined(CPU_AARCH64)
+#include "compemu_midfunc_arm64.cpp"
+#include "compemu_midfunc_arm64_2.cpp"
+#elif defined(CPU_arm)
+#include "compemu_midfunc_arm.cpp"
+#include "compemu_midfunc_arm2.cpp"
+#endif
+
+/********************************************************************
+ * Support functions exposed to gencomp. CREATE time                *
+ ********************************************************************/
+
+#ifdef __MACH__
+void cache_invalidate(void) {
+        // Invalidate cache on the JIT cache
+        sys_icache_invalidate(popallspace, POPALLSPACE_SIZE + MAX_JIT_CACHE * 1024);
+}
+#endif
+
+uintptr get_const(int r)
+{
+    Dif(!isconst(r)) {
+        jit_abort("Register %d should be constant, but isn't", r);
+    }
+    return live.state[r].val;
+}
+
+uae_u8* compemu_host_pc_from_const(uintptr pc_const)
+{
+    return (uae_u8*)pc_const;
+}
+
+void sync_m68k_pc(void)
+{
+    if (m68k_pc_offset) {
+        arm_ADD_l_ri(PC_P, m68k_pc_offset);
+        comp_pc_p += m68k_pc_offset;
+        m68k_pc_offset = 0;
+    }
+}
+
+/********************************************************************
+ * Support functions exposed to newcpu                              *
+ ********************************************************************/
+
+void compiler_init(void)
+{
+    static bool initialized = false;
+    if (initialized)
+        return;
+
+    flush_icache = flush_icache_none;
+
+    flush_icache = lazy_flush ? flush_icache_lazy : flush_icache_hard;
+
+    initialized = true;
+
+#ifdef PROFILE_UNTRANSLATED_INSNS
+    jit_log("<JIT compiler> : gather statistics on untranslated insns count");
+#endif
+
+#ifdef PROFILE_COMPILE_TIME
+    jit_log("<JIT compiler> : gather statistics on translation time");
+    emul_start_time = clock();
+#endif
+}
+
+void compiler_exit(void)
+{
+
+#ifdef PROFILE_COMPILE_TIME
+    emul_end_time = clock();
+#endif
+
+#ifdef UAE
+#else
+#if DEBUG
+#if defined(USE_DATA_BUFFER)
+    jit_log("data_wasted = %ld bytes", data_wasted);
+#endif
+#endif
+
+    // Deallocate translation cache
+    if (compiled_code) {
+#if defined(CPU_AARCH64)
+        /* Don't free separately if part of the combined popallspace block */
+        if (compiled_code != popall_combined_cache_start) {
+            vm_release(compiled_code, cache_size * 1024);
+        }
+#else
+        vm_release(compiled_code, cache_size * 1024);
+#endif
+        compiled_code = 0;
+    }
+
+    // Deallocate popallspace
+    if (popallspace) {
+#if defined(CPU_AARCH64)
+        vm_release(popallspace, popall_combined_alloc_size ? popall_combined_alloc_size : POPALLSPACE_SIZE);
+        popall_combined_alloc_size = 0;
+        popall_combined_cache_start = NULL;
+        popall_combined_cache_kb = 0;
+#else
+        vm_release(popallspace, POPALLSPACE_SIZE);
+#endif
+        popallspace = 0;
+    }
+#endif
+
+#ifdef PROFILE_COMPILE_TIME
+    jit_log("### Compile Block statistics");
+    jit_log("Number of calls to compile_block : %d", compile_count);
+    uae_u32 emul_time = emul_end_time - emul_start_time;
+    jit_log("Total emulation time   : %.1f sec", double(emul_time) / double(CLOCKS_PER_SEC));
+    jit_log("Total compilation time : %.1f sec (%.1f%%)", double(compile_time) / double(CLOCKS_PER_SEC), 100.0 * double(compile_time) / double(emul_time));
+#endif
+
+#ifdef PROFILE_UNTRANSLATED_INSNS
+    uae_u64 untranslated_count = 0;
+    for (int i = 0; i < 65536; i++) {
+        opcode_nums[i] = i;
+        untranslated_count += raw_cputbl_count[i];
+    }
+    bug("Sorting out untranslated instructions count, total %llu...\n", untranslated_count);
+    qsort(opcode_nums, 65536, sizeof(uae_u16), untranslated_compfn);
+    jit_log("Rank  Opc      Count Name\n");
+    for (int i = 0; i < untranslated_top_ten; i++) {
+        uae_u32 count = raw_cputbl_count[opcode_nums[i]];
+        struct instr* dp;
+        struct mnemolookup* lookup;
+        if (!count)
+            break;
+        dp = table68k + opcode_nums[i];
+        for (lookup = lookuptab; lookup->mnemo != (instrmnem)dp->mnemo; lookup++)
+            ;
+        bug(_T("%03d: %04x %10u %s\n"), i, opcode_nums[i], count, lookup->name);
+    }
+#endif
+
+#ifdef RECORD_REGISTER_USAGE
+    int reg_count_ids[16];
+    uint64 tot_reg_count = 0;
+    for (int i = 0; i < 16; i++) {
+        reg_count_ids[i] = i;
+        tot_reg_count += reg_count[i];
+    }
+    qsort(reg_count_ids, 16, sizeof(int), reg_count_compare);
+    uint64 cum_reg_count = 0;
+    for (int i = 0; i < 16; i++) {
+        int r = reg_count_ids[i];
+        cum_reg_count += reg_count[r];
+        jit_log("%c%d : %16ld %2.1f%% [%2.1f]", r < 8 ? 'D' : 'A', r % 8,
+            reg_count[r],
+            100.0 * double(reg_count[r]) / double(tot_reg_count),
+            100.0 * double(cum_reg_count) / double(tot_reg_count));
+    }
+#endif
+
+	exit_table68k();
+}
+
+static void init_comp(void)
+{
+    int i;
+    uae_s8* au = always_used;
+
+    for (i = 0; i < VREGS; i++) {
+        live.state[i].realreg = -1;
+        live.state[i].val = 0;
+        set_status(i, UNDEF);
+    }
+    for (i = 0; i < SCRATCH_REGS; ++i)
+        live.scratch_in_use[i] = 0;
+
+    for (i = 0; i < VFREGS; i++) {
+        live.fate[i].status = UNDEF;
+        live.fate[i].realreg = -1;
+        live.fate[i].needflush = NF_SCRATCH;
+    }
+
+    for (i = 0; i < VREGS; i++) {
+        if (i < 16) { /* First 16 registers map to 68k registers */
+            live.state[i].mem = &regs.regs[i];
+            set_status(i, INMEM);
+        } else if (i >= S1) {
+            live.state[i].mem = &regs.scratchregs[i - S1];
+        }
+    }
+    live.state[PC_P].mem = (uae_u32*)&(regs.pc_p);
+    set_const(PC_P, (uintptr)comp_pc_p);
+
+    live.state[FLAGX].mem = (uae_u32*)&(regflags.x);
+    set_status(FLAGX, INMEM);
+
+    live.state[FLAGTMP].mem = (uae_u32*)&(regflags.nzcv);
+
+    set_status(FLAGTMP, INMEM);
+    flags_carry_inverted = false;
+
+
+    for (i = 0; i < VFREGS; i++) {
+        if (i < 8) { /* First 8 registers map to 68k FPU registers */
+            live.fate[i].mem = (uae_u32*)(&regs.fp[i].fp);
+            live.fate[i].needflush = NF_TOMEM;
+            live.fate[i].status = INMEM;
+        } else if (i == FP_RESULT) {
+            live.fate[i].mem = (uae_u32*)(&regs.fp_result.fp);
+            live.fate[i].needflush = NF_TOMEM;
+            live.fate[i].status = INMEM;
+        } else {
+            live.fate[i].mem = (uae_u32*)(&regs.scratchfregs[i - 8]);
+        }
+    }
+
+    for (i = 0; i < N_REGS; i++) {
+        live.nat[i].touched = 0;
+        live.nat[i].nholds = 0;
+        live.nat[i].locked = 0;
+        if (*au == i) {
+            live.nat[i].locked = 1;
+            au++;
+        }
+    }
+
+    for (i = 0; i < N_FREGS; i++) {
+        live.fat[i].nholds = 0;
+    }
+
+    touchcnt = 1;
+    m68k_pc_offset = 0;
+    live.flags_in_flags = TRASH;
+    live.flags_on_stack = VALID;
+    live.flags_are_important = 1;
+
+    regs.jit_exception = 0;
+}
+
+/* Only do this if you really mean it! The next call should be to init!*/
+static void flush(int save_regs)
+{
+    int i;
+
+    log_flush();
+    flush_flags(); /* low level */
+    sync_m68k_pc(); /* mid level */
+
+    if (save_regs) {
+        for (i = 0; i < VFREGS; i++) {
+            if (live.fate[i].needflush == NF_SCRATCH || live.fate[i].status == CLEAN) {
+                f_disassociate(i);
+            }
+        }
+        for (i = 0; i <= FLAGTMP; i++) {
+            switch (live.state[i].status) {
+            case INMEM:
+                if (live.state[i].val) {
+                    write_log("JIT: flush INMEM and val != 0!\n");
+                }
+                break;
+            case CLEAN:
+            case DIRTY:
+                tomem(i);
+                break;
+            case ISCONST:
+                if (i != PC_P)
+                    writeback_const(i);
+                break;
+            default:
+                break;
+            }
+        }
+        for (i = 0; i <= FP_RESULT; i++) {
+            if (live.fate[i].status == DIRTY) {
+                f_evict(i);
+            }
+        }
+    }
+}
+
+int alloc_scratch(void)
+{
+    for (int i = 0; i < SCRATCH_REGS; ++i) {
+        if (live.scratch_in_use[i] == 0) {
+            live.scratch_in_use[i] = 1;
+            return S1 + i;
+        }
+    }
+    jit_log("Running out of scratch register.");
+    abort();
+}
+
+void release_scratch(int i)
+{
+    if (i < S1 || i >= S1 + SCRATCH_REGS)
+        jit_log("release_scratch(): %d is not a scratch reg.", i);
+    if (live.scratch_in_use[i - S1]) {
+        forget_about(i);
+        live.scratch_in_use[i - S1] = 0;
+    }
+    else {
+        jit_log("release_scratch(): %d not in use.", i);
+    }
+}
+
+static void freescratch(void)
+{
+    int i;
+    for (i = 0; i < N_REGS; i++) {
+#if defined(CPU_AARCH64)
+        if (live.nat[i].locked && i > 5 && i < 18) {
+#elif defined(CPU_arm)
+        if (live.nat[i].locked && i != 2 && i != 3 && i != 10 && i != 11 && i != 12) {
+#else
+        if (live.nat[i].locked && i != 4 && i != 12) {
+#endif
+            jit_log("Warning! %d is locked", i);
+        }
+    }
+
+    for (i = S1; i < VREGS; i++)
+        forget_about(i);
+    for (i = 0; i < SCRATCH_REGS; ++i)
+        live.scratch_in_use[i] = 0;
+
+#ifdef USE_JIT_FPU
+    f_forget_about(FS1);
+#endif
+}
+
+/********************************************************************
+ * Memory access and related functions, CREATE time                 *
+ ********************************************************************/
+
+void register_branch(uintptr not_taken, uintptr taken, uae_u8 cond)
+{
+    next_pc_p = not_taken;
+    taken_pc_p = taken;
+    branch_cc = cond;
+}
+
+void register_possible_exception(void)
+{
+    may_raise_exception = true;
+}
+
+/* Note: get_handler may fail in 64 Bit environments, if direct_handler_to_use is
+ *       outside 32 bit
+ */
+static uintptr get_handler(uintptr addr)
+{
+    blockinfo* bi = get_blockinfo_addr_new((void*)(uintptr)addr);
+    return (uintptr)bi->direct_handler_to_use;
+}
+
+/* This version assumes that it is writing *real* memory, and *will* fail
+ *  if that assumption is wrong! No branches, no second chances, just
+ *  straight go-for-it attitude */
+
+static void writemem_real(int address, int source, int size)
+{
+    if (currprefs.address_space_24) {
+        switch (size) {
+        case 1: jnf_MEM_WRITE24_OFF_b(address, source); break;
+        case 2: jnf_MEM_WRITE24_OFF_w(address, source); break;
+        case 4: jnf_MEM_WRITE24_OFF_l(address, source); break;
+        }
+    } else {
+        switch (size) {
+        case 1: jnf_MEM_WRITE_OFF_b(address, source); break;
+        case 2: jnf_MEM_WRITE_OFF_w(address, source); break;
+        case 4: jnf_MEM_WRITE_OFF_l(address, source); break;
+        }
+    }
+}
+
+static inline void writemem_special(int address, int source, int offset)
+{
+    jnf_MEM_WRITEMEMBANK(address, source, offset);
+}
+
+void writebyte(int address, int source)
+{
+    if ((special_mem & S_WRITE) || distrust_byte() || jit_n_addr_unsafe)
+        writemem_special(address, source, SIZEOF_VOID_P * 5);
+    else
+        writemem_real(address, source, 1);
+}
+
+void writeword(int address, int source)
+{
+    if ((special_mem & S_WRITE) || distrust_word() || jit_n_addr_unsafe)
+        writemem_special(address, source, SIZEOF_VOID_P * 4);
+    else
+        writemem_real(address, source, 2);
+}
+
+void writelong(int address, int source)
+{
+    if ((special_mem & S_WRITE) || distrust_long() || jit_n_addr_unsafe)
+        writemem_special(address, source, SIZEOF_VOID_P * 3);
+    else
+        writemem_real(address, source, 4);
+}
+
+// Now the same for clobber variant
+void writeword_clobber(int address, int source)
+{
+    if ((special_mem & S_WRITE) || distrust_word() || jit_n_addr_unsafe)
+        writemem_special(address, source, SIZEOF_VOID_P * 4);
+    else
+        writemem_real(address, source, 2);
+    forget_about(source);
+}
+
+void writelong_clobber(int address, int source)
+{
+    if ((special_mem & S_WRITE) || distrust_long() || jit_n_addr_unsafe)
+        writemem_special(address, source, SIZEOF_VOID_P * 3);
+    else
+        writemem_real(address, source, 4);
+    forget_about(source);
+}
+
+
+/* This version assumes that it is reading *real* memory, and *will* fail
+ *  if that assumption is wrong! No branches, no second chances, just
+ *  straight go-for-it attitude */
+
+static void readmem_real(int address, int dest, int size)
+{
+    if (currprefs.address_space_24) {
+        switch (size) {
+        case 1: jnf_MEM_READ24_OFF_b(dest, address); break;
+        case 2: jnf_MEM_READ24_OFF_w(dest, address); break;
+        case 4: jnf_MEM_READ24_OFF_l(dest, address); break;
+        }
+    } else {
+        switch (size) {
+        case 1: jnf_MEM_READ_OFF_b(dest, address); break;
+        case 2: jnf_MEM_READ_OFF_w(dest, address); break;
+        case 4: jnf_MEM_READ_OFF_l(dest, address); break;
+        }
+    }
+}
+
+static inline void readmem_special(int address, int dest, int offset)
+{
+    jnf_MEM_READMEMBANK(dest, address, offset);
+}
+
+void readbyte(int address, int dest)
+{
+    if ((special_mem & S_READ) || distrust_byte() || jit_n_addr_unsafe)
+        readmem_special(address, dest, SIZEOF_VOID_P * 2);
+    else
+        readmem_real(address, dest, 1);
+}
+
+void readword(int address, int dest)
+{
+    if ((special_mem & S_READ) || distrust_word() || jit_n_addr_unsafe)
+        readmem_special(address, dest, SIZEOF_VOID_P * 1);
+    else
+        readmem_real(address, dest, 2);
+}
+
+void readlong(int address, int dest)
+{
+    if ((special_mem & S_READ) || distrust_long() || jit_n_addr_unsafe)
+        readmem_special(address, dest, SIZEOF_VOID_P * 0);
+    else
+        readmem_real(address, dest, 4);
+}
+
+/* This one might appear a bit odd... */
+STATIC_INLINE void get_n_addr_old(int address, int dest)
+{
+    readmem_special(address, dest, SIZEOF_VOID_P * 6);
+}
+
+STATIC_INLINE void get_n_addr_real(int address, int dest)
+{
+    if (currprefs.address_space_24)
+        jnf_MEM_GETADR24_OFF(dest, address);
+    else
+        jnf_MEM_GETADR_OFF(dest, address);
+}
+
+void get_n_addr(int address, int dest)
+{
+    if (special_mem || distrust_addr() || jit_n_addr_unsafe)
+        get_n_addr_old(address, dest);
+    else
+        get_n_addr_real(address, dest);
+}
+
+void get_n_addr_jmp(int address, int dest)
+{
+    /* For this, we need to get the same address as the rest of UAE
+       would --- otherwise we end up translating everything twice */
+    if (special_mem || distrust_addr() || jit_n_addr_unsafe)
+        get_n_addr_old(address, dest);
+    else
+        jnf_MEM_GETADR_JMP_OFF(dest, address);
+}
+
+/* base is a register, but dp is an actual value.
+   target is a register */
+void calc_disp_ea_020(int base, uae_u32 dp, int target)
+{
+    int reg = (dp >> 12) & 15;
+    int regd_shift = (dp >> 9) & 3;
+
+    if (dp & 0x100) {
+        int ignorebase = (dp & 0x80);
+        int ignorereg = (dp & 0x40);
+        int addbase = 0;
+        int outer = 0;
+
+        if ((dp & 0x30) == 0x20)
+            addbase = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset += 2) - 2);
+        if ((dp & 0x30) == 0x30)
+            addbase = comp_get_ilong((m68k_pc_offset += 4) - 4);
+
+        if ((dp & 0x3) == 0x2)
+            outer = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset += 2) - 2);
+        if ((dp & 0x3) == 0x3)
+            outer = comp_get_ilong((m68k_pc_offset += 4) - 4);
+
+        if ((dp & 0x4) == 0) {  /* add regd *before* the get_long */
+            if (!ignorereg) {
+                disp_ea20_target_mov(target, reg, regd_shift, ((dp & 0x800) == 0));
+            } else {
+                mov_l_ri(target, 0);
+            }
+
+            /* target is now regd */
+            if (!ignorebase)
+                arm_ADD_l(target, base);
+            arm_ADD_l_ri(target, addbase);
+            if (dp & 0x03)
+                readlong(target, target);
+        } else { /* do the getlong first, then add regd */
+            if (!ignorebase) {
+                mov_l_rr(target, base);
+                arm_ADD_l_ri(target, addbase);
+            } else {
+                mov_l_ri(target, addbase);
+            }
+            if (dp & 0x03)
+                readlong(target, target);
+
+            if (!ignorereg) {
+                disp_ea20_target_add(target, reg, regd_shift, ((dp & 0x800) == 0));
+            }
+        }
+        arm_ADD_l_ri(target, outer);
+    } else { /* 68000 version */
+        if ((dp & 0x800) == 0) { /* Sign extend */
+            sign_extend_16_rr(target, reg);
+            lea_l_brr_indexed(target, base, target, 1 << regd_shift, (uae_s8)dp);
+        } else {
+            lea_l_brr_indexed(target, base, reg, 1 << regd_shift, (uae_s8)dp);
+        }
+    }
+}
+
+void set_cache_state(int enabled)
+{
+    if (enabled != cache_enabled)
+        flush_icache_hard(3);
+    cache_enabled = enabled;
+}
+
+int get_cache_state(void)
+{
+	return cache_enabled;
+}
+
+uae_u32 get_jitted_size(void)
+{
+	if (compiled_code)
+		return JITPTR current_compile_p - JITPTR compiled_code;
+	return 0;
+}
+
+static uint8 *do_alloc_code(uint32 size, int depth)
+{
+	UNUSED(depth);
+    uint8*code = (uint8 *)vm_acquire_code(size, VM_MAP_DEFAULT | VM_MAP_32BIT);
+	return code == VM_MAP_FAILED ? NULL : code;
+}
+
+static inline uint8 *alloc_code(uint32 size)
+{
+    uint8 *ptr = do_alloc_code(size, 0);
+	/* allocated code must fit in 32-bit boundaries */
+#ifdef CPU_64_BIT
+#if defined(CPU_AARCH64)
+	/* ARM64 JIT is 64-bit pointer clean - tolerate high addresses. */
+	if (ptr && (uintptr)ptr + size > (uintptr)0xffffffff) {
+		static bool arm64_high_jit_logged = false;
+		if (!arm64_high_jit_logged) {
+			jit_log("ARM64: JIT code allocated above 32-bit boundary at %p (size %u)", ptr, size);
+			arm64_high_jit_logged = true;
+		}
+	}
+#else
+	if (ptr && (uintptr)ptr + size > (uintptr)0xffffffff) {
+		jit_log("WARNING: JIT code allocated above 32-bit boundary at %p (size %u)", ptr, size);
+		vm_release(ptr, size);
+		return NULL;
+	}
+#endif
+#endif
+	return ptr;
+}
+
+#if defined(CPU_AARCH64)
+static inline bool arm64_uncond_branch_reachable(uintptr from, uintptr to)
+{
+	/* AArch64 B immediate range: signed 26-bit immediate, shifted left by 2. */
+	const intptr_t diff = (intptr_t)to - (intptr_t)from;
+	const intptr_t min = -(128 * 1024 * 1024);
+	const intptr_t max = (128 * 1024 * 1024) - 4;
+	return diff >= min && diff <= max;
+}
+
+static inline bool arm64_cache_reaches_popall(uint8 *cache_start, uint32 cache_size_bytes)
+{
+	if (!cache_start || !cache_size_bytes || !popallspace) {
+		return false;
+	}
+	const uintptr popall = (uintptr)popallspace;
+	const uintptr start = (uintptr)cache_start;
+	const uintptr end = start + cache_size_bytes - 4;
+	return arm64_uncond_branch_reachable(start, popall) &&
+		arm64_uncond_branch_reachable(end, popall);
+}
+
+#if defined(__APPLE__)
+static uint8 *alloc_code_near_popall(uint32 size)
+{
+	if (!popallspace || size == 0) {
+		return alloc_code(size);
+	}
+#ifdef MAP_JIT
+	const int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
+	const int flags = MAP_PRIVATE | MAP_ANON | MAP_JIT;
+	const uintptr page = (uintptr)uae_vm_page_size();
+	const uintptr anchor = (uintptr)popallspace;
+	const intptr_t max_delta = 120 * 1024 * 1024;
+	const intptr_t step = 4 * 1024 * 1024;
+
+	for (intptr_t delta = 0; delta <= max_delta; delta += step) {
+		for (int dir = 0; dir < 2; dir++) {
+			if (delta == 0 && dir == 1) {
+				continue;
+			}
+			const intptr_t signed_delta = dir == 0 ? delta : -delta;
+			uintptr hint = (uintptr)((intptr_t)anchor + signed_delta);
+			hint &= ~(page - 1);
+			void *p = mmap((void *)hint, size, prot, flags, -1, 0);
+			if (p == MAP_FAILED) {
+				continue;
+			}
+			uint8 *code = (uint8 *)p;
+			if (arm64_cache_reaches_popall(code, size)) {
+				return code;
+			}
+			munmap(code, size);
+		}
+	}
+#endif
+	/* Fallback allocation may place cache out of branch range, checked by caller. */
+	return alloc_code(size);
+}
+#endif /* __APPLE__ */
+#endif /* CPU_AARCH64 */
+
+void alloc_cache(void)
+{
+    if (compiled_code) {
+        flush_icache_hard(3);
+#if defined(CPU_AARCH64)
+        /* Don't free if it's part of the combined popallspace block */
+        if (compiled_code != popall_combined_cache_start) {
+            vm_release(compiled_code, cache_size * 1024);
+        }
+#else
+		vm_release(compiled_code, cache_size * 1024);
+#endif
+        compiled_code = 0;
+    }
+
+    cache_size = currprefs.cachesize;
+    if (cache_size == 0)
+        return;
+
+#if defined(CPU_AARCH64)
+	/* Use pre-allocated cache from the combined popallspace block if available */
+	if (popall_combined_cache_start && (uint32)cache_size <= popall_combined_cache_kb) {
+		compiled_code = popall_combined_cache_start;
+	} else {
+		/* Fall back to separate allocation */
+		while (!compiled_code && cache_size) {
+			const uint32 cache_bytes = cache_size * 1024;
+#if defined(__APPLE__)
+			compiled_code = alloc_code_near_popall(cache_bytes);
+#else
+			compiled_code = alloc_code(cache_bytes);
+#endif
+			if (compiled_code && !arm64_cache_reaches_popall(compiled_code, cache_bytes)) {
+				jit_log("ARM64: JIT cache %p (size %u) is out of branch range from popallspace %p",
+					compiled_code, cache_bytes, popallspace);
+				vm_release(compiled_code, cache_bytes);
+				compiled_code = NULL;
+			}
+			if (compiled_code == NULL) {
+				compiled_code = 0;
+				cache_size /= 2;
+			}
+		}
+	}
+#else
+	while (!compiled_code && cache_size) {
+		const uint32 cache_bytes = cache_size * 1024;
+		compiled_code = alloc_code(cache_bytes);
+		if (compiled_code == NULL) {
+			compiled_code = 0;
+			cache_size /= 2;
+		}
+	}
+	if (compiled_code) {
+		if (!vm_protect(compiled_code, cache_size * 1024, VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE)) {
+			jit_log("WARNING: Failed to set JIT cache to RWX - JIT may crash");
+		}
+	}
+#endif
+
+    if (compiled_code) {
+#if defined(CPU_AARCH64)
+		static bool arm64_jit_mode_logged = false;
+		if (!arm64_jit_mode_logged) {
+#if defined(__APPLE__)
+			jit_log("ARM64 macOS JIT mode: MAP_JIT + write/execute switching");
+#elif defined(__ANDROID__)
+			jit_log("ARM64 Android JIT mode: RWX anonymous mapping");
+#else
+			jit_log("ARM64 JIT mode: RWX anonymous mapping");
+#endif
+			arm64_jit_mode_logged = true;
+		}
+#endif
+        jit_log("<JIT compiler> : actual translation cache size : %d KB at %p-%p\n", cache_size, compiled_code, compiled_code + cache_size * 1024);
+#ifdef USE_DATA_BUFFER
+        max_compile_start = compiled_code + cache_size * 1024 - BYTES_PER_INST - DATA_BUFFER_SIZE;
+#else
+        max_compile_start = compiled_code + cache_size * 1024 - BYTES_PER_INST;
+#endif
+        current_compile_p = compiled_code;
+        current_cache_size = 0;
+#if defined(USE_DATA_BUFFER)
+        reset_data_buffer();
+#endif
+    }
+}
+
+static void calc_checksum(blockinfo* bi, uae_u32* c1, uae_u32* c2)
+{
+    uae_u32 k1 = 0;
+    uae_u32 k2 = 0;
+
+    checksum_info* csi = bi->csi;
+    Dif(!csi) abort();
+    while (csi) {
+        uae_s32 len = csi->length;
+        uintptr tmp = (uintptr)csi->start_p;
+        uae_u32* pos;
+
+        len += (tmp & 3);
+        tmp &= ~((uintptr)3);
+        pos = (uae_u32*)tmp;
+
+        if (len >= 0 && len <= MAX_CHECKSUM_LEN) {
+            while (len > 0) {
+                k1 += *pos;
+                k2 ^= *pos;
+                pos++;
+                len -= 4;
+            }
+        }
+
+        csi = csi->next;
+    }
+
+    *c1 = k1;
+    *c2 = k2;
+}
+
+int check_for_cache_miss(void)
+{
+    blockinfo* bi = get_blockinfo_addr(regs.pc_p);
+
+    if (bi) {
+        int cl = cacheline(regs.pc_p);
+        if (bi != cache_tags[cl + 1].bi) {
+            raise_in_cl_list(bi);
+            return 1;
+        }
+    }
+    return 0;
+}
+
+
+static void recompile_block(void)
+{
+#if defined(JIT_DEBUG_MEM_CORRUPTION) && !defined(_WIN32)
+    jit_dbg_check_vec2_dispatch("recompile_block");
+#endif
+    /* An existing block's countdown code has expired. We need to make
+       sure that execute_normal doesn't refuse to recompile due to a
+       perceived cache miss... */
+    blockinfo* bi = get_blockinfo_addr(regs.pc_p);
+
+    Dif(!bi)
+        jit_abort("recompile_block");
+    raise_in_cl_list(bi);
+    execute_normal();
+}
+
+static void cache_miss(void)
+{
+#if defined(JIT_DEBUG_MEM_CORRUPTION) && !defined(_WIN32)
+    jit_dbg_check_vec2_dispatch("cache_miss");
+#endif
+    blockinfo* bi = get_blockinfo_addr(regs.pc_p);
+#if COMP_DEBUG
+    uae_u32     cl = cacheline(regs.pc_p);
+    blockinfo* bi2 = get_blockinfo(cl);
+#endif
+
+    if (!bi) {
+        execute_normal(); /* Compile this block now */
+        return;
+    }
+    Dif(!bi2 || bi == bi2) {
+        jit_abort("Unexplained cache miss %p %p", bi, bi2);
+    }
+    raise_in_cl_list(bi);
+}
+
+static int called_check_checksum(blockinfo* bi);
+
+static inline int block_check_checksum(blockinfo* bi)
+{
+    uae_u32 c1, c2;
+    int isgood;
+
+    if (bi->status != BI_NEED_CHECK)
+        return 1;  /* This block is in a checked state */
+
+    if (bi->c1 || bi->c2)
+        calc_checksum(bi, &c1, &c2);
+    else
+        c1 = c2 = 1;  /* Make sure it doesn't match */
+
+    isgood = (c1 == bi->c1 && c2 == bi->c2);
+
+    if (isgood) {
+        /* This block is still OK. So we reactivate. Of course, that
+           means we have to move it into the needs-to-be-flushed list */
+        bi->handler_to_use = bi->handler;
+        set_dhtu(bi, bi->direct_handler);
+        bi->status = BI_CHECKING;
+        isgood = called_check_checksum(bi) != 0;
+    }
+    if (isgood) {
+        jit_log2("reactivate %p/%p (%x %x/%x %x)", bi, bi->pc_p, c1, c2, bi->c1, bi->c2);
+        remove_from_list(bi);
+        add_to_active(bi);
+        raise_in_cl_list(bi);
+        bi->status = BI_ACTIVE;
+    } else {
+        /* This block actually changed. We need to invalidate it,
+           and set it up to be recompiled */
+        jit_log2("discard %p/%p (%x %x/%x %x)", bi, bi->pc_p, c1, c2, bi->c1, bi->c2);
+        invalidate_block(bi);
+        raise_in_cl_list(bi);
+    }
+    return isgood;
+}
+
+static int called_check_checksum(blockinfo* bi)
+{
+    int isgood = 1;
+    int i;
+
+    for (i = 0; i < 2 && isgood; i++) {
+        if (bi->dep[i].jmp_off) {
+            isgood = block_check_checksum(bi->dep[i].target);
+        }
+    }
+    return isgood;
+}
+
+static void check_checksum(void)
+{
+    blockinfo* bi = get_blockinfo_addr(regs.pc_p);
+    uae_u32 cl = cacheline(regs.pc_p);
+    blockinfo* bi2 = get_blockinfo(cl);
+
+    /* These are not the droids you are looking for...  */
+    if (!bi) {
+        /* Whoever is the primary target is in a dormant state, but
+           calling it was accidental, and we should just compile this
+           new block */
+        execute_normal();
+        return;
+    }
+    if (bi != bi2) {
+        /* The block was hit accidentally, but it does exist. Cache miss */
+        cache_miss();
+        return;
+    }
+
+    if (!block_check_checksum(bi))
+        execute_normal();
+}
+
+STATIC_INLINE void match_states(blockinfo* bi)
+{
+    if (bi->status == BI_NEED_CHECK) {
+        block_check_checksum(bi);
+    }
+}
+
+STATIC_INLINE void create_popalls(void)
+{
+    int i, r;
+
+    if (popallspace == NULL) {
+#if defined(CPU_AARCH64)
+        /* On ARM64, allocate popallspace + JIT cache as one contiguous block
+         * to guarantee the cache is within B/BL branch range (+-128 MB). */
+        if (currprefs.cachesize > 0) {
+            const uint32 cache_kb = currprefs.cachesize;
+            const size_t cache_bytes = (size_t)cache_kb * 1024;
+            const size_t combined_size = POPALLSPACE_SIZE + cache_bytes;
+            jit_log("ARM64: allocating popallspace+cache (cache=%u KB, total=%zu bytes)",
+                cache_kb, combined_size);
+            popallspace = alloc_code(combined_size);
+            if (popallspace) {
+                popall_combined_alloc_size = combined_size;
+                popall_combined_cache_start = popallspace + POPALLSPACE_SIZE;
+                popall_combined_cache_kb = cache_kb;
+                jit_log("ARM64: combined popallspace+cache allocation at %p (%u KB cache)",
+                    popallspace, cache_kb);
+            } else {
+                /* Fall back to popallspace-only allocation */
+                popall_combined_alloc_size = 0;
+                popall_combined_cache_start = NULL;
+                popall_combined_cache_kb = 0;
+                jit_log("ARM64: combined popallspace+cache allocation failed; retrying popallspace-only (%u bytes)",
+                    (unsigned)POPALLSPACE_SIZE);
+                popallspace = alloc_code(POPALLSPACE_SIZE);
+            }
+        } else {
+            popall_combined_alloc_size = 0;
+            popall_combined_cache_start = NULL;
+            popall_combined_cache_kb = 0;
+            popallspace = alloc_code(POPALLSPACE_SIZE);
+        }
+        if (popallspace == NULL) {
+#else
+        if ((popallspace = alloc_code(POPALLSPACE_SIZE)) == NULL) {
+#endif
+            jit_log("WARNING: Could not allocate popallspace!");
+            if (currprefs.cachesize > 0)
+            {
+#if defined(_WIN32) && defined(CPU_AARCH64)
+                /* Windows ARM64: RWX allocations can be denied by VBS/HVCI or
+                 * similar security policies (commonly seen in VMware WoA VMs).
+                 * Rather than jit_abort() (which kills the process), log
+                 * clearly and fall back to the interpreter - the caller will
+                 * call disable_jit_runtime() on our NULL pushall_call_handler. */
+                jit_log("ARM64: Windows RWX allocation denied - disabling JIT. "
+                    "Check VBS/HVCI/Arbitrary Code Guard policy in the VM.");
+#else
+                jit_abort("Could not allocate popallspace!");
+#endif
+            }
+            /* This is not fatal if JIT is not used. If JIT is
+             * turned on, it will crash, but it would have crashed
+             * anyway. */
+            return;
+        }
+    }
+#if !defined(CPU_AARCH64)
+    /* On non-ARM64, code memory was allocated RW-only; this is a no-op there.
+     * On ARM64, code memory is already RWX from allocation - skip. */
+    vm_protect(popallspace, POPALLSPACE_SIZE, VM_PAGE_READ | VM_PAGE_WRITE);
+#endif
+	jit_begin_write_window();
+
+    current_compile_p = popallspace;
+    set_target(current_compile_p);
+
+#if defined(CPU_arm) && !defined(ARMV6T2) && !defined(CPU_AARCH64)
+    reset_data_buffer();
+    data_long(0, 0); // Make sure we emit the branch over the first buffer outside pushall_call_handler
+#endif
+
+  /* We need to guarantee 16-byte stack alignment on x86 at any point
+     within the JIT generated code. We have multiple exit points
+     possible but a single entry. A "jmp" is used so that we don't
+     have to generate stack alignment in generated code that has to
+     call external functions (e.g. a generic instruction handler).
+
+     In summary, JIT generated code is not leaf so we have to deal
+     with it here to maintain correct stack alignment. */
+    current_compile_p = get_target();
+    pushall_call_handler = get_target();
+    raw_push_regs_to_preserve();
+#ifdef JIT_DEBUG
+    write_log("Address of regs: 0x%016x, regs.pc_p: 0x%016x\n", &regs, &regs.pc_p);
+    write_log("Address of natmem_offset: 0x%016x, natmem_offset = 0x%016x\n", &natmem_offset, natmem_offset);
+    write_log("Address of cache_tags: 0x%016x\n", cache_tags);
+#endif
+    compemu_raw_init_r_regstruct((uintptr)&regs);
+    compemu_raw_jmp_pc_tag();
+
+    /* now the exit points */
+    popall_execute_normal_setpc = get_target();
+    uintptr idx = (uintptr) & (regs.pc_p) - (uintptr)&regs;
+#if defined(CPU_AARCH64)
+    STR_xXi(REG_WORK1, R_REGSTRUCT, idx);
+#else
+    STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+#endif
+    popall_execute_normal = get_target();
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)execute_normal);
+
+    popall_check_checksum_setpc = get_target();
+#if defined(CPU_AARCH64)
+    STR_xXi(REG_WORK1, R_REGSTRUCT, idx);
+#else
+    STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+#endif
+    popall_check_checksum = get_target();
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)check_checksum);
+
+    popall_exec_nostats_setpc = get_target();
+#if defined(CPU_AARCH64)
+    STR_xXi(REG_WORK1, R_REGSTRUCT, idx);
+#else
+    STR_rRI(REG_WORK1, R_REGSTRUCT, idx);
+#endif
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)exec_nostats);
+
+    popall_recompile_block = get_target();
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)recompile_block);
+
+    popall_do_nothing = get_target();
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)do_nothing);
+
+    popall_cache_miss = get_target();
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)cache_miss);
+
+    popall_execute_exception = get_target();
+    raw_pop_preserved_regs();
+    compemu_raw_jmp((uintptr)execute_exception);
+
+#if defined(USE_DATA_BUFFER)
+    reset_data_buffer();
+#endif
+
+    // no need to further write into popallspace
+#if defined(CPU_AARCH64)
+    // ARM64 has separate I-cache and D-cache: we MUST flush the I-cache
+    // after writing code before making it executable, or we'll execute
+    // stale/random data from the I-cache.
+    flush_cpu_icache((void *)popallspace, (void *)get_target());
+#endif
+#if !defined(CPU_AARCH64)
+	vm_protect(popallspace, POPALLSPACE_SIZE, VM_PAGE_READ | VM_PAGE_EXECUTE);
+#endif
+	jit_end_write_window();
+}
+
+static inline void reset_lists(void)
+{
+    int i;
+
+    for (i = 0; i < MAX_HOLD_BI; i++)
+        hold_bi[i] = NULL;
+    active = NULL;
+    dormant = NULL;
+}
+
+static void prepare_block(blockinfo* bi)
+{
+    int i;
+
+	jit_begin_write_window();
+    set_target(current_compile_p);
+    bi->direct_pen = (cpuop_func*)get_target();
+    compemu_raw_execute_normal((uintptr) & (bi->pc_p));
+
+    bi->direct_pcc = (cpuop_func*)get_target();
+    compemu_raw_check_checksum((uintptr) & (bi->pc_p));
+
+    flush_cpu_icache((void*)current_compile_p, (void*)target);
+	jit_end_write_window();
+    current_compile_p = get_target();
+
+    bi->deplist = NULL;
+    for (i = 0; i < 2; i++) {
+        bi->dep[i].prev_p = NULL;
+        bi->dep[i].next = NULL;
+    }
+    bi->status = BI_INVALID;
+    bi->needed_flags = FLAG_ALL;
+}
+
+void compemu_reset(void)
+{
+    flush_icache = lazy_flush ? flush_icache_lazy : flush_icache_hard;
+    set_cache_state(0);
+}
+
+// OPCODE is in big endian format
+static inline void reset_compop(int opcode)
+{
+    compfunctbl[opcode] = NULL;
+    nfcompfunctbl[opcode] = NULL;
+}
+
+void build_comp(void)
+{
+    int i, j;
+    unsigned long opcode;
+    const struct comptbl* tbl = op_smalltbl_0_comp_ff;
+    const struct comptbl* nftbl = op_smalltbl_0_comp_nf;
+    unsigned int cpu_level = (currprefs.cpu_model - 68000) / 10;
+    if (cpu_level > 4)
+        cpu_level--;
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+    const struct cputbl* nfctbl = uaegetjitcputbl();
+#endif
+
+    regs.mem_banks = (uintptr)mem_banks;
+    regs.cache_tags = (uintptr)cache_tags;
+
+    jit_log("<JIT compiler> : building compiler function tables");
+
+    for (opcode = 0; opcode < 65536; opcode++) {
+        reset_compop(opcode);
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+        nfcpufunctbl[opcode] = op_illg;
+#endif
+        prop[opcode].use_flags = FLAG_ALL;
+        prop[opcode].set_flags = FLAG_ALL;
+        prop[opcode].cflow = fl_trap; // ILLEGAL instructions do trap
+    }
+
+    for (i = 0; tbl[i].opcode < 65536; i++) {
+        int cflow = table68k[tbl[i].opcode].cflow;
+        if (follow_const_jumps && (tbl[i].specific & COMP_OPCODE_ISCJUMP))
+            cflow = fl_const_jump;
+        else
+            cflow &= ~fl_const_jump;
+        prop[cft_map(tbl[i].opcode)].cflow = cflow;
+
+        bool uses_fpu = (tbl[i].specific & COMP_OPCODE_USES_FPU) != 0;
+        if (uses_fpu && avoid_fpu)
+            compfunctbl[cft_map(tbl[i].opcode)] = NULL;
+        else
+            compfunctbl[cft_map(tbl[i].opcode)] = tbl[i].handler;
+    }
+
+    for (i = 0; nftbl[i].opcode < 65536; i++) {
+        bool uses_fpu = (tbl[i].specific & COMP_OPCODE_USES_FPU) != 0;
+        if (uses_fpu && avoid_fpu)
+            nfcompfunctbl[cft_map(nftbl[i].opcode)] = NULL;
+        else
+            nfcompfunctbl[cft_map(nftbl[i].opcode)] = nftbl[i].handler;
+        for (j = 0; nfctbl[j].handler_ff; j++) {
+            if (nfctbl[j].opcode == nftbl[i].opcode) {
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+#ifdef NOFLAGS_SUPPORT_GENCPU
+                nfcpufunctbl[cft_map(nftbl[i].opcode)] = nfctbl[j].handler_nf;
+#else
+                nfcpufunctbl[cft_map(nftbl[i].opcode)] = nfctbl[j].handler_ff;
+#endif
+#endif
+                break;
+            }
+        }
+        if (!nfctbl[j].handler_ff && currprefs.cachesize) {
+            int mnemo = table68k[nftbl[i].opcode].mnemo;
+            struct mnemolookup* lookup;
+            for (lookup = lookuptab; lookup->mnemo != mnemo; lookup++)
+                ;
+            char* s = ua(lookup->name);
+            jit_log("%04x (%s) unavailable", nftbl[i].opcode, s);
+            xfree(s);
+        }
+    }
+
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+#ifdef NOFLAGS_SUPPORT_GENCPU
+    for (i = 0; nfctbl[i].handler_nf; i++) {
+        nfcpufunctbl[cft_map(nfctbl[i].opcode)] = nfctbl[i].handler_nf;
+    }
+#else
+    for (i = 0; nfctbl[i].handler_ff; i++) {
+        nfcpufunctbl[cft_map(nfctbl[i].opcode)] = nfctbl[i].handler_ff;
+    }
+#endif
+#endif
+
+    for (opcode = 0; opcode < 65536; opcode++) {
+        compop_func* f;
+        compop_func* nff;
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+        cpuop_func* nfcf;
+#endif
+        int isaddx, cflow;
+
+        if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
+            continue;
+
+        if (table68k[opcode].handler != -1) {
+            f = compfunctbl[cft_map(table68k[opcode].handler)];
+            nff = nfcompfunctbl[cft_map(table68k[opcode].handler)];
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+            nfcf = nfcpufunctbl[cft_map(table68k[opcode].handler)];
+#endif
+            isaddx = prop[cft_map(table68k[opcode].handler)].is_addx;
+            prop[cft_map(opcode)].is_addx = isaddx;
+            cflow = prop[cft_map(table68k[opcode].handler)].cflow;
+            prop[cft_map(opcode)].cflow = cflow;
+            compfunctbl[cft_map(opcode)] = f;
+            nfcompfunctbl[cft_map(opcode)] = nff;
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+            Dif(nfcf == op_illg)
+                abort();
+            nfcpufunctbl[cft_map(opcode)] = nfcf;
+#endif
+        }
+        prop[cft_map(opcode)].set_flags = table68k[opcode].flagdead;
+        prop[cft_map(opcode)].use_flags = table68k[opcode].flaglive;
+        /* Unconditional jumps don't evaluate condition codes, so they
+         * don't actually use any flags themselves */
+        if (prop[cft_map(opcode)].cflow & fl_const_jump)
+            prop[cft_map(opcode)].use_flags = 0;
+    }
+
+    for (i = 0; nfctbl[i].handler_ff != NULL; i++) {
+        if (nfctbl[i].specific)
+            nfcpufunctbl[cft_map(tbl[i].opcode)] = nfctbl[i].handler_ff;
+    }
+
+    int count = 0;
+    for (opcode = 0; opcode < 65536; opcode++) {
+        if (compfunctbl[cft_map(opcode)])
+            count++;
+    }
+    jit_log("<JIT compiler> : supposedly %d compileable opcodes!", count);
+
+	/* Initialise state */
+	create_popalls();
+	if (!pushall_call_handler || !popall_execute_normal) {
+		disable_jit_runtime("failed to initialize JIT dispatcher stubs (popallspace)");
+		return;
+	}
+	alloc_cache();
+	if (currprefs.cachesize == 0)
+		return;
+	if (!compiled_code) {
+		disable_jit_runtime("failed to allocate ARM64 JIT code cache");
+		return;
+	}
+	reset_lists();
+
+    for (i = 0; i < TAGSIZE; i += 2) {
+        cache_tags[i].handler = (cpuop_func*)popall_execute_normal;
+        cache_tags[i + 1].bi = NULL;
+    }
+    compemu_reset();
+}
+
+static void flush_icache_none(int v)
+{
+    /* Nothing to do.  */
+}
+
+void flush_icache_hard(int n)
+{
+    blockinfo* bi, * dbi;
+
+    bi = active;
+    while (bi) {
+        cache_tags[cacheline(bi->pc_p)].handler = (cpuop_func*)popall_execute_normal;
+        cache_tags[cacheline(bi->pc_p) + 1].bi = NULL;
+        dbi = bi;
+        bi = bi->next;
+        free_blockinfo(dbi);
+    }
+    bi = dormant;
+    while (bi) {
+        cache_tags[cacheline(bi->pc_p)].handler = (cpuop_func*)popall_execute_normal;
+        cache_tags[cacheline(bi->pc_p) + 1].bi = NULL;
+        dbi = bi;
+        bi = bi->next;
+        free_blockinfo(dbi);
+    }
+
+    reset_lists();
+    if (!compiled_code)
+        return;
+
+#if defined(USE_DATA_BUFFER)
+    reset_data_buffer();
+#endif
+
+    current_compile_p = compiled_code;
+    set_special(0); /* To get out of compiled code */
+}
+
+/* "Soft flushing" --- instead of actually throwing everything away,
+we simply mark everything as "needs to be checked".
+*/
+
+static inline void flush_icache_lazy(int v)
+{
+    blockinfo* bi;
+    blockinfo* bi2;
+
+    if (!active)
+        return;
+
+    bi = active;
+    while (bi) {
+        uae_u32 cl = cacheline(bi->pc_p);
+        if (bi->status == BI_INVALID || bi->status == BI_NEED_RECOMP) {
+            if (bi == cache_tags[cl + 1].bi)
+                cache_tags[cl].handler = (cpuop_func*)popall_execute_normal;
+            bi->handler_to_use = (cpuop_func*)popall_execute_normal;
+            set_dhtu(bi, bi->direct_pen);
+            bi->status = BI_INVALID;
+        } else {
+            if (bi == cache_tags[cl + 1].bi)
+                cache_tags[cl].handler = (cpuop_func*)popall_check_checksum;
+            bi->handler_to_use = (cpuop_func*)popall_check_checksum;
+            set_dhtu(bi, bi->direct_pcc);
+            bi->status = BI_NEED_CHECK;
+        }
+        bi2 = bi;
+        bi = bi->next;
+    }
+    /* bi2 is now the last entry in the active list */
+    bi2->next = dormant;
+    if (dormant)
+        dormant->prev_p = &(bi2->next);
+
+    dormant = active;
+    active->prev_p = &dormant;
+    active = NULL;
+}
+
+int failure;
+
+static inline unsigned int get_opcode_cft_map(unsigned int f)
+{
+    return uae_bswap_16(f);
+}
+#define DO_GET_OPCODE(a) (get_opcode_cft_map((uae_u16)*(a)))
+
+void compile_block(cpu_history* pc_hist, int blocklen, int totcycles)
+{
+    if (cache_enabled && compiled_code && currprefs.cpu_model >= 68020) {
+		jit_begin_write_window();
+#ifdef PROFILE_COMPILE_TIME
+        compile_count++;
+        clock_t start_time = clock();
+#endif
+
+        /* OK, here we need to 'compile' a block */
+        int i;
+        int r;
+        int was_comp = 0;
+        uae_u8 liveflags[MAXRUN + 1];
+        bool trace_in_rom = isinrom((uintptr)pc_hist[0].location) != 0;
+        uintptr max_pcp = (uintptr)pc_hist[blocklen - 1].location;
+        uintptr min_pcp = max_pcp;
+        uae_u32 cl = cacheline(pc_hist[0].location);
+		void* specflags=(void*)&regs.spcflags;
+        blockinfo* bi = NULL;
+        blockinfo* bi2;
+		int extra_len=0;
+
+        redo_current_block = 0;
+        if (current_compile_p >= MAX_COMPILE_PTR)
+            flush_icache_hard(3);
+
+        alloc_blockinfos();
+
+        bi = get_blockinfo_addr_new(pc_hist[0].location);
+        bi2 = get_blockinfo(cl);
+
+        optlev = bi->optlevel;
+#if defined(CPU_AARCH64)
+        /* When cpu_compatible is set, force blocks to interpreter mode */
+        if (currprefs.cpu_compatible) {
+            optlev = 0;
+        }
+#endif
+        if (bi->status != BI_INVALID) {
+            Dif(bi != bi2) {
+                /* I don't think it can happen anymore. Shouldn't, in
+                   any case. So let's make sure... */
+                jit_abort("WOOOWOO count=%d, ol=%d %p %p", bi->count, bi->optlevel, bi->handler_to_use, cache_tags[cl].handler);
+            }
+
+            Dif(bi->count != -1 && bi->status != BI_NEED_RECOMP) {
+                jit_abort("bi->count=%d, bi->status=%d,bi->optlevel=%d", bi->count, bi->status, bi->optlevel);
+                /* What the heck? We are not supposed to be here! */
+            }
+        }
+        if (bi->count == -1) {
+#if defined(CPU_AARCH64)
+            if (currprefs.cpu_compatible) {
+                optlev = 0;
+            } else
+#endif
+            {
+            optlev++;
+            while (!optcount[optlev])
+                optlev++;
+            bi->count = optcount[optlev] - 1;
+            }
+        }
+        current_block_pc_p = JITPTR pc_hist[0].location;
+
+        /* Save successor needed_flags BEFORE remove_deps clears them.
+           On recompilation, deps still point to the previous successor blocks.
+           Use their needed_flags to initialize liveflags[blocklen] more
+           precisely than the conservative FLAG_ALL. This allows the backward
+           liveflags analysis to eliminate more flag operations within the block.
+           First compilation or after invalidation: deps are NULL, falls back to FLAG_ALL.
+           Only use needed_flags from blocks that have actually been compiled
+           (status != BI_INVALID), since uncompiled blocks have uninitialized flags. */
+        uae_u8 successor_flags = FLAG_ALL;
+        if (bi->dep[0].target && bi->dep[0].target->status != BI_INVALID) {
+            successor_flags = bi->dep[0].target->needed_flags;
+            if (bi->dep[1].target) {
+                if (bi->dep[1].target->status != BI_INVALID)
+                    successor_flags |= bi->dep[1].target->needed_flags;
+                else
+                    successor_flags = FLAG_ALL; /* dep[1] uncompiled, be conservative */
+            }
+        }
+
+        remove_deps(bi); /* We are about to create new code */
+        bi->optlevel = optlev;
+        bi->pc_p = (uae_u8*)pc_hist[0].location;
+        free_checksum_info_chain(bi->csi);
+        bi->csi = NULL;
+
+        liveflags[blocklen] = successor_flags; /* Use successor info if available, else FLAG_ALL */
+        i = blocklen;
+        while (i--) {
+            uae_u16* currpcp = pc_hist[i].location;
+            uae_u32 op = DO_GET_OPCODE(currpcp);
+
+            trace_in_rom = trace_in_rom && isinrom((uintptr)currpcp);
+            if (follow_const_jumps && is_const_jump(op)) {
+                checksum_info* csi = alloc_checksum_info();
+                csi->start_p = (uae_u8*)min_pcp;
+                csi->length = JITPTR max_pcp - JITPTR min_pcp + LONGEST_68K_INST;
+                csi->next = bi->csi;
+                bi->csi = csi;
+                max_pcp = (uintptr)currpcp;
+            }
+            min_pcp = (uintptr)currpcp;
+
+            if (!currprefs.compnf) {
+                liveflags[i] = FLAG_ALL;
+            }
+            else
+            {
+                liveflags[i] = ((liveflags[i + 1] & (~prop[op].set_flags)) | prop[op].use_flags);
+                if (prop[op].is_addx && (liveflags[i + 1] & FLAG_Z) == 0)
+                    liveflags[i] &= ~FLAG_Z;
+            }
+        }
+
+        checksum_info* csi = alloc_checksum_info();
+        csi->start_p = (uae_u8*)min_pcp;
+        csi->length = max_pcp - min_pcp + LONGEST_68K_INST;
+        csi->next = bi->csi;
+        bi->csi = csi;
+
+        bi->needed_flags = liveflags[0];
+
+        /* This is the non-direct handler */
+        was_comp = 0;
+
+        bi->direct_handler = (cpuop_func*)get_target();
+        set_dhtu(bi, bi->direct_handler);
+        bi->status = BI_COMPILING;
+        current_block_start_target = (uintptr)get_target();
+
+        if (bi->count >= 0) { /* Need to generate countdown code */
+            compemu_raw_set_pc_i((uintptr)pc_hist[0].location);
+            compemu_raw_dec_m((uintptr) & (bi->count));
+            compemu_raw_maybe_recompile();
+        }
+        if (optlev == 0) { /* No need to actually translate */
+          /* Execute normally without keeping stats */
+            compemu_raw_exec_nostats((uintptr)pc_hist[0].location);
+        } else {
+            reg_alloc_run = 0;
+            next_pc_p = 0;
+            taken_pc_p = 0;
+            branch_cc = 0; // Only to be initialized. Will be set together with next_pc_p
+
+            comp_pc_p = (uae_u8*)pc_hist[0].location;
+            init_comp();
+            was_comp = 1;
+
+            for (i = 0; i < blocklen && get_target() < MAX_COMPILE_PTR; i++) {
+                may_raise_exception = false;
+                cpuop_func** cputbl;
+                compop_func** comptbl;
+                uae_u32 opcode = DO_GET_OPCODE(pc_hist[i].location);
+                needed_flags = (liveflags[i + 1] & prop[opcode].set_flags);
+                special_mem = pc_hist[i].specmem;
+                if (!needed_flags && currprefs.compnf) {
+#ifdef NOFLAGS_SUPPORT_GENCOMP
+                    cputbl = nfcpufunctbl;
+#else
+                    cputbl = cpufunctbl;
+#endif
+                    comptbl = nfcompfunctbl;
+                } else {
+                    cputbl = cpufunctbl;
+                    comptbl = compfunctbl;
+                }
+
+
+                failure = 1; // gb-- defaults to failure state
+                if (comptbl[opcode] && optlev > 1) {
+                    failure = 0;
+                    if (!was_comp) {
+                        comp_pc_p = (uae_u8*)pc_hist[i].location;
+                        init_comp();
+                    }
+                    was_comp = 1;
+
+                    comptbl[opcode](opcode);
+                    freescratch();
+                    if (!(liveflags[i + 1] & FLAG_CZNV)) {
+                        /* We can forget about flags */
+                        dont_care_flags();
+                    }
+                }
+
+
+                if (failure) {
+                    if (was_comp) {
+                        flush(1);
+                        was_comp = 0;
+                    }
+                    compemu_raw_mov_l_ri(REG_PAR1, (uae_u32)opcode);
+                    compemu_raw_mov_l_rr(REG_PAR2, R_REGSTRUCT);
+                    compemu_raw_set_pc_i((uintptr)pc_hist[i].location);
+                    compemu_raw_call((uintptr)cputbl[opcode]);
+#ifdef PROFILE_UNTRANSLATED_INSNS
+                    // raw_cputbl_count[] is indexed with plain opcode (in m68k order)
+                    compemu_raw_inc_opcount(opcode);
+#endif
+
+                    if (i < blocklen - 1) {
+                        uae_u8* branchadd;
+
+                        /* if (SPCFLAGS_TEST(SPCFLAG_ALL)) popall_do_nothing() */
+                        compemu_raw_mov_l_rm(0, (uintptr)specflags);
+#if defined(USE_DATA_BUFFER)
+                        data_check_end(8, 64);
+#endif
+                        compemu_raw_maybe_do_nothing(scaled_cycles(totcycles));
+                    }
+                } else if (may_raise_exception) {
+#if defined(USE_DATA_BUFFER)
+                    data_check_end(8, 64);
+#endif
+                    compemu_raw_handle_except(scaled_cycles(totcycles));
+                    may_raise_exception = false;
+                }
+            }
+            if (next_pc_p && taken_pc_p &&
+                was_comp && taken_pc_p == current_block_pc_p)
+            {
+                blockinfo* bi1 = get_blockinfo_addr_new((void*)next_pc_p);
+                blockinfo* bi2 = get_blockinfo_addr_new((void*)taken_pc_p);
+                uae_u8 x = bi1->needed_flags;
+
+                if (x == 0xff) {  /* Block not yet compiled - use conservative single-op lookahead */
+                    uae_u16* next = (uae_u16*)next_pc_p;
+                    uae_u32 op = DO_GET_OPCODE(next);
+
+                    x = FLAG_ALL;
+                    x &= (~prop[op].set_flags);
+                    x |= prop[op].use_flags;
+                }
+                /* else: bi1->needed_flags already has the full block's requirements */
+
+                x |= bi2->needed_flags;
+                if (!(x & FLAG_CZNV)) {
+                    /* Save flags to memory FIRST, so the interpreter slow path
+                       (countdown < 0 -> popall_do_nothing) has correct regflags.nzcv.
+                       Then mark flags as unimportant so successor blocks benefit
+                       from not needing to restore them. flush(1) will see
+                       flags_on_stack==VALID and skip the redundant save. */
+                    flush_flags();
+                    dont_care_flags();
+                }
+            }
+            log_flush();
+
+            if (next_pc_p) { /* A branch was registered */
+                uintptr t1 = next_pc_p;
+                uintptr t2 = taken_pc_p;
+                int cc = branch_cc; // this is native (ARM) condition code
+
+                uae_u32* branchadd;
+                uae_u32* tba;
+                bigstate tmp;
+                blockinfo* tbi;
+
+                if (taken_pc_p < next_pc_p) {
+                    /* backward branch. Optimize for the "taken" case ---
+                       which means the raw_jcc should fall through when
+                       the 68k branch is taken. */
+                    t1 = taken_pc_p;
+                    t2 = next_pc_p;
+                    if (cc < NATIVE_CC_AL)
+                        cc = branch_cc ^ 1;
+                    else if (cc > NATIVE_CC_AL)
+                        cc = 0x10 | (branch_cc ^ 0xf);
+                }
+
+#if defined(USE_DATA_BUFFER)
+                data_check_end(8, 128);
+#endif
+                flush(1);                       // Emitted code of this call doesn't modify flags
+                compemu_raw_jcc_l_oponly(cc);   // Last emitted opcode is branch to target
+                branchadd = (uae_u32*)get_target() - 1;
+
+                /* predicted outcome */
+                tbi = get_blockinfo_addr_new((void*)t1);
+                match_states(tbi);
+
+                tba = compemu_raw_endblock_pc_isconst(scaled_cycles(totcycles), t1);
+                write_jmp_target(tba, get_handler(t1));
+                create_jmpdep(bi, 0, tba, t1);
+
+                /* not-predicted outcome */
+                write_jmp_target(branchadd, (uintptr)get_target());
+                tbi = get_blockinfo_addr_new((void*)t2);
+                match_states(tbi);
+
+                tba = compemu_raw_endblock_pc_isconst(scaled_cycles(totcycles), t2);
+                write_jmp_target(tba, get_handler(t2));
+                create_jmpdep(bi, 1, tba, t2);
+            } else {
+                if (was_comp) {
+                    flush(1);
+                }
+
+                /* Let's find out where next_handler is... */
+                if (was_comp && isinreg(PC_P)) {
+#if defined(USE_DATA_BUFFER)
+                    data_check_end(4, 64);
+#endif
+                    r = live.state[PC_P].realreg;
+                    compemu_raw_endblock_pc_inreg(r, scaled_cycles(totcycles));
+                } else if (was_comp && isconst(PC_P)) {
+                    uintptr v = live.state[PC_P].val;
+                    uae_u32* tba;
+                    blockinfo* tbi;
+
+
+                    tbi = get_blockinfo_addr_new((void*)v);
+                    match_states(tbi);
+
+#if defined(USE_DATA_BUFFER)
+                    data_check_end(4, 64);
+#endif
+                    tba = compemu_raw_endblock_pc_isconst(scaled_cycles(totcycles), v);
+                    write_jmp_target(tba, get_handler(v));
+                    create_jmpdep(bi, 0, tba, v);
+                } else {
+                    r = REG_PC_TMP;
+                    compemu_raw_mov_l_rm(r, (uintptr)&regs.pc_p);
+#if defined(USE_DATA_BUFFER)
+                    data_check_end(4, 64);
+#endif
+                    compemu_raw_endblock_pc_inreg(r, scaled_cycles(totcycles));
+                }
+            }
+        }
+
+        remove_from_list(bi);
+        if (trace_in_rom) {
+            // No need to checksum that block trace on cache invalidation
+            free_checksum_info_chain(bi->csi);
+            bi->csi = NULL;
+            add_to_dormant(bi);
+        } else {
+            calc_checksum(bi, &(bi->c1), &(bi->c2));
+            add_to_active(bi);
+        }
+
+        current_cache_size += JITPTR get_target() - JITPTR current_compile_p;
+
+        /* This is the non-direct handler */
+        bi->handler = bi->handler_to_use = (cpuop_func*)get_target();
+        compemu_raw_cmp_pc((uintptr)pc_hist[0].location);
+        compemu_raw_maybe_cachemiss();
+        comp_pc_p = (uae_u8*)pc_hist[0].location;
+
+        bi->status = BI_FINALIZING;
+        init_comp();
+        match_states(bi);
+        flush(1);
+
+        compemu_raw_jmp((uintptr)bi->direct_handler);
+
+
+
+        flush_cpu_icache((void*)current_block_start_target, (void*)target);
+        current_compile_p = get_target();
+        raise_in_cl_list(bi);
+        bi->nexthandler = current_compile_p;
+
+        /* We will flush soon, anyway, so let's do it now */
+        if (current_compile_p >= MAX_COMPILE_PTR)
+            flush_icache_hard(3);
+
+        bi->status = BI_ACTIVE;
+        if (redo_current_block)
+            block_need_recompile(bi);
+
+#if defined(JIT_DEBUG_MEM_CORRUPTION) && !defined(_WIN32)
+        jit_dbg_check_vec2_dispatch("compile_block_end");
+#endif
+
+#ifdef PROFILE_COMPILE_TIME
+        compile_time += (clock() - start_time);
+#endif
+        /* Account for compilation time */
+        do_extra_cycles(totcycles);
+		jit_end_write_window();
+    }
+}
+
+#endif /* JIT */
diff --git a/jit/arm/compstbl_arm.cpp b/jit/arm/compstbl_arm.cpp
new file mode 100644
index 00000000..6fd15a47
--- /dev/null
+++ b/jit/arm/compstbl_arm.cpp
@@ -0,0 +1,3746 @@
+#include "sysconfig.h"
+#if defined(JIT)
+#include "sysdeps.h"
+#include "options.h"
+#include "uae/memory.h"
+#include "readcpu.h"
+#include "newcpu.h"
+#include "comptbl_arm.h"
+#include "debug.h"
+extern const struct comptbl op_smalltbl_0_comp_ff[] = { { op_0_0_comp_ff, 0, 0x00000002 }, /* OR */
+{ op_10_0_comp_ff, 16, 0x00000002 }, /* OR */
+{ op_18_0_comp_ff, 24, 0x00000002 }, /* OR */
+{ op_20_0_comp_ff, 32, 0x00000002 }, /* OR */
+{ op_28_0_comp_ff, 40, 0x00000002 }, /* OR */
+{ op_30_0_comp_ff, 48, 0x00000002 }, /* OR */
+{ op_38_0_comp_ff, 56, 0x00000002 }, /* OR */
+{ op_39_0_comp_ff, 57, 0x00000002 }, /* OR */
+{ op_3c_0_comp_ff, 60, 0x00000002 }, /* ORSR */
+{ op_40_0_comp_ff, 64, 0x00000002 }, /* OR */
+{ op_50_0_comp_ff, 80, 0x00000002 }, /* OR */
+{ op_58_0_comp_ff, 88, 0x00000002 }, /* OR */
+{ op_60_0_comp_ff, 96, 0x00000002 }, /* OR */
+{ op_68_0_comp_ff, 104, 0x00000002 }, /* OR */
+{ op_70_0_comp_ff, 112, 0x00000002 }, /* OR */
+{ op_78_0_comp_ff, 120, 0x00000002 }, /* OR */
+{ op_79_0_comp_ff, 121, 0x00000002 }, /* OR */
+{ NULL, 124, 0x00000002 }, /* ORSR */
+{ op_80_0_comp_ff, 128, 0x00000002 }, /* OR */
+{ op_90_0_comp_ff, 144, 0x00000002 }, /* OR */
+{ op_98_0_comp_ff, 152, 0x00000002 }, /* OR */
+{ op_a0_0_comp_ff, 160, 0x00000002 }, /* OR */
+{ op_a8_0_comp_ff, 168, 0x00000002 }, /* OR */
+{ op_b0_0_comp_ff, 176, 0x00000002 }, /* OR */
+{ op_b8_0_comp_ff, 184, 0x00000002 }, /* OR */
+{ op_b9_0_comp_ff, 185, 0x00000002 }, /* OR */
+{ NULL, 208, 0x00000001 }, /* CHK2 */
+{ NULL, 232, 0x00000001 }, /* CHK2 */
+{ NULL, 240, 0x00000001 }, /* CHK2 */
+{ NULL, 248, 0x00000001 }, /* CHK2 */
+{ NULL, 249, 0x00000001 }, /* CHK2 */
+{ NULL, 250, 0x00000001 }, /* CHK2 */
+{ NULL, 251, 0x00000001 }, /* CHK2 */
+{ op_100_0_comp_ff, 256, 0x00000000 }, /* BTST */
+{ NULL, 264, 0x00000001 }, /* MVPMR */
+{ op_110_0_comp_ff, 272, 0x00000000 }, /* BTST */
+{ op_118_0_comp_ff, 280, 0x00000000 }, /* BTST */
+{ op_120_0_comp_ff, 288, 0x00000000 }, /* BTST */
+{ op_128_0_comp_ff, 296, 0x00000002 }, /* BTST */
+{ op_130_0_comp_ff, 304, 0x00000002 }, /* BTST */
+{ op_138_0_comp_ff, 312, 0x00000002 }, /* BTST */
+{ op_139_0_comp_ff, 313, 0x00000002 }, /* BTST */
+{ op_13a_0_comp_ff, 314, 0x00000002 }, /* BTST */
+{ op_13b_0_comp_ff, 315, 0x00000002 }, /* BTST */
+{ op_13c_0_comp_ff, 316, 0x00000002 }, /* BTST */
+{ op_140_0_comp_ff, 320, 0x00000000 }, /* BCHG */
+{ NULL, 328, 0x00000001 }, /* MVPMR */
+{ op_150_0_comp_ff, 336, 0x00000000 }, /* BCHG */
+{ op_158_0_comp_ff, 344, 0x00000000 }, /* BCHG */
+{ op_160_0_comp_ff, 352, 0x00000000 }, /* BCHG */
+{ op_168_0_comp_ff, 360, 0x00000002 }, /* BCHG */
+{ op_170_0_comp_ff, 368, 0x00000002 }, /* BCHG */
+{ op_178_0_comp_ff, 376, 0x00000002 }, /* BCHG */
+{ op_179_0_comp_ff, 377, 0x00000002 }, /* BCHG */
+{ op_180_0_comp_ff, 384, 0x00000000 }, /* BCLR */
+{ NULL, 392, 0x00000001 }, /* MVPRM */
+{ op_190_0_comp_ff, 400, 0x00000000 }, /* BCLR */
+{ op_198_0_comp_ff, 408, 0x00000000 }, /* BCLR */
+{ op_1a0_0_comp_ff, 416, 0x00000000 }, /* BCLR */
+{ op_1a8_0_comp_ff, 424, 0x00000002 }, /* BCLR */
+{ op_1b0_0_comp_ff, 432, 0x00000002 }, /* BCLR */
+{ op_1b8_0_comp_ff, 440, 0x00000002 }, /* BCLR */
+{ op_1b9_0_comp_ff, 441, 0x00000002 }, /* BCLR */
+{ op_1c0_0_comp_ff, 448, 0x00000000 }, /* BSET */
+{ NULL, 456, 0x00000001 }, /* MVPRM */
+{ op_1d0_0_comp_ff, 464, 0x00000000 }, /* BSET */
+{ op_1d8_0_comp_ff, 472, 0x00000000 }, /* BSET */
+{ op_1e0_0_comp_ff, 480, 0x00000000 }, /* BSET */
+{ op_1e8_0_comp_ff, 488, 0x00000002 }, /* BSET */
+{ op_1f0_0_comp_ff, 496, 0x00000002 }, /* BSET */
+{ op_1f8_0_comp_ff, 504, 0x00000002 }, /* BSET */
+{ op_1f9_0_comp_ff, 505, 0x00000002 }, /* BSET */
+{ op_200_0_comp_ff, 512, 0x00000002 }, /* AND */
+{ op_210_0_comp_ff, 528, 0x00000002 }, /* AND */
+{ op_218_0_comp_ff, 536, 0x00000002 }, /* AND */
+{ op_220_0_comp_ff, 544, 0x00000002 }, /* AND */
+{ op_228_0_comp_ff, 552, 0x00000002 }, /* AND */
+{ op_230_0_comp_ff, 560, 0x00000002 }, /* AND */
+{ op_238_0_comp_ff, 568, 0x00000002 }, /* AND */
+{ op_239_0_comp_ff, 569, 0x00000002 }, /* AND */
+{ op_23c_0_comp_ff, 572, 0x00000002 }, /* ANDSR */
+{ op_240_0_comp_ff, 576, 0x00000002 }, /* AND */
+{ op_250_0_comp_ff, 592, 0x00000002 }, /* AND */
+{ op_258_0_comp_ff, 600, 0x00000002 }, /* AND */
+{ op_260_0_comp_ff, 608, 0x00000002 }, /* AND */
+{ op_268_0_comp_ff, 616, 0x00000002 }, /* AND */
+{ op_270_0_comp_ff, 624, 0x00000002 }, /* AND */
+{ op_278_0_comp_ff, 632, 0x00000002 }, /* AND */
+{ op_279_0_comp_ff, 633, 0x00000002 }, /* AND */
+{ NULL, 636, 0x00000002 }, /* ANDSR */
+{ op_280_0_comp_ff, 640, 0x00000002 }, /* AND */
+{ op_290_0_comp_ff, 656, 0x00000002 }, /* AND */
+{ op_298_0_comp_ff, 664, 0x00000002 }, /* AND */
+{ op_2a0_0_comp_ff, 672, 0x00000002 }, /* AND */
+{ op_2a8_0_comp_ff, 680, 0x00000002 }, /* AND */
+{ op_2b0_0_comp_ff, 688, 0x00000002 }, /* AND */
+{ op_2b8_0_comp_ff, 696, 0x00000002 }, /* AND */
+{ op_2b9_0_comp_ff, 697, 0x00000002 }, /* AND */
+{ NULL, 720, 0x00000001 }, /* CHK2 */
+{ NULL, 744, 0x00000001 }, /* CHK2 */
+{ NULL, 752, 0x00000001 }, /* CHK2 */
+{ NULL, 760, 0x00000001 }, /* CHK2 */
+{ NULL, 761, 0x00000001 }, /* CHK2 */
+{ NULL, 762, 0x00000001 }, /* CHK2 */
+{ NULL, 763, 0x00000001 }, /* CHK2 */
+{ op_400_0_comp_ff, 1024, 0x00000002 }, /* SUB */
+{ op_410_0_comp_ff, 1040, 0x00000002 }, /* SUB */
+{ op_418_0_comp_ff, 1048, 0x00000002 }, /* SUB */
+{ op_420_0_comp_ff, 1056, 0x00000002 }, /* SUB */
+{ op_428_0_comp_ff, 1064, 0x00000002 }, /* SUB */
+{ op_430_0_comp_ff, 1072, 0x00000002 }, /* SUB */
+{ op_438_0_comp_ff, 1080, 0x00000002 }, /* SUB */
+{ op_439_0_comp_ff, 1081, 0x00000002 }, /* SUB */
+{ op_440_0_comp_ff, 1088, 0x00000002 }, /* SUB */
+{ op_450_0_comp_ff, 1104, 0x00000002 }, /* SUB */
+{ op_458_0_comp_ff, 1112, 0x00000002 }, /* SUB */
+{ op_460_0_comp_ff, 1120, 0x00000002 }, /* SUB */
+{ op_468_0_comp_ff, 1128, 0x00000002 }, /* SUB */
+{ op_470_0_comp_ff, 1136, 0x00000002 }, /* SUB */
+{ op_478_0_comp_ff, 1144, 0x00000002 }, /* SUB */
+{ op_479_0_comp_ff, 1145, 0x00000002 }, /* SUB */
+{ op_480_0_comp_ff, 1152, 0x00000002 }, /* SUB */
+{ op_490_0_comp_ff, 1168, 0x00000002 }, /* SUB */
+{ op_498_0_comp_ff, 1176, 0x00000002 }, /* SUB */
+{ op_4a0_0_comp_ff, 1184, 0x00000002 }, /* SUB */
+{ op_4a8_0_comp_ff, 1192, 0x00000002 }, /* SUB */
+{ op_4b0_0_comp_ff, 1200, 0x00000002 }, /* SUB */
+{ op_4b8_0_comp_ff, 1208, 0x00000002 }, /* SUB */
+{ op_4b9_0_comp_ff, 1209, 0x00000002 }, /* SUB */
+{ NULL, 1232, 0x00000001 }, /* CHK2 */
+{ NULL, 1256, 0x00000001 }, /* CHK2 */
+{ NULL, 1264, 0x00000001 }, /* CHK2 */
+{ NULL, 1272, 0x00000001 }, /* CHK2 */
+{ NULL, 1273, 0x00000001 }, /* CHK2 */
+{ NULL, 1274, 0x00000001 }, /* CHK2 */
+{ NULL, 1275, 0x00000001 }, /* CHK2 */
+{ op_600_0_comp_ff, 1536, 0x00000002 }, /* ADD */
+{ op_610_0_comp_ff, 1552, 0x00000002 }, /* ADD */
+{ op_618_0_comp_ff, 1560, 0x00000002 }, /* ADD */
+{ op_620_0_comp_ff, 1568, 0x00000002 }, /* ADD */
+{ op_628_0_comp_ff, 1576, 0x00000002 }, /* ADD */
+{ op_630_0_comp_ff, 1584, 0x00000002 }, /* ADD */
+{ op_638_0_comp_ff, 1592, 0x00000002 }, /* ADD */
+{ op_639_0_comp_ff, 1593, 0x00000002 }, /* ADD */
+{ op_640_0_comp_ff, 1600, 0x00000002 }, /* ADD */
+{ op_650_0_comp_ff, 1616, 0x00000002 }, /* ADD */
+{ op_658_0_comp_ff, 1624, 0x00000002 }, /* ADD */
+{ op_660_0_comp_ff, 1632, 0x00000002 }, /* ADD */
+{ op_668_0_comp_ff, 1640, 0x00000002 }, /* ADD */
+{ op_670_0_comp_ff, 1648, 0x00000002 }, /* ADD */
+{ op_678_0_comp_ff, 1656, 0x00000002 }, /* ADD */
+{ op_679_0_comp_ff, 1657, 0x00000002 }, /* ADD */
+{ op_680_0_comp_ff, 1664, 0x00000002 }, /* ADD */
+{ op_690_0_comp_ff, 1680, 0x00000002 }, /* ADD */
+{ op_698_0_comp_ff, 1688, 0x00000002 }, /* ADD */
+{ op_6a0_0_comp_ff, 1696, 0x00000002 }, /* ADD */
+{ op_6a8_0_comp_ff, 1704, 0x00000002 }, /* ADD */
+{ op_6b0_0_comp_ff, 1712, 0x00000002 }, /* ADD */
+{ op_6b8_0_comp_ff, 1720, 0x00000002 }, /* ADD */
+{ op_6b9_0_comp_ff, 1721, 0x00000002 }, /* ADD */
+{ NULL, 1728, 0x00000001 }, /* RTM */
+{ NULL, 1736, 0x00000001 }, /* RTM */
+{ NULL, 1744, 0x00000001 }, /* CALLM */
+{ NULL, 1768, 0x00000001 }, /* CALLM */
+{ NULL, 1776, 0x00000001 }, /* CALLM */
+{ NULL, 1784, 0x00000001 }, /* CALLM */
+{ NULL, 1785, 0x00000001 }, /* CALLM */
+{ NULL, 1786, 0x00000001 }, /* CALLM */
+{ NULL, 1787, 0x00000001 }, /* CALLM */
+{ op_800_0_comp_ff, 2048, 0x00000002 }, /* BTST */
+{ op_810_0_comp_ff, 2064, 0x00000002 }, /* BTST */
+{ op_818_0_comp_ff, 2072, 0x00000002 }, /* BTST */
+{ op_820_0_comp_ff, 2080, 0x00000002 }, /* BTST */
+{ op_828_0_comp_ff, 2088, 0x00000002 }, /* BTST */
+{ op_830_0_comp_ff, 2096, 0x00000002 }, /* BTST */
+{ op_838_0_comp_ff, 2104, 0x00000002 }, /* BTST */
+{ op_839_0_comp_ff, 2105, 0x00000002 }, /* BTST */
+{ op_83a_0_comp_ff, 2106, 0x00000002 }, /* BTST */
+{ op_83b_0_comp_ff, 2107, 0x00000002 }, /* BTST */
+{ op_840_0_comp_ff, 2112, 0x00000002 }, /* BCHG */
+{ op_850_0_comp_ff, 2128, 0x00000002 }, /* BCHG */
+{ op_858_0_comp_ff, 2136, 0x00000002 }, /* BCHG */
+{ op_860_0_comp_ff, 2144, 0x00000002 }, /* BCHG */
+{ op_868_0_comp_ff, 2152, 0x00000002 }, /* BCHG */
+{ op_870_0_comp_ff, 2160, 0x00000002 }, /* BCHG */
+{ op_878_0_comp_ff, 2168, 0x00000002 }, /* BCHG */
+{ op_879_0_comp_ff, 2169, 0x00000002 }, /* BCHG */
+{ op_880_0_comp_ff, 2176, 0x00000002 }, /* BCLR */
+{ op_890_0_comp_ff, 2192, 0x00000002 }, /* BCLR */
+{ op_898_0_comp_ff, 2200, 0x00000002 }, /* BCLR */
+{ op_8a0_0_comp_ff, 2208, 0x00000002 }, /* BCLR */
+{ op_8a8_0_comp_ff, 2216, 0x00000002 }, /* BCLR */
+{ op_8b0_0_comp_ff, 2224, 0x00000002 }, /* BCLR */
+{ op_8b8_0_comp_ff, 2232, 0x00000002 }, /* BCLR */
+{ op_8b9_0_comp_ff, 2233, 0x00000002 }, /* BCLR */
+{ op_8c0_0_comp_ff, 2240, 0x00000002 }, /* BSET */
+{ op_8d0_0_comp_ff, 2256, 0x00000002 }, /* BSET */
+{ op_8d8_0_comp_ff, 2264, 0x00000002 }, /* BSET */
+{ op_8e0_0_comp_ff, 2272, 0x00000002 }, /* BSET */
+{ op_8e8_0_comp_ff, 2280, 0x00000002 }, /* BSET */
+{ op_8f0_0_comp_ff, 2288, 0x00000002 }, /* BSET */
+{ op_8f8_0_comp_ff, 2296, 0x00000002 }, /* BSET */
+{ op_8f9_0_comp_ff, 2297, 0x00000002 }, /* BSET */
+{ op_a00_0_comp_ff, 2560, 0x00000002 }, /* EOR */
+{ op_a10_0_comp_ff, 2576, 0x00000002 }, /* EOR */
+{ op_a18_0_comp_ff, 2584, 0x00000002 }, /* EOR */
+{ op_a20_0_comp_ff, 2592, 0x00000002 }, /* EOR */
+{ op_a28_0_comp_ff, 2600, 0x00000002 }, /* EOR */
+{ op_a30_0_comp_ff, 2608, 0x00000002 }, /* EOR */
+{ op_a38_0_comp_ff, 2616, 0x00000002 }, /* EOR */
+{ op_a39_0_comp_ff, 2617, 0x00000002 }, /* EOR */
+{ op_a3c_0_comp_ff, 2620, 0x00000002 }, /* EORSR */
+{ op_a40_0_comp_ff, 2624, 0x00000002 }, /* EOR */
+{ op_a50_0_comp_ff, 2640, 0x00000002 }, /* EOR */
+{ op_a58_0_comp_ff, 2648, 0x00000002 }, /* EOR */
+{ op_a60_0_comp_ff, 2656, 0x00000002 }, /* EOR */
+{ op_a68_0_comp_ff, 2664, 0x00000002 }, /* EOR */
+{ op_a70_0_comp_ff, 2672, 0x00000002 }, /* EOR */
+{ op_a78_0_comp_ff, 2680, 0x00000002 }, /* EOR */
+{ op_a79_0_comp_ff, 2681, 0x00000002 }, /* EOR */
+{ NULL, 2684, 0x00000002 }, /* EORSR */
+{ op_a80_0_comp_ff, 2688, 0x00000002 }, /* EOR */
+{ op_a90_0_comp_ff, 2704, 0x00000002 }, /* EOR */
+{ op_a98_0_comp_ff, 2712, 0x00000002 }, /* EOR */
+{ op_aa0_0_comp_ff, 2720, 0x00000002 }, /* EOR */
+{ op_aa8_0_comp_ff, 2728, 0x00000002 }, /* EOR */
+{ op_ab0_0_comp_ff, 2736, 0x00000002 }, /* EOR */
+{ op_ab8_0_comp_ff, 2744, 0x00000002 }, /* EOR */
+{ op_ab9_0_comp_ff, 2745, 0x00000002 }, /* EOR */
+{ NULL, 2768, 0x00000000 }, /* CAS */
+{ NULL, 2776, 0x00000000 }, /* CAS */
+{ NULL, 2784, 0x00000000 }, /* CAS */
+{ NULL, 2792, 0x00000000 }, /* CAS */
+{ NULL, 2800, 0x00000000 }, /* CAS */
+{ NULL, 2808, 0x00000000 }, /* CAS */
+{ NULL, 2809, 0x00000000 }, /* CAS */
+{ op_c00_0_comp_ff, 3072, 0x00000002 }, /* CMP */
+{ op_c10_0_comp_ff, 3088, 0x00000002 }, /* CMP */
+{ op_c18_0_comp_ff, 3096, 0x00000002 }, /* CMP */
+{ op_c20_0_comp_ff, 3104, 0x00000002 }, /* CMP */
+{ op_c28_0_comp_ff, 3112, 0x00000002 }, /* CMP */
+{ op_c30_0_comp_ff, 3120, 0x00000002 }, /* CMP */
+{ op_c38_0_comp_ff, 3128, 0x00000002 }, /* CMP */
+{ op_c39_0_comp_ff, 3129, 0x00000002 }, /* CMP */
+{ op_c3a_0_comp_ff, 3130, 0x00000002 }, /* CMP */
+{ op_c3b_0_comp_ff, 3131, 0x00000002 }, /* CMP */
+{ op_c40_0_comp_ff, 3136, 0x00000002 }, /* CMP */
+{ op_c50_0_comp_ff, 3152, 0x00000002 }, /* CMP */
+{ op_c58_0_comp_ff, 3160, 0x00000002 }, /* CMP */
+{ op_c60_0_comp_ff, 3168, 0x00000002 }, /* CMP */
+{ op_c68_0_comp_ff, 3176, 0x00000002 }, /* CMP */
+{ op_c70_0_comp_ff, 3184, 0x00000002 }, /* CMP */
+{ op_c78_0_comp_ff, 3192, 0x00000002 }, /* CMP */
+{ op_c79_0_comp_ff, 3193, 0x00000002 }, /* CMP */
+{ op_c7a_0_comp_ff, 3194, 0x00000002 }, /* CMP */
+{ op_c7b_0_comp_ff, 3195, 0x00000002 }, /* CMP */
+{ op_c80_0_comp_ff, 3200, 0x00000002 }, /* CMP */
+{ op_c90_0_comp_ff, 3216, 0x00000002 }, /* CMP */
+{ op_c98_0_comp_ff, 3224, 0x00000002 }, /* CMP */
+{ op_ca0_0_comp_ff, 3232, 0x00000002 }, /* CMP */
+{ op_ca8_0_comp_ff, 3240, 0x00000002 }, /* CMP */
+{ op_cb0_0_comp_ff, 3248, 0x00000002 }, /* CMP */
+{ op_cb8_0_comp_ff, 3256, 0x00000002 }, /* CMP */
+{ op_cb9_0_comp_ff, 3257, 0x00000002 }, /* CMP */
+{ op_cba_0_comp_ff, 3258, 0x00000002 }, /* CMP */
+{ op_cbb_0_comp_ff, 3259, 0x00000002 }, /* CMP */
+{ NULL, 3280, 0x00000000 }, /* CAS */
+{ NULL, 3288, 0x00000000 }, /* CAS */
+{ NULL, 3296, 0x00000000 }, /* CAS */
+{ NULL, 3304, 0x00000000 }, /* CAS */
+{ NULL, 3312, 0x00000000 }, /* CAS */
+{ NULL, 3320, 0x00000000 }, /* CAS */
+{ NULL, 3321, 0x00000000 }, /* CAS */
+{ NULL, 3324, 0x00000000 }, /* CAS2 */
+{ NULL, 3600, 0x00000001 }, /* MOVES */
+{ NULL, 3608, 0x00000001 }, /* MOVES */
+{ NULL, 3616, 0x00000001 }, /* MOVES */
+{ NULL, 3624, 0x00000001 }, /* MOVES */
+{ NULL, 3632, 0x00000001 }, /* MOVES */
+{ NULL, 3640, 0x00000001 }, /* MOVES */
+{ NULL, 3641, 0x00000001 }, /* MOVES */
+{ NULL, 3664, 0x00000001 }, /* MOVES */
+{ NULL, 3672, 0x00000001 }, /* MOVES */
+{ NULL, 3680, 0x00000001 }, /* MOVES */
+{ NULL, 3688, 0x00000001 }, /* MOVES */
+{ NULL, 3696, 0x00000001 }, /* MOVES */
+{ NULL, 3704, 0x00000001 }, /* MOVES */
+{ NULL, 3705, 0x00000001 }, /* MOVES */
+{ NULL, 3728, 0x00000001 }, /* MOVES */
+{ NULL, 3736, 0x00000001 }, /* MOVES */
+{ NULL, 3744, 0x00000001 }, /* MOVES */
+{ NULL, 3752, 0x00000001 }, /* MOVES */
+{ NULL, 3760, 0x00000001 }, /* MOVES */
+{ NULL, 3768, 0x00000001 }, /* MOVES */
+{ NULL, 3769, 0x00000001 }, /* MOVES */
+{ NULL, 3792, 0x00000000 }, /* CAS */
+{ NULL, 3800, 0x00000000 }, /* CAS */
+{ NULL, 3808, 0x00000000 }, /* CAS */
+{ NULL, 3816, 0x00000000 }, /* CAS */
+{ NULL, 3824, 0x00000000 }, /* CAS */
+{ NULL, 3832, 0x00000000 }, /* CAS */
+{ NULL, 3833, 0x00000000 }, /* CAS */
+{ NULL, 3836, 0x00000000 }, /* CAS2 */
+{ op_1000_0_comp_ff, 4096, 0x00000000 }, /* MOVE */
+{ op_1010_0_comp_ff, 4112, 0x00000000 }, /* MOVE */
+{ op_1018_0_comp_ff, 4120, 0x00000000 }, /* MOVE */
+{ op_1020_0_comp_ff, 4128, 0x00000000 }, /* MOVE */
+{ op_1028_0_comp_ff, 4136, 0x00000002 }, /* MOVE */
+{ op_1030_0_comp_ff, 4144, 0x00000002 }, /* MOVE */
+{ op_1038_0_comp_ff, 4152, 0x00000002 }, /* MOVE */
+{ op_1039_0_comp_ff, 4153, 0x00000002 }, /* MOVE */
+{ op_103a_0_comp_ff, 4154, 0x00000002 }, /* MOVE */
+{ op_103b_0_comp_ff, 4155, 0x00000002 }, /* MOVE */
+{ op_103c_0_comp_ff, 4156, 0x00000002 }, /* MOVE */
+{ op_1080_0_comp_ff, 4224, 0x00000000 }, /* MOVE */
+{ op_1090_0_comp_ff, 4240, 0x00000000 }, /* MOVE */
+{ op_1098_0_comp_ff, 4248, 0x00000000 }, /* MOVE */
+{ op_10a0_0_comp_ff, 4256, 0x00000000 }, /* MOVE */
+{ op_10a8_0_comp_ff, 4264, 0x00000002 }, /* MOVE */
+{ op_10b0_0_comp_ff, 4272, 0x00000002 }, /* MOVE */
+{ op_10b8_0_comp_ff, 4280, 0x00000002 }, /* MOVE */
+{ op_10b9_0_comp_ff, 4281, 0x00000002 }, /* MOVE */
+{ op_10ba_0_comp_ff, 4282, 0x00000002 }, /* MOVE */
+{ op_10bb_0_comp_ff, 4283, 0x00000002 }, /* MOVE */
+{ op_10bc_0_comp_ff, 4284, 0x00000002 }, /* MOVE */
+{ op_10c0_0_comp_ff, 4288, 0x00000000 }, /* MOVE */
+{ op_10d0_0_comp_ff, 4304, 0x00000000 }, /* MOVE */
+{ op_10d8_0_comp_ff, 4312, 0x00000000 }, /* MOVE */
+{ op_10e0_0_comp_ff, 4320, 0x00000000 }, /* MOVE */
+{ op_10e8_0_comp_ff, 4328, 0x00000002 }, /* MOVE */
+{ op_10f0_0_comp_ff, 4336, 0x00000002 }, /* MOVE */
+{ op_10f8_0_comp_ff, 4344, 0x00000002 }, /* MOVE */
+{ op_10f9_0_comp_ff, 4345, 0x00000002 }, /* MOVE */
+{ op_10fa_0_comp_ff, 4346, 0x00000002 }, /* MOVE */
+{ op_10fb_0_comp_ff, 4347, 0x00000002 }, /* MOVE */
+{ op_10fc_0_comp_ff, 4348, 0x00000002 }, /* MOVE */
+{ op_1100_0_comp_ff, 4352, 0x00000000 }, /* MOVE */
+{ op_1110_0_comp_ff, 4368, 0x00000000 }, /* MOVE */
+{ op_1118_0_comp_ff, 4376, 0x00000000 }, /* MOVE */
+{ op_1120_0_comp_ff, 4384, 0x00000000 }, /* MOVE */
+{ op_1128_0_comp_ff, 4392, 0x00000002 }, /* MOVE */
+{ op_1130_0_comp_ff, 4400, 0x00000002 }, /* MOVE */
+{ op_1138_0_comp_ff, 4408, 0x00000002 }, /* MOVE */
+{ op_1139_0_comp_ff, 4409, 0x00000002 }, /* MOVE */
+{ op_113a_0_comp_ff, 4410, 0x00000002 }, /* MOVE */
+{ op_113b_0_comp_ff, 4411, 0x00000002 }, /* MOVE */
+{ op_113c_0_comp_ff, 4412, 0x00000002 }, /* MOVE */
+{ op_1140_0_comp_ff, 4416, 0x00000002 }, /* MOVE */
+{ op_1150_0_comp_ff, 4432, 0x00000002 }, /* MOVE */
+{ op_1158_0_comp_ff, 4440, 0x00000002 }, /* MOVE */
+{ op_1160_0_comp_ff, 4448, 0x00000002 }, /* MOVE */
+{ op_1168_0_comp_ff, 4456, 0x00000002 }, /* MOVE */
+{ op_1170_0_comp_ff, 4464, 0x00000002 }, /* MOVE */
+{ op_1178_0_comp_ff, 4472, 0x00000002 }, /* MOVE */
+{ op_1179_0_comp_ff, 4473, 0x00000002 }, /* MOVE */
+{ op_117a_0_comp_ff, 4474, 0x00000002 }, /* MOVE */
+{ op_117b_0_comp_ff, 4475, 0x00000002 }, /* MOVE */
+{ op_117c_0_comp_ff, 4476, 0x00000002 }, /* MOVE */
+{ op_1180_0_comp_ff, 4480, 0x00000002 }, /* MOVE */
+{ op_1190_0_comp_ff, 4496, 0x00000002 }, /* MOVE */
+{ op_1198_0_comp_ff, 4504, 0x00000002 }, /* MOVE */
+{ op_11a0_0_comp_ff, 4512, 0x00000002 }, /* MOVE */
+{ op_11a8_0_comp_ff, 4520, 0x00000002 }, /* MOVE */
+{ op_11b0_0_comp_ff, 4528, 0x00000002 }, /* MOVE */
+{ op_11b8_0_comp_ff, 4536, 0x00000002 }, /* MOVE */
+{ op_11b9_0_comp_ff, 4537, 0x00000002 }, /* MOVE */
+{ op_11ba_0_comp_ff, 4538, 0x00000002 }, /* MOVE */
+{ op_11bb_0_comp_ff, 4539, 0x00000002 }, /* MOVE */
+{ op_11bc_0_comp_ff, 4540, 0x00000002 }, /* MOVE */
+{ op_11c0_0_comp_ff, 4544, 0x00000002 }, /* MOVE */
+{ op_11d0_0_comp_ff, 4560, 0x00000002 }, /* MOVE */
+{ op_11d8_0_comp_ff, 4568, 0x00000002 }, /* MOVE */
+{ op_11e0_0_comp_ff, 4576, 0x00000002 }, /* MOVE */
+{ op_11e8_0_comp_ff, 4584, 0x00000002 }, /* MOVE */
+{ op_11f0_0_comp_ff, 4592, 0x00000002 }, /* MOVE */
+{ op_11f8_0_comp_ff, 4600, 0x00000002 }, /* MOVE */
+{ op_11f9_0_comp_ff, 4601, 0x00000002 }, /* MOVE */
+{ op_11fa_0_comp_ff, 4602, 0x00000002 }, /* MOVE */
+{ op_11fb_0_comp_ff, 4603, 0x00000002 }, /* MOVE */
+{ op_11fc_0_comp_ff, 4604, 0x00000002 }, /* MOVE */
+{ op_13c0_0_comp_ff, 5056, 0x00000002 }, /* MOVE */
+{ op_13d0_0_comp_ff, 5072, 0x00000002 }, /* MOVE */
+{ op_13d8_0_comp_ff, 5080, 0x00000002 }, /* MOVE */
+{ op_13e0_0_comp_ff, 5088, 0x00000002 }, /* MOVE */
+{ op_13e8_0_comp_ff, 5096, 0x00000002 }, /* MOVE */
+{ op_13f0_0_comp_ff, 5104, 0x00000002 }, /* MOVE */
+{ op_13f8_0_comp_ff, 5112, 0x00000002 }, /* MOVE */
+{ op_13f9_0_comp_ff, 5113, 0x00000002 }, /* MOVE */
+{ op_13fa_0_comp_ff, 5114, 0x00000002 }, /* MOVE */
+{ op_13fb_0_comp_ff, 5115, 0x00000002 }, /* MOVE */
+{ op_13fc_0_comp_ff, 5116, 0x00000002 }, /* MOVE */
+{ op_2000_0_comp_ff, 8192, 0x00000000 }, /* MOVE */
+{ op_2008_0_comp_ff, 8200, 0x00000000 }, /* MOVE */
+{ op_2010_0_comp_ff, 8208, 0x00000000 }, /* MOVE */
+{ op_2018_0_comp_ff, 8216, 0x00000000 }, /* MOVE */
+{ op_2020_0_comp_ff, 8224, 0x00000000 }, /* MOVE */
+{ op_2028_0_comp_ff, 8232, 0x00000002 }, /* MOVE */
+{ op_2030_0_comp_ff, 8240, 0x00000002 }, /* MOVE */
+{ op_2038_0_comp_ff, 8248, 0x00000002 }, /* MOVE */
+{ op_2039_0_comp_ff, 8249, 0x00000002 }, /* MOVE */
+{ op_203a_0_comp_ff, 8250, 0x00000002 }, /* MOVE */
+{ op_203b_0_comp_ff, 8251, 0x00000002 }, /* MOVE */
+{ op_203c_0_comp_ff, 8252, 0x00000002 }, /* MOVE */
+{ op_2040_0_comp_ff, 8256, 0x00000000 }, /* MOVEA */
+{ op_2048_0_comp_ff, 8264, 0x00000000 }, /* MOVEA */
+{ op_2050_0_comp_ff, 8272, 0x00000000 }, /* MOVEA */
+{ op_2058_0_comp_ff, 8280, 0x00000000 }, /* MOVEA */
+{ op_2060_0_comp_ff, 8288, 0x00000000 }, /* MOVEA */
+{ op_2068_0_comp_ff, 8296, 0x00000002 }, /* MOVEA */
+{ op_2070_0_comp_ff, 8304, 0x00000002 }, /* MOVEA */
+{ op_2078_0_comp_ff, 8312, 0x00000002 }, /* MOVEA */
+{ op_2079_0_comp_ff, 8313, 0x00000002 }, /* MOVEA */
+{ op_207a_0_comp_ff, 8314, 0x00000002 }, /* MOVEA */
+{ op_207b_0_comp_ff, 8315, 0x00000002 }, /* MOVEA */
+{ op_207c_0_comp_ff, 8316, 0x00000002 }, /* MOVEA */
+{ op_2080_0_comp_ff, 8320, 0x00000000 }, /* MOVE */
+{ op_2088_0_comp_ff, 8328, 0x00000000 }, /* MOVE */
+{ op_2090_0_comp_ff, 8336, 0x00000000 }, /* MOVE */
+{ op_2098_0_comp_ff, 8344, 0x00000000 }, /* MOVE */
+{ op_20a0_0_comp_ff, 8352, 0x00000000 }, /* MOVE */
+{ op_20a8_0_comp_ff, 8360, 0x00000002 }, /* MOVE */
+{ op_20b0_0_comp_ff, 8368, 0x00000002 }, /* MOVE */
+{ op_20b8_0_comp_ff, 8376, 0x00000002 }, /* MOVE */
+{ op_20b9_0_comp_ff, 8377, 0x00000002 }, /* MOVE */
+{ op_20ba_0_comp_ff, 8378, 0x00000002 }, /* MOVE */
+{ op_20bb_0_comp_ff, 8379, 0x00000002 }, /* MOVE */
+{ op_20bc_0_comp_ff, 8380, 0x00000002 }, /* MOVE */
+{ op_20c0_0_comp_ff, 8384, 0x00000000 }, /* MOVE */
+{ op_20c8_0_comp_ff, 8392, 0x00000000 }, /* MOVE */
+{ op_20d0_0_comp_ff, 8400, 0x00000000 }, /* MOVE */
+{ op_20d8_0_comp_ff, 8408, 0x00000000 }, /* MOVE */
+{ op_20e0_0_comp_ff, 8416, 0x00000000 }, /* MOVE */
+{ op_20e8_0_comp_ff, 8424, 0x00000002 }, /* MOVE */
+{ op_20f0_0_comp_ff, 8432, 0x00000002 }, /* MOVE */
+{ op_20f8_0_comp_ff, 8440, 0x00000002 }, /* MOVE */
+{ op_20f9_0_comp_ff, 8441, 0x00000002 }, /* MOVE */
+{ op_20fa_0_comp_ff, 8442, 0x00000002 }, /* MOVE */
+{ op_20fb_0_comp_ff, 8443, 0x00000002 }, /* MOVE */
+{ op_20fc_0_comp_ff, 8444, 0x00000002 }, /* MOVE */
+{ op_2100_0_comp_ff, 8448, 0x00000000 }, /* MOVE */
+{ op_2108_0_comp_ff, 8456, 0x00000000 }, /* MOVE */
+{ op_2110_0_comp_ff, 8464, 0x00000000 }, /* MOVE */
+{ op_2118_0_comp_ff, 8472, 0x00000000 }, /* MOVE */
+{ op_2120_0_comp_ff, 8480, 0x00000000 }, /* MOVE */
+{ op_2128_0_comp_ff, 8488, 0x00000002 }, /* MOVE */
+{ op_2130_0_comp_ff, 8496, 0x00000002 }, /* MOVE */
+{ op_2138_0_comp_ff, 8504, 0x00000002 }, /* MOVE */
+{ op_2139_0_comp_ff, 8505, 0x00000002 }, /* MOVE */
+{ op_213a_0_comp_ff, 8506, 0x00000002 }, /* MOVE */
+{ op_213b_0_comp_ff, 8507, 0x00000002 }, /* MOVE */
+{ op_213c_0_comp_ff, 8508, 0x00000002 }, /* MOVE */
+{ op_2140_0_comp_ff, 8512, 0x00000002 }, /* MOVE */
+{ op_2148_0_comp_ff, 8520, 0x00000002 }, /* MOVE */
+{ op_2150_0_comp_ff, 8528, 0x00000002 }, /* MOVE */
+{ op_2158_0_comp_ff, 8536, 0x00000002 }, /* MOVE */
+{ op_2160_0_comp_ff, 8544, 0x00000002 }, /* MOVE */
+{ op_2168_0_comp_ff, 8552, 0x00000002 }, /* MOVE */
+{ op_2170_0_comp_ff, 8560, 0x00000002 }, /* MOVE */
+{ op_2178_0_comp_ff, 8568, 0x00000002 }, /* MOVE */
+{ op_2179_0_comp_ff, 8569, 0x00000002 }, /* MOVE */
+{ op_217a_0_comp_ff, 8570, 0x00000002 }, /* MOVE */
+{ op_217b_0_comp_ff, 8571, 0x00000002 }, /* MOVE */
+{ op_217c_0_comp_ff, 8572, 0x00000002 }, /* MOVE */
+{ op_2180_0_comp_ff, 8576, 0x00000002 }, /* MOVE */
+{ op_2188_0_comp_ff, 8584, 0x00000002 }, /* MOVE */
+{ op_2190_0_comp_ff, 8592, 0x00000002 }, /* MOVE */
+{ op_2198_0_comp_ff, 8600, 0x00000002 }, /* MOVE */
+{ op_21a0_0_comp_ff, 8608, 0x00000002 }, /* MOVE */
+{ op_21a8_0_comp_ff, 8616, 0x00000002 }, /* MOVE */
+{ op_21b0_0_comp_ff, 8624, 0x00000002 }, /* MOVE */
+{ op_21b8_0_comp_ff, 8632, 0x00000002 }, /* MOVE */
+{ op_21b9_0_comp_ff, 8633, 0x00000002 }, /* MOVE */
+{ op_21ba_0_comp_ff, 8634, 0x00000002 }, /* MOVE */
+{ op_21bb_0_comp_ff, 8635, 0x00000002 }, /* MOVE */
+{ op_21bc_0_comp_ff, 8636, 0x00000002 }, /* MOVE */
+{ op_21c0_0_comp_ff, 8640, 0x00000002 }, /* MOVE */
+{ op_21c8_0_comp_ff, 8648, 0x00000002 }, /* MOVE */
+{ op_21d0_0_comp_ff, 8656, 0x00000002 }, /* MOVE */
+{ op_21d8_0_comp_ff, 8664, 0x00000002 }, /* MOVE */
+{ op_21e0_0_comp_ff, 8672, 0x00000002 }, /* MOVE */
+{ op_21e8_0_comp_ff, 8680, 0x00000002 }, /* MOVE */
+{ op_21f0_0_comp_ff, 8688, 0x00000002 }, /* MOVE */
+{ op_21f8_0_comp_ff, 8696, 0x00000002 }, /* MOVE */
+{ op_21f9_0_comp_ff, 8697, 0x00000002 }, /* MOVE */
+{ op_21fa_0_comp_ff, 8698, 0x00000002 }, /* MOVE */
+{ op_21fb_0_comp_ff, 8699, 0x00000002 }, /* MOVE */
+{ op_21fc_0_comp_ff, 8700, 0x00000002 }, /* MOVE */
+{ op_23c0_0_comp_ff, 9152, 0x00000002 }, /* MOVE */
+{ op_23c8_0_comp_ff, 9160, 0x00000002 }, /* MOVE */
+{ op_23d0_0_comp_ff, 9168, 0x00000002 }, /* MOVE */
+{ op_23d8_0_comp_ff, 9176, 0x00000002 }, /* MOVE */
+{ op_23e0_0_comp_ff, 9184, 0x00000002 }, /* MOVE */
+{ op_23e8_0_comp_ff, 9192, 0x00000002 }, /* MOVE */
+{ op_23f0_0_comp_ff, 9200, 0x00000002 }, /* MOVE */
+{ op_23f8_0_comp_ff, 9208, 0x00000002 }, /* MOVE */
+{ op_23f9_0_comp_ff, 9209, 0x00000002 }, /* MOVE */
+{ op_23fa_0_comp_ff, 9210, 0x00000002 }, /* MOVE */
+{ op_23fb_0_comp_ff, 9211, 0x00000002 }, /* MOVE */
+{ op_23fc_0_comp_ff, 9212, 0x00000002 }, /* MOVE */
+{ op_3000_0_comp_ff, 12288, 0x00000000 }, /* MOVE */
+{ op_3008_0_comp_ff, 12296, 0x00000000 }, /* MOVE */
+{ op_3010_0_comp_ff, 12304, 0x00000000 }, /* MOVE */
+{ op_3018_0_comp_ff, 12312, 0x00000000 }, /* MOVE */
+{ op_3020_0_comp_ff, 12320, 0x00000000 }, /* MOVE */
+{ op_3028_0_comp_ff, 12328, 0x00000002 }, /* MOVE */
+{ op_3030_0_comp_ff, 12336, 0x00000002 }, /* MOVE */
+{ op_3038_0_comp_ff, 12344, 0x00000002 }, /* MOVE */
+{ op_3039_0_comp_ff, 12345, 0x00000002 }, /* MOVE */
+{ op_303a_0_comp_ff, 12346, 0x00000002 }, /* MOVE */
+{ op_303b_0_comp_ff, 12347, 0x00000002 }, /* MOVE */
+{ op_303c_0_comp_ff, 12348, 0x00000002 }, /* MOVE */
+{ op_3040_0_comp_ff, 12352, 0x00000000 }, /* MOVEA */
+{ op_3048_0_comp_ff, 12360, 0x00000000 }, /* MOVEA */
+{ op_3050_0_comp_ff, 12368, 0x00000000 }, /* MOVEA */
+{ op_3058_0_comp_ff, 12376, 0x00000000 }, /* MOVEA */
+{ op_3060_0_comp_ff, 12384, 0x00000000 }, /* MOVEA */
+{ op_3068_0_comp_ff, 12392, 0x00000002 }, /* MOVEA */
+{ op_3070_0_comp_ff, 12400, 0x00000002 }, /* MOVEA */
+{ op_3078_0_comp_ff, 12408, 0x00000002 }, /* MOVEA */
+{ op_3079_0_comp_ff, 12409, 0x00000002 }, /* MOVEA */
+{ op_307a_0_comp_ff, 12410, 0x00000002 }, /* MOVEA */
+{ op_307b_0_comp_ff, 12411, 0x00000002 }, /* MOVEA */
+{ op_307c_0_comp_ff, 12412, 0x00000002 }, /* MOVEA */
+{ op_3080_0_comp_ff, 12416, 0x00000000 }, /* MOVE */
+{ op_3088_0_comp_ff, 12424, 0x00000000 }, /* MOVE */
+{ op_3090_0_comp_ff, 12432, 0x00000000 }, /* MOVE */
+{ op_3098_0_comp_ff, 12440, 0x00000000 }, /* MOVE */
+{ op_30a0_0_comp_ff, 12448, 0x00000000 }, /* MOVE */
+{ op_30a8_0_comp_ff, 12456, 0x00000002 }, /* MOVE */
+{ op_30b0_0_comp_ff, 12464, 0x00000002 }, /* MOVE */
+{ op_30b8_0_comp_ff, 12472, 0x00000002 }, /* MOVE */
+{ op_30b9_0_comp_ff, 12473, 0x00000002 }, /* MOVE */
+{ op_30ba_0_comp_ff, 12474, 0x00000002 }, /* MOVE */
+{ op_30bb_0_comp_ff, 12475, 0x00000002 }, /* MOVE */
+{ op_30bc_0_comp_ff, 12476, 0x00000002 }, /* MOVE */
+{ op_30c0_0_comp_ff, 12480, 0x00000000 }, /* MOVE */
+{ op_30c8_0_comp_ff, 12488, 0x00000000 }, /* MOVE */
+{ op_30d0_0_comp_ff, 12496, 0x00000000 }, /* MOVE */
+{ op_30d8_0_comp_ff, 12504, 0x00000000 }, /* MOVE */
+{ op_30e0_0_comp_ff, 12512, 0x00000000 }, /* MOVE */
+{ op_30e8_0_comp_ff, 12520, 0x00000002 }, /* MOVE */
+{ op_30f0_0_comp_ff, 12528, 0x00000002 }, /* MOVE */
+{ op_30f8_0_comp_ff, 12536, 0x00000002 }, /* MOVE */
+{ op_30f9_0_comp_ff, 12537, 0x00000002 }, /* MOVE */
+{ op_30fa_0_comp_ff, 12538, 0x00000002 }, /* MOVE */
+{ op_30fb_0_comp_ff, 12539, 0x00000002 }, /* MOVE */
+{ op_30fc_0_comp_ff, 12540, 0x00000002 }, /* MOVE */
+{ op_3100_0_comp_ff, 12544, 0x00000000 }, /* MOVE */
+{ op_3108_0_comp_ff, 12552, 0x00000000 }, /* MOVE */
+{ op_3110_0_comp_ff, 12560, 0x00000000 }, /* MOVE */
+{ op_3118_0_comp_ff, 12568, 0x00000000 }, /* MOVE */
+{ op_3120_0_comp_ff, 12576, 0x00000000 }, /* MOVE */
+{ op_3128_0_comp_ff, 12584, 0x00000002 }, /* MOVE */
+{ op_3130_0_comp_ff, 12592, 0x00000002 }, /* MOVE */
+{ op_3138_0_comp_ff, 12600, 0x00000002 }, /* MOVE */
+{ op_3139_0_comp_ff, 12601, 0x00000002 }, /* MOVE */
+{ op_313a_0_comp_ff, 12602, 0x00000002 }, /* MOVE */
+{ op_313b_0_comp_ff, 12603, 0x00000002 }, /* MOVE */
+{ op_313c_0_comp_ff, 12604, 0x00000002 }, /* MOVE */
+{ op_3140_0_comp_ff, 12608, 0x00000002 }, /* MOVE */
+{ op_3148_0_comp_ff, 12616, 0x00000002 }, /* MOVE */
+{ op_3150_0_comp_ff, 12624, 0x00000002 }, /* MOVE */
+{ op_3158_0_comp_ff, 12632, 0x00000002 }, /* MOVE */
+{ op_3160_0_comp_ff, 12640, 0x00000002 }, /* MOVE */
+{ op_3168_0_comp_ff, 12648, 0x00000002 }, /* MOVE */
+{ op_3170_0_comp_ff, 12656, 0x00000002 }, /* MOVE */
+{ op_3178_0_comp_ff, 12664, 0x00000002 }, /* MOVE */
+{ op_3179_0_comp_ff, 12665, 0x00000002 }, /* MOVE */
+{ op_317a_0_comp_ff, 12666, 0x00000002 }, /* MOVE */
+{ op_317b_0_comp_ff, 12667, 0x00000002 }, /* MOVE */
+{ op_317c_0_comp_ff, 12668, 0x00000002 }, /* MOVE */
+{ op_3180_0_comp_ff, 12672, 0x00000002 }, /* MOVE */
+{ op_3188_0_comp_ff, 12680, 0x00000002 }, /* MOVE */
+{ op_3190_0_comp_ff, 12688, 0x00000002 }, /* MOVE */
+{ op_3198_0_comp_ff, 12696, 0x00000002 }, /* MOVE */
+{ op_31a0_0_comp_ff, 12704, 0x00000002 }, /* MOVE */
+{ op_31a8_0_comp_ff, 12712, 0x00000002 }, /* MOVE */
+{ op_31b0_0_comp_ff, 12720, 0x00000002 }, /* MOVE */
+{ op_31b8_0_comp_ff, 12728, 0x00000002 }, /* MOVE */
+{ op_31b9_0_comp_ff, 12729, 0x00000002 }, /* MOVE */
+{ op_31ba_0_comp_ff, 12730, 0x00000002 }, /* MOVE */
+{ op_31bb_0_comp_ff, 12731, 0x00000002 }, /* MOVE */
+{ op_31bc_0_comp_ff, 12732, 0x00000002 }, /* MOVE */
+{ op_31c0_0_comp_ff, 12736, 0x00000002 }, /* MOVE */
+{ op_31c8_0_comp_ff, 12744, 0x00000002 }, /* MOVE */
+{ op_31d0_0_comp_ff, 12752, 0x00000002 }, /* MOVE */
+{ op_31d8_0_comp_ff, 12760, 0x00000002 }, /* MOVE */
+{ op_31e0_0_comp_ff, 12768, 0x00000002 }, /* MOVE */
+{ op_31e8_0_comp_ff, 12776, 0x00000002 }, /* MOVE */
+{ op_31f0_0_comp_ff, 12784, 0x00000002 }, /* MOVE */
+{ op_31f8_0_comp_ff, 12792, 0x00000002 }, /* MOVE */
+{ op_31f9_0_comp_ff, 12793, 0x00000002 }, /* MOVE */
+{ op_31fa_0_comp_ff, 12794, 0x00000002 }, /* MOVE */
+{ op_31fb_0_comp_ff, 12795, 0x00000002 }, /* MOVE */
+{ op_31fc_0_comp_ff, 12796, 0x00000002 }, /* MOVE */
+{ op_33c0_0_comp_ff, 13248, 0x00000002 }, /* MOVE */
+{ op_33c8_0_comp_ff, 13256, 0x00000002 }, /* MOVE */
+{ op_33d0_0_comp_ff, 13264, 0x00000002 }, /* MOVE */
+{ op_33d8_0_comp_ff, 13272, 0x00000002 }, /* MOVE */
+{ op_33e0_0_comp_ff, 13280, 0x00000002 }, /* MOVE */
+{ op_33e8_0_comp_ff, 13288, 0x00000002 }, /* MOVE */
+{ op_33f0_0_comp_ff, 13296, 0x00000002 }, /* MOVE */
+{ op_33f8_0_comp_ff, 13304, 0x00000002 }, /* MOVE */
+{ op_33f9_0_comp_ff, 13305, 0x00000002 }, /* MOVE */
+{ op_33fa_0_comp_ff, 13306, 0x00000002 }, /* MOVE */
+{ op_33fb_0_comp_ff, 13307, 0x00000002 }, /* MOVE */
+{ op_33fc_0_comp_ff, 13308, 0x00000002 }, /* MOVE */
+{ op_4000_0_comp_ff, 16384, 0x00000008 }, /* NEGX */
+{ op_4010_0_comp_ff, 16400, 0x00000008 }, /* NEGX */
+{ op_4018_0_comp_ff, 16408, 0x00000008 }, /* NEGX */
+{ op_4020_0_comp_ff, 16416, 0x00000008 }, /* NEGX */
+{ op_4028_0_comp_ff, 16424, 0x0000000a }, /* NEGX */
+{ op_4030_0_comp_ff, 16432, 0x0000000a }, /* NEGX */
+{ op_4038_0_comp_ff, 16440, 0x0000000a }, /* NEGX */
+{ op_4039_0_comp_ff, 16441, 0x0000000a }, /* NEGX */
+{ op_4040_0_comp_ff, 16448, 0x00000008 }, /* NEGX */
+{ op_4050_0_comp_ff, 16464, 0x00000008 }, /* NEGX */
+{ op_4058_0_comp_ff, 16472, 0x00000008 }, /* NEGX */
+{ op_4060_0_comp_ff, 16480, 0x00000008 }, /* NEGX */
+{ op_4068_0_comp_ff, 16488, 0x0000000a }, /* NEGX */
+{ op_4070_0_comp_ff, 16496, 0x0000000a }, /* NEGX */
+{ op_4078_0_comp_ff, 16504, 0x0000000a }, /* NEGX */
+{ op_4079_0_comp_ff, 16505, 0x0000000a }, /* NEGX */
+{ op_4080_0_comp_ff, 16512, 0x00000008 }, /* NEGX */
+{ op_4090_0_comp_ff, 16528, 0x00000008 }, /* NEGX */
+{ op_4098_0_comp_ff, 16536, 0x00000008 }, /* NEGX */
+{ op_40a0_0_comp_ff, 16544, 0x00000008 }, /* NEGX */
+{ op_40a8_0_comp_ff, 16552, 0x0000000a }, /* NEGX */
+{ op_40b0_0_comp_ff, 16560, 0x0000000a }, /* NEGX */
+{ op_40b8_0_comp_ff, 16568, 0x0000000a }, /* NEGX */
+{ op_40b9_0_comp_ff, 16569, 0x0000000a }, /* NEGX */
+{ NULL, 16576, 0x00000001 }, /* MVSR2 */
+{ NULL, 16592, 0x00000001 }, /* MVSR2 */
+{ NULL, 16600, 0x00000001 }, /* MVSR2 */
+{ NULL, 16608, 0x00000001 }, /* MVSR2 */
+{ NULL, 16616, 0x00000001 }, /* MVSR2 */
+{ NULL, 16624, 0x00000001 }, /* MVSR2 */
+{ NULL, 16632, 0x00000001 }, /* MVSR2 */
+{ NULL, 16633, 0x00000001 }, /* MVSR2 */
+{ NULL, 16640, 0x00000001 }, /* CHK */
+{ NULL, 16656, 0x00000001 }, /* CHK */
+{ NULL, 16664, 0x00000001 }, /* CHK */
+{ NULL, 16672, 0x00000001 }, /* CHK */
+{ NULL, 16680, 0x00000001 }, /* CHK */
+{ NULL, 16688, 0x00000001 }, /* CHK */
+{ NULL, 16696, 0x00000001 }, /* CHK */
+{ NULL, 16697, 0x00000001 }, /* CHK */
+{ NULL, 16698, 0x00000001 }, /* CHK */
+{ NULL, 16699, 0x00000001 }, /* CHK */
+{ NULL, 16700, 0x00000001 }, /* CHK */
+{ NULL, 16768, 0x00000001 }, /* CHK */
+{ NULL, 16784, 0x00000001 }, /* CHK */
+{ NULL, 16792, 0x00000001 }, /* CHK */
+{ NULL, 16800, 0x00000001 }, /* CHK */
+{ NULL, 16808, 0x00000001 }, /* CHK */
+{ NULL, 16816, 0x00000001 }, /* CHK */
+{ NULL, 16824, 0x00000001 }, /* CHK */
+{ NULL, 16825, 0x00000001 }, /* CHK */
+{ NULL, 16826, 0x00000001 }, /* CHK */
+{ NULL, 16827, 0x00000001 }, /* CHK */
+{ NULL, 16828, 0x00000001 }, /* CHK */
+{ op_41d0_0_comp_ff, 16848, 0x00000000 }, /* LEA */
+{ op_41e8_0_comp_ff, 16872, 0x00000002 }, /* LEA */
+{ op_41f0_0_comp_ff, 16880, 0x00000002 }, /* LEA */
+{ op_41f8_0_comp_ff, 16888, 0x00000002 }, /* LEA */
+{ op_41f9_0_comp_ff, 16889, 0x00000002 }, /* LEA */
+{ op_41fa_0_comp_ff, 16890, 0x00000002 }, /* LEA */
+{ op_41fb_0_comp_ff, 16891, 0x00000002 }, /* LEA */
+{ op_4200_0_comp_ff, 16896, 0x00000000 }, /* CLR */
+{ op_4210_0_comp_ff, 16912, 0x00000000 }, /* CLR */
+{ op_4218_0_comp_ff, 16920, 0x00000000 }, /* CLR */
+{ op_4220_0_comp_ff, 16928, 0x00000000 }, /* CLR */
+{ op_4228_0_comp_ff, 16936, 0x00000002 }, /* CLR */
+{ op_4230_0_comp_ff, 16944, 0x00000002 }, /* CLR */
+{ op_4238_0_comp_ff, 16952, 0x00000002 }, /* CLR */
+{ op_4239_0_comp_ff, 16953, 0x00000002 }, /* CLR */
+{ op_4240_0_comp_ff, 16960, 0x00000000 }, /* CLR */
+{ op_4250_0_comp_ff, 16976, 0x00000000 }, /* CLR */
+{ op_4258_0_comp_ff, 16984, 0x00000000 }, /* CLR */
+{ op_4260_0_comp_ff, 16992, 0x00000000 }, /* CLR */
+{ op_4268_0_comp_ff, 17000, 0x00000002 }, /* CLR */
+{ op_4270_0_comp_ff, 17008, 0x00000002 }, /* CLR */
+{ op_4278_0_comp_ff, 17016, 0x00000002 }, /* CLR */
+{ op_4279_0_comp_ff, 17017, 0x00000002 }, /* CLR */
+{ op_4280_0_comp_ff, 17024, 0x00000000 }, /* CLR */
+{ op_4290_0_comp_ff, 17040, 0x00000000 }, /* CLR */
+{ op_4298_0_comp_ff, 17048, 0x00000000 }, /* CLR */
+{ op_42a0_0_comp_ff, 17056, 0x00000000 }, /* CLR */
+{ op_42a8_0_comp_ff, 17064, 0x00000002 }, /* CLR */
+{ op_42b0_0_comp_ff, 17072, 0x00000002 }, /* CLR */
+{ op_42b8_0_comp_ff, 17080, 0x00000002 }, /* CLR */
+{ op_42b9_0_comp_ff, 17081, 0x00000002 }, /* CLR */
+{ NULL, 17088, 0x00000001 }, /* MVSR2 */
+{ NULL, 17104, 0x00000001 }, /* MVSR2 */
+{ NULL, 17112, 0x00000001 }, /* MVSR2 */
+{ NULL, 17120, 0x00000001 }, /* MVSR2 */
+{ NULL, 17128, 0x00000001 }, /* MVSR2 */
+{ NULL, 17136, 0x00000001 }, /* MVSR2 */
+{ NULL, 17144, 0x00000001 }, /* MVSR2 */
+{ NULL, 17145, 0x00000001 }, /* MVSR2 */
+{ op_4400_0_comp_ff, 17408, 0x00000000 }, /* NEG */
+{ op_4410_0_comp_ff, 17424, 0x00000000 }, /* NEG */
+{ op_4418_0_comp_ff, 17432, 0x00000000 }, /* NEG */
+{ op_4420_0_comp_ff, 17440, 0x00000000 }, /* NEG */
+{ op_4428_0_comp_ff, 17448, 0x00000002 }, /* NEG */
+{ op_4430_0_comp_ff, 17456, 0x00000002 }, /* NEG */
+{ op_4438_0_comp_ff, 17464, 0x00000002 }, /* NEG */
+{ op_4439_0_comp_ff, 17465, 0x00000002 }, /* NEG */
+{ op_4440_0_comp_ff, 17472, 0x00000000 }, /* NEG */
+{ op_4450_0_comp_ff, 17488, 0x00000000 }, /* NEG */
+{ op_4458_0_comp_ff, 17496, 0x00000000 }, /* NEG */
+{ op_4460_0_comp_ff, 17504, 0x00000000 }, /* NEG */
+{ op_4468_0_comp_ff, 17512, 0x00000002 }, /* NEG */
+{ op_4470_0_comp_ff, 17520, 0x00000002 }, /* NEG */
+{ op_4478_0_comp_ff, 17528, 0x00000002 }, /* NEG */
+{ op_4479_0_comp_ff, 17529, 0x00000002 }, /* NEG */
+{ op_4480_0_comp_ff, 17536, 0x00000000 }, /* NEG */
+{ op_4490_0_comp_ff, 17552, 0x00000000 }, /* NEG */
+{ op_4498_0_comp_ff, 17560, 0x00000000 }, /* NEG */
+{ op_44a0_0_comp_ff, 17568, 0x00000000 }, /* NEG */
+{ op_44a8_0_comp_ff, 17576, 0x00000002 }, /* NEG */
+{ op_44b0_0_comp_ff, 17584, 0x00000002 }, /* NEG */
+{ op_44b8_0_comp_ff, 17592, 0x00000002 }, /* NEG */
+{ op_44b9_0_comp_ff, 17593, 0x00000002 }, /* NEG */
+{ NULL, 17600, 0x00000001 }, /* MV2SR */
+{ NULL, 17616, 0x00000001 }, /* MV2SR */
+{ NULL, 17624, 0x00000001 }, /* MV2SR */
+{ NULL, 17632, 0x00000001 }, /* MV2SR */
+{ NULL, 17640, 0x00000001 }, /* MV2SR */
+{ NULL, 17648, 0x00000001 }, /* MV2SR */
+{ NULL, 17656, 0x00000001 }, /* MV2SR */
+{ NULL, 17657, 0x00000001 }, /* MV2SR */
+{ NULL, 17658, 0x00000001 }, /* MV2SR */
+{ NULL, 17659, 0x00000001 }, /* MV2SR */
+{ NULL, 17660, 0x00000001 }, /* MV2SR */
+{ op_4600_0_comp_ff, 17920, 0x00000000 }, /* NOT */
+{ op_4610_0_comp_ff, 17936, 0x00000000 }, /* NOT */
+{ op_4618_0_comp_ff, 17944, 0x00000000 }, /* NOT */
+{ op_4620_0_comp_ff, 17952, 0x00000000 }, /* NOT */
+{ op_4628_0_comp_ff, 17960, 0x00000002 }, /* NOT */
+{ op_4630_0_comp_ff, 17968, 0x00000002 }, /* NOT */
+{ op_4638_0_comp_ff, 17976, 0x00000002 }, /* NOT */
+{ op_4639_0_comp_ff, 17977, 0x00000002 }, /* NOT */
+{ op_4640_0_comp_ff, 17984, 0x00000000 }, /* NOT */
+{ op_4650_0_comp_ff, 18000, 0x00000000 }, /* NOT */
+{ op_4658_0_comp_ff, 18008, 0x00000000 }, /* NOT */
+{ op_4660_0_comp_ff, 18016, 0x00000000 }, /* NOT */
+{ op_4668_0_comp_ff, 18024, 0x00000002 }, /* NOT */
+{ op_4670_0_comp_ff, 18032, 0x00000002 }, /* NOT */
+{ op_4678_0_comp_ff, 18040, 0x00000002 }, /* NOT */
+{ op_4679_0_comp_ff, 18041, 0x00000002 }, /* NOT */
+{ op_4680_0_comp_ff, 18048, 0x00000000 }, /* NOT */
+{ op_4690_0_comp_ff, 18064, 0x00000000 }, /* NOT */
+{ op_4698_0_comp_ff, 18072, 0x00000000 }, /* NOT */
+{ op_46a0_0_comp_ff, 18080, 0x00000000 }, /* NOT */
+{ op_46a8_0_comp_ff, 18088, 0x00000002 }, /* NOT */
+{ op_46b0_0_comp_ff, 18096, 0x00000002 }, /* NOT */
+{ op_46b8_0_comp_ff, 18104, 0x00000002 }, /* NOT */
+{ op_46b9_0_comp_ff, 18105, 0x00000002 }, /* NOT */
+{ NULL, 18112, 0x00000001 }, /* MV2SR */
+{ NULL, 18128, 0x00000001 }, /* MV2SR */
+{ NULL, 18136, 0x00000001 }, /* MV2SR */
+{ NULL, 18144, 0x00000001 }, /* MV2SR */
+{ NULL, 18152, 0x00000001 }, /* MV2SR */
+{ NULL, 18160, 0x00000001 }, /* MV2SR */
+{ NULL, 18168, 0x00000001 }, /* MV2SR */
+{ NULL, 18169, 0x00000001 }, /* MV2SR */
+{ NULL, 18170, 0x00000001 }, /* MV2SR */
+{ NULL, 18171, 0x00000001 }, /* MV2SR */
+{ NULL, 18172, 0x00000001 }, /* MV2SR */
+{ NULL, 18432, 0x00000000 }, /* NBCD */
+{ op_4808_0_comp_ff, 18440, 0x00000002 }, /* LINK */
+{ NULL, 18448, 0x00000000 }, /* NBCD */
+{ NULL, 18456, 0x00000000 }, /* NBCD */
+{ NULL, 18464, 0x00000000 }, /* NBCD */
+{ NULL, 18472, 0x00000000 }, /* NBCD */
+{ NULL, 18480, 0x00000000 }, /* NBCD */
+{ NULL, 18488, 0x00000000 }, /* NBCD */
+{ NULL, 18489, 0x00000000 }, /* NBCD */
+{ op_4840_0_comp_ff, 18496, 0x00000000 }, /* SWAP */
+{ NULL, 18504, 0x00000001 }, /* BKPT */
+{ op_4850_0_comp_ff, 18512, 0x00000000 }, /* PEA */
+{ op_4868_0_comp_ff, 18536, 0x00000002 }, /* PEA */
+{ op_4870_0_comp_ff, 18544, 0x00000002 }, /* PEA */
+{ op_4878_0_comp_ff, 18552, 0x00000002 }, /* PEA */
+{ op_4879_0_comp_ff, 18553, 0x00000002 }, /* PEA */
+{ op_487a_0_comp_ff, 18554, 0x00000002 }, /* PEA */
+{ op_487b_0_comp_ff, 18555, 0x00000002 }, /* PEA */
+{ op_4880_0_comp_ff, 18560, 0x00000000 }, /* EXT */
+{ op_4890_0_comp_ff, 18576, 0x00000002 }, /* MVMLE */
+{ op_48a0_0_comp_ff, 18592, 0x00000002 }, /* MVMLE */
+{ op_48a8_0_comp_ff, 18600, 0x00000002 }, /* MVMLE */
+{ op_48b0_0_comp_ff, 18608, 0x00000002 }, /* MVMLE */
+{ op_48b8_0_comp_ff, 18616, 0x00000002 }, /* MVMLE */
+{ op_48b9_0_comp_ff, 18617, 0x00000002 }, /* MVMLE */
+{ op_48c0_0_comp_ff, 18624, 0x00000000 }, /* EXT */
+{ op_48d0_0_comp_ff, 18640, 0x00000002 }, /* MVMLE */
+{ op_48e0_0_comp_ff, 18656, 0x00000002 }, /* MVMLE */
+{ op_48e8_0_comp_ff, 18664, 0x00000002 }, /* MVMLE */
+{ op_48f0_0_comp_ff, 18672, 0x00000002 }, /* MVMLE */
+{ op_48f8_0_comp_ff, 18680, 0x00000002 }, /* MVMLE */
+{ op_48f9_0_comp_ff, 18681, 0x00000002 }, /* MVMLE */
+{ op_49c0_0_comp_ff, 18880, 0x00000000 }, /* EXT */
+{ op_4a00_0_comp_ff, 18944, 0x00000000 }, /* TST */
+{ op_4a10_0_comp_ff, 18960, 0x00000000 }, /* TST */
+{ op_4a18_0_comp_ff, 18968, 0x00000000 }, /* TST */
+{ op_4a20_0_comp_ff, 18976, 0x00000000 }, /* TST */
+{ op_4a28_0_comp_ff, 18984, 0x00000002 }, /* TST */
+{ op_4a30_0_comp_ff, 18992, 0x00000002 }, /* TST */
+{ op_4a38_0_comp_ff, 19000, 0x00000002 }, /* TST */
+{ op_4a39_0_comp_ff, 19001, 0x00000002 }, /* TST */
+{ op_4a3a_0_comp_ff, 19002, 0x00000002 }, /* TST */
+{ op_4a3b_0_comp_ff, 19003, 0x00000002 }, /* TST */
+{ op_4a3c_0_comp_ff, 19004, 0x00000002 }, /* TST */
+{ op_4a40_0_comp_ff, 19008, 0x00000000 }, /* TST */
+{ op_4a48_0_comp_ff, 19016, 0x00000000 }, /* TST */
+{ op_4a50_0_comp_ff, 19024, 0x00000000 }, /* TST */
+{ op_4a58_0_comp_ff, 19032, 0x00000000 }, /* TST */
+{ op_4a60_0_comp_ff, 19040, 0x00000000 }, /* TST */
+{ op_4a68_0_comp_ff, 19048, 0x00000002 }, /* TST */
+{ op_4a70_0_comp_ff, 19056, 0x00000002 }, /* TST */
+{ op_4a78_0_comp_ff, 19064, 0x00000002 }, /* TST */
+{ op_4a79_0_comp_ff, 19065, 0x00000002 }, /* TST */
+{ op_4a7a_0_comp_ff, 19066, 0x00000002 }, /* TST */
+{ op_4a7b_0_comp_ff, 19067, 0x00000002 }, /* TST */
+{ op_4a7c_0_comp_ff, 19068, 0x00000002 }, /* TST */
+{ op_4a80_0_comp_ff, 19072, 0x00000000 }, /* TST */
+{ op_4a88_0_comp_ff, 19080, 0x00000000 }, /* TST */
+{ op_4a90_0_comp_ff, 19088, 0x00000000 }, /* TST */
+{ op_4a98_0_comp_ff, 19096, 0x00000000 }, /* TST */
+{ op_4aa0_0_comp_ff, 19104, 0x00000000 }, /* TST */
+{ op_4aa8_0_comp_ff, 19112, 0x00000002 }, /* TST */
+{ op_4ab0_0_comp_ff, 19120, 0x00000002 }, /* TST */
+{ op_4ab8_0_comp_ff, 19128, 0x00000002 }, /* TST */
+{ op_4ab9_0_comp_ff, 19129, 0x00000002 }, /* TST */
+{ op_4aba_0_comp_ff, 19130, 0x00000002 }, /* TST */
+{ op_4abb_0_comp_ff, 19131, 0x00000002 }, /* TST */
+{ op_4abc_0_comp_ff, 19132, 0x00000002 }, /* TST */
+{ NULL, 19136, 0x00000000 }, /* TAS */
+{ NULL, 19152, 0x00000000 }, /* TAS */
+{ NULL, 19160, 0x00000000 }, /* TAS */
+{ NULL, 19168, 0x00000000 }, /* TAS */
+{ NULL, 19176, 0x00000000 }, /* TAS */
+{ NULL, 19184, 0x00000000 }, /* TAS */
+{ NULL, 19192, 0x00000000 }, /* TAS */
+{ NULL, 19193, 0x00000000 }, /* TAS */
+{ op_4c00_0_comp_ff, 19456, 0x00000002 }, /* MULL */
+{ op_4c10_0_comp_ff, 19472, 0x00000002 }, /* MULL */
+{ op_4c18_0_comp_ff, 19480, 0x00000002 }, /* MULL */
+{ op_4c20_0_comp_ff, 19488, 0x00000002 }, /* MULL */
+{ op_4c28_0_comp_ff, 19496, 0x00000002 }, /* MULL */
+{ op_4c30_0_comp_ff, 19504, 0x00000002 }, /* MULL */
+{ op_4c38_0_comp_ff, 19512, 0x00000002 }, /* MULL */
+{ op_4c39_0_comp_ff, 19513, 0x00000002 }, /* MULL */
+{ op_4c3a_0_comp_ff, 19514, 0x00000002 }, /* MULL */
+{ op_4c3b_0_comp_ff, 19515, 0x00000002 }, /* MULL */
+{ op_4c3c_0_comp_ff, 19516, 0x00000002 }, /* MULL */
+{ op_4c40_0_comp_ff, 19520, 0x00000002 }, /* DIVL */
+{ op_4c50_0_comp_ff, 19536, 0x00000002 }, /* DIVL */
+{ op_4c58_0_comp_ff, 19544, 0x00000002 }, /* DIVL */
+{ op_4c60_0_comp_ff, 19552, 0x00000002 }, /* DIVL */
+{ op_4c68_0_comp_ff, 19560, 0x00000002 }, /* DIVL */
+{ op_4c70_0_comp_ff, 19568, 0x00000002 }, /* DIVL */
+{ op_4c78_0_comp_ff, 19576, 0x00000002 }, /* DIVL */
+{ op_4c79_0_comp_ff, 19577, 0x00000002 }, /* DIVL */
+{ op_4c7a_0_comp_ff, 19578, 0x00000002 }, /* DIVL */
+{ op_4c7b_0_comp_ff, 19579, 0x00000002 }, /* DIVL */
+{ op_4c7c_0_comp_ff, 19580, 0x00000002 }, /* DIVL */
+{ op_4c90_0_comp_ff, 19600, 0x00000002 }, /* MVMEL */
+{ op_4c98_0_comp_ff, 19608, 0x00000002 }, /* MVMEL */
+{ op_4ca8_0_comp_ff, 19624, 0x00000002 }, /* MVMEL */
+{ op_4cb0_0_comp_ff, 19632, 0x00000002 }, /* MVMEL */
+{ op_4cb8_0_comp_ff, 19640, 0x00000002 }, /* MVMEL */
+{ op_4cb9_0_comp_ff, 19641, 0x00000002 }, /* MVMEL */
+{ op_4cba_0_comp_ff, 19642, 0x00000002 }, /* MVMEL */
+{ op_4cbb_0_comp_ff, 19643, 0x00000002 }, /* MVMEL */
+{ op_4cd0_0_comp_ff, 19664, 0x00000002 }, /* MVMEL */
+{ op_4cd8_0_comp_ff, 19672, 0x00000002 }, /* MVMEL */
+{ op_4ce8_0_comp_ff, 19688, 0x00000002 }, /* MVMEL */
+{ op_4cf0_0_comp_ff, 19696, 0x00000002 }, /* MVMEL */
+{ op_4cf8_0_comp_ff, 19704, 0x00000002 }, /* MVMEL */
+{ op_4cf9_0_comp_ff, 19705, 0x00000002 }, /* MVMEL */
+{ op_4cfa_0_comp_ff, 19706, 0x00000002 }, /* MVMEL */
+{ op_4cfb_0_comp_ff, 19707, 0x00000002 }, /* MVMEL */
+{ NULL, 20032, 0x00000001 }, /* TRAP */
+{ op_4e50_0_comp_ff, 20048, 0x00000002 }, /* LINK */
+{ op_4e58_0_comp_ff, 20056, 0x00000000 }, /* UNLK */
+{ NULL, 20064, 0x00000001 }, /* MVR2USP */
+{ NULL, 20072, 0x00000001 }, /* MVUSP2R */
+{ NULL, 20080, 0x00000001 }, /* RESET */
+{ op_4e71_0_comp_ff, 20081, 0x00000000 }, /* NOP */
+{ NULL, 20082, 0x00000001 }, /* STOP */
+{ NULL, 20083, 0x00000001 }, /* RTE */
+{ op_4e74_0_comp_ff, 20084, 0x00000003 }, /* RTD */
+{ op_4e75_0_comp_ff, 20085, 0x00000001 }, /* RTS */
+{ NULL, 20086, 0x00000001 }, /* TRAPV */
+{ NULL, 20087, 0x00000001 }, /* RTR */
+{ NULL, 20090, 0x00000001 }, /* MOVEC2 */
+{ NULL, 20091, 0x00000001 }, /* MOVE2C */
+{ op_4e90_0_comp_ff, 20112, 0x00000001 }, /* JSR */
+{ op_4ea8_0_comp_ff, 20136, 0x00000003 }, /* JSR */
+{ op_4eb0_0_comp_ff, 20144, 0x00000003 }, /* JSR */
+{ op_4eb8_0_comp_ff, 20152, 0x00000003 }, /* JSR */
+{ op_4eb9_0_comp_ff, 20153, 0x00000003 }, /* JSR */
+{ op_4eba_0_comp_ff, 20154, 0x00000003 }, /* JSR */
+{ op_4ebb_0_comp_ff, 20155, 0x00000003 }, /* JSR */
+{ op_4ed0_0_comp_ff, 20176, 0x00000001 }, /* JMP */
+{ op_4ee8_0_comp_ff, 20200, 0x00000003 }, /* JMP */
+{ op_4ef0_0_comp_ff, 20208, 0x00000003 }, /* JMP */
+{ op_4ef8_0_comp_ff, 20216, 0x00000003 }, /* JMP */
+{ op_4ef9_0_comp_ff, 20217, 0x00000003 }, /* JMP */
+{ op_4efa_0_comp_ff, 20218, 0x00000003 }, /* JMP */
+{ op_4efb_0_comp_ff, 20219, 0x00000003 }, /* JMP */
+{ op_5000_0_comp_ff, 20480, 0x00000000 }, /* ADD */
+{ op_5010_0_comp_ff, 20496, 0x00000000 }, /* ADD */
+{ op_5018_0_comp_ff, 20504, 0x00000000 }, /* ADD */
+{ op_5020_0_comp_ff, 20512, 0x00000000 }, /* ADD */
+{ op_5028_0_comp_ff, 20520, 0x00000002 }, /* ADD */
+{ op_5030_0_comp_ff, 20528, 0x00000002 }, /* ADD */
+{ op_5038_0_comp_ff, 20536, 0x00000002 }, /* ADD */
+{ op_5039_0_comp_ff, 20537, 0x00000002 }, /* ADD */
+{ op_5040_0_comp_ff, 20544, 0x00000000 }, /* ADD */
+{ op_5048_0_comp_ff, 20552, 0x00000000 }, /* ADDA */
+{ op_5050_0_comp_ff, 20560, 0x00000000 }, /* ADD */
+{ op_5058_0_comp_ff, 20568, 0x00000000 }, /* ADD */
+{ op_5060_0_comp_ff, 20576, 0x00000000 }, /* ADD */
+{ op_5068_0_comp_ff, 20584, 0x00000002 }, /* ADD */
+{ op_5070_0_comp_ff, 20592, 0x00000002 }, /* ADD */
+{ op_5078_0_comp_ff, 20600, 0x00000002 }, /* ADD */
+{ op_5079_0_comp_ff, 20601, 0x00000002 }, /* ADD */
+{ op_5080_0_comp_ff, 20608, 0x00000000 }, /* ADD */
+{ op_5088_0_comp_ff, 20616, 0x00000000 }, /* ADDA */
+{ op_5090_0_comp_ff, 20624, 0x00000000 }, /* ADD */
+{ op_5098_0_comp_ff, 20632, 0x00000000 }, /* ADD */
+{ op_50a0_0_comp_ff, 20640, 0x00000000 }, /* ADD */
+{ op_50a8_0_comp_ff, 20648, 0x00000002 }, /* ADD */
+{ op_50b0_0_comp_ff, 20656, 0x00000002 }, /* ADD */
+{ op_50b8_0_comp_ff, 20664, 0x00000002 }, /* ADD */
+{ op_50b9_0_comp_ff, 20665, 0x00000002 }, /* ADD */
+{ op_50c0_0_comp_ff, 20672, 0x00000000 }, /* Scc */
+{ op_50c8_0_comp_ff, 20680, 0x00000003 }, /* DBcc */
+{ op_50d0_0_comp_ff, 20688, 0x00000000 }, /* Scc */
+{ op_50d8_0_comp_ff, 20696, 0x00000000 }, /* Scc */
+{ op_50e0_0_comp_ff, 20704, 0x00000000 }, /* Scc */
+{ op_50e8_0_comp_ff, 20712, 0x00000002 }, /* Scc */
+{ op_50f0_0_comp_ff, 20720, 0x00000002 }, /* Scc */
+{ op_50f8_0_comp_ff, 20728, 0x00000002 }, /* Scc */
+{ op_50f9_0_comp_ff, 20729, 0x00000002 }, /* Scc */
+{ NULL, 20730, 0x00000001 }, /* TRAPcc */
+{ NULL, 20731, 0x00000001 }, /* TRAPcc */
+{ NULL, 20732, 0x00000001 }, /* TRAPcc */
+{ op_5100_0_comp_ff, 20736, 0x00000000 }, /* SUB */
+{ op_5110_0_comp_ff, 20752, 0x00000000 }, /* SUB */
+{ op_5118_0_comp_ff, 20760, 0x00000000 }, /* SUB */
+{ op_5120_0_comp_ff, 20768, 0x00000000 }, /* SUB */
+{ op_5128_0_comp_ff, 20776, 0x00000002 }, /* SUB */
+{ op_5130_0_comp_ff, 20784, 0x00000002 }, /* SUB */
+{ op_5138_0_comp_ff, 20792, 0x00000002 }, /* SUB */
+{ op_5139_0_comp_ff, 20793, 0x00000002 }, /* SUB */
+{ op_5140_0_comp_ff, 20800, 0x00000000 }, /* SUB */
+{ op_5148_0_comp_ff, 20808, 0x00000000 }, /* SUBA */
+{ op_5150_0_comp_ff, 20816, 0x00000000 }, /* SUB */
+{ op_5158_0_comp_ff, 20824, 0x00000000 }, /* SUB */
+{ op_5160_0_comp_ff, 20832, 0x00000000 }, /* SUB */
+{ op_5168_0_comp_ff, 20840, 0x00000002 }, /* SUB */
+{ op_5170_0_comp_ff, 20848, 0x00000002 }, /* SUB */
+{ op_5178_0_comp_ff, 20856, 0x00000002 }, /* SUB */
+{ op_5179_0_comp_ff, 20857, 0x00000002 }, /* SUB */
+{ op_5180_0_comp_ff, 20864, 0x00000000 }, /* SUB */
+{ op_5188_0_comp_ff, 20872, 0x00000000 }, /* SUBA */
+{ op_5190_0_comp_ff, 20880, 0x00000000 }, /* SUB */
+{ op_5198_0_comp_ff, 20888, 0x00000000 }, /* SUB */
+{ op_51a0_0_comp_ff, 20896, 0x00000000 }, /* SUB */
+{ op_51a8_0_comp_ff, 20904, 0x00000002 }, /* SUB */
+{ op_51b0_0_comp_ff, 20912, 0x00000002 }, /* SUB */
+{ op_51b8_0_comp_ff, 20920, 0x00000002 }, /* SUB */
+{ op_51b9_0_comp_ff, 20921, 0x00000002 }, /* SUB */
+{ op_51c0_0_comp_ff, 20928, 0x00000000 }, /* Scc */
+{ op_51c8_0_comp_ff, 20936, 0x00000003 }, /* DBcc */
+{ op_51d0_0_comp_ff, 20944, 0x00000000 }, /* Scc */
+{ op_51d8_0_comp_ff, 20952, 0x00000000 }, /* Scc */
+{ op_51e0_0_comp_ff, 20960, 0x00000000 }, /* Scc */
+{ op_51e8_0_comp_ff, 20968, 0x00000002 }, /* Scc */
+{ op_51f0_0_comp_ff, 20976, 0x00000002 }, /* Scc */
+{ op_51f8_0_comp_ff, 20984, 0x00000002 }, /* Scc */
+{ op_51f9_0_comp_ff, 20985, 0x00000002 }, /* Scc */
+{ NULL, 20986, 0x00000001 }, /* TRAPcc */
+{ NULL, 20987, 0x00000001 }, /* TRAPcc */
+{ NULL, 20988, 0x00000001 }, /* TRAPcc */
+{ op_52c0_0_comp_ff, 21184, 0x00000000 }, /* Scc */
+{ op_52c8_0_comp_ff, 21192, 0x00000003 }, /* DBcc */
+{ op_52d0_0_comp_ff, 21200, 0x00000000 }, /* Scc */
+{ op_52d8_0_comp_ff, 21208, 0x00000000 }, /* Scc */
+{ op_52e0_0_comp_ff, 21216, 0x00000000 }, /* Scc */
+{ op_52e8_0_comp_ff, 21224, 0x00000002 }, /* Scc */
+{ op_52f0_0_comp_ff, 21232, 0x00000002 }, /* Scc */
+{ op_52f8_0_comp_ff, 21240, 0x00000002 }, /* Scc */
+{ op_52f9_0_comp_ff, 21241, 0x00000002 }, /* Scc */
+{ NULL, 21242, 0x00000001 }, /* TRAPcc */
+{ NULL, 21243, 0x00000001 }, /* TRAPcc */
+{ NULL, 21244, 0x00000001 }, /* TRAPcc */
+{ op_53c0_0_comp_ff, 21440, 0x00000000 }, /* Scc */
+{ op_53c8_0_comp_ff, 21448, 0x00000003 }, /* DBcc */
+{ op_53d0_0_comp_ff, 21456, 0x00000000 }, /* Scc */
+{ op_53d8_0_comp_ff, 21464, 0x00000000 }, /* Scc */
+{ op_53e0_0_comp_ff, 21472, 0x00000000 }, /* Scc */
+{ op_53e8_0_comp_ff, 21480, 0x00000002 }, /* Scc */
+{ op_53f0_0_comp_ff, 21488, 0x00000002 }, /* Scc */
+{ op_53f8_0_comp_ff, 21496, 0x00000002 }, /* Scc */
+{ op_53f9_0_comp_ff, 21497, 0x00000002 }, /* Scc */
+{ NULL, 21498, 0x00000001 }, /* TRAPcc */
+{ NULL, 21499, 0x00000001 }, /* TRAPcc */
+{ NULL, 21500, 0x00000001 }, /* TRAPcc */
+{ op_54c0_0_comp_ff, 21696, 0x00000000 }, /* Scc */
+{ op_54c8_0_comp_ff, 21704, 0x00000003 }, /* DBcc */
+{ op_54d0_0_comp_ff, 21712, 0x00000000 }, /* Scc */
+{ op_54d8_0_comp_ff, 21720, 0x00000000 }, /* Scc */
+{ op_54e0_0_comp_ff, 21728, 0x00000000 }, /* Scc */
+{ op_54e8_0_comp_ff, 21736, 0x00000002 }, /* Scc */
+{ op_54f0_0_comp_ff, 21744, 0x00000002 }, /* Scc */
+{ op_54f8_0_comp_ff, 21752, 0x00000002 }, /* Scc */
+{ op_54f9_0_comp_ff, 21753, 0x00000002 }, /* Scc */
+{ NULL, 21754, 0x00000001 }, /* TRAPcc */
+{ NULL, 21755, 0x00000001 }, /* TRAPcc */
+{ NULL, 21756, 0x00000001 }, /* TRAPcc */
+{ op_55c0_0_comp_ff, 21952, 0x00000000 }, /* Scc */
+{ op_55c8_0_comp_ff, 21960, 0x00000003 }, /* DBcc */
+{ op_55d0_0_comp_ff, 21968, 0x00000000 }, /* Scc */
+{ op_55d8_0_comp_ff, 21976, 0x00000000 }, /* Scc */
+{ op_55e0_0_comp_ff, 21984, 0x00000000 }, /* Scc */
+{ op_55e8_0_comp_ff, 21992, 0x00000002 }, /* Scc */
+{ op_55f0_0_comp_ff, 22000, 0x00000002 }, /* Scc */
+{ op_55f8_0_comp_ff, 22008, 0x00000002 }, /* Scc */
+{ op_55f9_0_comp_ff, 22009, 0x00000002 }, /* Scc */
+{ NULL, 22010, 0x00000001 }, /* TRAPcc */
+{ NULL, 22011, 0x00000001 }, /* TRAPcc */
+{ NULL, 22012, 0x00000001 }, /* TRAPcc */
+{ op_56c0_0_comp_ff, 22208, 0x00000000 }, /* Scc */
+{ op_56c8_0_comp_ff, 22216, 0x00000003 }, /* DBcc */
+{ op_56d0_0_comp_ff, 22224, 0x00000000 }, /* Scc */
+{ op_56d8_0_comp_ff, 22232, 0x00000000 }, /* Scc */
+{ op_56e0_0_comp_ff, 22240, 0x00000000 }, /* Scc */
+{ op_56e8_0_comp_ff, 22248, 0x00000002 }, /* Scc */
+{ op_56f0_0_comp_ff, 22256, 0x00000002 }, /* Scc */
+{ op_56f8_0_comp_ff, 22264, 0x00000002 }, /* Scc */
+{ op_56f9_0_comp_ff, 22265, 0x00000002 }, /* Scc */
+{ NULL, 22266, 0x00000001 }, /* TRAPcc */
+{ NULL, 22267, 0x00000001 }, /* TRAPcc */
+{ NULL, 22268, 0x00000001 }, /* TRAPcc */
+{ op_57c0_0_comp_ff, 22464, 0x00000000 }, /* Scc */
+{ op_57c8_0_comp_ff, 22472, 0x00000003 }, /* DBcc */
+{ op_57d0_0_comp_ff, 22480, 0x00000000 }, /* Scc */
+{ op_57d8_0_comp_ff, 22488, 0x00000000 }, /* Scc */
+{ op_57e0_0_comp_ff, 22496, 0x00000000 }, /* Scc */
+{ op_57e8_0_comp_ff, 22504, 0x00000002 }, /* Scc */
+{ op_57f0_0_comp_ff, 22512, 0x00000002 }, /* Scc */
+{ op_57f8_0_comp_ff, 22520, 0x00000002 }, /* Scc */
+{ op_57f9_0_comp_ff, 22521, 0x00000002 }, /* Scc */
+{ NULL, 22522, 0x00000001 }, /* TRAPcc */
+{ NULL, 22523, 0x00000001 }, /* TRAPcc */
+{ NULL, 22524, 0x00000001 }, /* TRAPcc */
+{ op_58c0_0_comp_ff, 22720, 0x00000000 }, /* Scc */
+{ op_58c8_0_comp_ff, 22728, 0x00000003 }, /* DBcc */
+{ op_58d0_0_comp_ff, 22736, 0x00000000 }, /* Scc */
+{ op_58d8_0_comp_ff, 22744, 0x00000000 }, /* Scc */
+{ op_58e0_0_comp_ff, 22752, 0x00000000 }, /* Scc */
+{ op_58e8_0_comp_ff, 22760, 0x00000002 }, /* Scc */
+{ op_58f0_0_comp_ff, 22768, 0x00000002 }, /* Scc */
+{ op_58f8_0_comp_ff, 22776, 0x00000002 }, /* Scc */
+{ op_58f9_0_comp_ff, 22777, 0x00000002 }, /* Scc */
+{ NULL, 22778, 0x00000001 }, /* TRAPcc */
+{ NULL, 22779, 0x00000001 }, /* TRAPcc */
+{ NULL, 22780, 0x00000001 }, /* TRAPcc */
+{ op_59c0_0_comp_ff, 22976, 0x00000000 }, /* Scc */
+{ op_59c8_0_comp_ff, 22984, 0x00000003 }, /* DBcc */
+{ op_59d0_0_comp_ff, 22992, 0x00000000 }, /* Scc */
+{ op_59d8_0_comp_ff, 23000, 0x00000000 }, /* Scc */
+{ op_59e0_0_comp_ff, 23008, 0x00000000 }, /* Scc */
+{ op_59e8_0_comp_ff, 23016, 0x00000002 }, /* Scc */
+{ op_59f0_0_comp_ff, 23024, 0x00000002 }, /* Scc */
+{ op_59f8_0_comp_ff, 23032, 0x00000002 }, /* Scc */
+{ op_59f9_0_comp_ff, 23033, 0x00000002 }, /* Scc */
+{ NULL, 23034, 0x00000001 }, /* TRAPcc */
+{ NULL, 23035, 0x00000001 }, /* TRAPcc */
+{ NULL, 23036, 0x00000001 }, /* TRAPcc */
+{ op_5ac0_0_comp_ff, 23232, 0x00000000 }, /* Scc */
+{ op_5ac8_0_comp_ff, 23240, 0x00000003 }, /* DBcc */
+{ op_5ad0_0_comp_ff, 23248, 0x00000000 }, /* Scc */
+{ op_5ad8_0_comp_ff, 23256, 0x00000000 }, /* Scc */
+{ op_5ae0_0_comp_ff, 23264, 0x00000000 }, /* Scc */
+{ op_5ae8_0_comp_ff, 23272, 0x00000002 }, /* Scc */
+{ op_5af0_0_comp_ff, 23280, 0x00000002 }, /* Scc */
+{ op_5af8_0_comp_ff, 23288, 0x00000002 }, /* Scc */
+{ op_5af9_0_comp_ff, 23289, 0x00000002 }, /* Scc */
+{ NULL, 23290, 0x00000001 }, /* TRAPcc */
+{ NULL, 23291, 0x00000001 }, /* TRAPcc */
+{ NULL, 23292, 0x00000001 }, /* TRAPcc */
+{ op_5bc0_0_comp_ff, 23488, 0x00000000 }, /* Scc */
+{ op_5bc8_0_comp_ff, 23496, 0x00000003 }, /* DBcc */
+{ op_5bd0_0_comp_ff, 23504, 0x00000000 }, /* Scc */
+{ op_5bd8_0_comp_ff, 23512, 0x00000000 }, /* Scc */
+{ op_5be0_0_comp_ff, 23520, 0x00000000 }, /* Scc */
+{ op_5be8_0_comp_ff, 23528, 0x00000002 }, /* Scc */
+{ op_5bf0_0_comp_ff, 23536, 0x00000002 }, /* Scc */
+{ op_5bf8_0_comp_ff, 23544, 0x00000002 }, /* Scc */
+{ op_5bf9_0_comp_ff, 23545, 0x00000002 }, /* Scc */
+{ NULL, 23546, 0x00000001 }, /* TRAPcc */
+{ NULL, 23547, 0x00000001 }, /* TRAPcc */
+{ NULL, 23548, 0x00000001 }, /* TRAPcc */
+{ op_5cc0_0_comp_ff, 23744, 0x00000000 }, /* Scc */
+{ op_5cc8_0_comp_ff, 23752, 0x00000003 }, /* DBcc */
+{ op_5cd0_0_comp_ff, 23760, 0x00000000 }, /* Scc */
+{ op_5cd8_0_comp_ff, 23768, 0x00000000 }, /* Scc */
+{ op_5ce0_0_comp_ff, 23776, 0x00000000 }, /* Scc */
+{ op_5ce8_0_comp_ff, 23784, 0x00000002 }, /* Scc */
+{ op_5cf0_0_comp_ff, 23792, 0x00000002 }, /* Scc */
+{ op_5cf8_0_comp_ff, 23800, 0x00000002 }, /* Scc */
+{ op_5cf9_0_comp_ff, 23801, 0x00000002 }, /* Scc */
+{ NULL, 23802, 0x00000001 }, /* TRAPcc */
+{ NULL, 23803, 0x00000001 }, /* TRAPcc */
+{ NULL, 23804, 0x00000001 }, /* TRAPcc */
+{ op_5dc0_0_comp_ff, 24000, 0x00000000 }, /* Scc */
+{ op_5dc8_0_comp_ff, 24008, 0x00000003 }, /* DBcc */
+{ op_5dd0_0_comp_ff, 24016, 0x00000000 }, /* Scc */
+{ op_5dd8_0_comp_ff, 24024, 0x00000000 }, /* Scc */
+{ op_5de0_0_comp_ff, 24032, 0x00000000 }, /* Scc */
+{ op_5de8_0_comp_ff, 24040, 0x00000002 }, /* Scc */
+{ op_5df0_0_comp_ff, 24048, 0x00000002 }, /* Scc */
+{ op_5df8_0_comp_ff, 24056, 0x00000002 }, /* Scc */
+{ op_5df9_0_comp_ff, 24057, 0x00000002 }, /* Scc */
+{ NULL, 24058, 0x00000001 }, /* TRAPcc */
+{ NULL, 24059, 0x00000001 }, /* TRAPcc */
+{ NULL, 24060, 0x00000001 }, /* TRAPcc */
+{ op_5ec0_0_comp_ff, 24256, 0x00000000 }, /* Scc */
+{ op_5ec8_0_comp_ff, 24264, 0x00000003 }, /* DBcc */
+{ op_5ed0_0_comp_ff, 24272, 0x00000000 }, /* Scc */
+{ op_5ed8_0_comp_ff, 24280, 0x00000000 }, /* Scc */
+{ op_5ee0_0_comp_ff, 24288, 0x00000000 }, /* Scc */
+{ op_5ee8_0_comp_ff, 24296, 0x00000002 }, /* Scc */
+{ op_5ef0_0_comp_ff, 24304, 0x00000002 }, /* Scc */
+{ op_5ef8_0_comp_ff, 24312, 0x00000002 }, /* Scc */
+{ op_5ef9_0_comp_ff, 24313, 0x00000002 }, /* Scc */
+{ NULL, 24314, 0x00000001 }, /* TRAPcc */
+{ NULL, 24315, 0x00000001 }, /* TRAPcc */
+{ NULL, 24316, 0x00000001 }, /* TRAPcc */
+{ op_5fc0_0_comp_ff, 24512, 0x00000000 }, /* Scc */
+{ op_5fc8_0_comp_ff, 24520, 0x00000003 }, /* DBcc */
+{ op_5fd0_0_comp_ff, 24528, 0x00000000 }, /* Scc */
+{ op_5fd8_0_comp_ff, 24536, 0x00000000 }, /* Scc */
+{ op_5fe0_0_comp_ff, 24544, 0x00000000 }, /* Scc */
+{ op_5fe8_0_comp_ff, 24552, 0x00000002 }, /* Scc */
+{ op_5ff0_0_comp_ff, 24560, 0x00000002 }, /* Scc */
+{ op_5ff8_0_comp_ff, 24568, 0x00000002 }, /* Scc */
+{ op_5ff9_0_comp_ff, 24569, 0x00000002 }, /* Scc */
+{ NULL, 24570, 0x00000001 }, /* TRAPcc */
+{ NULL, 24571, 0x00000001 }, /* TRAPcc */
+{ NULL, 24572, 0x00000001 }, /* TRAPcc */
+{ op_6000_0_comp_ff, 24576, 0x00000012 }, /* Bcc */
+{ op_6001_0_comp_ff, 24577, 0x00000010 }, /* Bcc */
+{ op_60ff_0_comp_ff, 24831, 0x00000012 }, /* Bcc */
+{ op_6100_0_comp_ff, 24832, 0x00000012 }, /* BSR */
+{ op_6101_0_comp_ff, 24833, 0x00000010 }, /* BSR */
+{ op_61ff_0_comp_ff, 25087, 0x00000012 }, /* BSR */
+{ op_6200_0_comp_ff, 25088, 0x00000003 }, /* Bcc */
+{ op_6201_0_comp_ff, 25089, 0x00000001 }, /* Bcc */
+{ op_62ff_0_comp_ff, 25343, 0x00000003 }, /* Bcc */
+{ op_6300_0_comp_ff, 25344, 0x00000003 }, /* Bcc */
+{ op_6301_0_comp_ff, 25345, 0x00000001 }, /* Bcc */
+{ op_63ff_0_comp_ff, 25599, 0x00000003 }, /* Bcc */
+{ op_6400_0_comp_ff, 25600, 0x00000003 }, /* Bcc */
+{ op_6401_0_comp_ff, 25601, 0x00000001 }, /* Bcc */
+{ op_64ff_0_comp_ff, 25855, 0x00000003 }, /* Bcc */
+{ op_6500_0_comp_ff, 25856, 0x00000003 }, /* Bcc */
+{ op_6501_0_comp_ff, 25857, 0x00000001 }, /* Bcc */
+{ op_65ff_0_comp_ff, 26111, 0x00000003 }, /* Bcc */
+{ op_6600_0_comp_ff, 26112, 0x00000003 }, /* Bcc */
+{ op_6601_0_comp_ff, 26113, 0x00000001 }, /* Bcc */
+{ op_66ff_0_comp_ff, 26367, 0x00000003 }, /* Bcc */
+{ op_6700_0_comp_ff, 26368, 0x00000003 }, /* Bcc */
+{ op_6701_0_comp_ff, 26369, 0x00000001 }, /* Bcc */
+{ op_67ff_0_comp_ff, 26623, 0x00000003 }, /* Bcc */
+{ op_6800_0_comp_ff, 26624, 0x00000003 }, /* Bcc */
+{ op_6801_0_comp_ff, 26625, 0x00000001 }, /* Bcc */
+{ op_68ff_0_comp_ff, 26879, 0x00000003 }, /* Bcc */
+{ op_6900_0_comp_ff, 26880, 0x00000003 }, /* Bcc */
+{ op_6901_0_comp_ff, 26881, 0x00000001 }, /* Bcc */
+{ op_69ff_0_comp_ff, 27135, 0x00000003 }, /* Bcc */
+{ op_6a00_0_comp_ff, 27136, 0x00000003 }, /* Bcc */
+{ op_6a01_0_comp_ff, 27137, 0x00000001 }, /* Bcc */
+{ op_6aff_0_comp_ff, 27391, 0x00000003 }, /* Bcc */
+{ op_6b00_0_comp_ff, 27392, 0x00000003 }, /* Bcc */
+{ op_6b01_0_comp_ff, 27393, 0x00000001 }, /* Bcc */
+{ op_6bff_0_comp_ff, 27647, 0x00000003 }, /* Bcc */
+{ op_6c00_0_comp_ff, 27648, 0x00000003 }, /* Bcc */
+{ op_6c01_0_comp_ff, 27649, 0x00000001 }, /* Bcc */
+{ op_6cff_0_comp_ff, 27903, 0x00000003 }, /* Bcc */
+{ op_6d00_0_comp_ff, 27904, 0x00000003 }, /* Bcc */
+{ op_6d01_0_comp_ff, 27905, 0x00000001 }, /* Bcc */
+{ op_6dff_0_comp_ff, 28159, 0x00000003 }, /* Bcc */
+{ op_6e00_0_comp_ff, 28160, 0x00000003 }, /* Bcc */
+{ op_6e01_0_comp_ff, 28161, 0x00000001 }, /* Bcc */
+{ op_6eff_0_comp_ff, 28415, 0x00000003 }, /* Bcc */
+{ op_6f00_0_comp_ff, 28416, 0x00000003 }, /* Bcc */
+{ op_6f01_0_comp_ff, 28417, 0x00000001 }, /* Bcc */
+{ op_6fff_0_comp_ff, 28671, 0x00000003 }, /* Bcc */
+{ op_7000_0_comp_ff, 28672, 0x00000000 }, /* MOVE */
+{ op_8000_0_comp_ff, 32768, 0x00000000 }, /* OR */
+{ op_8010_0_comp_ff, 32784, 0x00000000 }, /* OR */
+{ op_8018_0_comp_ff, 32792, 0x00000000 }, /* OR */
+{ op_8020_0_comp_ff, 32800, 0x00000000 }, /* OR */
+{ op_8028_0_comp_ff, 32808, 0x00000002 }, /* OR */
+{ op_8030_0_comp_ff, 32816, 0x00000002 }, /* OR */
+{ op_8038_0_comp_ff, 32824, 0x00000002 }, /* OR */
+{ op_8039_0_comp_ff, 32825, 0x00000002 }, /* OR */
+{ op_803a_0_comp_ff, 32826, 0x00000002 }, /* OR */
+{ op_803b_0_comp_ff, 32827, 0x00000002 }, /* OR */
+{ op_803c_0_comp_ff, 32828, 0x00000002 }, /* OR */
+{ op_8040_0_comp_ff, 32832, 0x00000000 }, /* OR */
+{ op_8050_0_comp_ff, 32848, 0x00000000 }, /* OR */
+{ op_8058_0_comp_ff, 32856, 0x00000000 }, /* OR */
+{ op_8060_0_comp_ff, 32864, 0x00000000 }, /* OR */
+{ op_8068_0_comp_ff, 32872, 0x00000002 }, /* OR */
+{ op_8070_0_comp_ff, 32880, 0x00000002 }, /* OR */
+{ op_8078_0_comp_ff, 32888, 0x00000002 }, /* OR */
+{ op_8079_0_comp_ff, 32889, 0x00000002 }, /* OR */
+{ op_807a_0_comp_ff, 32890, 0x00000002 }, /* OR */
+{ op_807b_0_comp_ff, 32891, 0x00000002 }, /* OR */
+{ op_807c_0_comp_ff, 32892, 0x00000002 }, /* OR */
+{ op_8080_0_comp_ff, 32896, 0x00000000 }, /* OR */
+{ op_8090_0_comp_ff, 32912, 0x00000000 }, /* OR */
+{ op_8098_0_comp_ff, 32920, 0x00000000 }, /* OR */
+{ op_80a0_0_comp_ff, 32928, 0x00000000 }, /* OR */
+{ op_80a8_0_comp_ff, 32936, 0x00000002 }, /* OR */
+{ op_80b0_0_comp_ff, 32944, 0x00000002 }, /* OR */
+{ op_80b8_0_comp_ff, 32952, 0x00000002 }, /* OR */
+{ op_80b9_0_comp_ff, 32953, 0x00000002 }, /* OR */
+{ op_80ba_0_comp_ff, 32954, 0x00000002 }, /* OR */
+{ op_80bb_0_comp_ff, 32955, 0x00000002 }, /* OR */
+{ op_80bc_0_comp_ff, 32956, 0x00000002 }, /* OR */
+{ op_80c0_0_comp_ff, 32960, 0x00000000 }, /* DIVU */
+{ op_80d0_0_comp_ff, 32976, 0x00000000 }, /* DIVU */
+{ op_80d8_0_comp_ff, 32984, 0x00000000 }, /* DIVU */
+{ op_80e0_0_comp_ff, 32992, 0x00000000 }, /* DIVU */
+{ op_80e8_0_comp_ff, 33000, 0x00000002 }, /* DIVU */
+{ op_80f0_0_comp_ff, 33008, 0x00000002 }, /* DIVU */
+{ op_80f8_0_comp_ff, 33016, 0x00000002 }, /* DIVU */
+{ op_80f9_0_comp_ff, 33017, 0x00000002 }, /* DIVU */
+{ op_80fa_0_comp_ff, 33018, 0x00000002 }, /* DIVU */
+{ op_80fb_0_comp_ff, 33019, 0x00000002 }, /* DIVU */
+{ op_80fc_0_comp_ff, 33020, 0x00000002 }, /* DIVU */
+{ NULL, 33024, 0x00000000 }, /* SBCD */
+{ NULL, 33032, 0x00000000 }, /* SBCD */
+{ op_8110_0_comp_ff, 33040, 0x00000000 }, /* OR */
+{ op_8118_0_comp_ff, 33048, 0x00000000 }, /* OR */
+{ op_8120_0_comp_ff, 33056, 0x00000000 }, /* OR */
+{ op_8128_0_comp_ff, 33064, 0x00000002 }, /* OR */
+{ op_8130_0_comp_ff, 33072, 0x00000002 }, /* OR */
+{ op_8138_0_comp_ff, 33080, 0x00000002 }, /* OR */
+{ op_8139_0_comp_ff, 33081, 0x00000002 }, /* OR */
+{ NULL, 33088, 0x00000000 }, /* PACK */
+{ NULL, 33096, 0x00000000 }, /* PACK */
+{ op_8150_0_comp_ff, 33104, 0x00000000 }, /* OR */
+{ op_8158_0_comp_ff, 33112, 0x00000000 }, /* OR */
+{ op_8160_0_comp_ff, 33120, 0x00000000 }, /* OR */
+{ op_8168_0_comp_ff, 33128, 0x00000002 }, /* OR */
+{ op_8170_0_comp_ff, 33136, 0x00000002 }, /* OR */
+{ op_8178_0_comp_ff, 33144, 0x00000002 }, /* OR */
+{ op_8179_0_comp_ff, 33145, 0x00000002 }, /* OR */
+{ NULL, 33152, 0x00000000 }, /* UNPK */
+{ NULL, 33160, 0x00000000 }, /* UNPK */
+{ op_8190_0_comp_ff, 33168, 0x00000000 }, /* OR */
+{ op_8198_0_comp_ff, 33176, 0x00000000 }, /* OR */
+{ op_81a0_0_comp_ff, 33184, 0x00000000 }, /* OR */
+{ op_81a8_0_comp_ff, 33192, 0x00000002 }, /* OR */
+{ op_81b0_0_comp_ff, 33200, 0x00000002 }, /* OR */
+{ op_81b8_0_comp_ff, 33208, 0x00000002 }, /* OR */
+{ op_81b9_0_comp_ff, 33209, 0x00000002 }, /* OR */
+{ op_81c0_0_comp_ff, 33216, 0x00000000 }, /* DIVS */
+{ op_81d0_0_comp_ff, 33232, 0x00000000 }, /* DIVS */
+{ op_81d8_0_comp_ff, 33240, 0x00000000 }, /* DIVS */
+{ op_81e0_0_comp_ff, 33248, 0x00000000 }, /* DIVS */
+{ op_81e8_0_comp_ff, 33256, 0x00000002 }, /* DIVS */
+{ op_81f0_0_comp_ff, 33264, 0x00000002 }, /* DIVS */
+{ op_81f8_0_comp_ff, 33272, 0x00000002 }, /* DIVS */
+{ op_81f9_0_comp_ff, 33273, 0x00000002 }, /* DIVS */
+{ op_81fa_0_comp_ff, 33274, 0x00000002 }, /* DIVS */
+{ op_81fb_0_comp_ff, 33275, 0x00000002 }, /* DIVS */
+{ op_81fc_0_comp_ff, 33276, 0x00000002 }, /* DIVS */
+{ op_9000_0_comp_ff, 36864, 0x00000000 }, /* SUB */
+{ op_9010_0_comp_ff, 36880, 0x00000000 }, /* SUB */
+{ op_9018_0_comp_ff, 36888, 0x00000000 }, /* SUB */
+{ op_9020_0_comp_ff, 36896, 0x00000000 }, /* SUB */
+{ op_9028_0_comp_ff, 36904, 0x00000002 }, /* SUB */
+{ op_9030_0_comp_ff, 36912, 0x00000002 }, /* SUB */
+{ op_9038_0_comp_ff, 36920, 0x00000002 }, /* SUB */
+{ op_9039_0_comp_ff, 36921, 0x00000002 }, /* SUB */
+{ op_903a_0_comp_ff, 36922, 0x00000002 }, /* SUB */
+{ op_903b_0_comp_ff, 36923, 0x00000002 }, /* SUB */
+{ op_903c_0_comp_ff, 36924, 0x00000002 }, /* SUB */
+{ op_9040_0_comp_ff, 36928, 0x00000000 }, /* SUB */
+{ op_9048_0_comp_ff, 36936, 0x00000000 }, /* SUB */
+{ op_9050_0_comp_ff, 36944, 0x00000000 }, /* SUB */
+{ op_9058_0_comp_ff, 36952, 0x00000000 }, /* SUB */
+{ op_9060_0_comp_ff, 36960, 0x00000000 }, /* SUB */
+{ op_9068_0_comp_ff, 36968, 0x00000002 }, /* SUB */
+{ op_9070_0_comp_ff, 36976, 0x00000002 }, /* SUB */
+{ op_9078_0_comp_ff, 36984, 0x00000002 }, /* SUB */
+{ op_9079_0_comp_ff, 36985, 0x00000002 }, /* SUB */
+{ op_907a_0_comp_ff, 36986, 0x00000002 }, /* SUB */
+{ op_907b_0_comp_ff, 36987, 0x00000002 }, /* SUB */
+{ op_907c_0_comp_ff, 36988, 0x00000002 }, /* SUB */
+{ op_9080_0_comp_ff, 36992, 0x00000000 }, /* SUB */
+{ op_9088_0_comp_ff, 37000, 0x00000000 }, /* SUB */
+{ op_9090_0_comp_ff, 37008, 0x00000000 }, /* SUB */
+{ op_9098_0_comp_ff, 37016, 0x00000000 }, /* SUB */
+{ op_90a0_0_comp_ff, 37024, 0x00000000 }, /* SUB */
+{ op_90a8_0_comp_ff, 37032, 0x00000002 }, /* SUB */
+{ op_90b0_0_comp_ff, 37040, 0x00000002 }, /* SUB */
+{ op_90b8_0_comp_ff, 37048, 0x00000002 }, /* SUB */
+{ op_90b9_0_comp_ff, 37049, 0x00000002 }, /* SUB */
+{ op_90ba_0_comp_ff, 37050, 0x00000002 }, /* SUB */
+{ op_90bb_0_comp_ff, 37051, 0x00000002 }, /* SUB */
+{ op_90bc_0_comp_ff, 37052, 0x00000002 }, /* SUB */
+{ op_90c0_0_comp_ff, 37056, 0x00000000 }, /* SUBA */
+{ op_90c8_0_comp_ff, 37064, 0x00000000 }, /* SUBA */
+{ op_90d0_0_comp_ff, 37072, 0x00000000 }, /* SUBA */
+{ op_90d8_0_comp_ff, 37080, 0x00000000 }, /* SUBA */
+{ op_90e0_0_comp_ff, 37088, 0x00000000 }, /* SUBA */
+{ op_90e8_0_comp_ff, 37096, 0x00000002 }, /* SUBA */
+{ op_90f0_0_comp_ff, 37104, 0x00000002 }, /* SUBA */
+{ op_90f8_0_comp_ff, 37112, 0x00000002 }, /* SUBA */
+{ op_90f9_0_comp_ff, 37113, 0x00000002 }, /* SUBA */
+{ op_90fa_0_comp_ff, 37114, 0x00000002 }, /* SUBA */
+{ op_90fb_0_comp_ff, 37115, 0x00000002 }, /* SUBA */
+{ op_90fc_0_comp_ff, 37116, 0x00000002 }, /* SUBA */
+{ op_9100_0_comp_ff, 37120, 0x00000008 }, /* SUBX */
+{ op_9108_0_comp_ff, 37128, 0x00000008 }, /* SUBX */
+{ op_9110_0_comp_ff, 37136, 0x00000000 }, /* SUB */
+{ op_9118_0_comp_ff, 37144, 0x00000000 }, /* SUB */
+{ op_9120_0_comp_ff, 37152, 0x00000000 }, /* SUB */
+{ op_9128_0_comp_ff, 37160, 0x00000002 }, /* SUB */
+{ op_9130_0_comp_ff, 37168, 0x00000002 }, /* SUB */
+{ op_9138_0_comp_ff, 37176, 0x00000002 }, /* SUB */
+{ op_9139_0_comp_ff, 37177, 0x00000002 }, /* SUB */
+{ op_9140_0_comp_ff, 37184, 0x00000008 }, /* SUBX */
+{ op_9148_0_comp_ff, 37192, 0x00000008 }, /* SUBX */
+{ op_9150_0_comp_ff, 37200, 0x00000000 }, /* SUB */
+{ op_9158_0_comp_ff, 37208, 0x00000000 }, /* SUB */
+{ op_9160_0_comp_ff, 37216, 0x00000000 }, /* SUB */
+{ op_9168_0_comp_ff, 37224, 0x00000002 }, /* SUB */
+{ op_9170_0_comp_ff, 37232, 0x00000002 }, /* SUB */
+{ op_9178_0_comp_ff, 37240, 0x00000002 }, /* SUB */
+{ op_9179_0_comp_ff, 37241, 0x00000002 }, /* SUB */
+{ op_9180_0_comp_ff, 37248, 0x00000008 }, /* SUBX */
+{ op_9188_0_comp_ff, 37256, 0x00000008 }, /* SUBX */
+{ op_9190_0_comp_ff, 37264, 0x00000000 }, /* SUB */
+{ op_9198_0_comp_ff, 37272, 0x00000000 }, /* SUB */
+{ op_91a0_0_comp_ff, 37280, 0x00000000 }, /* SUB */
+{ op_91a8_0_comp_ff, 37288, 0x00000002 }, /* SUB */
+{ op_91b0_0_comp_ff, 37296, 0x00000002 }, /* SUB */
+{ op_91b8_0_comp_ff, 37304, 0x00000002 }, /* SUB */
+{ op_91b9_0_comp_ff, 37305, 0x00000002 }, /* SUB */
+{ op_91c0_0_comp_ff, 37312, 0x00000000 }, /* SUBA */
+{ op_91c8_0_comp_ff, 37320, 0x00000000 }, /* SUBA */
+{ op_91d0_0_comp_ff, 37328, 0x00000000 }, /* SUBA */
+{ op_91d8_0_comp_ff, 37336, 0x00000000 }, /* SUBA */
+{ op_91e0_0_comp_ff, 37344, 0x00000000 }, /* SUBA */
+{ op_91e8_0_comp_ff, 37352, 0x00000002 }, /* SUBA */
+{ op_91f0_0_comp_ff, 37360, 0x00000002 }, /* SUBA */
+{ op_91f8_0_comp_ff, 37368, 0x00000002 }, /* SUBA */
+{ op_91f9_0_comp_ff, 37369, 0x00000002 }, /* SUBA */
+{ op_91fa_0_comp_ff, 37370, 0x00000002 }, /* SUBA */
+{ op_91fb_0_comp_ff, 37371, 0x00000002 }, /* SUBA */
+{ op_91fc_0_comp_ff, 37372, 0x00000002 }, /* SUBA */
+{ op_b000_0_comp_ff, 45056, 0x00000000 }, /* CMP */
+{ op_b010_0_comp_ff, 45072, 0x00000000 }, /* CMP */
+{ op_b018_0_comp_ff, 45080, 0x00000000 }, /* CMP */
+{ op_b020_0_comp_ff, 45088, 0x00000000 }, /* CMP */
+{ op_b028_0_comp_ff, 45096, 0x00000002 }, /* CMP */
+{ op_b030_0_comp_ff, 45104, 0x00000002 }, /* CMP */
+{ op_b038_0_comp_ff, 45112, 0x00000002 }, /* CMP */
+{ op_b039_0_comp_ff, 45113, 0x00000002 }, /* CMP */
+{ op_b03a_0_comp_ff, 45114, 0x00000002 }, /* CMP */
+{ op_b03b_0_comp_ff, 45115, 0x00000002 }, /* CMP */
+{ op_b03c_0_comp_ff, 45116, 0x00000002 }, /* CMP */
+{ op_b040_0_comp_ff, 45120, 0x00000000 }, /* CMP */
+{ op_b048_0_comp_ff, 45128, 0x00000000 }, /* CMP */
+{ op_b050_0_comp_ff, 45136, 0x00000000 }, /* CMP */
+{ op_b058_0_comp_ff, 45144, 0x00000000 }, /* CMP */
+{ op_b060_0_comp_ff, 45152, 0x00000000 }, /* CMP */
+{ op_b068_0_comp_ff, 45160, 0x00000002 }, /* CMP */
+{ op_b070_0_comp_ff, 45168, 0x00000002 }, /* CMP */
+{ op_b078_0_comp_ff, 45176, 0x00000002 }, /* CMP */
+{ op_b079_0_comp_ff, 45177, 0x00000002 }, /* CMP */
+{ op_b07a_0_comp_ff, 45178, 0x00000002 }, /* CMP */
+{ op_b07b_0_comp_ff, 45179, 0x00000002 }, /* CMP */
+{ op_b07c_0_comp_ff, 45180, 0x00000002 }, /* CMP */
+{ op_b080_0_comp_ff, 45184, 0x00000000 }, /* CMP */
+{ op_b088_0_comp_ff, 45192, 0x00000000 }, /* CMP */
+{ op_b090_0_comp_ff, 45200, 0x00000000 }, /* CMP */
+{ op_b098_0_comp_ff, 45208, 0x00000000 }, /* CMP */
+{ op_b0a0_0_comp_ff, 45216, 0x00000000 }, /* CMP */
+{ op_b0a8_0_comp_ff, 45224, 0x00000002 }, /* CMP */
+{ op_b0b0_0_comp_ff, 45232, 0x00000002 }, /* CMP */
+{ op_b0b8_0_comp_ff, 45240, 0x00000002 }, /* CMP */
+{ op_b0b9_0_comp_ff, 45241, 0x00000002 }, /* CMP */
+{ op_b0ba_0_comp_ff, 45242, 0x00000002 }, /* CMP */
+{ op_b0bb_0_comp_ff, 45243, 0x00000002 }, /* CMP */
+{ op_b0bc_0_comp_ff, 45244, 0x00000002 }, /* CMP */
+{ op_b0c0_0_comp_ff, 45248, 0x00000000 }, /* CMPA */
+{ op_b0c8_0_comp_ff, 45256, 0x00000000 }, /* CMPA */
+{ op_b0d0_0_comp_ff, 45264, 0x00000000 }, /* CMPA */
+{ op_b0d8_0_comp_ff, 45272, 0x00000000 }, /* CMPA */
+{ op_b0e0_0_comp_ff, 45280, 0x00000000 }, /* CMPA */
+{ op_b0e8_0_comp_ff, 45288, 0x00000002 }, /* CMPA */
+{ op_b0f0_0_comp_ff, 45296, 0x00000002 }, /* CMPA */
+{ op_b0f8_0_comp_ff, 45304, 0x00000002 }, /* CMPA */
+{ op_b0f9_0_comp_ff, 45305, 0x00000002 }, /* CMPA */
+{ op_b0fa_0_comp_ff, 45306, 0x00000002 }, /* CMPA */
+{ op_b0fb_0_comp_ff, 45307, 0x00000002 }, /* CMPA */
+{ op_b0fc_0_comp_ff, 45308, 0x00000002 }, /* CMPA */
+{ op_b100_0_comp_ff, 45312, 0x00000000 }, /* EOR */
+{ op_b108_0_comp_ff, 45320, 0x00000000 }, /* CMPM */
+{ op_b110_0_comp_ff, 45328, 0x00000000 }, /* EOR */
+{ op_b118_0_comp_ff, 45336, 0x00000000 }, /* EOR */
+{ op_b120_0_comp_ff, 45344, 0x00000000 }, /* EOR */
+{ op_b128_0_comp_ff, 45352, 0x00000002 }, /* EOR */
+{ op_b130_0_comp_ff, 45360, 0x00000002 }, /* EOR */
+{ op_b138_0_comp_ff, 45368, 0x00000002 }, /* EOR */
+{ op_b139_0_comp_ff, 45369, 0x00000002 }, /* EOR */
+{ op_b140_0_comp_ff, 45376, 0x00000000 }, /* EOR */
+{ op_b148_0_comp_ff, 45384, 0x00000000 }, /* CMPM */
+{ op_b150_0_comp_ff, 45392, 0x00000000 }, /* EOR */
+{ op_b158_0_comp_ff, 45400, 0x00000000 }, /* EOR */
+{ op_b160_0_comp_ff, 45408, 0x00000000 }, /* EOR */
+{ op_b168_0_comp_ff, 45416, 0x00000002 }, /* EOR */
+{ op_b170_0_comp_ff, 45424, 0x00000002 }, /* EOR */
+{ op_b178_0_comp_ff, 45432, 0x00000002 }, /* EOR */
+{ op_b179_0_comp_ff, 45433, 0x00000002 }, /* EOR */
+{ op_b180_0_comp_ff, 45440, 0x00000000 }, /* EOR */
+{ op_b188_0_comp_ff, 45448, 0x00000000 }, /* CMPM */
+{ op_b190_0_comp_ff, 45456, 0x00000000 }, /* EOR */
+{ op_b198_0_comp_ff, 45464, 0x00000000 }, /* EOR */
+{ op_b1a0_0_comp_ff, 45472, 0x00000000 }, /* EOR */
+{ op_b1a8_0_comp_ff, 45480, 0x00000002 }, /* EOR */
+{ op_b1b0_0_comp_ff, 45488, 0x00000002 }, /* EOR */
+{ op_b1b8_0_comp_ff, 45496, 0x00000002 }, /* EOR */
+{ op_b1b9_0_comp_ff, 45497, 0x00000002 }, /* EOR */
+{ op_b1c0_0_comp_ff, 45504, 0x00000000 }, /* CMPA */
+{ op_b1c8_0_comp_ff, 45512, 0x00000000 }, /* CMPA */
+{ op_b1d0_0_comp_ff, 45520, 0x00000000 }, /* CMPA */
+{ op_b1d8_0_comp_ff, 45528, 0x00000000 }, /* CMPA */
+{ op_b1e0_0_comp_ff, 45536, 0x00000000 }, /* CMPA */
+{ op_b1e8_0_comp_ff, 45544, 0x00000002 }, /* CMPA */
+{ op_b1f0_0_comp_ff, 45552, 0x00000002 }, /* CMPA */
+{ op_b1f8_0_comp_ff, 45560, 0x00000002 }, /* CMPA */
+{ op_b1f9_0_comp_ff, 45561, 0x00000002 }, /* CMPA */
+{ op_b1fa_0_comp_ff, 45562, 0x00000002 }, /* CMPA */
+{ op_b1fb_0_comp_ff, 45563, 0x00000002 }, /* CMPA */
+{ op_b1fc_0_comp_ff, 45564, 0x00000002 }, /* CMPA */
+{ op_c000_0_comp_ff, 49152, 0x00000000 }, /* AND */
+{ op_c010_0_comp_ff, 49168, 0x00000000 }, /* AND */
+{ op_c018_0_comp_ff, 49176, 0x00000000 }, /* AND */
+{ op_c020_0_comp_ff, 49184, 0x00000000 }, /* AND */
+{ op_c028_0_comp_ff, 49192, 0x00000002 }, /* AND */
+{ op_c030_0_comp_ff, 49200, 0x00000002 }, /* AND */
+{ op_c038_0_comp_ff, 49208, 0x00000002 }, /* AND */
+{ op_c039_0_comp_ff, 49209, 0x00000002 }, /* AND */
+{ op_c03a_0_comp_ff, 49210, 0x00000002 }, /* AND */
+{ op_c03b_0_comp_ff, 49211, 0x00000002 }, /* AND */
+{ op_c03c_0_comp_ff, 49212, 0x00000002 }, /* AND */
+{ op_c040_0_comp_ff, 49216, 0x00000000 }, /* AND */
+{ op_c050_0_comp_ff, 49232, 0x00000000 }, /* AND */
+{ op_c058_0_comp_ff, 49240, 0x00000000 }, /* AND */
+{ op_c060_0_comp_ff, 49248, 0x00000000 }, /* AND */
+{ op_c068_0_comp_ff, 49256, 0x00000002 }, /* AND */
+{ op_c070_0_comp_ff, 49264, 0x00000002 }, /* AND */
+{ op_c078_0_comp_ff, 49272, 0x00000002 }, /* AND */
+{ op_c079_0_comp_ff, 49273, 0x00000002 }, /* AND */
+{ op_c07a_0_comp_ff, 49274, 0x00000002 }, /* AND */
+{ op_c07b_0_comp_ff, 49275, 0x00000002 }, /* AND */
+{ op_c07c_0_comp_ff, 49276, 0x00000002 }, /* AND */
+{ op_c080_0_comp_ff, 49280, 0x00000000 }, /* AND */
+{ op_c090_0_comp_ff, 49296, 0x00000000 }, /* AND */
+{ op_c098_0_comp_ff, 49304, 0x00000000 }, /* AND */
+{ op_c0a0_0_comp_ff, 49312, 0x00000000 }, /* AND */
+{ op_c0a8_0_comp_ff, 49320, 0x00000002 }, /* AND */
+{ op_c0b0_0_comp_ff, 49328, 0x00000002 }, /* AND */
+{ op_c0b8_0_comp_ff, 49336, 0x00000002 }, /* AND */
+{ op_c0b9_0_comp_ff, 49337, 0x00000002 }, /* AND */
+{ op_c0ba_0_comp_ff, 49338, 0x00000002 }, /* AND */
+{ op_c0bb_0_comp_ff, 49339, 0x00000002 }, /* AND */
+{ op_c0bc_0_comp_ff, 49340, 0x00000002 }, /* AND */
+{ op_c0c0_0_comp_ff, 49344, 0x00000000 }, /* MULU */
+{ op_c0d0_0_comp_ff, 49360, 0x00000000 }, /* MULU */
+{ op_c0d8_0_comp_ff, 49368, 0x00000000 }, /* MULU */
+{ op_c0e0_0_comp_ff, 49376, 0x00000000 }, /* MULU */
+{ op_c0e8_0_comp_ff, 49384, 0x00000002 }, /* MULU */
+{ op_c0f0_0_comp_ff, 49392, 0x00000002 }, /* MULU */
+{ op_c0f8_0_comp_ff, 49400, 0x00000002 }, /* MULU */
+{ op_c0f9_0_comp_ff, 49401, 0x00000002 }, /* MULU */
+{ op_c0fa_0_comp_ff, 49402, 0x00000002 }, /* MULU */
+{ op_c0fb_0_comp_ff, 49403, 0x00000002 }, /* MULU */
+{ op_c0fc_0_comp_ff, 49404, 0x00000002 }, /* MULU */
+{ NULL, 49408, 0x00000000 }, /* ABCD */
+{ NULL, 49416, 0x00000000 }, /* ABCD */
+{ op_c110_0_comp_ff, 49424, 0x00000000 }, /* AND */
+{ op_c118_0_comp_ff, 49432, 0x00000000 }, /* AND */
+{ op_c120_0_comp_ff, 49440, 0x00000000 }, /* AND */
+{ op_c128_0_comp_ff, 49448, 0x00000002 }, /* AND */
+{ op_c130_0_comp_ff, 49456, 0x00000002 }, /* AND */
+{ op_c138_0_comp_ff, 49464, 0x00000002 }, /* AND */
+{ op_c139_0_comp_ff, 49465, 0x00000002 }, /* AND */
+{ op_c140_0_comp_ff, 49472, 0x00000000 }, /* EXG */
+{ op_c148_0_comp_ff, 49480, 0x00000000 }, /* EXG */
+{ op_c150_0_comp_ff, 49488, 0x00000000 }, /* AND */
+{ op_c158_0_comp_ff, 49496, 0x00000000 }, /* AND */
+{ op_c160_0_comp_ff, 49504, 0x00000000 }, /* AND */
+{ op_c168_0_comp_ff, 49512, 0x00000002 }, /* AND */
+{ op_c170_0_comp_ff, 49520, 0x00000002 }, /* AND */
+{ op_c178_0_comp_ff, 49528, 0x00000002 }, /* AND */
+{ op_c179_0_comp_ff, 49529, 0x00000002 }, /* AND */
+{ op_c188_0_comp_ff, 49544, 0x00000000 }, /* EXG */
+{ op_c190_0_comp_ff, 49552, 0x00000000 }, /* AND */
+{ op_c198_0_comp_ff, 49560, 0x00000000 }, /* AND */
+{ op_c1a0_0_comp_ff, 49568, 0x00000000 }, /* AND */
+{ op_c1a8_0_comp_ff, 49576, 0x00000002 }, /* AND */
+{ op_c1b0_0_comp_ff, 49584, 0x00000002 }, /* AND */
+{ op_c1b8_0_comp_ff, 49592, 0x00000002 }, /* AND */
+{ op_c1b9_0_comp_ff, 49593, 0x00000002 }, /* AND */
+{ op_c1c0_0_comp_ff, 49600, 0x00000000 }, /* MULS */
+{ op_c1d0_0_comp_ff, 49616, 0x00000000 }, /* MULS */
+{ op_c1d8_0_comp_ff, 49624, 0x00000000 }, /* MULS */
+{ op_c1e0_0_comp_ff, 49632, 0x00000000 }, /* MULS */
+{ op_c1e8_0_comp_ff, 49640, 0x00000002 }, /* MULS */
+{ op_c1f0_0_comp_ff, 49648, 0x00000002 }, /* MULS */
+{ op_c1f8_0_comp_ff, 49656, 0x00000002 }, /* MULS */
+{ op_c1f9_0_comp_ff, 49657, 0x00000002 }, /* MULS */
+{ op_c1fa_0_comp_ff, 49658, 0x00000002 }, /* MULS */
+{ op_c1fb_0_comp_ff, 49659, 0x00000002 }, /* MULS */
+{ op_c1fc_0_comp_ff, 49660, 0x00000002 }, /* MULS */
+{ op_d000_0_comp_ff, 53248, 0x00000000 }, /* ADD */
+{ op_d010_0_comp_ff, 53264, 0x00000000 }, /* ADD */
+{ op_d018_0_comp_ff, 53272, 0x00000000 }, /* ADD */
+{ op_d020_0_comp_ff, 53280, 0x00000000 }, /* ADD */
+{ op_d028_0_comp_ff, 53288, 0x00000002 }, /* ADD */
+{ op_d030_0_comp_ff, 53296, 0x00000002 }, /* ADD */
+{ op_d038_0_comp_ff, 53304, 0x00000002 }, /* ADD */
+{ op_d039_0_comp_ff, 53305, 0x00000002 }, /* ADD */
+{ op_d03a_0_comp_ff, 53306, 0x00000002 }, /* ADD */
+{ op_d03b_0_comp_ff, 53307, 0x00000002 }, /* ADD */
+{ op_d03c_0_comp_ff, 53308, 0x00000002 }, /* ADD */
+{ op_d040_0_comp_ff, 53312, 0x00000000 }, /* ADD */
+{ op_d048_0_comp_ff, 53320, 0x00000000 }, /* ADD */
+{ op_d050_0_comp_ff, 53328, 0x00000000 }, /* ADD */
+{ op_d058_0_comp_ff, 53336, 0x00000000 }, /* ADD */
+{ op_d060_0_comp_ff, 53344, 0x00000000 }, /* ADD */
+{ op_d068_0_comp_ff, 53352, 0x00000002 }, /* ADD */
+{ op_d070_0_comp_ff, 53360, 0x00000002 }, /* ADD */
+{ op_d078_0_comp_ff, 53368, 0x00000002 }, /* ADD */
+{ op_d079_0_comp_ff, 53369, 0x00000002 }, /* ADD */
+{ op_d07a_0_comp_ff, 53370, 0x00000002 }, /* ADD */
+{ op_d07b_0_comp_ff, 53371, 0x00000002 }, /* ADD */
+{ op_d07c_0_comp_ff, 53372, 0x00000002 }, /* ADD */
+{ op_d080_0_comp_ff, 53376, 0x00000000 }, /* ADD */
+{ op_d088_0_comp_ff, 53384, 0x00000000 }, /* ADD */
+{ op_d090_0_comp_ff, 53392, 0x00000000 }, /* ADD */
+{ op_d098_0_comp_ff, 53400, 0x00000000 }, /* ADD */
+{ op_d0a0_0_comp_ff, 53408, 0x00000000 }, /* ADD */
+{ op_d0a8_0_comp_ff, 53416, 0x00000002 }, /* ADD */
+{ op_d0b0_0_comp_ff, 53424, 0x00000002 }, /* ADD */
+{ op_d0b8_0_comp_ff, 53432, 0x00000002 }, /* ADD */
+{ op_d0b9_0_comp_ff, 53433, 0x00000002 }, /* ADD */
+{ op_d0ba_0_comp_ff, 53434, 0x00000002 }, /* ADD */
+{ op_d0bb_0_comp_ff, 53435, 0x00000002 }, /* ADD */
+{ op_d0bc_0_comp_ff, 53436, 0x00000002 }, /* ADD */
+{ op_d0c0_0_comp_ff, 53440, 0x00000000 }, /* ADDA */
+{ op_d0c8_0_comp_ff, 53448, 0x00000000 }, /* ADDA */
+{ op_d0d0_0_comp_ff, 53456, 0x00000000 }, /* ADDA */
+{ op_d0d8_0_comp_ff, 53464, 0x00000000 }, /* ADDA */
+{ op_d0e0_0_comp_ff, 53472, 0x00000000 }, /* ADDA */
+{ op_d0e8_0_comp_ff, 53480, 0x00000002 }, /* ADDA */
+{ op_d0f0_0_comp_ff, 53488, 0x00000002 }, /* ADDA */
+{ op_d0f8_0_comp_ff, 53496, 0x00000002 }, /* ADDA */
+{ op_d0f9_0_comp_ff, 53497, 0x00000002 }, /* ADDA */
+{ op_d0fa_0_comp_ff, 53498, 0x00000002 }, /* ADDA */
+{ op_d0fb_0_comp_ff, 53499, 0x00000002 }, /* ADDA */
+{ op_d0fc_0_comp_ff, 53500, 0x00000002 }, /* ADDA */
+{ op_d100_0_comp_ff, 53504, 0x00000008 }, /* ADDX */
+{ op_d108_0_comp_ff, 53512, 0x00000008 }, /* ADDX */
+{ op_d110_0_comp_ff, 53520, 0x00000000 }, /* ADD */
+{ op_d118_0_comp_ff, 53528, 0x00000000 }, /* ADD */
+{ op_d120_0_comp_ff, 53536, 0x00000000 }, /* ADD */
+{ op_d128_0_comp_ff, 53544, 0x00000002 }, /* ADD */
+{ op_d130_0_comp_ff, 53552, 0x00000002 }, /* ADD */
+{ op_d138_0_comp_ff, 53560, 0x00000002 }, /* ADD */
+{ op_d139_0_comp_ff, 53561, 0x00000002 }, /* ADD */
+{ op_d140_0_comp_ff, 53568, 0x00000008 }, /* ADDX */
+{ op_d148_0_comp_ff, 53576, 0x00000008 }, /* ADDX */
+{ op_d150_0_comp_ff, 53584, 0x00000000 }, /* ADD */
+{ op_d158_0_comp_ff, 53592, 0x00000000 }, /* ADD */
+{ op_d160_0_comp_ff, 53600, 0x00000000 }, /* ADD */
+{ op_d168_0_comp_ff, 53608, 0x00000002 }, /* ADD */
+{ op_d170_0_comp_ff, 53616, 0x00000002 }, /* ADD */
+{ op_d178_0_comp_ff, 53624, 0x00000002 }, /* ADD */
+{ op_d179_0_comp_ff, 53625, 0x00000002 }, /* ADD */
+{ op_d180_0_comp_ff, 53632, 0x00000008 }, /* ADDX */
+{ op_d188_0_comp_ff, 53640, 0x00000008 }, /* ADDX */
+{ op_d190_0_comp_ff, 53648, 0x00000000 }, /* ADD */
+{ op_d198_0_comp_ff, 53656, 0x00000000 }, /* ADD */
+{ op_d1a0_0_comp_ff, 53664, 0x00000000 }, /* ADD */
+{ op_d1a8_0_comp_ff, 53672, 0x00000002 }, /* ADD */
+{ op_d1b0_0_comp_ff, 53680, 0x00000002 }, /* ADD */
+{ op_d1b8_0_comp_ff, 53688, 0x00000002 }, /* ADD */
+{ op_d1b9_0_comp_ff, 53689, 0x00000002 }, /* ADD */
+{ op_d1c0_0_comp_ff, 53696, 0x00000000 }, /* ADDA */
+{ op_d1c8_0_comp_ff, 53704, 0x00000000 }, /* ADDA */
+{ op_d1d0_0_comp_ff, 53712, 0x00000000 }, /* ADDA */
+{ op_d1d8_0_comp_ff, 53720, 0x00000000 }, /* ADDA */
+{ op_d1e0_0_comp_ff, 53728, 0x00000000 }, /* ADDA */
+{ op_d1e8_0_comp_ff, 53736, 0x00000002 }, /* ADDA */
+{ op_d1f0_0_comp_ff, 53744, 0x00000002 }, /* ADDA */
+{ op_d1f8_0_comp_ff, 53752, 0x00000002 }, /* ADDA */
+{ op_d1f9_0_comp_ff, 53753, 0x00000002 }, /* ADDA */
+{ op_d1fa_0_comp_ff, 53754, 0x00000002 }, /* ADDA */
+{ op_d1fb_0_comp_ff, 53755, 0x00000002 }, /* ADDA */
+{ op_d1fc_0_comp_ff, 53756, 0x00000002 }, /* ADDA */
+{ op_e000_0_comp_ff, 57344, 0x00000000 }, /* ASR */
+{ op_e008_0_comp_ff, 57352, 0x00000000 }, /* LSR */
+{ op_e010_0_comp_ff, 57360, 0x00000008 }, /* ROXR */
+{ op_e018_0_comp_ff, 57368, 0x00000000 }, /* ROR */
+{ op_e020_0_comp_ff, 57376, 0x00000000 }, /* ASR */
+{ op_e028_0_comp_ff, 57384, 0x00000000 }, /* LSR */
+{ op_e030_0_comp_ff, 57392, 0x00000008 }, /* ROXR */
+{ op_e038_0_comp_ff, 57400, 0x00000000 }, /* ROR */
+{ op_e040_0_comp_ff, 57408, 0x00000000 }, /* ASR */
+{ op_e048_0_comp_ff, 57416, 0x00000000 }, /* LSR */
+{ op_e050_0_comp_ff, 57424, 0x00000008 }, /* ROXR */
+{ op_e058_0_comp_ff, 57432, 0x00000000 }, /* ROR */
+{ op_e060_0_comp_ff, 57440, 0x00000000 }, /* ASR */
+{ op_e068_0_comp_ff, 57448, 0x00000000 }, /* LSR */
+{ op_e070_0_comp_ff, 57456, 0x00000008 }, /* ROXR */
+{ op_e078_0_comp_ff, 57464, 0x00000000 }, /* ROR */
+{ op_e080_0_comp_ff, 57472, 0x00000000 }, /* ASR */
+{ op_e088_0_comp_ff, 57480, 0x00000000 }, /* LSR */
+{ op_e090_0_comp_ff, 57488, 0x00000008 }, /* ROXR */
+{ op_e098_0_comp_ff, 57496, 0x00000000 }, /* ROR */
+{ op_e0a0_0_comp_ff, 57504, 0x00000000 }, /* ASR */
+{ op_e0a8_0_comp_ff, 57512, 0x00000000 }, /* LSR */
+{ op_e0b0_0_comp_ff, 57520, 0x00000008 }, /* ROXR */
+{ op_e0b8_0_comp_ff, 57528, 0x00000000 }, /* ROR */
+{ op_e0d0_0_comp_ff, 57552, 0x00000000 }, /* ASRW */
+{ op_e0d8_0_comp_ff, 57560, 0x00000000 }, /* ASRW */
+{ op_e0e0_0_comp_ff, 57568, 0x00000000 }, /* ASRW */
+{ op_e0e8_0_comp_ff, 57576, 0x00000002 }, /* ASRW */
+{ op_e0f0_0_comp_ff, 57584, 0x00000002 }, /* ASRW */
+{ op_e0f8_0_comp_ff, 57592, 0x00000002 }, /* ASRW */
+{ op_e0f9_0_comp_ff, 57593, 0x00000002 }, /* ASRW */
+{ op_e100_0_comp_ff, 57600, 0x00000000 }, /* ASL */
+{ op_e108_0_comp_ff, 57608, 0x00000000 }, /* LSL */
+{ op_e110_0_comp_ff, 57616, 0x00000008 }, /* ROXL */
+{ op_e118_0_comp_ff, 57624, 0x00000000 }, /* ROL */
+{ op_e120_0_comp_ff, 57632, 0x00000000 }, /* ASL */
+{ op_e128_0_comp_ff, 57640, 0x00000000 }, /* LSL */
+{ op_e130_0_comp_ff, 57648, 0x00000008 }, /* ROXL */
+{ op_e138_0_comp_ff, 57656, 0x00000000 }, /* ROL */
+{ op_e140_0_comp_ff, 57664, 0x00000000 }, /* ASL */
+{ op_e148_0_comp_ff, 57672, 0x00000000 }, /* LSL */
+{ op_e150_0_comp_ff, 57680, 0x00000008 }, /* ROXL */
+{ op_e158_0_comp_ff, 57688, 0x00000000 }, /* ROL */
+{ op_e160_0_comp_ff, 57696, 0x00000000 }, /* ASL */
+{ op_e168_0_comp_ff, 57704, 0x00000000 }, /* LSL */
+{ op_e170_0_comp_ff, 57712, 0x00000008 }, /* ROXL */
+{ op_e178_0_comp_ff, 57720, 0x00000000 }, /* ROL */
+{ op_e180_0_comp_ff, 57728, 0x00000000 }, /* ASL */
+{ op_e188_0_comp_ff, 57736, 0x00000000 }, /* LSL */
+{ op_e190_0_comp_ff, 57744, 0x00000008 }, /* ROXL */
+{ op_e198_0_comp_ff, 57752, 0x00000000 }, /* ROL */
+{ op_e1a0_0_comp_ff, 57760, 0x00000000 }, /* ASL */
+{ op_e1a8_0_comp_ff, 57768, 0x00000000 }, /* LSL */
+{ op_e1b0_0_comp_ff, 57776, 0x00000008 }, /* ROXL */
+{ op_e1b8_0_comp_ff, 57784, 0x00000000 }, /* ROL */
+{ op_e1d0_0_comp_ff, 57808, 0x00000000 }, /* ASLW */
+{ op_e1d8_0_comp_ff, 57816, 0x00000000 }, /* ASLW */
+{ op_e1e0_0_comp_ff, 57824, 0x00000000 }, /* ASLW */
+{ op_e1e8_0_comp_ff, 57832, 0x00000002 }, /* ASLW */
+{ op_e1f0_0_comp_ff, 57840, 0x00000002 }, /* ASLW */
+{ op_e1f8_0_comp_ff, 57848, 0x00000002 }, /* ASLW */
+{ op_e1f9_0_comp_ff, 57849, 0x00000002 }, /* ASLW */
+{ op_e2d0_0_comp_ff, 58064, 0x00000000 }, /* LSRW */
+{ op_e2d8_0_comp_ff, 58072, 0x00000000 }, /* LSRW */
+{ op_e2e0_0_comp_ff, 58080, 0x00000000 }, /* LSRW */
+{ op_e2e8_0_comp_ff, 58088, 0x00000002 }, /* LSRW */
+{ op_e2f0_0_comp_ff, 58096, 0x00000002 }, /* LSRW */
+{ op_e2f8_0_comp_ff, 58104, 0x00000002 }, /* LSRW */
+{ op_e2f9_0_comp_ff, 58105, 0x00000002 }, /* LSRW */
+{ op_e3d0_0_comp_ff, 58320, 0x00000000 }, /* LSLW */
+{ op_e3d8_0_comp_ff, 58328, 0x00000000 }, /* LSLW */
+{ op_e3e0_0_comp_ff, 58336, 0x00000000 }, /* LSLW */
+{ op_e3e8_0_comp_ff, 58344, 0x00000002 }, /* LSLW */
+{ op_e3f0_0_comp_ff, 58352, 0x00000002 }, /* LSLW */
+{ op_e3f8_0_comp_ff, 58360, 0x00000002 }, /* LSLW */
+{ op_e3f9_0_comp_ff, 58361, 0x00000002 }, /* LSLW */
+{ NULL, 58576, 0x00000008 }, /* ROXRW */
+{ NULL, 58584, 0x00000008 }, /* ROXRW */
+{ NULL, 58592, 0x00000008 }, /* ROXRW */
+{ NULL, 58600, 0x0000000a }, /* ROXRW */
+{ NULL, 58608, 0x0000000a }, /* ROXRW */
+{ NULL, 58616, 0x0000000a }, /* ROXRW */
+{ NULL, 58617, 0x0000000a }, /* ROXRW */
+{ NULL, 58832, 0x00000008 }, /* ROXLW */
+{ NULL, 58840, 0x00000008 }, /* ROXLW */
+{ NULL, 58848, 0x00000008 }, /* ROXLW */
+{ NULL, 58856, 0x0000000a }, /* ROXLW */
+{ NULL, 58864, 0x0000000a }, /* ROXLW */
+{ NULL, 58872, 0x0000000a }, /* ROXLW */
+{ NULL, 58873, 0x0000000a }, /* ROXLW */
+{ op_e6d0_0_comp_ff, 59088, 0x00000000 }, /* RORW */
+{ op_e6d8_0_comp_ff, 59096, 0x00000000 }, /* RORW */
+{ op_e6e0_0_comp_ff, 59104, 0x00000000 }, /* RORW */
+{ op_e6e8_0_comp_ff, 59112, 0x00000002 }, /* RORW */
+{ op_e6f0_0_comp_ff, 59120, 0x00000002 }, /* RORW */
+{ op_e6f8_0_comp_ff, 59128, 0x00000002 }, /* RORW */
+{ op_e6f9_0_comp_ff, 59129, 0x00000002 }, /* RORW */
+{ op_e7d0_0_comp_ff, 59344, 0x00000000 }, /* ROLW */
+{ op_e7d8_0_comp_ff, 59352, 0x00000000 }, /* ROLW */
+{ op_e7e0_0_comp_ff, 59360, 0x00000000 }, /* ROLW */
+{ op_e7e8_0_comp_ff, 59368, 0x00000002 }, /* ROLW */
+{ op_e7f0_0_comp_ff, 59376, 0x00000002 }, /* ROLW */
+{ op_e7f8_0_comp_ff, 59384, 0x00000002 }, /* ROLW */
+{ op_e7f9_0_comp_ff, 59385, 0x00000002 }, /* ROLW */
+{ NULL, 59584, 0x00000000 }, /* BFTST */
+{ NULL, 59600, 0x00000000 }, /* BFTST */
+{ NULL, 59624, 0x00000000 }, /* BFTST */
+{ NULL, 59632, 0x00000000 }, /* BFTST */
+{ NULL, 59640, 0x00000000 }, /* BFTST */
+{ NULL, 59641, 0x00000000 }, /* BFTST */
+{ NULL, 59642, 0x00000000 }, /* BFTST */
+{ NULL, 59643, 0x00000000 }, /* BFTST */
+{ NULL, 59840, 0x00000000 }, /* BFEXTU */
+{ NULL, 59856, 0x00000000 }, /* BFEXTU */
+{ NULL, 59880, 0x00000000 }, /* BFEXTU */
+{ NULL, 59888, 0x00000000 }, /* BFEXTU */
+{ NULL, 59896, 0x00000000 }, /* BFEXTU */
+{ NULL, 59897, 0x00000000 }, /* BFEXTU */
+{ NULL, 59898, 0x00000000 }, /* BFEXTU */
+{ NULL, 59899, 0x00000000 }, /* BFEXTU */
+{ NULL, 60096, 0x00000000 }, /* BFCHG */
+{ NULL, 60112, 0x00000000 }, /* BFCHG */
+{ NULL, 60136, 0x00000000 }, /* BFCHG */
+{ NULL, 60144, 0x00000000 }, /* BFCHG */
+{ NULL, 60152, 0x00000000 }, /* BFCHG */
+{ NULL, 60153, 0x00000000 }, /* BFCHG */
+{ NULL, 60352, 0x00000000 }, /* BFEXTS */
+{ NULL, 60368, 0x00000000 }, /* BFEXTS */
+{ NULL, 60392, 0x00000000 }, /* BFEXTS */
+{ NULL, 60400, 0x00000000 }, /* BFEXTS */
+{ NULL, 60408, 0x00000000 }, /* BFEXTS */
+{ NULL, 60409, 0x00000000 }, /* BFEXTS */
+{ NULL, 60410, 0x00000000 }, /* BFEXTS */
+{ NULL, 60411, 0x00000000 }, /* BFEXTS */
+{ NULL, 60608, 0x00000000 }, /* BFCLR */
+{ NULL, 60624, 0x00000000 }, /* BFCLR */
+{ NULL, 60648, 0x00000000 }, /* BFCLR */
+{ NULL, 60656, 0x00000000 }, /* BFCLR */
+{ NULL, 60664, 0x00000000 }, /* BFCLR */
+{ NULL, 60665, 0x00000000 }, /* BFCLR */
+{ NULL, 60864, 0x00000000 }, /* BFFFO */
+{ NULL, 60880, 0x00000000 }, /* BFFFO */
+{ NULL, 60904, 0x00000000 }, /* BFFFO */
+{ NULL, 60912, 0x00000000 }, /* BFFFO */
+{ NULL, 60920, 0x00000000 }, /* BFFFO */
+{ NULL, 60921, 0x00000000 }, /* BFFFO */
+{ NULL, 60922, 0x00000000 }, /* BFFFO */
+{ NULL, 60923, 0x00000000 }, /* BFFFO */
+{ NULL, 61120, 0x00000000 }, /* BFSET */
+{ NULL, 61136, 0x00000000 }, /* BFSET */
+{ NULL, 61160, 0x00000000 }, /* BFSET */
+{ NULL, 61168, 0x00000000 }, /* BFSET */
+{ NULL, 61176, 0x00000000 }, /* BFSET */
+{ NULL, 61177, 0x00000000 }, /* BFSET */
+{ op_efc0_0_comp_ff, 61376, 0x00000002 }, /* BFINS */
+{ op_efd0_0_comp_ff, 61392, 0x00000002 }, /* BFINS */
+{ op_efe8_0_comp_ff, 61416, 0x00000002 }, /* BFINS */
+{ op_eff0_0_comp_ff, 61424, 0x00000002 }, /* BFINS */
+{ op_eff8_0_comp_ff, 61432, 0x00000002 }, /* BFINS */
+{ op_eff9_0_comp_ff, 61433, 0x00000002 }, /* BFINS */
+{ NULL, 61440, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61448, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61456, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61464, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61472, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61480, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61488, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61496, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61497, 0x00000001 }, /* MMUOP030 */
+{ op_f200_0_comp_ff, 61952, 0x00000022 }, /* FPP */
+{ op_f208_0_comp_ff, 61960, 0x00000022 }, /* FPP */
+{ op_f210_0_comp_ff, 61968, 0x00000022 }, /* FPP */
+{ op_f218_0_comp_ff, 61976, 0x00000022 }, /* FPP */
+{ op_f220_0_comp_ff, 61984, 0x00000022 }, /* FPP */
+{ op_f228_0_comp_ff, 61992, 0x00000022 }, /* FPP */
+{ op_f230_0_comp_ff, 62000, 0x00000022 }, /* FPP */
+{ op_f238_0_comp_ff, 62008, 0x00000022 }, /* FPP */
+{ op_f239_0_comp_ff, 62009, 0x00000022 }, /* FPP */
+{ op_f23a_0_comp_ff, 62010, 0x00000022 }, /* FPP */
+{ op_f23b_0_comp_ff, 62011, 0x00000022 }, /* FPP */
+{ op_f23c_0_comp_ff, 62012, 0x00000022 }, /* FPP */
+{ op_f240_0_comp_ff, 62016, 0x00000006 }, /* FScc */
+{ NULL, 62024, 0x00000021 }, /* FDBcc */
+{ op_f250_0_comp_ff, 62032, 0x00000006 }, /* FScc */
+{ op_f258_0_comp_ff, 62040, 0x00000006 }, /* FScc */
+{ op_f260_0_comp_ff, 62048, 0x00000006 }, /* FScc */
+{ op_f268_0_comp_ff, 62056, 0x00000006 }, /* FScc */
+{ op_f270_0_comp_ff, 62064, 0x00000006 }, /* FScc */
+{ op_f278_0_comp_ff, 62072, 0x00000006 }, /* FScc */
+{ op_f279_0_comp_ff, 62073, 0x00000006 }, /* FScc */
+{ NULL, 62074, 0x00000021 }, /* FTRAPcc */
+{ NULL, 62075, 0x00000021 }, /* FTRAPcc */
+{ NULL, 62076, 0x00000021 }, /* FTRAPcc */
+{ op_f280_0_comp_ff, 62080, 0x00000005 }, /* FBcc */
+{ op_f2c0_0_comp_ff, 62144, 0x00000005 }, /* FBcc */
+{ NULL, 62224, 0x00000020 }, /* FSAVE */
+{ NULL, 62240, 0x00000020 }, /* FSAVE */
+{ NULL, 62248, 0x00000020 }, /* FSAVE */
+{ NULL, 62256, 0x00000020 }, /* FSAVE */
+{ NULL, 62264, 0x00000020 }, /* FSAVE */
+{ NULL, 62265, 0x00000020 }, /* FSAVE */
+{ NULL, 62288, 0x00000020 }, /* FRESTORE */
+{ NULL, 62296, 0x00000020 }, /* FRESTORE */
+{ NULL, 62312, 0x00000020 }, /* FRESTORE */
+{ NULL, 62320, 0x00000020 }, /* FRESTORE */
+{ NULL, 62328, 0x00000020 }, /* FRESTORE */
+{ NULL, 62329, 0x00000020 }, /* FRESTORE */
+{ NULL, 62330, 0x00000020 }, /* FRESTORE */
+{ NULL, 62331, 0x00000020 }, /* FRESTORE */
+{ NULL, 62472, 0x00000001 }, /* CINVL */
+{ NULL, 62480, 0x00000001 }, /* CINVP */
+{ NULL, 62488, 0x00000001 }, /* CINVA */
+{ NULL, 62489, 0x00000001 }, /* CINVA */
+{ NULL, 62490, 0x00000001 }, /* CINVA */
+{ NULL, 62491, 0x00000001 }, /* CINVA */
+{ NULL, 62492, 0x00000001 }, /* CINVA */
+{ NULL, 62493, 0x00000001 }, /* CINVA */
+{ NULL, 62494, 0x00000001 }, /* CINVA */
+{ NULL, 62495, 0x00000001 }, /* CINVA */
+{ NULL, 62504, 0x00000001 }, /* CPUSHL */
+{ NULL, 62512, 0x00000001 }, /* CPUSHP */
+{ NULL, 62520, 0x00000001 }, /* CPUSHA */
+{ NULL, 62521, 0x00000001 }, /* CPUSHA */
+{ NULL, 62522, 0x00000001 }, /* CPUSHA */
+{ NULL, 62523, 0x00000001 }, /* CPUSHA */
+{ NULL, 62524, 0x00000001 }, /* CPUSHA */
+{ NULL, 62525, 0x00000001 }, /* CPUSHA */
+{ NULL, 62526, 0x00000001 }, /* CPUSHA */
+{ NULL, 62527, 0x00000001 }, /* CPUSHA */
+{ NULL, 62720, 0x00000001 }, /* PFLUSHN */
+{ NULL, 62728, 0x00000001 }, /* PFLUSH */
+{ NULL, 62736, 0x00000001 }, /* PFLUSHAN */
+{ NULL, 62744, 0x00000001 }, /* PFLUSHA */
+{ NULL, 62792, 0x00000001 }, /* PTESTW */
+{ NULL, 62824, 0x00000001 }, /* PTESTR */
+{ op_f600_0_comp_ff, 62976, 0x00000002 }, /* MOVE16 */
+{ op_f608_0_comp_ff, 62984, 0x00000002 }, /* MOVE16 */
+{ op_f610_0_comp_ff, 62992, 0x00000002 }, /* MOVE16 */
+{ op_f618_0_comp_ff, 63000, 0x00000002 }, /* MOVE16 */
+{ op_f620_0_comp_ff, 63008, 0x00000002 }, /* MOVE16 */
+{ 0, 65536, 0 }};
+extern const struct comptbl op_smalltbl_0_comp_nf[] = { { op_0_0_comp_nf, 0, 0x00000002 }, /* OR */
+{ op_10_0_comp_nf, 16, 0x00000002 }, /* OR */
+{ op_18_0_comp_nf, 24, 0x00000002 }, /* OR */
+{ op_20_0_comp_nf, 32, 0x00000002 }, /* OR */
+{ op_28_0_comp_nf, 40, 0x00000002 }, /* OR */
+{ op_30_0_comp_nf, 48, 0x00000002 }, /* OR */
+{ op_38_0_comp_nf, 56, 0x00000002 }, /* OR */
+{ op_39_0_comp_nf, 57, 0x00000002 }, /* OR */
+{ op_3c_0_comp_nf, 60, 0x00000002 }, /* ORSR */
+{ op_40_0_comp_nf, 64, 0x00000002 }, /* OR */
+{ op_50_0_comp_nf, 80, 0x00000002 }, /* OR */
+{ op_58_0_comp_nf, 88, 0x00000002 }, /* OR */
+{ op_60_0_comp_nf, 96, 0x00000002 }, /* OR */
+{ op_68_0_comp_nf, 104, 0x00000002 }, /* OR */
+{ op_70_0_comp_nf, 112, 0x00000002 }, /* OR */
+{ op_78_0_comp_nf, 120, 0x00000002 }, /* OR */
+{ op_79_0_comp_nf, 121, 0x00000002 }, /* OR */
+{ NULL, 124, 0x00000002 }, /* ORSR */
+{ op_80_0_comp_nf, 128, 0x00000002 }, /* OR */
+{ op_90_0_comp_nf, 144, 0x00000002 }, /* OR */
+{ op_98_0_comp_nf, 152, 0x00000002 }, /* OR */
+{ op_a0_0_comp_nf, 160, 0x00000002 }, /* OR */
+{ op_a8_0_comp_nf, 168, 0x00000002 }, /* OR */
+{ op_b0_0_comp_nf, 176, 0x00000002 }, /* OR */
+{ op_b8_0_comp_nf, 184, 0x00000002 }, /* OR */
+{ op_b9_0_comp_nf, 185, 0x00000002 }, /* OR */
+{ NULL, 208, 0x00000001 }, /* CHK2 */
+{ NULL, 232, 0x00000001 }, /* CHK2 */
+{ NULL, 240, 0x00000001 }, /* CHK2 */
+{ NULL, 248, 0x00000001 }, /* CHK2 */
+{ NULL, 249, 0x00000001 }, /* CHK2 */
+{ NULL, 250, 0x00000001 }, /* CHK2 */
+{ NULL, 251, 0x00000001 }, /* CHK2 */
+{ op_100_0_comp_nf, 256, 0x00000000 }, /* BTST */
+{ NULL, 264, 0x00000001 }, /* MVPMR */
+{ op_110_0_comp_nf, 272, 0x00000000 }, /* BTST */
+{ op_118_0_comp_nf, 280, 0x00000000 }, /* BTST */
+{ op_120_0_comp_nf, 288, 0x00000000 }, /* BTST */
+{ op_128_0_comp_nf, 296, 0x00000002 }, /* BTST */
+{ op_130_0_comp_nf, 304, 0x00000002 }, /* BTST */
+{ op_138_0_comp_nf, 312, 0x00000002 }, /* BTST */
+{ op_139_0_comp_nf, 313, 0x00000002 }, /* BTST */
+{ op_13a_0_comp_nf, 314, 0x00000002 }, /* BTST */
+{ op_13b_0_comp_nf, 315, 0x00000002 }, /* BTST */
+{ op_13c_0_comp_nf, 316, 0x00000002 }, /* BTST */
+{ op_140_0_comp_nf, 320, 0x00000000 }, /* BCHG */
+{ NULL, 328, 0x00000001 }, /* MVPMR */
+{ op_150_0_comp_nf, 336, 0x00000000 }, /* BCHG */
+{ op_158_0_comp_nf, 344, 0x00000000 }, /* BCHG */
+{ op_160_0_comp_nf, 352, 0x00000000 }, /* BCHG */
+{ op_168_0_comp_nf, 360, 0x00000002 }, /* BCHG */
+{ op_170_0_comp_nf, 368, 0x00000002 }, /* BCHG */
+{ op_178_0_comp_nf, 376, 0x00000002 }, /* BCHG */
+{ op_179_0_comp_nf, 377, 0x00000002 }, /* BCHG */
+{ op_180_0_comp_nf, 384, 0x00000000 }, /* BCLR */
+{ NULL, 392, 0x00000001 }, /* MVPRM */
+{ op_190_0_comp_nf, 400, 0x00000000 }, /* BCLR */
+{ op_198_0_comp_nf, 408, 0x00000000 }, /* BCLR */
+{ op_1a0_0_comp_nf, 416, 0x00000000 }, /* BCLR */
+{ op_1a8_0_comp_nf, 424, 0x00000002 }, /* BCLR */
+{ op_1b0_0_comp_nf, 432, 0x00000002 }, /* BCLR */
+{ op_1b8_0_comp_nf, 440, 0x00000002 }, /* BCLR */
+{ op_1b9_0_comp_nf, 441, 0x00000002 }, /* BCLR */
+{ op_1c0_0_comp_nf, 448, 0x00000000 }, /* BSET */
+{ NULL, 456, 0x00000001 }, /* MVPRM */
+{ op_1d0_0_comp_nf, 464, 0x00000000 }, /* BSET */
+{ op_1d8_0_comp_nf, 472, 0x00000000 }, /* BSET */
+{ op_1e0_0_comp_nf, 480, 0x00000000 }, /* BSET */
+{ op_1e8_0_comp_nf, 488, 0x00000002 }, /* BSET */
+{ op_1f0_0_comp_nf, 496, 0x00000002 }, /* BSET */
+{ op_1f8_0_comp_nf, 504, 0x00000002 }, /* BSET */
+{ op_1f9_0_comp_nf, 505, 0x00000002 }, /* BSET */
+{ op_200_0_comp_nf, 512, 0x00000002 }, /* AND */
+{ op_210_0_comp_nf, 528, 0x00000002 }, /* AND */
+{ op_218_0_comp_nf, 536, 0x00000002 }, /* AND */
+{ op_220_0_comp_nf, 544, 0x00000002 }, /* AND */
+{ op_228_0_comp_nf, 552, 0x00000002 }, /* AND */
+{ op_230_0_comp_nf, 560, 0x00000002 }, /* AND */
+{ op_238_0_comp_nf, 568, 0x00000002 }, /* AND */
+{ op_239_0_comp_nf, 569, 0x00000002 }, /* AND */
+{ op_23c_0_comp_nf, 572, 0x00000002 }, /* ANDSR */
+{ op_240_0_comp_nf, 576, 0x00000002 }, /* AND */
+{ op_250_0_comp_nf, 592, 0x00000002 }, /* AND */
+{ op_258_0_comp_nf, 600, 0x00000002 }, /* AND */
+{ op_260_0_comp_nf, 608, 0x00000002 }, /* AND */
+{ op_268_0_comp_nf, 616, 0x00000002 }, /* AND */
+{ op_270_0_comp_nf, 624, 0x00000002 }, /* AND */
+{ op_278_0_comp_nf, 632, 0x00000002 }, /* AND */
+{ op_279_0_comp_nf, 633, 0x00000002 }, /* AND */
+{ NULL, 636, 0x00000002 }, /* ANDSR */
+{ op_280_0_comp_nf, 640, 0x00000002 }, /* AND */
+{ op_290_0_comp_nf, 656, 0x00000002 }, /* AND */
+{ op_298_0_comp_nf, 664, 0x00000002 }, /* AND */
+{ op_2a0_0_comp_nf, 672, 0x00000002 }, /* AND */
+{ op_2a8_0_comp_nf, 680, 0x00000002 }, /* AND */
+{ op_2b0_0_comp_nf, 688, 0x00000002 }, /* AND */
+{ op_2b8_0_comp_nf, 696, 0x00000002 }, /* AND */
+{ op_2b9_0_comp_nf, 697, 0x00000002 }, /* AND */
+{ NULL, 720, 0x00000001 }, /* CHK2 */
+{ NULL, 744, 0x00000001 }, /* CHK2 */
+{ NULL, 752, 0x00000001 }, /* CHK2 */
+{ NULL, 760, 0x00000001 }, /* CHK2 */
+{ NULL, 761, 0x00000001 }, /* CHK2 */
+{ NULL, 762, 0x00000001 }, /* CHK2 */
+{ NULL, 763, 0x00000001 }, /* CHK2 */
+{ op_400_0_comp_nf, 1024, 0x00000002 }, /* SUB */
+{ op_410_0_comp_nf, 1040, 0x00000002 }, /* SUB */
+{ op_418_0_comp_nf, 1048, 0x00000002 }, /* SUB */
+{ op_420_0_comp_nf, 1056, 0x00000002 }, /* SUB */
+{ op_428_0_comp_nf, 1064, 0x00000002 }, /* SUB */
+{ op_430_0_comp_nf, 1072, 0x00000002 }, /* SUB */
+{ op_438_0_comp_nf, 1080, 0x00000002 }, /* SUB */
+{ op_439_0_comp_nf, 1081, 0x00000002 }, /* SUB */
+{ op_440_0_comp_nf, 1088, 0x00000002 }, /* SUB */
+{ op_450_0_comp_nf, 1104, 0x00000002 }, /* SUB */
+{ op_458_0_comp_nf, 1112, 0x00000002 }, /* SUB */
+{ op_460_0_comp_nf, 1120, 0x00000002 }, /* SUB */
+{ op_468_0_comp_nf, 1128, 0x00000002 }, /* SUB */
+{ op_470_0_comp_nf, 1136, 0x00000002 }, /* SUB */
+{ op_478_0_comp_nf, 1144, 0x00000002 }, /* SUB */
+{ op_479_0_comp_nf, 1145, 0x00000002 }, /* SUB */
+{ op_480_0_comp_nf, 1152, 0x00000002 }, /* SUB */
+{ op_490_0_comp_nf, 1168, 0x00000002 }, /* SUB */
+{ op_498_0_comp_nf, 1176, 0x00000002 }, /* SUB */
+{ op_4a0_0_comp_nf, 1184, 0x00000002 }, /* SUB */
+{ op_4a8_0_comp_nf, 1192, 0x00000002 }, /* SUB */
+{ op_4b0_0_comp_nf, 1200, 0x00000002 }, /* SUB */
+{ op_4b8_0_comp_nf, 1208, 0x00000002 }, /* SUB */
+{ op_4b9_0_comp_nf, 1209, 0x00000002 }, /* SUB */
+{ NULL, 1232, 0x00000001 }, /* CHK2 */
+{ NULL, 1256, 0x00000001 }, /* CHK2 */
+{ NULL, 1264, 0x00000001 }, /* CHK2 */
+{ NULL, 1272, 0x00000001 }, /* CHK2 */
+{ NULL, 1273, 0x00000001 }, /* CHK2 */
+{ NULL, 1274, 0x00000001 }, /* CHK2 */
+{ NULL, 1275, 0x00000001 }, /* CHK2 */
+{ op_600_0_comp_nf, 1536, 0x00000002 }, /* ADD */
+{ op_610_0_comp_nf, 1552, 0x00000002 }, /* ADD */
+{ op_618_0_comp_nf, 1560, 0x00000002 }, /* ADD */
+{ op_620_0_comp_nf, 1568, 0x00000002 }, /* ADD */
+{ op_628_0_comp_nf, 1576, 0x00000002 }, /* ADD */
+{ op_630_0_comp_nf, 1584, 0x00000002 }, /* ADD */
+{ op_638_0_comp_nf, 1592, 0x00000002 }, /* ADD */
+{ op_639_0_comp_nf, 1593, 0x00000002 }, /* ADD */
+{ op_640_0_comp_nf, 1600, 0x00000002 }, /* ADD */
+{ op_650_0_comp_nf, 1616, 0x00000002 }, /* ADD */
+{ op_658_0_comp_nf, 1624, 0x00000002 }, /* ADD */
+{ op_660_0_comp_nf, 1632, 0x00000002 }, /* ADD */
+{ op_668_0_comp_nf, 1640, 0x00000002 }, /* ADD */
+{ op_670_0_comp_nf, 1648, 0x00000002 }, /* ADD */
+{ op_678_0_comp_nf, 1656, 0x00000002 }, /* ADD */
+{ op_679_0_comp_nf, 1657, 0x00000002 }, /* ADD */
+{ op_680_0_comp_nf, 1664, 0x00000002 }, /* ADD */
+{ op_690_0_comp_nf, 1680, 0x00000002 }, /* ADD */
+{ op_698_0_comp_nf, 1688, 0x00000002 }, /* ADD */
+{ op_6a0_0_comp_nf, 1696, 0x00000002 }, /* ADD */
+{ op_6a8_0_comp_nf, 1704, 0x00000002 }, /* ADD */
+{ op_6b0_0_comp_nf, 1712, 0x00000002 }, /* ADD */
+{ op_6b8_0_comp_nf, 1720, 0x00000002 }, /* ADD */
+{ op_6b9_0_comp_nf, 1721, 0x00000002 }, /* ADD */
+{ NULL, 1728, 0x00000001 }, /* RTM */
+{ NULL, 1736, 0x00000001 }, /* RTM */
+{ NULL, 1744, 0x00000001 }, /* CALLM */
+{ NULL, 1768, 0x00000001 }, /* CALLM */
+{ NULL, 1776, 0x00000001 }, /* CALLM */
+{ NULL, 1784, 0x00000001 }, /* CALLM */
+{ NULL, 1785, 0x00000001 }, /* CALLM */
+{ NULL, 1786, 0x00000001 }, /* CALLM */
+{ NULL, 1787, 0x00000001 }, /* CALLM */
+{ op_800_0_comp_nf, 2048, 0x00000002 }, /* BTST */
+{ op_810_0_comp_nf, 2064, 0x00000002 }, /* BTST */
+{ op_818_0_comp_nf, 2072, 0x00000002 }, /* BTST */
+{ op_820_0_comp_nf, 2080, 0x00000002 }, /* BTST */
+{ op_828_0_comp_nf, 2088, 0x00000002 }, /* BTST */
+{ op_830_0_comp_nf, 2096, 0x00000002 }, /* BTST */
+{ op_838_0_comp_nf, 2104, 0x00000002 }, /* BTST */
+{ op_839_0_comp_nf, 2105, 0x00000002 }, /* BTST */
+{ op_83a_0_comp_nf, 2106, 0x00000002 }, /* BTST */
+{ op_83b_0_comp_nf, 2107, 0x00000002 }, /* BTST */
+{ op_840_0_comp_nf, 2112, 0x00000002 }, /* BCHG */
+{ op_850_0_comp_nf, 2128, 0x00000002 }, /* BCHG */
+{ op_858_0_comp_nf, 2136, 0x00000002 }, /* BCHG */
+{ op_860_0_comp_nf, 2144, 0x00000002 }, /* BCHG */
+{ op_868_0_comp_nf, 2152, 0x00000002 }, /* BCHG */
+{ op_870_0_comp_nf, 2160, 0x00000002 }, /* BCHG */
+{ op_878_0_comp_nf, 2168, 0x00000002 }, /* BCHG */
+{ op_879_0_comp_nf, 2169, 0x00000002 }, /* BCHG */
+{ op_880_0_comp_nf, 2176, 0x00000002 }, /* BCLR */
+{ op_890_0_comp_nf, 2192, 0x00000002 }, /* BCLR */
+{ op_898_0_comp_nf, 2200, 0x00000002 }, /* BCLR */
+{ op_8a0_0_comp_nf, 2208, 0x00000002 }, /* BCLR */
+{ op_8a8_0_comp_nf, 2216, 0x00000002 }, /* BCLR */
+{ op_8b0_0_comp_nf, 2224, 0x00000002 }, /* BCLR */
+{ op_8b8_0_comp_nf, 2232, 0x00000002 }, /* BCLR */
+{ op_8b9_0_comp_nf, 2233, 0x00000002 }, /* BCLR */
+{ op_8c0_0_comp_nf, 2240, 0x00000002 }, /* BSET */
+{ op_8d0_0_comp_nf, 2256, 0x00000002 }, /* BSET */
+{ op_8d8_0_comp_nf, 2264, 0x00000002 }, /* BSET */
+{ op_8e0_0_comp_nf, 2272, 0x00000002 }, /* BSET */
+{ op_8e8_0_comp_nf, 2280, 0x00000002 }, /* BSET */
+{ op_8f0_0_comp_nf, 2288, 0x00000002 }, /* BSET */
+{ op_8f8_0_comp_nf, 2296, 0x00000002 }, /* BSET */
+{ op_8f9_0_comp_nf, 2297, 0x00000002 }, /* BSET */
+{ op_a00_0_comp_nf, 2560, 0x00000002 }, /* EOR */
+{ op_a10_0_comp_nf, 2576, 0x00000002 }, /* EOR */
+{ op_a18_0_comp_nf, 2584, 0x00000002 }, /* EOR */
+{ op_a20_0_comp_nf, 2592, 0x00000002 }, /* EOR */
+{ op_a28_0_comp_nf, 2600, 0x00000002 }, /* EOR */
+{ op_a30_0_comp_nf, 2608, 0x00000002 }, /* EOR */
+{ op_a38_0_comp_nf, 2616, 0x00000002 }, /* EOR */
+{ op_a39_0_comp_nf, 2617, 0x00000002 }, /* EOR */
+{ op_a3c_0_comp_nf, 2620, 0x00000002 }, /* EORSR */
+{ op_a40_0_comp_nf, 2624, 0x00000002 }, /* EOR */
+{ op_a50_0_comp_nf, 2640, 0x00000002 }, /* EOR */
+{ op_a58_0_comp_nf, 2648, 0x00000002 }, /* EOR */
+{ op_a60_0_comp_nf, 2656, 0x00000002 }, /* EOR */
+{ op_a68_0_comp_nf, 2664, 0x00000002 }, /* EOR */
+{ op_a70_0_comp_nf, 2672, 0x00000002 }, /* EOR */
+{ op_a78_0_comp_nf, 2680, 0x00000002 }, /* EOR */
+{ op_a79_0_comp_nf, 2681, 0x00000002 }, /* EOR */
+{ NULL, 2684, 0x00000002 }, /* EORSR */
+{ op_a80_0_comp_nf, 2688, 0x00000002 }, /* EOR */
+{ op_a90_0_comp_nf, 2704, 0x00000002 }, /* EOR */
+{ op_a98_0_comp_nf, 2712, 0x00000002 }, /* EOR */
+{ op_aa0_0_comp_nf, 2720, 0x00000002 }, /* EOR */
+{ op_aa8_0_comp_nf, 2728, 0x00000002 }, /* EOR */
+{ op_ab0_0_comp_nf, 2736, 0x00000002 }, /* EOR */
+{ op_ab8_0_comp_nf, 2744, 0x00000002 }, /* EOR */
+{ op_ab9_0_comp_nf, 2745, 0x00000002 }, /* EOR */
+{ NULL, 2768, 0x00000000 }, /* CAS */
+{ NULL, 2776, 0x00000000 }, /* CAS */
+{ NULL, 2784, 0x00000000 }, /* CAS */
+{ NULL, 2792, 0x00000000 }, /* CAS */
+{ NULL, 2800, 0x00000000 }, /* CAS */
+{ NULL, 2808, 0x00000000 }, /* CAS */
+{ NULL, 2809, 0x00000000 }, /* CAS */
+{ op_c00_0_comp_nf, 3072, 0x00000002 }, /* CMP */
+{ op_c10_0_comp_nf, 3088, 0x00000002 }, /* CMP */
+{ op_c18_0_comp_nf, 3096, 0x00000002 }, /* CMP */
+{ op_c20_0_comp_nf, 3104, 0x00000002 }, /* CMP */
+{ op_c28_0_comp_nf, 3112, 0x00000002 }, /* CMP */
+{ op_c30_0_comp_nf, 3120, 0x00000002 }, /* CMP */
+{ op_c38_0_comp_nf, 3128, 0x00000002 }, /* CMP */
+{ op_c39_0_comp_nf, 3129, 0x00000002 }, /* CMP */
+{ op_c3a_0_comp_nf, 3130, 0x00000002 }, /* CMP */
+{ op_c3b_0_comp_nf, 3131, 0x00000002 }, /* CMP */
+{ op_c40_0_comp_nf, 3136, 0x00000002 }, /* CMP */
+{ op_c50_0_comp_nf, 3152, 0x00000002 }, /* CMP */
+{ op_c58_0_comp_nf, 3160, 0x00000002 }, /* CMP */
+{ op_c60_0_comp_nf, 3168, 0x00000002 }, /* CMP */
+{ op_c68_0_comp_nf, 3176, 0x00000002 }, /* CMP */
+{ op_c70_0_comp_nf, 3184, 0x00000002 }, /* CMP */
+{ op_c78_0_comp_nf, 3192, 0x00000002 }, /* CMP */
+{ op_c79_0_comp_nf, 3193, 0x00000002 }, /* CMP */
+{ op_c7a_0_comp_nf, 3194, 0x00000002 }, /* CMP */
+{ op_c7b_0_comp_nf, 3195, 0x00000002 }, /* CMP */
+{ op_c80_0_comp_nf, 3200, 0x00000002 }, /* CMP */
+{ op_c90_0_comp_nf, 3216, 0x00000002 }, /* CMP */
+{ op_c98_0_comp_nf, 3224, 0x00000002 }, /* CMP */
+{ op_ca0_0_comp_nf, 3232, 0x00000002 }, /* CMP */
+{ op_ca8_0_comp_nf, 3240, 0x00000002 }, /* CMP */
+{ op_cb0_0_comp_nf, 3248, 0x00000002 }, /* CMP */
+{ op_cb8_0_comp_nf, 3256, 0x00000002 }, /* CMP */
+{ op_cb9_0_comp_nf, 3257, 0x00000002 }, /* CMP */
+{ op_cba_0_comp_nf, 3258, 0x00000002 }, /* CMP */
+{ op_cbb_0_comp_nf, 3259, 0x00000002 }, /* CMP */
+{ NULL, 3280, 0x00000000 }, /* CAS */
+{ NULL, 3288, 0x00000000 }, /* CAS */
+{ NULL, 3296, 0x00000000 }, /* CAS */
+{ NULL, 3304, 0x00000000 }, /* CAS */
+{ NULL, 3312, 0x00000000 }, /* CAS */
+{ NULL, 3320, 0x00000000 }, /* CAS */
+{ NULL, 3321, 0x00000000 }, /* CAS */
+{ NULL, 3324, 0x00000000 }, /* CAS2 */
+{ NULL, 3600, 0x00000001 }, /* MOVES */
+{ NULL, 3608, 0x00000001 }, /* MOVES */
+{ NULL, 3616, 0x00000001 }, /* MOVES */
+{ NULL, 3624, 0x00000001 }, /* MOVES */
+{ NULL, 3632, 0x00000001 }, /* MOVES */
+{ NULL, 3640, 0x00000001 }, /* MOVES */
+{ NULL, 3641, 0x00000001 }, /* MOVES */
+{ NULL, 3664, 0x00000001 }, /* MOVES */
+{ NULL, 3672, 0x00000001 }, /* MOVES */
+{ NULL, 3680, 0x00000001 }, /* MOVES */
+{ NULL, 3688, 0x00000001 }, /* MOVES */
+{ NULL, 3696, 0x00000001 }, /* MOVES */
+{ NULL, 3704, 0x00000001 }, /* MOVES */
+{ NULL, 3705, 0x00000001 }, /* MOVES */
+{ NULL, 3728, 0x00000001 }, /* MOVES */
+{ NULL, 3736, 0x00000001 }, /* MOVES */
+{ NULL, 3744, 0x00000001 }, /* MOVES */
+{ NULL, 3752, 0x00000001 }, /* MOVES */
+{ NULL, 3760, 0x00000001 }, /* MOVES */
+{ NULL, 3768, 0x00000001 }, /* MOVES */
+{ NULL, 3769, 0x00000001 }, /* MOVES */
+{ NULL, 3792, 0x00000000 }, /* CAS */
+{ NULL, 3800, 0x00000000 }, /* CAS */
+{ NULL, 3808, 0x00000000 }, /* CAS */
+{ NULL, 3816, 0x00000000 }, /* CAS */
+{ NULL, 3824, 0x00000000 }, /* CAS */
+{ NULL, 3832, 0x00000000 }, /* CAS */
+{ NULL, 3833, 0x00000000 }, /* CAS */
+{ NULL, 3836, 0x00000000 }, /* CAS2 */
+{ op_1000_0_comp_nf, 4096, 0x00000000 }, /* MOVE */
+{ op_1010_0_comp_nf, 4112, 0x00000000 }, /* MOVE */
+{ op_1018_0_comp_nf, 4120, 0x00000000 }, /* MOVE */
+{ op_1020_0_comp_nf, 4128, 0x00000000 }, /* MOVE */
+{ op_1028_0_comp_nf, 4136, 0x00000002 }, /* MOVE */
+{ op_1030_0_comp_nf, 4144, 0x00000002 }, /* MOVE */
+{ op_1038_0_comp_nf, 4152, 0x00000002 }, /* MOVE */
+{ op_1039_0_comp_nf, 4153, 0x00000002 }, /* MOVE */
+{ op_103a_0_comp_nf, 4154, 0x00000002 }, /* MOVE */
+{ op_103b_0_comp_nf, 4155, 0x00000002 }, /* MOVE */
+{ op_103c_0_comp_nf, 4156, 0x00000002 }, /* MOVE */
+{ op_1080_0_comp_nf, 4224, 0x00000000 }, /* MOVE */
+{ op_1090_0_comp_nf, 4240, 0x00000000 }, /* MOVE */
+{ op_1098_0_comp_nf, 4248, 0x00000000 }, /* MOVE */
+{ op_10a0_0_comp_nf, 4256, 0x00000000 }, /* MOVE */
+{ op_10a8_0_comp_nf, 4264, 0x00000002 }, /* MOVE */
+{ op_10b0_0_comp_nf, 4272, 0x00000002 }, /* MOVE */
+{ op_10b8_0_comp_nf, 4280, 0x00000002 }, /* MOVE */
+{ op_10b9_0_comp_nf, 4281, 0x00000002 }, /* MOVE */
+{ op_10ba_0_comp_nf, 4282, 0x00000002 }, /* MOVE */
+{ op_10bb_0_comp_nf, 4283, 0x00000002 }, /* MOVE */
+{ op_10bc_0_comp_nf, 4284, 0x00000002 }, /* MOVE */
+{ op_10c0_0_comp_nf, 4288, 0x00000000 }, /* MOVE */
+{ op_10d0_0_comp_nf, 4304, 0x00000000 }, /* MOVE */
+{ op_10d8_0_comp_nf, 4312, 0x00000000 }, /* MOVE */
+{ op_10e0_0_comp_nf, 4320, 0x00000000 }, /* MOVE */
+{ op_10e8_0_comp_nf, 4328, 0x00000002 }, /* MOVE */
+{ op_10f0_0_comp_nf, 4336, 0x00000002 }, /* MOVE */
+{ op_10f8_0_comp_nf, 4344, 0x00000002 }, /* MOVE */
+{ op_10f9_0_comp_nf, 4345, 0x00000002 }, /* MOVE */
+{ op_10fa_0_comp_nf, 4346, 0x00000002 }, /* MOVE */
+{ op_10fb_0_comp_nf, 4347, 0x00000002 }, /* MOVE */
+{ op_10fc_0_comp_nf, 4348, 0x00000002 }, /* MOVE */
+{ op_1100_0_comp_nf, 4352, 0x00000000 }, /* MOVE */
+{ op_1110_0_comp_nf, 4368, 0x00000000 }, /* MOVE */
+{ op_1118_0_comp_nf, 4376, 0x00000000 }, /* MOVE */
+{ op_1120_0_comp_nf, 4384, 0x00000000 }, /* MOVE */
+{ op_1128_0_comp_nf, 4392, 0x00000002 }, /* MOVE */
+{ op_1130_0_comp_nf, 4400, 0x00000002 }, /* MOVE */
+{ op_1138_0_comp_nf, 4408, 0x00000002 }, /* MOVE */
+{ op_1139_0_comp_nf, 4409, 0x00000002 }, /* MOVE */
+{ op_113a_0_comp_nf, 4410, 0x00000002 }, /* MOVE */
+{ op_113b_0_comp_nf, 4411, 0x00000002 }, /* MOVE */
+{ op_113c_0_comp_nf, 4412, 0x00000002 }, /* MOVE */
+{ op_1140_0_comp_nf, 4416, 0x00000002 }, /* MOVE */
+{ op_1150_0_comp_nf, 4432, 0x00000002 }, /* MOVE */
+{ op_1158_0_comp_nf, 4440, 0x00000002 }, /* MOVE */
+{ op_1160_0_comp_nf, 4448, 0x00000002 }, /* MOVE */
+{ op_1168_0_comp_nf, 4456, 0x00000002 }, /* MOVE */
+{ op_1170_0_comp_nf, 4464, 0x00000002 }, /* MOVE */
+{ op_1178_0_comp_nf, 4472, 0x00000002 }, /* MOVE */
+{ op_1179_0_comp_nf, 4473, 0x00000002 }, /* MOVE */
+{ op_117a_0_comp_nf, 4474, 0x00000002 }, /* MOVE */
+{ op_117b_0_comp_nf, 4475, 0x00000002 }, /* MOVE */
+{ op_117c_0_comp_nf, 4476, 0x00000002 }, /* MOVE */
+{ op_1180_0_comp_nf, 4480, 0x00000002 }, /* MOVE */
+{ op_1190_0_comp_nf, 4496, 0x00000002 }, /* MOVE */
+{ op_1198_0_comp_nf, 4504, 0x00000002 }, /* MOVE */
+{ op_11a0_0_comp_nf, 4512, 0x00000002 }, /* MOVE */
+{ op_11a8_0_comp_nf, 4520, 0x00000002 }, /* MOVE */
+{ op_11b0_0_comp_nf, 4528, 0x00000002 }, /* MOVE */
+{ op_11b8_0_comp_nf, 4536, 0x00000002 }, /* MOVE */
+{ op_11b9_0_comp_nf, 4537, 0x00000002 }, /* MOVE */
+{ op_11ba_0_comp_nf, 4538, 0x00000002 }, /* MOVE */
+{ op_11bb_0_comp_nf, 4539, 0x00000002 }, /* MOVE */
+{ op_11bc_0_comp_nf, 4540, 0x00000002 }, /* MOVE */
+{ op_11c0_0_comp_nf, 4544, 0x00000002 }, /* MOVE */
+{ op_11d0_0_comp_nf, 4560, 0x00000002 }, /* MOVE */
+{ op_11d8_0_comp_nf, 4568, 0x00000002 }, /* MOVE */
+{ op_11e0_0_comp_nf, 4576, 0x00000002 }, /* MOVE */
+{ op_11e8_0_comp_nf, 4584, 0x00000002 }, /* MOVE */
+{ op_11f0_0_comp_nf, 4592, 0x00000002 }, /* MOVE */
+{ op_11f8_0_comp_nf, 4600, 0x00000002 }, /* MOVE */
+{ op_11f9_0_comp_nf, 4601, 0x00000002 }, /* MOVE */
+{ op_11fa_0_comp_nf, 4602, 0x00000002 }, /* MOVE */
+{ op_11fb_0_comp_nf, 4603, 0x00000002 }, /* MOVE */
+{ op_11fc_0_comp_nf, 4604, 0x00000002 }, /* MOVE */
+{ op_13c0_0_comp_nf, 5056, 0x00000002 }, /* MOVE */
+{ op_13d0_0_comp_nf, 5072, 0x00000002 }, /* MOVE */
+{ op_13d8_0_comp_nf, 5080, 0x00000002 }, /* MOVE */
+{ op_13e0_0_comp_nf, 5088, 0x00000002 }, /* MOVE */
+{ op_13e8_0_comp_nf, 5096, 0x00000002 }, /* MOVE */
+{ op_13f0_0_comp_nf, 5104, 0x00000002 }, /* MOVE */
+{ op_13f8_0_comp_nf, 5112, 0x00000002 }, /* MOVE */
+{ op_13f9_0_comp_nf, 5113, 0x00000002 }, /* MOVE */
+{ op_13fa_0_comp_nf, 5114, 0x00000002 }, /* MOVE */
+{ op_13fb_0_comp_nf, 5115, 0x00000002 }, /* MOVE */
+{ op_13fc_0_comp_nf, 5116, 0x00000002 }, /* MOVE */
+{ op_2000_0_comp_nf, 8192, 0x00000000 }, /* MOVE */
+{ op_2008_0_comp_nf, 8200, 0x00000000 }, /* MOVE */
+{ op_2010_0_comp_nf, 8208, 0x00000000 }, /* MOVE */
+{ op_2018_0_comp_nf, 8216, 0x00000000 }, /* MOVE */
+{ op_2020_0_comp_nf, 8224, 0x00000000 }, /* MOVE */
+{ op_2028_0_comp_nf, 8232, 0x00000002 }, /* MOVE */
+{ op_2030_0_comp_nf, 8240, 0x00000002 }, /* MOVE */
+{ op_2038_0_comp_nf, 8248, 0x00000002 }, /* MOVE */
+{ op_2039_0_comp_nf, 8249, 0x00000002 }, /* MOVE */
+{ op_203a_0_comp_nf, 8250, 0x00000002 }, /* MOVE */
+{ op_203b_0_comp_nf, 8251, 0x00000002 }, /* MOVE */
+{ op_203c_0_comp_nf, 8252, 0x00000002 }, /* MOVE */
+{ op_2040_0_comp_nf, 8256, 0x00000000 }, /* MOVEA */
+{ op_2048_0_comp_nf, 8264, 0x00000000 }, /* MOVEA */
+{ op_2050_0_comp_nf, 8272, 0x00000000 }, /* MOVEA */
+{ op_2058_0_comp_nf, 8280, 0x00000000 }, /* MOVEA */
+{ op_2060_0_comp_nf, 8288, 0x00000000 }, /* MOVEA */
+{ op_2068_0_comp_nf, 8296, 0x00000002 }, /* MOVEA */
+{ op_2070_0_comp_nf, 8304, 0x00000002 }, /* MOVEA */
+{ op_2078_0_comp_nf, 8312, 0x00000002 }, /* MOVEA */
+{ op_2079_0_comp_nf, 8313, 0x00000002 }, /* MOVEA */
+{ op_207a_0_comp_nf, 8314, 0x00000002 }, /* MOVEA */
+{ op_207b_0_comp_nf, 8315, 0x00000002 }, /* MOVEA */
+{ op_207c_0_comp_nf, 8316, 0x00000002 }, /* MOVEA */
+{ op_2080_0_comp_nf, 8320, 0x00000000 }, /* MOVE */
+{ op_2088_0_comp_nf, 8328, 0x00000000 }, /* MOVE */
+{ op_2090_0_comp_nf, 8336, 0x00000000 }, /* MOVE */
+{ op_2098_0_comp_nf, 8344, 0x00000000 }, /* MOVE */
+{ op_20a0_0_comp_nf, 8352, 0x00000000 }, /* MOVE */
+{ op_20a8_0_comp_nf, 8360, 0x00000002 }, /* MOVE */
+{ op_20b0_0_comp_nf, 8368, 0x00000002 }, /* MOVE */
+{ op_20b8_0_comp_nf, 8376, 0x00000002 }, /* MOVE */
+{ op_20b9_0_comp_nf, 8377, 0x00000002 }, /* MOVE */
+{ op_20ba_0_comp_nf, 8378, 0x00000002 }, /* MOVE */
+{ op_20bb_0_comp_nf, 8379, 0x00000002 }, /* MOVE */
+{ op_20bc_0_comp_nf, 8380, 0x00000002 }, /* MOVE */
+{ op_20c0_0_comp_nf, 8384, 0x00000000 }, /* MOVE */
+{ op_20c8_0_comp_nf, 8392, 0x00000000 }, /* MOVE */
+{ op_20d0_0_comp_nf, 8400, 0x00000000 }, /* MOVE */
+{ op_20d8_0_comp_nf, 8408, 0x00000000 }, /* MOVE */
+{ op_20e0_0_comp_nf, 8416, 0x00000000 }, /* MOVE */
+{ op_20e8_0_comp_nf, 8424, 0x00000002 }, /* MOVE */
+{ op_20f0_0_comp_nf, 8432, 0x00000002 }, /* MOVE */
+{ op_20f8_0_comp_nf, 8440, 0x00000002 }, /* MOVE */
+{ op_20f9_0_comp_nf, 8441, 0x00000002 }, /* MOVE */
+{ op_20fa_0_comp_nf, 8442, 0x00000002 }, /* MOVE */
+{ op_20fb_0_comp_nf, 8443, 0x00000002 }, /* MOVE */
+{ op_20fc_0_comp_nf, 8444, 0x00000002 }, /* MOVE */
+{ op_2100_0_comp_nf, 8448, 0x00000000 }, /* MOVE */
+{ op_2108_0_comp_nf, 8456, 0x00000000 }, /* MOVE */
+{ op_2110_0_comp_nf, 8464, 0x00000000 }, /* MOVE */
+{ op_2118_0_comp_nf, 8472, 0x00000000 }, /* MOVE */
+{ op_2120_0_comp_nf, 8480, 0x00000000 }, /* MOVE */
+{ op_2128_0_comp_nf, 8488, 0x00000002 }, /* MOVE */
+{ op_2130_0_comp_nf, 8496, 0x00000002 }, /* MOVE */
+{ op_2138_0_comp_nf, 8504, 0x00000002 }, /* MOVE */
+{ op_2139_0_comp_nf, 8505, 0x00000002 }, /* MOVE */
+{ op_213a_0_comp_nf, 8506, 0x00000002 }, /* MOVE */
+{ op_213b_0_comp_nf, 8507, 0x00000002 }, /* MOVE */
+{ op_213c_0_comp_nf, 8508, 0x00000002 }, /* MOVE */
+{ op_2140_0_comp_nf, 8512, 0x00000002 }, /* MOVE */
+{ op_2148_0_comp_nf, 8520, 0x00000002 }, /* MOVE */
+{ op_2150_0_comp_nf, 8528, 0x00000002 }, /* MOVE */
+{ op_2158_0_comp_nf, 8536, 0x00000002 }, /* MOVE */
+{ op_2160_0_comp_nf, 8544, 0x00000002 }, /* MOVE */
+{ op_2168_0_comp_nf, 8552, 0x00000002 }, /* MOVE */
+{ op_2170_0_comp_nf, 8560, 0x00000002 }, /* MOVE */
+{ op_2178_0_comp_nf, 8568, 0x00000002 }, /* MOVE */
+{ op_2179_0_comp_nf, 8569, 0x00000002 }, /* MOVE */
+{ op_217a_0_comp_nf, 8570, 0x00000002 }, /* MOVE */
+{ op_217b_0_comp_nf, 8571, 0x00000002 }, /* MOVE */
+{ op_217c_0_comp_nf, 8572, 0x00000002 }, /* MOVE */
+{ op_2180_0_comp_nf, 8576, 0x00000002 }, /* MOVE */
+{ op_2188_0_comp_nf, 8584, 0x00000002 }, /* MOVE */
+{ op_2190_0_comp_nf, 8592, 0x00000002 }, /* MOVE */
+{ op_2198_0_comp_nf, 8600, 0x00000002 }, /* MOVE */
+{ op_21a0_0_comp_nf, 8608, 0x00000002 }, /* MOVE */
+{ op_21a8_0_comp_nf, 8616, 0x00000002 }, /* MOVE */
+{ op_21b0_0_comp_nf, 8624, 0x00000002 }, /* MOVE */
+{ op_21b8_0_comp_nf, 8632, 0x00000002 }, /* MOVE */
+{ op_21b9_0_comp_nf, 8633, 0x00000002 }, /* MOVE */
+{ op_21ba_0_comp_nf, 8634, 0x00000002 }, /* MOVE */
+{ op_21bb_0_comp_nf, 8635, 0x00000002 }, /* MOVE */
+{ op_21bc_0_comp_nf, 8636, 0x00000002 }, /* MOVE */
+{ op_21c0_0_comp_nf, 8640, 0x00000002 }, /* MOVE */
+{ op_21c8_0_comp_nf, 8648, 0x00000002 }, /* MOVE */
+{ op_21d0_0_comp_nf, 8656, 0x00000002 }, /* MOVE */
+{ op_21d8_0_comp_nf, 8664, 0x00000002 }, /* MOVE */
+{ op_21e0_0_comp_nf, 8672, 0x00000002 }, /* MOVE */
+{ op_21e8_0_comp_nf, 8680, 0x00000002 }, /* MOVE */
+{ op_21f0_0_comp_nf, 8688, 0x00000002 }, /* MOVE */
+{ op_21f8_0_comp_nf, 8696, 0x00000002 }, /* MOVE */
+{ op_21f9_0_comp_nf, 8697, 0x00000002 }, /* MOVE */
+{ op_21fa_0_comp_nf, 8698, 0x00000002 }, /* MOVE */
+{ op_21fb_0_comp_nf, 8699, 0x00000002 }, /* MOVE */
+{ op_21fc_0_comp_nf, 8700, 0x00000002 }, /* MOVE */
+{ op_23c0_0_comp_nf, 9152, 0x00000002 }, /* MOVE */
+{ op_23c8_0_comp_nf, 9160, 0x00000002 }, /* MOVE */
+{ op_23d0_0_comp_nf, 9168, 0x00000002 }, /* MOVE */
+{ op_23d8_0_comp_nf, 9176, 0x00000002 }, /* MOVE */
+{ op_23e0_0_comp_nf, 9184, 0x00000002 }, /* MOVE */
+{ op_23e8_0_comp_nf, 9192, 0x00000002 }, /* MOVE */
+{ op_23f0_0_comp_nf, 9200, 0x00000002 }, /* MOVE */
+{ op_23f8_0_comp_nf, 9208, 0x00000002 }, /* MOVE */
+{ op_23f9_0_comp_nf, 9209, 0x00000002 }, /* MOVE */
+{ op_23fa_0_comp_nf, 9210, 0x00000002 }, /* MOVE */
+{ op_23fb_0_comp_nf, 9211, 0x00000002 }, /* MOVE */
+{ op_23fc_0_comp_nf, 9212, 0x00000002 }, /* MOVE */
+{ op_3000_0_comp_nf, 12288, 0x00000000 }, /* MOVE */
+{ op_3008_0_comp_nf, 12296, 0x00000000 }, /* MOVE */
+{ op_3010_0_comp_nf, 12304, 0x00000000 }, /* MOVE */
+{ op_3018_0_comp_nf, 12312, 0x00000000 }, /* MOVE */
+{ op_3020_0_comp_nf, 12320, 0x00000000 }, /* MOVE */
+{ op_3028_0_comp_nf, 12328, 0x00000002 }, /* MOVE */
+{ op_3030_0_comp_nf, 12336, 0x00000002 }, /* MOVE */
+{ op_3038_0_comp_nf, 12344, 0x00000002 }, /* MOVE */
+{ op_3039_0_comp_nf, 12345, 0x00000002 }, /* MOVE */
+{ op_303a_0_comp_nf, 12346, 0x00000002 }, /* MOVE */
+{ op_303b_0_comp_nf, 12347, 0x00000002 }, /* MOVE */
+{ op_303c_0_comp_nf, 12348, 0x00000002 }, /* MOVE */
+{ op_3040_0_comp_nf, 12352, 0x00000000 }, /* MOVEA */
+{ op_3048_0_comp_nf, 12360, 0x00000000 }, /* MOVEA */
+{ op_3050_0_comp_nf, 12368, 0x00000000 }, /* MOVEA */
+{ op_3058_0_comp_nf, 12376, 0x00000000 }, /* MOVEA */
+{ op_3060_0_comp_nf, 12384, 0x00000000 }, /* MOVEA */
+{ op_3068_0_comp_nf, 12392, 0x00000002 }, /* MOVEA */
+{ op_3070_0_comp_nf, 12400, 0x00000002 }, /* MOVEA */
+{ op_3078_0_comp_nf, 12408, 0x00000002 }, /* MOVEA */
+{ op_3079_0_comp_nf, 12409, 0x00000002 }, /* MOVEA */
+{ op_307a_0_comp_nf, 12410, 0x00000002 }, /* MOVEA */
+{ op_307b_0_comp_nf, 12411, 0x00000002 }, /* MOVEA */
+{ op_307c_0_comp_nf, 12412, 0x00000002 }, /* MOVEA */
+{ op_3080_0_comp_nf, 12416, 0x00000000 }, /* MOVE */
+{ op_3088_0_comp_nf, 12424, 0x00000000 }, /* MOVE */
+{ op_3090_0_comp_nf, 12432, 0x00000000 }, /* MOVE */
+{ op_3098_0_comp_nf, 12440, 0x00000000 }, /* MOVE */
+{ op_30a0_0_comp_nf, 12448, 0x00000000 }, /* MOVE */
+{ op_30a8_0_comp_nf, 12456, 0x00000002 }, /* MOVE */
+{ op_30b0_0_comp_nf, 12464, 0x00000002 }, /* MOVE */
+{ op_30b8_0_comp_nf, 12472, 0x00000002 }, /* MOVE */
+{ op_30b9_0_comp_nf, 12473, 0x00000002 }, /* MOVE */
+{ op_30ba_0_comp_nf, 12474, 0x00000002 }, /* MOVE */
+{ op_30bb_0_comp_nf, 12475, 0x00000002 }, /* MOVE */
+{ op_30bc_0_comp_nf, 12476, 0x00000002 }, /* MOVE */
+{ op_30c0_0_comp_nf, 12480, 0x00000000 }, /* MOVE */
+{ op_30c8_0_comp_nf, 12488, 0x00000000 }, /* MOVE */
+{ op_30d0_0_comp_nf, 12496, 0x00000000 }, /* MOVE */
+{ op_30d8_0_comp_nf, 12504, 0x00000000 }, /* MOVE */
+{ op_30e0_0_comp_nf, 12512, 0x00000000 }, /* MOVE */
+{ op_30e8_0_comp_nf, 12520, 0x00000002 }, /* MOVE */
+{ op_30f0_0_comp_nf, 12528, 0x00000002 }, /* MOVE */
+{ op_30f8_0_comp_nf, 12536, 0x00000002 }, /* MOVE */
+{ op_30f9_0_comp_nf, 12537, 0x00000002 }, /* MOVE */
+{ op_30fa_0_comp_nf, 12538, 0x00000002 }, /* MOVE */
+{ op_30fb_0_comp_nf, 12539, 0x00000002 }, /* MOVE */
+{ op_30fc_0_comp_nf, 12540, 0x00000002 }, /* MOVE */
+{ op_3100_0_comp_nf, 12544, 0x00000000 }, /* MOVE */
+{ op_3108_0_comp_nf, 12552, 0x00000000 }, /* MOVE */
+{ op_3110_0_comp_nf, 12560, 0x00000000 }, /* MOVE */
+{ op_3118_0_comp_nf, 12568, 0x00000000 }, /* MOVE */
+{ op_3120_0_comp_nf, 12576, 0x00000000 }, /* MOVE */
+{ op_3128_0_comp_nf, 12584, 0x00000002 }, /* MOVE */
+{ op_3130_0_comp_nf, 12592, 0x00000002 }, /* MOVE */
+{ op_3138_0_comp_nf, 12600, 0x00000002 }, /* MOVE */
+{ op_3139_0_comp_nf, 12601, 0x00000002 }, /* MOVE */
+{ op_313a_0_comp_nf, 12602, 0x00000002 }, /* MOVE */
+{ op_313b_0_comp_nf, 12603, 0x00000002 }, /* MOVE */
+{ op_313c_0_comp_nf, 12604, 0x00000002 }, /* MOVE */
+{ op_3140_0_comp_nf, 12608, 0x00000002 }, /* MOVE */
+{ op_3148_0_comp_nf, 12616, 0x00000002 }, /* MOVE */
+{ op_3150_0_comp_nf, 12624, 0x00000002 }, /* MOVE */
+{ op_3158_0_comp_nf, 12632, 0x00000002 }, /* MOVE */
+{ op_3160_0_comp_nf, 12640, 0x00000002 }, /* MOVE */
+{ op_3168_0_comp_nf, 12648, 0x00000002 }, /* MOVE */
+{ op_3170_0_comp_nf, 12656, 0x00000002 }, /* MOVE */
+{ op_3178_0_comp_nf, 12664, 0x00000002 }, /* MOVE */
+{ op_3179_0_comp_nf, 12665, 0x00000002 }, /* MOVE */
+{ op_317a_0_comp_nf, 12666, 0x00000002 }, /* MOVE */
+{ op_317b_0_comp_nf, 12667, 0x00000002 }, /* MOVE */
+{ op_317c_0_comp_nf, 12668, 0x00000002 }, /* MOVE */
+{ op_3180_0_comp_nf, 12672, 0x00000002 }, /* MOVE */
+{ op_3188_0_comp_nf, 12680, 0x00000002 }, /* MOVE */
+{ op_3190_0_comp_nf, 12688, 0x00000002 }, /* MOVE */
+{ op_3198_0_comp_nf, 12696, 0x00000002 }, /* MOVE */
+{ op_31a0_0_comp_nf, 12704, 0x00000002 }, /* MOVE */
+{ op_31a8_0_comp_nf, 12712, 0x00000002 }, /* MOVE */
+{ op_31b0_0_comp_nf, 12720, 0x00000002 }, /* MOVE */
+{ op_31b8_0_comp_nf, 12728, 0x00000002 }, /* MOVE */
+{ op_31b9_0_comp_nf, 12729, 0x00000002 }, /* MOVE */
+{ op_31ba_0_comp_nf, 12730, 0x00000002 }, /* MOVE */
+{ op_31bb_0_comp_nf, 12731, 0x00000002 }, /* MOVE */
+{ op_31bc_0_comp_nf, 12732, 0x00000002 }, /* MOVE */
+{ op_31c0_0_comp_nf, 12736, 0x00000002 }, /* MOVE */
+{ op_31c8_0_comp_nf, 12744, 0x00000002 }, /* MOVE */
+{ op_31d0_0_comp_nf, 12752, 0x00000002 }, /* MOVE */
+{ op_31d8_0_comp_nf, 12760, 0x00000002 }, /* MOVE */
+{ op_31e0_0_comp_nf, 12768, 0x00000002 }, /* MOVE */
+{ op_31e8_0_comp_nf, 12776, 0x00000002 }, /* MOVE */
+{ op_31f0_0_comp_nf, 12784, 0x00000002 }, /* MOVE */
+{ op_31f8_0_comp_nf, 12792, 0x00000002 }, /* MOVE */
+{ op_31f9_0_comp_nf, 12793, 0x00000002 }, /* MOVE */
+{ op_31fa_0_comp_nf, 12794, 0x00000002 }, /* MOVE */
+{ op_31fb_0_comp_nf, 12795, 0x00000002 }, /* MOVE */
+{ op_31fc_0_comp_nf, 12796, 0x00000002 }, /* MOVE */
+{ op_33c0_0_comp_nf, 13248, 0x00000002 }, /* MOVE */
+{ op_33c8_0_comp_nf, 13256, 0x00000002 }, /* MOVE */
+{ op_33d0_0_comp_nf, 13264, 0x00000002 }, /* MOVE */
+{ op_33d8_0_comp_nf, 13272, 0x00000002 }, /* MOVE */
+{ op_33e0_0_comp_nf, 13280, 0x00000002 }, /* MOVE */
+{ op_33e8_0_comp_nf, 13288, 0x00000002 }, /* MOVE */
+{ op_33f0_0_comp_nf, 13296, 0x00000002 }, /* MOVE */
+{ op_33f8_0_comp_nf, 13304, 0x00000002 }, /* MOVE */
+{ op_33f9_0_comp_nf, 13305, 0x00000002 }, /* MOVE */
+{ op_33fa_0_comp_nf, 13306, 0x00000002 }, /* MOVE */
+{ op_33fb_0_comp_nf, 13307, 0x00000002 }, /* MOVE */
+{ op_33fc_0_comp_nf, 13308, 0x00000002 }, /* MOVE */
+{ op_4000_0_comp_nf, 16384, 0x00000008 }, /* NEGX */
+{ op_4010_0_comp_nf, 16400, 0x00000008 }, /* NEGX */
+{ op_4018_0_comp_nf, 16408, 0x00000008 }, /* NEGX */
+{ op_4020_0_comp_nf, 16416, 0x00000008 }, /* NEGX */
+{ op_4028_0_comp_nf, 16424, 0x0000000a }, /* NEGX */
+{ op_4030_0_comp_nf, 16432, 0x0000000a }, /* NEGX */
+{ op_4038_0_comp_nf, 16440, 0x0000000a }, /* NEGX */
+{ op_4039_0_comp_nf, 16441, 0x0000000a }, /* NEGX */
+{ op_4040_0_comp_nf, 16448, 0x00000008 }, /* NEGX */
+{ op_4050_0_comp_nf, 16464, 0x00000008 }, /* NEGX */
+{ op_4058_0_comp_nf, 16472, 0x00000008 }, /* NEGX */
+{ op_4060_0_comp_nf, 16480, 0x00000008 }, /* NEGX */
+{ op_4068_0_comp_nf, 16488, 0x0000000a }, /* NEGX */
+{ op_4070_0_comp_nf, 16496, 0x0000000a }, /* NEGX */
+{ op_4078_0_comp_nf, 16504, 0x0000000a }, /* NEGX */
+{ op_4079_0_comp_nf, 16505, 0x0000000a }, /* NEGX */
+{ op_4080_0_comp_nf, 16512, 0x00000008 }, /* NEGX */
+{ op_4090_0_comp_nf, 16528, 0x00000008 }, /* NEGX */
+{ op_4098_0_comp_nf, 16536, 0x00000008 }, /* NEGX */
+{ op_40a0_0_comp_nf, 16544, 0x00000008 }, /* NEGX */
+{ op_40a8_0_comp_nf, 16552, 0x0000000a }, /* NEGX */
+{ op_40b0_0_comp_nf, 16560, 0x0000000a }, /* NEGX */
+{ op_40b8_0_comp_nf, 16568, 0x0000000a }, /* NEGX */
+{ op_40b9_0_comp_nf, 16569, 0x0000000a }, /* NEGX */
+{ NULL, 16576, 0x00000001 }, /* MVSR2 */
+{ NULL, 16592, 0x00000001 }, /* MVSR2 */
+{ NULL, 16600, 0x00000001 }, /* MVSR2 */
+{ NULL, 16608, 0x00000001 }, /* MVSR2 */
+{ NULL, 16616, 0x00000001 }, /* MVSR2 */
+{ NULL, 16624, 0x00000001 }, /* MVSR2 */
+{ NULL, 16632, 0x00000001 }, /* MVSR2 */
+{ NULL, 16633, 0x00000001 }, /* MVSR2 */
+{ NULL, 16640, 0x00000001 }, /* CHK */
+{ NULL, 16656, 0x00000001 }, /* CHK */
+{ NULL, 16664, 0x00000001 }, /* CHK */
+{ NULL, 16672, 0x00000001 }, /* CHK */
+{ NULL, 16680, 0x00000001 }, /* CHK */
+{ NULL, 16688, 0x00000001 }, /* CHK */
+{ NULL, 16696, 0x00000001 }, /* CHK */
+{ NULL, 16697, 0x00000001 }, /* CHK */
+{ NULL, 16698, 0x00000001 }, /* CHK */
+{ NULL, 16699, 0x00000001 }, /* CHK */
+{ NULL, 16700, 0x00000001 }, /* CHK */
+{ NULL, 16768, 0x00000001 }, /* CHK */
+{ NULL, 16784, 0x00000001 }, /* CHK */
+{ NULL, 16792, 0x00000001 }, /* CHK */
+{ NULL, 16800, 0x00000001 }, /* CHK */
+{ NULL, 16808, 0x00000001 }, /* CHK */
+{ NULL, 16816, 0x00000001 }, /* CHK */
+{ NULL, 16824, 0x00000001 }, /* CHK */
+{ NULL, 16825, 0x00000001 }, /* CHK */
+{ NULL, 16826, 0x00000001 }, /* CHK */
+{ NULL, 16827, 0x00000001 }, /* CHK */
+{ NULL, 16828, 0x00000001 }, /* CHK */
+{ op_41d0_0_comp_nf, 16848, 0x00000000 }, /* LEA */
+{ op_41e8_0_comp_nf, 16872, 0x00000002 }, /* LEA */
+{ op_41f0_0_comp_nf, 16880, 0x00000002 }, /* LEA */
+{ op_41f8_0_comp_nf, 16888, 0x00000002 }, /* LEA */
+{ op_41f9_0_comp_nf, 16889, 0x00000002 }, /* LEA */
+{ op_41fa_0_comp_nf, 16890, 0x00000002 }, /* LEA */
+{ op_41fb_0_comp_nf, 16891, 0x00000002 }, /* LEA */
+{ op_4200_0_comp_nf, 16896, 0x00000000 }, /* CLR */
+{ op_4210_0_comp_nf, 16912, 0x00000000 }, /* CLR */
+{ op_4218_0_comp_nf, 16920, 0x00000000 }, /* CLR */
+{ op_4220_0_comp_nf, 16928, 0x00000000 }, /* CLR */
+{ op_4228_0_comp_nf, 16936, 0x00000002 }, /* CLR */
+{ op_4230_0_comp_nf, 16944, 0x00000002 }, /* CLR */
+{ op_4238_0_comp_nf, 16952, 0x00000002 }, /* CLR */
+{ op_4239_0_comp_nf, 16953, 0x00000002 }, /* CLR */
+{ op_4240_0_comp_nf, 16960, 0x00000000 }, /* CLR */
+{ op_4250_0_comp_nf, 16976, 0x00000000 }, /* CLR */
+{ op_4258_0_comp_nf, 16984, 0x00000000 }, /* CLR */
+{ op_4260_0_comp_nf, 16992, 0x00000000 }, /* CLR */
+{ op_4268_0_comp_nf, 17000, 0x00000002 }, /* CLR */
+{ op_4270_0_comp_nf, 17008, 0x00000002 }, /* CLR */
+{ op_4278_0_comp_nf, 17016, 0x00000002 }, /* CLR */
+{ op_4279_0_comp_nf, 17017, 0x00000002 }, /* CLR */
+{ op_4280_0_comp_nf, 17024, 0x00000000 }, /* CLR */
+{ op_4290_0_comp_nf, 17040, 0x00000000 }, /* CLR */
+{ op_4298_0_comp_nf, 17048, 0x00000000 }, /* CLR */
+{ op_42a0_0_comp_nf, 17056, 0x00000000 }, /* CLR */
+{ op_42a8_0_comp_nf, 17064, 0x00000002 }, /* CLR */
+{ op_42b0_0_comp_nf, 17072, 0x00000002 }, /* CLR */
+{ op_42b8_0_comp_nf, 17080, 0x00000002 }, /* CLR */
+{ op_42b9_0_comp_nf, 17081, 0x00000002 }, /* CLR */
+{ NULL, 17088, 0x00000001 }, /* MVSR2 */
+{ NULL, 17104, 0x00000001 }, /* MVSR2 */
+{ NULL, 17112, 0x00000001 }, /* MVSR2 */
+{ NULL, 17120, 0x00000001 }, /* MVSR2 */
+{ NULL, 17128, 0x00000001 }, /* MVSR2 */
+{ NULL, 17136, 0x00000001 }, /* MVSR2 */
+{ NULL, 17144, 0x00000001 }, /* MVSR2 */
+{ NULL, 17145, 0x00000001 }, /* MVSR2 */
+{ op_4400_0_comp_nf, 17408, 0x00000000 }, /* NEG */
+{ op_4410_0_comp_nf, 17424, 0x00000000 }, /* NEG */
+{ op_4418_0_comp_nf, 17432, 0x00000000 }, /* NEG */
+{ op_4420_0_comp_nf, 17440, 0x00000000 }, /* NEG */
+{ op_4428_0_comp_nf, 17448, 0x00000002 }, /* NEG */
+{ op_4430_0_comp_nf, 17456, 0x00000002 }, /* NEG */
+{ op_4438_0_comp_nf, 17464, 0x00000002 }, /* NEG */
+{ op_4439_0_comp_nf, 17465, 0x00000002 }, /* NEG */
+{ op_4440_0_comp_nf, 17472, 0x00000000 }, /* NEG */
+{ op_4450_0_comp_nf, 17488, 0x00000000 }, /* NEG */
+{ op_4458_0_comp_nf, 17496, 0x00000000 }, /* NEG */
+{ op_4460_0_comp_nf, 17504, 0x00000000 }, /* NEG */
+{ op_4468_0_comp_nf, 17512, 0x00000002 }, /* NEG */
+{ op_4470_0_comp_nf, 17520, 0x00000002 }, /* NEG */
+{ op_4478_0_comp_nf, 17528, 0x00000002 }, /* NEG */
+{ op_4479_0_comp_nf, 17529, 0x00000002 }, /* NEG */
+{ op_4480_0_comp_nf, 17536, 0x00000000 }, /* NEG */
+{ op_4490_0_comp_nf, 17552, 0x00000000 }, /* NEG */
+{ op_4498_0_comp_nf, 17560, 0x00000000 }, /* NEG */
+{ op_44a0_0_comp_nf, 17568, 0x00000000 }, /* NEG */
+{ op_44a8_0_comp_nf, 17576, 0x00000002 }, /* NEG */
+{ op_44b0_0_comp_nf, 17584, 0x00000002 }, /* NEG */
+{ op_44b8_0_comp_nf, 17592, 0x00000002 }, /* NEG */
+{ op_44b9_0_comp_nf, 17593, 0x00000002 }, /* NEG */
+{ NULL, 17600, 0x00000001 }, /* MV2SR */
+{ NULL, 17616, 0x00000001 }, /* MV2SR */
+{ NULL, 17624, 0x00000001 }, /* MV2SR */
+{ NULL, 17632, 0x00000001 }, /* MV2SR */
+{ NULL, 17640, 0x00000001 }, /* MV2SR */
+{ NULL, 17648, 0x00000001 }, /* MV2SR */
+{ NULL, 17656, 0x00000001 }, /* MV2SR */
+{ NULL, 17657, 0x00000001 }, /* MV2SR */
+{ NULL, 17658, 0x00000001 }, /* MV2SR */
+{ NULL, 17659, 0x00000001 }, /* MV2SR */
+{ NULL, 17660, 0x00000001 }, /* MV2SR */
+{ op_4600_0_comp_nf, 17920, 0x00000000 }, /* NOT */
+{ op_4610_0_comp_nf, 17936, 0x00000000 }, /* NOT */
+{ op_4618_0_comp_nf, 17944, 0x00000000 }, /* NOT */
+{ op_4620_0_comp_nf, 17952, 0x00000000 }, /* NOT */
+{ op_4628_0_comp_nf, 17960, 0x00000002 }, /* NOT */
+{ op_4630_0_comp_nf, 17968, 0x00000002 }, /* NOT */
+{ op_4638_0_comp_nf, 17976, 0x00000002 }, /* NOT */
+{ op_4639_0_comp_nf, 17977, 0x00000002 }, /* NOT */
+{ op_4640_0_comp_nf, 17984, 0x00000000 }, /* NOT */
+{ op_4650_0_comp_nf, 18000, 0x00000000 }, /* NOT */
+{ op_4658_0_comp_nf, 18008, 0x00000000 }, /* NOT */
+{ op_4660_0_comp_nf, 18016, 0x00000000 }, /* NOT */
+{ op_4668_0_comp_nf, 18024, 0x00000002 }, /* NOT */
+{ op_4670_0_comp_nf, 18032, 0x00000002 }, /* NOT */
+{ op_4678_0_comp_nf, 18040, 0x00000002 }, /* NOT */
+{ op_4679_0_comp_nf, 18041, 0x00000002 }, /* NOT */
+{ op_4680_0_comp_nf, 18048, 0x00000000 }, /* NOT */
+{ op_4690_0_comp_nf, 18064, 0x00000000 }, /* NOT */
+{ op_4698_0_comp_nf, 18072, 0x00000000 }, /* NOT */
+{ op_46a0_0_comp_nf, 18080, 0x00000000 }, /* NOT */
+{ op_46a8_0_comp_nf, 18088, 0x00000002 }, /* NOT */
+{ op_46b0_0_comp_nf, 18096, 0x00000002 }, /* NOT */
+{ op_46b8_0_comp_nf, 18104, 0x00000002 }, /* NOT */
+{ op_46b9_0_comp_nf, 18105, 0x00000002 }, /* NOT */
+{ NULL, 18112, 0x00000001 }, /* MV2SR */
+{ NULL, 18128, 0x00000001 }, /* MV2SR */
+{ NULL, 18136, 0x00000001 }, /* MV2SR */
+{ NULL, 18144, 0x00000001 }, /* MV2SR */
+{ NULL, 18152, 0x00000001 }, /* MV2SR */
+{ NULL, 18160, 0x00000001 }, /* MV2SR */
+{ NULL, 18168, 0x00000001 }, /* MV2SR */
+{ NULL, 18169, 0x00000001 }, /* MV2SR */
+{ NULL, 18170, 0x00000001 }, /* MV2SR */
+{ NULL, 18171, 0x00000001 }, /* MV2SR */
+{ NULL, 18172, 0x00000001 }, /* MV2SR */
+{ NULL, 18432, 0x00000000 }, /* NBCD */
+{ op_4808_0_comp_nf, 18440, 0x00000002 }, /* LINK */
+{ NULL, 18448, 0x00000000 }, /* NBCD */
+{ NULL, 18456, 0x00000000 }, /* NBCD */
+{ NULL, 18464, 0x00000000 }, /* NBCD */
+{ NULL, 18472, 0x00000000 }, /* NBCD */
+{ NULL, 18480, 0x00000000 }, /* NBCD */
+{ NULL, 18488, 0x00000000 }, /* NBCD */
+{ NULL, 18489, 0x00000000 }, /* NBCD */
+{ op_4840_0_comp_nf, 18496, 0x00000000 }, /* SWAP */
+{ NULL, 18504, 0x00000001 }, /* BKPT */
+{ op_4850_0_comp_nf, 18512, 0x00000000 }, /* PEA */
+{ op_4868_0_comp_nf, 18536, 0x00000002 }, /* PEA */
+{ op_4870_0_comp_nf, 18544, 0x00000002 }, /* PEA */
+{ op_4878_0_comp_nf, 18552, 0x00000002 }, /* PEA */
+{ op_4879_0_comp_nf, 18553, 0x00000002 }, /* PEA */
+{ op_487a_0_comp_nf, 18554, 0x00000002 }, /* PEA */
+{ op_487b_0_comp_nf, 18555, 0x00000002 }, /* PEA */
+{ op_4880_0_comp_nf, 18560, 0x00000000 }, /* EXT */
+{ op_4890_0_comp_nf, 18576, 0x00000002 }, /* MVMLE */
+{ op_48a0_0_comp_nf, 18592, 0x00000002 }, /* MVMLE */
+{ op_48a8_0_comp_nf, 18600, 0x00000002 }, /* MVMLE */
+{ op_48b0_0_comp_nf, 18608, 0x00000002 }, /* MVMLE */
+{ op_48b8_0_comp_nf, 18616, 0x00000002 }, /* MVMLE */
+{ op_48b9_0_comp_nf, 18617, 0x00000002 }, /* MVMLE */
+{ op_48c0_0_comp_nf, 18624, 0x00000000 }, /* EXT */
+{ op_48d0_0_comp_nf, 18640, 0x00000002 }, /* MVMLE */
+{ op_48e0_0_comp_nf, 18656, 0x00000002 }, /* MVMLE */
+{ op_48e8_0_comp_nf, 18664, 0x00000002 }, /* MVMLE */
+{ op_48f0_0_comp_nf, 18672, 0x00000002 }, /* MVMLE */
+{ op_48f8_0_comp_nf, 18680, 0x00000002 }, /* MVMLE */
+{ op_48f9_0_comp_nf, 18681, 0x00000002 }, /* MVMLE */
+{ op_49c0_0_comp_nf, 18880, 0x00000000 }, /* EXT */
+{ op_4a00_0_comp_nf, 18944, 0x00000000 }, /* TST */
+{ op_4a10_0_comp_nf, 18960, 0x00000000 }, /* TST */
+{ op_4a18_0_comp_nf, 18968, 0x00000000 }, /* TST */
+{ op_4a20_0_comp_nf, 18976, 0x00000000 }, /* TST */
+{ op_4a28_0_comp_nf, 18984, 0x00000002 }, /* TST */
+{ op_4a30_0_comp_nf, 18992, 0x00000002 }, /* TST */
+{ op_4a38_0_comp_nf, 19000, 0x00000002 }, /* TST */
+{ op_4a39_0_comp_nf, 19001, 0x00000002 }, /* TST */
+{ op_4a3a_0_comp_nf, 19002, 0x00000002 }, /* TST */
+{ op_4a3b_0_comp_nf, 19003, 0x00000002 }, /* TST */
+{ op_4a3c_0_comp_nf, 19004, 0x00000002 }, /* TST */
+{ op_4a40_0_comp_nf, 19008, 0x00000000 }, /* TST */
+{ op_4a48_0_comp_nf, 19016, 0x00000000 }, /* TST */
+{ op_4a50_0_comp_nf, 19024, 0x00000000 }, /* TST */
+{ op_4a58_0_comp_nf, 19032, 0x00000000 }, /* TST */
+{ op_4a60_0_comp_nf, 19040, 0x00000000 }, /* TST */
+{ op_4a68_0_comp_nf, 19048, 0x00000002 }, /* TST */
+{ op_4a70_0_comp_nf, 19056, 0x00000002 }, /* TST */
+{ op_4a78_0_comp_nf, 19064, 0x00000002 }, /* TST */
+{ op_4a79_0_comp_nf, 19065, 0x00000002 }, /* TST */
+{ op_4a7a_0_comp_nf, 19066, 0x00000002 }, /* TST */
+{ op_4a7b_0_comp_nf, 19067, 0x00000002 }, /* TST */
+{ op_4a7c_0_comp_nf, 19068, 0x00000002 }, /* TST */
+{ op_4a80_0_comp_nf, 19072, 0x00000000 }, /* TST */
+{ op_4a88_0_comp_nf, 19080, 0x00000000 }, /* TST */
+{ op_4a90_0_comp_nf, 19088, 0x00000000 }, /* TST */
+{ op_4a98_0_comp_nf, 19096, 0x00000000 }, /* TST */
+{ op_4aa0_0_comp_nf, 19104, 0x00000000 }, /* TST */
+{ op_4aa8_0_comp_nf, 19112, 0x00000002 }, /* TST */
+{ op_4ab0_0_comp_nf, 19120, 0x00000002 }, /* TST */
+{ op_4ab8_0_comp_nf, 19128, 0x00000002 }, /* TST */
+{ op_4ab9_0_comp_nf, 19129, 0x00000002 }, /* TST */
+{ op_4aba_0_comp_nf, 19130, 0x00000002 }, /* TST */
+{ op_4abb_0_comp_nf, 19131, 0x00000002 }, /* TST */
+{ op_4abc_0_comp_nf, 19132, 0x00000002 }, /* TST */
+{ NULL, 19136, 0x00000000 }, /* TAS */
+{ NULL, 19152, 0x00000000 }, /* TAS */
+{ NULL, 19160, 0x00000000 }, /* TAS */
+{ NULL, 19168, 0x00000000 }, /* TAS */
+{ NULL, 19176, 0x00000000 }, /* TAS */
+{ NULL, 19184, 0x00000000 }, /* TAS */
+{ NULL, 19192, 0x00000000 }, /* TAS */
+{ NULL, 19193, 0x00000000 }, /* TAS */
+{ op_4c00_0_comp_nf, 19456, 0x00000002 }, /* MULL */
+{ op_4c10_0_comp_nf, 19472, 0x00000002 }, /* MULL */
+{ op_4c18_0_comp_nf, 19480, 0x00000002 }, /* MULL */
+{ op_4c20_0_comp_nf, 19488, 0x00000002 }, /* MULL */
+{ op_4c28_0_comp_nf, 19496, 0x00000002 }, /* MULL */
+{ op_4c30_0_comp_nf, 19504, 0x00000002 }, /* MULL */
+{ op_4c38_0_comp_nf, 19512, 0x00000002 }, /* MULL */
+{ op_4c39_0_comp_nf, 19513, 0x00000002 }, /* MULL */
+{ op_4c3a_0_comp_nf, 19514, 0x00000002 }, /* MULL */
+{ op_4c3b_0_comp_nf, 19515, 0x00000002 }, /* MULL */
+{ op_4c3c_0_comp_nf, 19516, 0x00000002 }, /* MULL */
+{ op_4c40_0_comp_nf, 19520, 0x00000002 }, /* DIVL */
+{ op_4c50_0_comp_nf, 19536, 0x00000002 }, /* DIVL */
+{ op_4c58_0_comp_nf, 19544, 0x00000002 }, /* DIVL */
+{ op_4c60_0_comp_nf, 19552, 0x00000002 }, /* DIVL */
+{ op_4c68_0_comp_nf, 19560, 0x00000002 }, /* DIVL */
+{ op_4c70_0_comp_nf, 19568, 0x00000002 }, /* DIVL */
+{ op_4c78_0_comp_nf, 19576, 0x00000002 }, /* DIVL */
+{ op_4c79_0_comp_nf, 19577, 0x00000002 }, /* DIVL */
+{ op_4c7a_0_comp_nf, 19578, 0x00000002 }, /* DIVL */
+{ op_4c7b_0_comp_nf, 19579, 0x00000002 }, /* DIVL */
+{ op_4c7c_0_comp_nf, 19580, 0x00000002 }, /* DIVL */
+{ op_4c90_0_comp_nf, 19600, 0x00000002 }, /* MVMEL */
+{ op_4c98_0_comp_nf, 19608, 0x00000002 }, /* MVMEL */
+{ op_4ca8_0_comp_nf, 19624, 0x00000002 }, /* MVMEL */
+{ op_4cb0_0_comp_nf, 19632, 0x00000002 }, /* MVMEL */
+{ op_4cb8_0_comp_nf, 19640, 0x00000002 }, /* MVMEL */
+{ op_4cb9_0_comp_nf, 19641, 0x00000002 }, /* MVMEL */
+{ op_4cba_0_comp_nf, 19642, 0x00000002 }, /* MVMEL */
+{ op_4cbb_0_comp_nf, 19643, 0x00000002 }, /* MVMEL */
+{ op_4cd0_0_comp_nf, 19664, 0x00000002 }, /* MVMEL */
+{ op_4cd8_0_comp_nf, 19672, 0x00000002 }, /* MVMEL */
+{ op_4ce8_0_comp_nf, 19688, 0x00000002 }, /* MVMEL */
+{ op_4cf0_0_comp_nf, 19696, 0x00000002 }, /* MVMEL */
+{ op_4cf8_0_comp_nf, 19704, 0x00000002 }, /* MVMEL */
+{ op_4cf9_0_comp_nf, 19705, 0x00000002 }, /* MVMEL */
+{ op_4cfa_0_comp_nf, 19706, 0x00000002 }, /* MVMEL */
+{ op_4cfb_0_comp_nf, 19707, 0x00000002 }, /* MVMEL */
+{ NULL, 20032, 0x00000001 }, /* TRAP */
+{ op_4e50_0_comp_nf, 20048, 0x00000002 }, /* LINK */
+{ op_4e58_0_comp_nf, 20056, 0x00000000 }, /* UNLK */
+{ NULL, 20064, 0x00000001 }, /* MVR2USP */
+{ NULL, 20072, 0x00000001 }, /* MVUSP2R */
+{ NULL, 20080, 0x00000001 }, /* RESET */
+{ op_4e71_0_comp_nf, 20081, 0x00000000 }, /* NOP */
+{ NULL, 20082, 0x00000001 }, /* STOP */
+{ NULL, 20083, 0x00000001 }, /* RTE */
+{ op_4e74_0_comp_nf, 20084, 0x00000003 }, /* RTD */
+{ op_4e75_0_comp_nf, 20085, 0x00000001 }, /* RTS */
+{ NULL, 20086, 0x00000001 }, /* TRAPV */
+{ NULL, 20087, 0x00000001 }, /* RTR */
+{ NULL, 20090, 0x00000001 }, /* MOVEC2 */
+{ NULL, 20091, 0x00000001 }, /* MOVE2C */
+{ op_4e90_0_comp_nf, 20112, 0x00000001 }, /* JSR */
+{ op_4ea8_0_comp_nf, 20136, 0x00000003 }, /* JSR */
+{ op_4eb0_0_comp_nf, 20144, 0x00000003 }, /* JSR */
+{ op_4eb8_0_comp_nf, 20152, 0x00000003 }, /* JSR */
+{ op_4eb9_0_comp_nf, 20153, 0x00000003 }, /* JSR */
+{ op_4eba_0_comp_nf, 20154, 0x00000003 }, /* JSR */
+{ op_4ebb_0_comp_nf, 20155, 0x00000003 }, /* JSR */
+{ op_4ed0_0_comp_nf, 20176, 0x00000001 }, /* JMP */
+{ op_4ee8_0_comp_nf, 20200, 0x00000003 }, /* JMP */
+{ op_4ef0_0_comp_nf, 20208, 0x00000003 }, /* JMP */
+{ op_4ef8_0_comp_nf, 20216, 0x00000003 }, /* JMP */
+{ op_4ef9_0_comp_nf, 20217, 0x00000003 }, /* JMP */
+{ op_4efa_0_comp_nf, 20218, 0x00000003 }, /* JMP */
+{ op_4efb_0_comp_nf, 20219, 0x00000003 }, /* JMP */
+{ op_5000_0_comp_nf, 20480, 0x00000000 }, /* ADD */
+{ op_5010_0_comp_nf, 20496, 0x00000000 }, /* ADD */
+{ op_5018_0_comp_nf, 20504, 0x00000000 }, /* ADD */
+{ op_5020_0_comp_nf, 20512, 0x00000000 }, /* ADD */
+{ op_5028_0_comp_nf, 20520, 0x00000002 }, /* ADD */
+{ op_5030_0_comp_nf, 20528, 0x00000002 }, /* ADD */
+{ op_5038_0_comp_nf, 20536, 0x00000002 }, /* ADD */
+{ op_5039_0_comp_nf, 20537, 0x00000002 }, /* ADD */
+{ op_5040_0_comp_nf, 20544, 0x00000000 }, /* ADD */
+{ op_5048_0_comp_nf, 20552, 0x00000000 }, /* ADDA */
+{ op_5050_0_comp_nf, 20560, 0x00000000 }, /* ADD */
+{ op_5058_0_comp_nf, 20568, 0x00000000 }, /* ADD */
+{ op_5060_0_comp_nf, 20576, 0x00000000 }, /* ADD */
+{ op_5068_0_comp_nf, 20584, 0x00000002 }, /* ADD */
+{ op_5070_0_comp_nf, 20592, 0x00000002 }, /* ADD */
+{ op_5078_0_comp_nf, 20600, 0x00000002 }, /* ADD */
+{ op_5079_0_comp_nf, 20601, 0x00000002 }, /* ADD */
+{ op_5080_0_comp_nf, 20608, 0x00000000 }, /* ADD */
+{ op_5088_0_comp_nf, 20616, 0x00000000 }, /* ADDA */
+{ op_5090_0_comp_nf, 20624, 0x00000000 }, /* ADD */
+{ op_5098_0_comp_nf, 20632, 0x00000000 }, /* ADD */
+{ op_50a0_0_comp_nf, 20640, 0x00000000 }, /* ADD */
+{ op_50a8_0_comp_nf, 20648, 0x00000002 }, /* ADD */
+{ op_50b0_0_comp_nf, 20656, 0x00000002 }, /* ADD */
+{ op_50b8_0_comp_nf, 20664, 0x00000002 }, /* ADD */
+{ op_50b9_0_comp_nf, 20665, 0x00000002 }, /* ADD */
+{ op_50c0_0_comp_nf, 20672, 0x00000000 }, /* Scc */
+{ op_50c8_0_comp_nf, 20680, 0x00000003 }, /* DBcc */
+{ op_50d0_0_comp_nf, 20688, 0x00000000 }, /* Scc */
+{ op_50d8_0_comp_nf, 20696, 0x00000000 }, /* Scc */
+{ op_50e0_0_comp_nf, 20704, 0x00000000 }, /* Scc */
+{ op_50e8_0_comp_nf, 20712, 0x00000002 }, /* Scc */
+{ op_50f0_0_comp_nf, 20720, 0x00000002 }, /* Scc */
+{ op_50f8_0_comp_nf, 20728, 0x00000002 }, /* Scc */
+{ op_50f9_0_comp_nf, 20729, 0x00000002 }, /* Scc */
+{ NULL, 20730, 0x00000001 }, /* TRAPcc */
+{ NULL, 20731, 0x00000001 }, /* TRAPcc */
+{ NULL, 20732, 0x00000001 }, /* TRAPcc */
+{ op_5100_0_comp_nf, 20736, 0x00000000 }, /* SUB */
+{ op_5110_0_comp_nf, 20752, 0x00000000 }, /* SUB */
+{ op_5118_0_comp_nf, 20760, 0x00000000 }, /* SUB */
+{ op_5120_0_comp_nf, 20768, 0x00000000 }, /* SUB */
+{ op_5128_0_comp_nf, 20776, 0x00000002 }, /* SUB */
+{ op_5130_0_comp_nf, 20784, 0x00000002 }, /* SUB */
+{ op_5138_0_comp_nf, 20792, 0x00000002 }, /* SUB */
+{ op_5139_0_comp_nf, 20793, 0x00000002 }, /* SUB */
+{ op_5140_0_comp_nf, 20800, 0x00000000 }, /* SUB */
+{ op_5148_0_comp_nf, 20808, 0x00000000 }, /* SUBA */
+{ op_5150_0_comp_nf, 20816, 0x00000000 }, /* SUB */
+{ op_5158_0_comp_nf, 20824, 0x00000000 }, /* SUB */
+{ op_5160_0_comp_nf, 20832, 0x00000000 }, /* SUB */
+{ op_5168_0_comp_nf, 20840, 0x00000002 }, /* SUB */
+{ op_5170_0_comp_nf, 20848, 0x00000002 }, /* SUB */
+{ op_5178_0_comp_nf, 20856, 0x00000002 }, /* SUB */
+{ op_5179_0_comp_nf, 20857, 0x00000002 }, /* SUB */
+{ op_5180_0_comp_nf, 20864, 0x00000000 }, /* SUB */
+{ op_5188_0_comp_nf, 20872, 0x00000000 }, /* SUBA */
+{ op_5190_0_comp_nf, 20880, 0x00000000 }, /* SUB */
+{ op_5198_0_comp_nf, 20888, 0x00000000 }, /* SUB */
+{ op_51a0_0_comp_nf, 20896, 0x00000000 }, /* SUB */
+{ op_51a8_0_comp_nf, 20904, 0x00000002 }, /* SUB */
+{ op_51b0_0_comp_nf, 20912, 0x00000002 }, /* SUB */
+{ op_51b8_0_comp_nf, 20920, 0x00000002 }, /* SUB */
+{ op_51b9_0_comp_nf, 20921, 0x00000002 }, /* SUB */
+{ op_51c0_0_comp_nf, 20928, 0x00000000 }, /* Scc */
+{ op_51c8_0_comp_nf, 20936, 0x00000003 }, /* DBcc */
+{ op_51d0_0_comp_nf, 20944, 0x00000000 }, /* Scc */
+{ op_51d8_0_comp_nf, 20952, 0x00000000 }, /* Scc */
+{ op_51e0_0_comp_nf, 20960, 0x00000000 }, /* Scc */
+{ op_51e8_0_comp_nf, 20968, 0x00000002 }, /* Scc */
+{ op_51f0_0_comp_nf, 20976, 0x00000002 }, /* Scc */
+{ op_51f8_0_comp_nf, 20984, 0x00000002 }, /* Scc */
+{ op_51f9_0_comp_nf, 20985, 0x00000002 }, /* Scc */
+{ NULL, 20986, 0x00000001 }, /* TRAPcc */
+{ NULL, 20987, 0x00000001 }, /* TRAPcc */
+{ NULL, 20988, 0x00000001 }, /* TRAPcc */
+{ op_52c0_0_comp_nf, 21184, 0x00000000 }, /* Scc */
+{ op_52c8_0_comp_nf, 21192, 0x00000003 }, /* DBcc */
+{ op_52d0_0_comp_nf, 21200, 0x00000000 }, /* Scc */
+{ op_52d8_0_comp_nf, 21208, 0x00000000 }, /* Scc */
+{ op_52e0_0_comp_nf, 21216, 0x00000000 }, /* Scc */
+{ op_52e8_0_comp_nf, 21224, 0x00000002 }, /* Scc */
+{ op_52f0_0_comp_nf, 21232, 0x00000002 }, /* Scc */
+{ op_52f8_0_comp_nf, 21240, 0x00000002 }, /* Scc */
+{ op_52f9_0_comp_nf, 21241, 0x00000002 }, /* Scc */
+{ NULL, 21242, 0x00000001 }, /* TRAPcc */
+{ NULL, 21243, 0x00000001 }, /* TRAPcc */
+{ NULL, 21244, 0x00000001 }, /* TRAPcc */
+{ op_53c0_0_comp_nf, 21440, 0x00000000 }, /* Scc */
+{ op_53c8_0_comp_nf, 21448, 0x00000003 }, /* DBcc */
+{ op_53d0_0_comp_nf, 21456, 0x00000000 }, /* Scc */
+{ op_53d8_0_comp_nf, 21464, 0x00000000 }, /* Scc */
+{ op_53e0_0_comp_nf, 21472, 0x00000000 }, /* Scc */
+{ op_53e8_0_comp_nf, 21480, 0x00000002 }, /* Scc */
+{ op_53f0_0_comp_nf, 21488, 0x00000002 }, /* Scc */
+{ op_53f8_0_comp_nf, 21496, 0x00000002 }, /* Scc */
+{ op_53f9_0_comp_nf, 21497, 0x00000002 }, /* Scc */
+{ NULL, 21498, 0x00000001 }, /* TRAPcc */
+{ NULL, 21499, 0x00000001 }, /* TRAPcc */
+{ NULL, 21500, 0x00000001 }, /* TRAPcc */
+{ op_54c0_0_comp_nf, 21696, 0x00000000 }, /* Scc */
+{ op_54c8_0_comp_nf, 21704, 0x00000003 }, /* DBcc */
+{ op_54d0_0_comp_nf, 21712, 0x00000000 }, /* Scc */
+{ op_54d8_0_comp_nf, 21720, 0x00000000 }, /* Scc */
+{ op_54e0_0_comp_nf, 21728, 0x00000000 }, /* Scc */
+{ op_54e8_0_comp_nf, 21736, 0x00000002 }, /* Scc */
+{ op_54f0_0_comp_nf, 21744, 0x00000002 }, /* Scc */
+{ op_54f8_0_comp_nf, 21752, 0x00000002 }, /* Scc */
+{ op_54f9_0_comp_nf, 21753, 0x00000002 }, /* Scc */
+{ NULL, 21754, 0x00000001 }, /* TRAPcc */
+{ NULL, 21755, 0x00000001 }, /* TRAPcc */
+{ NULL, 21756, 0x00000001 }, /* TRAPcc */
+{ op_55c0_0_comp_nf, 21952, 0x00000000 }, /* Scc */
+{ op_55c8_0_comp_nf, 21960, 0x00000003 }, /* DBcc */
+{ op_55d0_0_comp_nf, 21968, 0x00000000 }, /* Scc */
+{ op_55d8_0_comp_nf, 21976, 0x00000000 }, /* Scc */
+{ op_55e0_0_comp_nf, 21984, 0x00000000 }, /* Scc */
+{ op_55e8_0_comp_nf, 21992, 0x00000002 }, /* Scc */
+{ op_55f0_0_comp_nf, 22000, 0x00000002 }, /* Scc */
+{ op_55f8_0_comp_nf, 22008, 0x00000002 }, /* Scc */
+{ op_55f9_0_comp_nf, 22009, 0x00000002 }, /* Scc */
+{ NULL, 22010, 0x00000001 }, /* TRAPcc */
+{ NULL, 22011, 0x00000001 }, /* TRAPcc */
+{ NULL, 22012, 0x00000001 }, /* TRAPcc */
+{ op_56c0_0_comp_nf, 22208, 0x00000000 }, /* Scc */
+{ op_56c8_0_comp_nf, 22216, 0x00000003 }, /* DBcc */
+{ op_56d0_0_comp_nf, 22224, 0x00000000 }, /* Scc */
+{ op_56d8_0_comp_nf, 22232, 0x00000000 }, /* Scc */
+{ op_56e0_0_comp_nf, 22240, 0x00000000 }, /* Scc */
+{ op_56e8_0_comp_nf, 22248, 0x00000002 }, /* Scc */
+{ op_56f0_0_comp_nf, 22256, 0x00000002 }, /* Scc */
+{ op_56f8_0_comp_nf, 22264, 0x00000002 }, /* Scc */
+{ op_56f9_0_comp_nf, 22265, 0x00000002 }, /* Scc */
+{ NULL, 22266, 0x00000001 }, /* TRAPcc */
+{ NULL, 22267, 0x00000001 }, /* TRAPcc */
+{ NULL, 22268, 0x00000001 }, /* TRAPcc */
+{ op_57c0_0_comp_nf, 22464, 0x00000000 }, /* Scc */
+{ op_57c8_0_comp_nf, 22472, 0x00000003 }, /* DBcc */
+{ op_57d0_0_comp_nf, 22480, 0x00000000 }, /* Scc */
+{ op_57d8_0_comp_nf, 22488, 0x00000000 }, /* Scc */
+{ op_57e0_0_comp_nf, 22496, 0x00000000 }, /* Scc */
+{ op_57e8_0_comp_nf, 22504, 0x00000002 }, /* Scc */
+{ op_57f0_0_comp_nf, 22512, 0x00000002 }, /* Scc */
+{ op_57f8_0_comp_nf, 22520, 0x00000002 }, /* Scc */
+{ op_57f9_0_comp_nf, 22521, 0x00000002 }, /* Scc */
+{ NULL, 22522, 0x00000001 }, /* TRAPcc */
+{ NULL, 22523, 0x00000001 }, /* TRAPcc */
+{ NULL, 22524, 0x00000001 }, /* TRAPcc */
+{ op_58c0_0_comp_nf, 22720, 0x00000000 }, /* Scc */
+{ op_58c8_0_comp_nf, 22728, 0x00000003 }, /* DBcc */
+{ op_58d0_0_comp_nf, 22736, 0x00000000 }, /* Scc */
+{ op_58d8_0_comp_nf, 22744, 0x00000000 }, /* Scc */
+{ op_58e0_0_comp_nf, 22752, 0x00000000 }, /* Scc */
+{ op_58e8_0_comp_nf, 22760, 0x00000002 }, /* Scc */
+{ op_58f0_0_comp_nf, 22768, 0x00000002 }, /* Scc */
+{ op_58f8_0_comp_nf, 22776, 0x00000002 }, /* Scc */
+{ op_58f9_0_comp_nf, 22777, 0x00000002 }, /* Scc */
+{ NULL, 22778, 0x00000001 }, /* TRAPcc */
+{ NULL, 22779, 0x00000001 }, /* TRAPcc */
+{ NULL, 22780, 0x00000001 }, /* TRAPcc */
+{ op_59c0_0_comp_nf, 22976, 0x00000000 }, /* Scc */
+{ op_59c8_0_comp_nf, 22984, 0x00000003 }, /* DBcc */
+{ op_59d0_0_comp_nf, 22992, 0x00000000 }, /* Scc */
+{ op_59d8_0_comp_nf, 23000, 0x00000000 }, /* Scc */
+{ op_59e0_0_comp_nf, 23008, 0x00000000 }, /* Scc */
+{ op_59e8_0_comp_nf, 23016, 0x00000002 }, /* Scc */
+{ op_59f0_0_comp_nf, 23024, 0x00000002 }, /* Scc */
+{ op_59f8_0_comp_nf, 23032, 0x00000002 }, /* Scc */
+{ op_59f9_0_comp_nf, 23033, 0x00000002 }, /* Scc */
+{ NULL, 23034, 0x00000001 }, /* TRAPcc */
+{ NULL, 23035, 0x00000001 }, /* TRAPcc */
+{ NULL, 23036, 0x00000001 }, /* TRAPcc */
+{ op_5ac0_0_comp_nf, 23232, 0x00000000 }, /* Scc */
+{ op_5ac8_0_comp_nf, 23240, 0x00000003 }, /* DBcc */
+{ op_5ad0_0_comp_nf, 23248, 0x00000000 }, /* Scc */
+{ op_5ad8_0_comp_nf, 23256, 0x00000000 }, /* Scc */
+{ op_5ae0_0_comp_nf, 23264, 0x00000000 }, /* Scc */
+{ op_5ae8_0_comp_nf, 23272, 0x00000002 }, /* Scc */
+{ op_5af0_0_comp_nf, 23280, 0x00000002 }, /* Scc */
+{ op_5af8_0_comp_nf, 23288, 0x00000002 }, /* Scc */
+{ op_5af9_0_comp_nf, 23289, 0x00000002 }, /* Scc */
+{ NULL, 23290, 0x00000001 }, /* TRAPcc */
+{ NULL, 23291, 0x00000001 }, /* TRAPcc */
+{ NULL, 23292, 0x00000001 }, /* TRAPcc */
+{ op_5bc0_0_comp_nf, 23488, 0x00000000 }, /* Scc */
+{ op_5bc8_0_comp_nf, 23496, 0x00000003 }, /* DBcc */
+{ op_5bd0_0_comp_nf, 23504, 0x00000000 }, /* Scc */
+{ op_5bd8_0_comp_nf, 23512, 0x00000000 }, /* Scc */
+{ op_5be0_0_comp_nf, 23520, 0x00000000 }, /* Scc */
+{ op_5be8_0_comp_nf, 23528, 0x00000002 }, /* Scc */
+{ op_5bf0_0_comp_nf, 23536, 0x00000002 }, /* Scc */
+{ op_5bf8_0_comp_nf, 23544, 0x00000002 }, /* Scc */
+{ op_5bf9_0_comp_nf, 23545, 0x00000002 }, /* Scc */
+{ NULL, 23546, 0x00000001 }, /* TRAPcc */
+{ NULL, 23547, 0x00000001 }, /* TRAPcc */
+{ NULL, 23548, 0x00000001 }, /* TRAPcc */
+{ op_5cc0_0_comp_nf, 23744, 0x00000000 }, /* Scc */
+{ op_5cc8_0_comp_nf, 23752, 0x00000003 }, /* DBcc */
+{ op_5cd0_0_comp_nf, 23760, 0x00000000 }, /* Scc */
+{ op_5cd8_0_comp_nf, 23768, 0x00000000 }, /* Scc */
+{ op_5ce0_0_comp_nf, 23776, 0x00000000 }, /* Scc */
+{ op_5ce8_0_comp_nf, 23784, 0x00000002 }, /* Scc */
+{ op_5cf0_0_comp_nf, 23792, 0x00000002 }, /* Scc */
+{ op_5cf8_0_comp_nf, 23800, 0x00000002 }, /* Scc */
+{ op_5cf9_0_comp_nf, 23801, 0x00000002 }, /* Scc */
+{ NULL, 23802, 0x00000001 }, /* TRAPcc */
+{ NULL, 23803, 0x00000001 }, /* TRAPcc */
+{ NULL, 23804, 0x00000001 }, /* TRAPcc */
+{ op_5dc0_0_comp_nf, 24000, 0x00000000 }, /* Scc */
+{ op_5dc8_0_comp_nf, 24008, 0x00000003 }, /* DBcc */
+{ op_5dd0_0_comp_nf, 24016, 0x00000000 }, /* Scc */
+{ op_5dd8_0_comp_nf, 24024, 0x00000000 }, /* Scc */
+{ op_5de0_0_comp_nf, 24032, 0x00000000 }, /* Scc */
+{ op_5de8_0_comp_nf, 24040, 0x00000002 }, /* Scc */
+{ op_5df0_0_comp_nf, 24048, 0x00000002 }, /* Scc */
+{ op_5df8_0_comp_nf, 24056, 0x00000002 }, /* Scc */
+{ op_5df9_0_comp_nf, 24057, 0x00000002 }, /* Scc */
+{ NULL, 24058, 0x00000001 }, /* TRAPcc */
+{ NULL, 24059, 0x00000001 }, /* TRAPcc */
+{ NULL, 24060, 0x00000001 }, /* TRAPcc */
+{ op_5ec0_0_comp_nf, 24256, 0x00000000 }, /* Scc */
+{ op_5ec8_0_comp_nf, 24264, 0x00000003 }, /* DBcc */
+{ op_5ed0_0_comp_nf, 24272, 0x00000000 }, /* Scc */
+{ op_5ed8_0_comp_nf, 24280, 0x00000000 }, /* Scc */
+{ op_5ee0_0_comp_nf, 24288, 0x00000000 }, /* Scc */
+{ op_5ee8_0_comp_nf, 24296, 0x00000002 }, /* Scc */
+{ op_5ef0_0_comp_nf, 24304, 0x00000002 }, /* Scc */
+{ op_5ef8_0_comp_nf, 24312, 0x00000002 }, /* Scc */
+{ op_5ef9_0_comp_nf, 24313, 0x00000002 }, /* Scc */
+{ NULL, 24314, 0x00000001 }, /* TRAPcc */
+{ NULL, 24315, 0x00000001 }, /* TRAPcc */
+{ NULL, 24316, 0x00000001 }, /* TRAPcc */
+{ op_5fc0_0_comp_nf, 24512, 0x00000000 }, /* Scc */
+{ op_5fc8_0_comp_nf, 24520, 0x00000003 }, /* DBcc */
+{ op_5fd0_0_comp_nf, 24528, 0x00000000 }, /* Scc */
+{ op_5fd8_0_comp_nf, 24536, 0x00000000 }, /* Scc */
+{ op_5fe0_0_comp_nf, 24544, 0x00000000 }, /* Scc */
+{ op_5fe8_0_comp_nf, 24552, 0x00000002 }, /* Scc */
+{ op_5ff0_0_comp_nf, 24560, 0x00000002 }, /* Scc */
+{ op_5ff8_0_comp_nf, 24568, 0x00000002 }, /* Scc */
+{ op_5ff9_0_comp_nf, 24569, 0x00000002 }, /* Scc */
+{ NULL, 24570, 0x00000001 }, /* TRAPcc */
+{ NULL, 24571, 0x00000001 }, /* TRAPcc */
+{ NULL, 24572, 0x00000001 }, /* TRAPcc */
+{ op_6000_0_comp_nf, 24576, 0x00000012 }, /* Bcc */
+{ op_6001_0_comp_nf, 24577, 0x00000010 }, /* Bcc */
+{ op_60ff_0_comp_nf, 24831, 0x00000012 }, /* Bcc */
+{ op_6100_0_comp_nf, 24832, 0x00000012 }, /* BSR */
+{ op_6101_0_comp_nf, 24833, 0x00000010 }, /* BSR */
+{ op_61ff_0_comp_nf, 25087, 0x00000012 }, /* BSR */
+{ op_6200_0_comp_nf, 25088, 0x00000003 }, /* Bcc */
+{ op_6201_0_comp_nf, 25089, 0x00000001 }, /* Bcc */
+{ op_62ff_0_comp_nf, 25343, 0x00000003 }, /* Bcc */
+{ op_6300_0_comp_nf, 25344, 0x00000003 }, /* Bcc */
+{ op_6301_0_comp_nf, 25345, 0x00000001 }, /* Bcc */
+{ op_63ff_0_comp_nf, 25599, 0x00000003 }, /* Bcc */
+{ op_6400_0_comp_nf, 25600, 0x00000003 }, /* Bcc */
+{ op_6401_0_comp_nf, 25601, 0x00000001 }, /* Bcc */
+{ op_64ff_0_comp_nf, 25855, 0x00000003 }, /* Bcc */
+{ op_6500_0_comp_nf, 25856, 0x00000003 }, /* Bcc */
+{ op_6501_0_comp_nf, 25857, 0x00000001 }, /* Bcc */
+{ op_65ff_0_comp_nf, 26111, 0x00000003 }, /* Bcc */
+{ op_6600_0_comp_nf, 26112, 0x00000003 }, /* Bcc */
+{ op_6601_0_comp_nf, 26113, 0x00000001 }, /* Bcc */
+{ op_66ff_0_comp_nf, 26367, 0x00000003 }, /* Bcc */
+{ op_6700_0_comp_nf, 26368, 0x00000003 }, /* Bcc */
+{ op_6701_0_comp_nf, 26369, 0x00000001 }, /* Bcc */
+{ op_67ff_0_comp_nf, 26623, 0x00000003 }, /* Bcc */
+{ op_6800_0_comp_nf, 26624, 0x00000003 }, /* Bcc */
+{ op_6801_0_comp_nf, 26625, 0x00000001 }, /* Bcc */
+{ op_68ff_0_comp_nf, 26879, 0x00000003 }, /* Bcc */
+{ op_6900_0_comp_nf, 26880, 0x00000003 }, /* Bcc */
+{ op_6901_0_comp_nf, 26881, 0x00000001 }, /* Bcc */
+{ op_69ff_0_comp_nf, 27135, 0x00000003 }, /* Bcc */
+{ op_6a00_0_comp_nf, 27136, 0x00000003 }, /* Bcc */
+{ op_6a01_0_comp_nf, 27137, 0x00000001 }, /* Bcc */
+{ op_6aff_0_comp_nf, 27391, 0x00000003 }, /* Bcc */
+{ op_6b00_0_comp_nf, 27392, 0x00000003 }, /* Bcc */
+{ op_6b01_0_comp_nf, 27393, 0x00000001 }, /* Bcc */
+{ op_6bff_0_comp_nf, 27647, 0x00000003 }, /* Bcc */
+{ op_6c00_0_comp_nf, 27648, 0x00000003 }, /* Bcc */
+{ op_6c01_0_comp_nf, 27649, 0x00000001 }, /* Bcc */
+{ op_6cff_0_comp_nf, 27903, 0x00000003 }, /* Bcc */
+{ op_6d00_0_comp_nf, 27904, 0x00000003 }, /* Bcc */
+{ op_6d01_0_comp_nf, 27905, 0x00000001 }, /* Bcc */
+{ op_6dff_0_comp_nf, 28159, 0x00000003 }, /* Bcc */
+{ op_6e00_0_comp_nf, 28160, 0x00000003 }, /* Bcc */
+{ op_6e01_0_comp_nf, 28161, 0x00000001 }, /* Bcc */
+{ op_6eff_0_comp_nf, 28415, 0x00000003 }, /* Bcc */
+{ op_6f00_0_comp_nf, 28416, 0x00000003 }, /* Bcc */
+{ op_6f01_0_comp_nf, 28417, 0x00000001 }, /* Bcc */
+{ op_6fff_0_comp_nf, 28671, 0x00000003 }, /* Bcc */
+{ op_7000_0_comp_nf, 28672, 0x00000000 }, /* MOVE */
+{ op_8000_0_comp_nf, 32768, 0x00000000 }, /* OR */
+{ op_8010_0_comp_nf, 32784, 0x00000000 }, /* OR */
+{ op_8018_0_comp_nf, 32792, 0x00000000 }, /* OR */
+{ op_8020_0_comp_nf, 32800, 0x00000000 }, /* OR */
+{ op_8028_0_comp_nf, 32808, 0x00000002 }, /* OR */
+{ op_8030_0_comp_nf, 32816, 0x00000002 }, /* OR */
+{ op_8038_0_comp_nf, 32824, 0x00000002 }, /* OR */
+{ op_8039_0_comp_nf, 32825, 0x00000002 }, /* OR */
+{ op_803a_0_comp_nf, 32826, 0x00000002 }, /* OR */
+{ op_803b_0_comp_nf, 32827, 0x00000002 }, /* OR */
+{ op_803c_0_comp_nf, 32828, 0x00000002 }, /* OR */
+{ op_8040_0_comp_nf, 32832, 0x00000000 }, /* OR */
+{ op_8050_0_comp_nf, 32848, 0x00000000 }, /* OR */
+{ op_8058_0_comp_nf, 32856, 0x00000000 }, /* OR */
+{ op_8060_0_comp_nf, 32864, 0x00000000 }, /* OR */
+{ op_8068_0_comp_nf, 32872, 0x00000002 }, /* OR */
+{ op_8070_0_comp_nf, 32880, 0x00000002 }, /* OR */
+{ op_8078_0_comp_nf, 32888, 0x00000002 }, /* OR */
+{ op_8079_0_comp_nf, 32889, 0x00000002 }, /* OR */
+{ op_807a_0_comp_nf, 32890, 0x00000002 }, /* OR */
+{ op_807b_0_comp_nf, 32891, 0x00000002 }, /* OR */
+{ op_807c_0_comp_nf, 32892, 0x00000002 }, /* OR */
+{ op_8080_0_comp_nf, 32896, 0x00000000 }, /* OR */
+{ op_8090_0_comp_nf, 32912, 0x00000000 }, /* OR */
+{ op_8098_0_comp_nf, 32920, 0x00000000 }, /* OR */
+{ op_80a0_0_comp_nf, 32928, 0x00000000 }, /* OR */
+{ op_80a8_0_comp_nf, 32936, 0x00000002 }, /* OR */
+{ op_80b0_0_comp_nf, 32944, 0x00000002 }, /* OR */
+{ op_80b8_0_comp_nf, 32952, 0x00000002 }, /* OR */
+{ op_80b9_0_comp_nf, 32953, 0x00000002 }, /* OR */
+{ op_80ba_0_comp_nf, 32954, 0x00000002 }, /* OR */
+{ op_80bb_0_comp_nf, 32955, 0x00000002 }, /* OR */
+{ op_80bc_0_comp_nf, 32956, 0x00000002 }, /* OR */
+{ op_80c0_0_comp_nf, 32960, 0x00000000 }, /* DIVU */
+{ op_80d0_0_comp_nf, 32976, 0x00000000 }, /* DIVU */
+{ op_80d8_0_comp_nf, 32984, 0x00000000 }, /* DIVU */
+{ op_80e0_0_comp_nf, 32992, 0x00000000 }, /* DIVU */
+{ op_80e8_0_comp_nf, 33000, 0x00000002 }, /* DIVU */
+{ op_80f0_0_comp_nf, 33008, 0x00000002 }, /* DIVU */
+{ op_80f8_0_comp_nf, 33016, 0x00000002 }, /* DIVU */
+{ op_80f9_0_comp_nf, 33017, 0x00000002 }, /* DIVU */
+{ op_80fa_0_comp_nf, 33018, 0x00000002 }, /* DIVU */
+{ op_80fb_0_comp_nf, 33019, 0x00000002 }, /* DIVU */
+{ op_80fc_0_comp_nf, 33020, 0x00000002 }, /* DIVU */
+{ NULL, 33024, 0x00000000 }, /* SBCD */
+{ NULL, 33032, 0x00000000 }, /* SBCD */
+{ op_8110_0_comp_nf, 33040, 0x00000000 }, /* OR */
+{ op_8118_0_comp_nf, 33048, 0x00000000 }, /* OR */
+{ op_8120_0_comp_nf, 33056, 0x00000000 }, /* OR */
+{ op_8128_0_comp_nf, 33064, 0x00000002 }, /* OR */
+{ op_8130_0_comp_nf, 33072, 0x00000002 }, /* OR */
+{ op_8138_0_comp_nf, 33080, 0x00000002 }, /* OR */
+{ op_8139_0_comp_nf, 33081, 0x00000002 }, /* OR */
+{ NULL, 33088, 0x00000000 }, /* PACK */
+{ NULL, 33096, 0x00000000 }, /* PACK */
+{ op_8150_0_comp_nf, 33104, 0x00000000 }, /* OR */
+{ op_8158_0_comp_nf, 33112, 0x00000000 }, /* OR */
+{ op_8160_0_comp_nf, 33120, 0x00000000 }, /* OR */
+{ op_8168_0_comp_nf, 33128, 0x00000002 }, /* OR */
+{ op_8170_0_comp_nf, 33136, 0x00000002 }, /* OR */
+{ op_8178_0_comp_nf, 33144, 0x00000002 }, /* OR */
+{ op_8179_0_comp_nf, 33145, 0x00000002 }, /* OR */
+{ NULL, 33152, 0x00000000 }, /* UNPK */
+{ NULL, 33160, 0x00000000 }, /* UNPK */
+{ op_8190_0_comp_nf, 33168, 0x00000000 }, /* OR */
+{ op_8198_0_comp_nf, 33176, 0x00000000 }, /* OR */
+{ op_81a0_0_comp_nf, 33184, 0x00000000 }, /* OR */
+{ op_81a8_0_comp_nf, 33192, 0x00000002 }, /* OR */
+{ op_81b0_0_comp_nf, 33200, 0x00000002 }, /* OR */
+{ op_81b8_0_comp_nf, 33208, 0x00000002 }, /* OR */
+{ op_81b9_0_comp_nf, 33209, 0x00000002 }, /* OR */
+{ op_81c0_0_comp_nf, 33216, 0x00000000 }, /* DIVS */
+{ op_81d0_0_comp_nf, 33232, 0x00000000 }, /* DIVS */
+{ op_81d8_0_comp_nf, 33240, 0x00000000 }, /* DIVS */
+{ op_81e0_0_comp_nf, 33248, 0x00000000 }, /* DIVS */
+{ op_81e8_0_comp_nf, 33256, 0x00000002 }, /* DIVS */
+{ op_81f0_0_comp_nf, 33264, 0x00000002 }, /* DIVS */
+{ op_81f8_0_comp_nf, 33272, 0x00000002 }, /* DIVS */
+{ op_81f9_0_comp_nf, 33273, 0x00000002 }, /* DIVS */
+{ op_81fa_0_comp_nf, 33274, 0x00000002 }, /* DIVS */
+{ op_81fb_0_comp_nf, 33275, 0x00000002 }, /* DIVS */
+{ op_81fc_0_comp_nf, 33276, 0x00000002 }, /* DIVS */
+{ op_9000_0_comp_nf, 36864, 0x00000000 }, /* SUB */
+{ op_9010_0_comp_nf, 36880, 0x00000000 }, /* SUB */
+{ op_9018_0_comp_nf, 36888, 0x00000000 }, /* SUB */
+{ op_9020_0_comp_nf, 36896, 0x00000000 }, /* SUB */
+{ op_9028_0_comp_nf, 36904, 0x00000002 }, /* SUB */
+{ op_9030_0_comp_nf, 36912, 0x00000002 }, /* SUB */
+{ op_9038_0_comp_nf, 36920, 0x00000002 }, /* SUB */
+{ op_9039_0_comp_nf, 36921, 0x00000002 }, /* SUB */
+{ op_903a_0_comp_nf, 36922, 0x00000002 }, /* SUB */
+{ op_903b_0_comp_nf, 36923, 0x00000002 }, /* SUB */
+{ op_903c_0_comp_nf, 36924, 0x00000002 }, /* SUB */
+{ op_9040_0_comp_nf, 36928, 0x00000000 }, /* SUB */
+{ op_9048_0_comp_nf, 36936, 0x00000000 }, /* SUB */
+{ op_9050_0_comp_nf, 36944, 0x00000000 }, /* SUB */
+{ op_9058_0_comp_nf, 36952, 0x00000000 }, /* SUB */
+{ op_9060_0_comp_nf, 36960, 0x00000000 }, /* SUB */
+{ op_9068_0_comp_nf, 36968, 0x00000002 }, /* SUB */
+{ op_9070_0_comp_nf, 36976, 0x00000002 }, /* SUB */
+{ op_9078_0_comp_nf, 36984, 0x00000002 }, /* SUB */
+{ op_9079_0_comp_nf, 36985, 0x00000002 }, /* SUB */
+{ op_907a_0_comp_nf, 36986, 0x00000002 }, /* SUB */
+{ op_907b_0_comp_nf, 36987, 0x00000002 }, /* SUB */
+{ op_907c_0_comp_nf, 36988, 0x00000002 }, /* SUB */
+{ op_9080_0_comp_nf, 36992, 0x00000000 }, /* SUB */
+{ op_9088_0_comp_nf, 37000, 0x00000000 }, /* SUB */
+{ op_9090_0_comp_nf, 37008, 0x00000000 }, /* SUB */
+{ op_9098_0_comp_nf, 37016, 0x00000000 }, /* SUB */
+{ op_90a0_0_comp_nf, 37024, 0x00000000 }, /* SUB */
+{ op_90a8_0_comp_nf, 37032, 0x00000002 }, /* SUB */
+{ op_90b0_0_comp_nf, 37040, 0x00000002 }, /* SUB */
+{ op_90b8_0_comp_nf, 37048, 0x00000002 }, /* SUB */
+{ op_90b9_0_comp_nf, 37049, 0x00000002 }, /* SUB */
+{ op_90ba_0_comp_nf, 37050, 0x00000002 }, /* SUB */
+{ op_90bb_0_comp_nf, 37051, 0x00000002 }, /* SUB */
+{ op_90bc_0_comp_nf, 37052, 0x00000002 }, /* SUB */
+{ op_90c0_0_comp_nf, 37056, 0x00000000 }, /* SUBA */
+{ op_90c8_0_comp_nf, 37064, 0x00000000 }, /* SUBA */
+{ op_90d0_0_comp_nf, 37072, 0x00000000 }, /* SUBA */
+{ op_90d8_0_comp_nf, 37080, 0x00000000 }, /* SUBA */
+{ op_90e0_0_comp_nf, 37088, 0x00000000 }, /* SUBA */
+{ op_90e8_0_comp_nf, 37096, 0x00000002 }, /* SUBA */
+{ op_90f0_0_comp_nf, 37104, 0x00000002 }, /* SUBA */
+{ op_90f8_0_comp_nf, 37112, 0x00000002 }, /* SUBA */
+{ op_90f9_0_comp_nf, 37113, 0x00000002 }, /* SUBA */
+{ op_90fa_0_comp_nf, 37114, 0x00000002 }, /* SUBA */
+{ op_90fb_0_comp_nf, 37115, 0x00000002 }, /* SUBA */
+{ op_90fc_0_comp_nf, 37116, 0x00000002 }, /* SUBA */
+{ op_9100_0_comp_nf, 37120, 0x00000008 }, /* SUBX */
+{ op_9108_0_comp_nf, 37128, 0x00000008 }, /* SUBX */
+{ op_9110_0_comp_nf, 37136, 0x00000000 }, /* SUB */
+{ op_9118_0_comp_nf, 37144, 0x00000000 }, /* SUB */
+{ op_9120_0_comp_nf, 37152, 0x00000000 }, /* SUB */
+{ op_9128_0_comp_nf, 37160, 0x00000002 }, /* SUB */
+{ op_9130_0_comp_nf, 37168, 0x00000002 }, /* SUB */
+{ op_9138_0_comp_nf, 37176, 0x00000002 }, /* SUB */
+{ op_9139_0_comp_nf, 37177, 0x00000002 }, /* SUB */
+{ op_9140_0_comp_nf, 37184, 0x00000008 }, /* SUBX */
+{ op_9148_0_comp_nf, 37192, 0x00000008 }, /* SUBX */
+{ op_9150_0_comp_nf, 37200, 0x00000000 }, /* SUB */
+{ op_9158_0_comp_nf, 37208, 0x00000000 }, /* SUB */
+{ op_9160_0_comp_nf, 37216, 0x00000000 }, /* SUB */
+{ op_9168_0_comp_nf, 37224, 0x00000002 }, /* SUB */
+{ op_9170_0_comp_nf, 37232, 0x00000002 }, /* SUB */
+{ op_9178_0_comp_nf, 37240, 0x00000002 }, /* SUB */
+{ op_9179_0_comp_nf, 37241, 0x00000002 }, /* SUB */
+{ op_9180_0_comp_nf, 37248, 0x00000008 }, /* SUBX */
+{ op_9188_0_comp_nf, 37256, 0x00000008 }, /* SUBX */
+{ op_9190_0_comp_nf, 37264, 0x00000000 }, /* SUB */
+{ op_9198_0_comp_nf, 37272, 0x00000000 }, /* SUB */
+{ op_91a0_0_comp_nf, 37280, 0x00000000 }, /* SUB */
+{ op_91a8_0_comp_nf, 37288, 0x00000002 }, /* SUB */
+{ op_91b0_0_comp_nf, 37296, 0x00000002 }, /* SUB */
+{ op_91b8_0_comp_nf, 37304, 0x00000002 }, /* SUB */
+{ op_91b9_0_comp_nf, 37305, 0x00000002 }, /* SUB */
+{ op_91c0_0_comp_nf, 37312, 0x00000000 }, /* SUBA */
+{ op_91c8_0_comp_nf, 37320, 0x00000000 }, /* SUBA */
+{ op_91d0_0_comp_nf, 37328, 0x00000000 }, /* SUBA */
+{ op_91d8_0_comp_nf, 37336, 0x00000000 }, /* SUBA */
+{ op_91e0_0_comp_nf, 37344, 0x00000000 }, /* SUBA */
+{ op_91e8_0_comp_nf, 37352, 0x00000002 }, /* SUBA */
+{ op_91f0_0_comp_nf, 37360, 0x00000002 }, /* SUBA */
+{ op_91f8_0_comp_nf, 37368, 0x00000002 }, /* SUBA */
+{ op_91f9_0_comp_nf, 37369, 0x00000002 }, /* SUBA */
+{ op_91fa_0_comp_nf, 37370, 0x00000002 }, /* SUBA */
+{ op_91fb_0_comp_nf, 37371, 0x00000002 }, /* SUBA */
+{ op_91fc_0_comp_nf, 37372, 0x00000002 }, /* SUBA */
+{ op_b000_0_comp_nf, 45056, 0x00000000 }, /* CMP */
+{ op_b010_0_comp_nf, 45072, 0x00000000 }, /* CMP */
+{ op_b018_0_comp_nf, 45080, 0x00000000 }, /* CMP */
+{ op_b020_0_comp_nf, 45088, 0x00000000 }, /* CMP */
+{ op_b028_0_comp_nf, 45096, 0x00000002 }, /* CMP */
+{ op_b030_0_comp_nf, 45104, 0x00000002 }, /* CMP */
+{ op_b038_0_comp_nf, 45112, 0x00000002 }, /* CMP */
+{ op_b039_0_comp_nf, 45113, 0x00000002 }, /* CMP */
+{ op_b03a_0_comp_nf, 45114, 0x00000002 }, /* CMP */
+{ op_b03b_0_comp_nf, 45115, 0x00000002 }, /* CMP */
+{ op_b03c_0_comp_nf, 45116, 0x00000002 }, /* CMP */
+{ op_b040_0_comp_nf, 45120, 0x00000000 }, /* CMP */
+{ op_b048_0_comp_nf, 45128, 0x00000000 }, /* CMP */
+{ op_b050_0_comp_nf, 45136, 0x00000000 }, /* CMP */
+{ op_b058_0_comp_nf, 45144, 0x00000000 }, /* CMP */
+{ op_b060_0_comp_nf, 45152, 0x00000000 }, /* CMP */
+{ op_b068_0_comp_nf, 45160, 0x00000002 }, /* CMP */
+{ op_b070_0_comp_nf, 45168, 0x00000002 }, /* CMP */
+{ op_b078_0_comp_nf, 45176, 0x00000002 }, /* CMP */
+{ op_b079_0_comp_nf, 45177, 0x00000002 }, /* CMP */
+{ op_b07a_0_comp_nf, 45178, 0x00000002 }, /* CMP */
+{ op_b07b_0_comp_nf, 45179, 0x00000002 }, /* CMP */
+{ op_b07c_0_comp_nf, 45180, 0x00000002 }, /* CMP */
+{ op_b080_0_comp_nf, 45184, 0x00000000 }, /* CMP */
+{ op_b088_0_comp_nf, 45192, 0x00000000 }, /* CMP */
+{ op_b090_0_comp_nf, 45200, 0x00000000 }, /* CMP */
+{ op_b098_0_comp_nf, 45208, 0x00000000 }, /* CMP */
+{ op_b0a0_0_comp_nf, 45216, 0x00000000 }, /* CMP */
+{ op_b0a8_0_comp_nf, 45224, 0x00000002 }, /* CMP */
+{ op_b0b0_0_comp_nf, 45232, 0x00000002 }, /* CMP */
+{ op_b0b8_0_comp_nf, 45240, 0x00000002 }, /* CMP */
+{ op_b0b9_0_comp_nf, 45241, 0x00000002 }, /* CMP */
+{ op_b0ba_0_comp_nf, 45242, 0x00000002 }, /* CMP */
+{ op_b0bb_0_comp_nf, 45243, 0x00000002 }, /* CMP */
+{ op_b0bc_0_comp_nf, 45244, 0x00000002 }, /* CMP */
+{ op_b0c0_0_comp_nf, 45248, 0x00000000 }, /* CMPA */
+{ op_b0c8_0_comp_nf, 45256, 0x00000000 }, /* CMPA */
+{ op_b0d0_0_comp_nf, 45264, 0x00000000 }, /* CMPA */
+{ op_b0d8_0_comp_nf, 45272, 0x00000000 }, /* CMPA */
+{ op_b0e0_0_comp_nf, 45280, 0x00000000 }, /* CMPA */
+{ op_b0e8_0_comp_nf, 45288, 0x00000002 }, /* CMPA */
+{ op_b0f0_0_comp_nf, 45296, 0x00000002 }, /* CMPA */
+{ op_b0f8_0_comp_nf, 45304, 0x00000002 }, /* CMPA */
+{ op_b0f9_0_comp_nf, 45305, 0x00000002 }, /* CMPA */
+{ op_b0fa_0_comp_nf, 45306, 0x00000002 }, /* CMPA */
+{ op_b0fb_0_comp_nf, 45307, 0x00000002 }, /* CMPA */
+{ op_b0fc_0_comp_nf, 45308, 0x00000002 }, /* CMPA */
+{ op_b100_0_comp_nf, 45312, 0x00000000 }, /* EOR */
+{ op_b108_0_comp_nf, 45320, 0x00000000 }, /* CMPM */
+{ op_b110_0_comp_nf, 45328, 0x00000000 }, /* EOR */
+{ op_b118_0_comp_nf, 45336, 0x00000000 }, /* EOR */
+{ op_b120_0_comp_nf, 45344, 0x00000000 }, /* EOR */
+{ op_b128_0_comp_nf, 45352, 0x00000002 }, /* EOR */
+{ op_b130_0_comp_nf, 45360, 0x00000002 }, /* EOR */
+{ op_b138_0_comp_nf, 45368, 0x00000002 }, /* EOR */
+{ op_b139_0_comp_nf, 45369, 0x00000002 }, /* EOR */
+{ op_b140_0_comp_nf, 45376, 0x00000000 }, /* EOR */
+{ op_b148_0_comp_nf, 45384, 0x00000000 }, /* CMPM */
+{ op_b150_0_comp_nf, 45392, 0x00000000 }, /* EOR */
+{ op_b158_0_comp_nf, 45400, 0x00000000 }, /* EOR */
+{ op_b160_0_comp_nf, 45408, 0x00000000 }, /* EOR */
+{ op_b168_0_comp_nf, 45416, 0x00000002 }, /* EOR */
+{ op_b170_0_comp_nf, 45424, 0x00000002 }, /* EOR */
+{ op_b178_0_comp_nf, 45432, 0x00000002 }, /* EOR */
+{ op_b179_0_comp_nf, 45433, 0x00000002 }, /* EOR */
+{ op_b180_0_comp_nf, 45440, 0x00000000 }, /* EOR */
+{ op_b188_0_comp_nf, 45448, 0x00000000 }, /* CMPM */
+{ op_b190_0_comp_nf, 45456, 0x00000000 }, /* EOR */
+{ op_b198_0_comp_nf, 45464, 0x00000000 }, /* EOR */
+{ op_b1a0_0_comp_nf, 45472, 0x00000000 }, /* EOR */
+{ op_b1a8_0_comp_nf, 45480, 0x00000002 }, /* EOR */
+{ op_b1b0_0_comp_nf, 45488, 0x00000002 }, /* EOR */
+{ op_b1b8_0_comp_nf, 45496, 0x00000002 }, /* EOR */
+{ op_b1b9_0_comp_nf, 45497, 0x00000002 }, /* EOR */
+{ op_b1c0_0_comp_nf, 45504, 0x00000000 }, /* CMPA */
+{ op_b1c8_0_comp_nf, 45512, 0x00000000 }, /* CMPA */
+{ op_b1d0_0_comp_nf, 45520, 0x00000000 }, /* CMPA */
+{ op_b1d8_0_comp_nf, 45528, 0x00000000 }, /* CMPA */
+{ op_b1e0_0_comp_nf, 45536, 0x00000000 }, /* CMPA */
+{ op_b1e8_0_comp_nf, 45544, 0x00000002 }, /* CMPA */
+{ op_b1f0_0_comp_nf, 45552, 0x00000002 }, /* CMPA */
+{ op_b1f8_0_comp_nf, 45560, 0x00000002 }, /* CMPA */
+{ op_b1f9_0_comp_nf, 45561, 0x00000002 }, /* CMPA */
+{ op_b1fa_0_comp_nf, 45562, 0x00000002 }, /* CMPA */
+{ op_b1fb_0_comp_nf, 45563, 0x00000002 }, /* CMPA */
+{ op_b1fc_0_comp_nf, 45564, 0x00000002 }, /* CMPA */
+{ op_c000_0_comp_nf, 49152, 0x00000000 }, /* AND */
+{ op_c010_0_comp_nf, 49168, 0x00000000 }, /* AND */
+{ op_c018_0_comp_nf, 49176, 0x00000000 }, /* AND */
+{ op_c020_0_comp_nf, 49184, 0x00000000 }, /* AND */
+{ op_c028_0_comp_nf, 49192, 0x00000002 }, /* AND */
+{ op_c030_0_comp_nf, 49200, 0x00000002 }, /* AND */
+{ op_c038_0_comp_nf, 49208, 0x00000002 }, /* AND */
+{ op_c039_0_comp_nf, 49209, 0x00000002 }, /* AND */
+{ op_c03a_0_comp_nf, 49210, 0x00000002 }, /* AND */
+{ op_c03b_0_comp_nf, 49211, 0x00000002 }, /* AND */
+{ op_c03c_0_comp_nf, 49212, 0x00000002 }, /* AND */
+{ op_c040_0_comp_nf, 49216, 0x00000000 }, /* AND */
+{ op_c050_0_comp_nf, 49232, 0x00000000 }, /* AND */
+{ op_c058_0_comp_nf, 49240, 0x00000000 }, /* AND */
+{ op_c060_0_comp_nf, 49248, 0x00000000 }, /* AND */
+{ op_c068_0_comp_nf, 49256, 0x00000002 }, /* AND */
+{ op_c070_0_comp_nf, 49264, 0x00000002 }, /* AND */
+{ op_c078_0_comp_nf, 49272, 0x00000002 }, /* AND */
+{ op_c079_0_comp_nf, 49273, 0x00000002 }, /* AND */
+{ op_c07a_0_comp_nf, 49274, 0x00000002 }, /* AND */
+{ op_c07b_0_comp_nf, 49275, 0x00000002 }, /* AND */
+{ op_c07c_0_comp_nf, 49276, 0x00000002 }, /* AND */
+{ op_c080_0_comp_nf, 49280, 0x00000000 }, /* AND */
+{ op_c090_0_comp_nf, 49296, 0x00000000 }, /* AND */
+{ op_c098_0_comp_nf, 49304, 0x00000000 }, /* AND */
+{ op_c0a0_0_comp_nf, 49312, 0x00000000 }, /* AND */
+{ op_c0a8_0_comp_nf, 49320, 0x00000002 }, /* AND */
+{ op_c0b0_0_comp_nf, 49328, 0x00000002 }, /* AND */
+{ op_c0b8_0_comp_nf, 49336, 0x00000002 }, /* AND */
+{ op_c0b9_0_comp_nf, 49337, 0x00000002 }, /* AND */
+{ op_c0ba_0_comp_nf, 49338, 0x00000002 }, /* AND */
+{ op_c0bb_0_comp_nf, 49339, 0x00000002 }, /* AND */
+{ op_c0bc_0_comp_nf, 49340, 0x00000002 }, /* AND */
+{ op_c0c0_0_comp_nf, 49344, 0x00000000 }, /* MULU */
+{ op_c0d0_0_comp_nf, 49360, 0x00000000 }, /* MULU */
+{ op_c0d8_0_comp_nf, 49368, 0x00000000 }, /* MULU */
+{ op_c0e0_0_comp_nf, 49376, 0x00000000 }, /* MULU */
+{ op_c0e8_0_comp_nf, 49384, 0x00000002 }, /* MULU */
+{ op_c0f0_0_comp_nf, 49392, 0x00000002 }, /* MULU */
+{ op_c0f8_0_comp_nf, 49400, 0x00000002 }, /* MULU */
+{ op_c0f9_0_comp_nf, 49401, 0x00000002 }, /* MULU */
+{ op_c0fa_0_comp_nf, 49402, 0x00000002 }, /* MULU */
+{ op_c0fb_0_comp_nf, 49403, 0x00000002 }, /* MULU */
+{ op_c0fc_0_comp_nf, 49404, 0x00000002 }, /* MULU */
+{ NULL, 49408, 0x00000000 }, /* ABCD */
+{ NULL, 49416, 0x00000000 }, /* ABCD */
+{ op_c110_0_comp_nf, 49424, 0x00000000 }, /* AND */
+{ op_c118_0_comp_nf, 49432, 0x00000000 }, /* AND */
+{ op_c120_0_comp_nf, 49440, 0x00000000 }, /* AND */
+{ op_c128_0_comp_nf, 49448, 0x00000002 }, /* AND */
+{ op_c130_0_comp_nf, 49456, 0x00000002 }, /* AND */
+{ op_c138_0_comp_nf, 49464, 0x00000002 }, /* AND */
+{ op_c139_0_comp_nf, 49465, 0x00000002 }, /* AND */
+{ op_c140_0_comp_nf, 49472, 0x00000000 }, /* EXG */
+{ op_c148_0_comp_nf, 49480, 0x00000000 }, /* EXG */
+{ op_c150_0_comp_nf, 49488, 0x00000000 }, /* AND */
+{ op_c158_0_comp_nf, 49496, 0x00000000 }, /* AND */
+{ op_c160_0_comp_nf, 49504, 0x00000000 }, /* AND */
+{ op_c168_0_comp_nf, 49512, 0x00000002 }, /* AND */
+{ op_c170_0_comp_nf, 49520, 0x00000002 }, /* AND */
+{ op_c178_0_comp_nf, 49528, 0x00000002 }, /* AND */
+{ op_c179_0_comp_nf, 49529, 0x00000002 }, /* AND */
+{ op_c188_0_comp_nf, 49544, 0x00000000 }, /* EXG */
+{ op_c190_0_comp_nf, 49552, 0x00000000 }, /* AND */
+{ op_c198_0_comp_nf, 49560, 0x00000000 }, /* AND */
+{ op_c1a0_0_comp_nf, 49568, 0x00000000 }, /* AND */
+{ op_c1a8_0_comp_nf, 49576, 0x00000002 }, /* AND */
+{ op_c1b0_0_comp_nf, 49584, 0x00000002 }, /* AND */
+{ op_c1b8_0_comp_nf, 49592, 0x00000002 }, /* AND */
+{ op_c1b9_0_comp_nf, 49593, 0x00000002 }, /* AND */
+{ op_c1c0_0_comp_nf, 49600, 0x00000000 }, /* MULS */
+{ op_c1d0_0_comp_nf, 49616, 0x00000000 }, /* MULS */
+{ op_c1d8_0_comp_nf, 49624, 0x00000000 }, /* MULS */
+{ op_c1e0_0_comp_nf, 49632, 0x00000000 }, /* MULS */
+{ op_c1e8_0_comp_nf, 49640, 0x00000002 }, /* MULS */
+{ op_c1f0_0_comp_nf, 49648, 0x00000002 }, /* MULS */
+{ op_c1f8_0_comp_nf, 49656, 0x00000002 }, /* MULS */
+{ op_c1f9_0_comp_nf, 49657, 0x00000002 }, /* MULS */
+{ op_c1fa_0_comp_nf, 49658, 0x00000002 }, /* MULS */
+{ op_c1fb_0_comp_nf, 49659, 0x00000002 }, /* MULS */
+{ op_c1fc_0_comp_nf, 49660, 0x00000002 }, /* MULS */
+{ op_d000_0_comp_nf, 53248, 0x00000000 }, /* ADD */
+{ op_d010_0_comp_nf, 53264, 0x00000000 }, /* ADD */
+{ op_d018_0_comp_nf, 53272, 0x00000000 }, /* ADD */
+{ op_d020_0_comp_nf, 53280, 0x00000000 }, /* ADD */
+{ op_d028_0_comp_nf, 53288, 0x00000002 }, /* ADD */
+{ op_d030_0_comp_nf, 53296, 0x00000002 }, /* ADD */
+{ op_d038_0_comp_nf, 53304, 0x00000002 }, /* ADD */
+{ op_d039_0_comp_nf, 53305, 0x00000002 }, /* ADD */
+{ op_d03a_0_comp_nf, 53306, 0x00000002 }, /* ADD */
+{ op_d03b_0_comp_nf, 53307, 0x00000002 }, /* ADD */
+{ op_d03c_0_comp_nf, 53308, 0x00000002 }, /* ADD */
+{ op_d040_0_comp_nf, 53312, 0x00000000 }, /* ADD */
+{ op_d048_0_comp_nf, 53320, 0x00000000 }, /* ADD */
+{ op_d050_0_comp_nf, 53328, 0x00000000 }, /* ADD */
+{ op_d058_0_comp_nf, 53336, 0x00000000 }, /* ADD */
+{ op_d060_0_comp_nf, 53344, 0x00000000 }, /* ADD */
+{ op_d068_0_comp_nf, 53352, 0x00000002 }, /* ADD */
+{ op_d070_0_comp_nf, 53360, 0x00000002 }, /* ADD */
+{ op_d078_0_comp_nf, 53368, 0x00000002 }, /* ADD */
+{ op_d079_0_comp_nf, 53369, 0x00000002 }, /* ADD */
+{ op_d07a_0_comp_nf, 53370, 0x00000002 }, /* ADD */
+{ op_d07b_0_comp_nf, 53371, 0x00000002 }, /* ADD */
+{ op_d07c_0_comp_nf, 53372, 0x00000002 }, /* ADD */
+{ op_d080_0_comp_nf, 53376, 0x00000000 }, /* ADD */
+{ op_d088_0_comp_nf, 53384, 0x00000000 }, /* ADD */
+{ op_d090_0_comp_nf, 53392, 0x00000000 }, /* ADD */
+{ op_d098_0_comp_nf, 53400, 0x00000000 }, /* ADD */
+{ op_d0a0_0_comp_nf, 53408, 0x00000000 }, /* ADD */
+{ op_d0a8_0_comp_nf, 53416, 0x00000002 }, /* ADD */
+{ op_d0b0_0_comp_nf, 53424, 0x00000002 }, /* ADD */
+{ op_d0b8_0_comp_nf, 53432, 0x00000002 }, /* ADD */
+{ op_d0b9_0_comp_nf, 53433, 0x00000002 }, /* ADD */
+{ op_d0ba_0_comp_nf, 53434, 0x00000002 }, /* ADD */
+{ op_d0bb_0_comp_nf, 53435, 0x00000002 }, /* ADD */
+{ op_d0bc_0_comp_nf, 53436, 0x00000002 }, /* ADD */
+{ op_d0c0_0_comp_nf, 53440, 0x00000000 }, /* ADDA */
+{ op_d0c8_0_comp_nf, 53448, 0x00000000 }, /* ADDA */
+{ op_d0d0_0_comp_nf, 53456, 0x00000000 }, /* ADDA */
+{ op_d0d8_0_comp_nf, 53464, 0x00000000 }, /* ADDA */
+{ op_d0e0_0_comp_nf, 53472, 0x00000000 }, /* ADDA */
+{ op_d0e8_0_comp_nf, 53480, 0x00000002 }, /* ADDA */
+{ op_d0f0_0_comp_nf, 53488, 0x00000002 }, /* ADDA */
+{ op_d0f8_0_comp_nf, 53496, 0x00000002 }, /* ADDA */
+{ op_d0f9_0_comp_nf, 53497, 0x00000002 }, /* ADDA */
+{ op_d0fa_0_comp_nf, 53498, 0x00000002 }, /* ADDA */
+{ op_d0fb_0_comp_nf, 53499, 0x00000002 }, /* ADDA */
+{ op_d0fc_0_comp_nf, 53500, 0x00000002 }, /* ADDA */
+{ op_d100_0_comp_nf, 53504, 0x00000008 }, /* ADDX */
+{ op_d108_0_comp_nf, 53512, 0x00000008 }, /* ADDX */
+{ op_d110_0_comp_nf, 53520, 0x00000000 }, /* ADD */
+{ op_d118_0_comp_nf, 53528, 0x00000000 }, /* ADD */
+{ op_d120_0_comp_nf, 53536, 0x00000000 }, /* ADD */
+{ op_d128_0_comp_nf, 53544, 0x00000002 }, /* ADD */
+{ op_d130_0_comp_nf, 53552, 0x00000002 }, /* ADD */
+{ op_d138_0_comp_nf, 53560, 0x00000002 }, /* ADD */
+{ op_d139_0_comp_nf, 53561, 0x00000002 }, /* ADD */
+{ op_d140_0_comp_nf, 53568, 0x00000008 }, /* ADDX */
+{ op_d148_0_comp_nf, 53576, 0x00000008 }, /* ADDX */
+{ op_d150_0_comp_nf, 53584, 0x00000000 }, /* ADD */
+{ op_d158_0_comp_nf, 53592, 0x00000000 }, /* ADD */
+{ op_d160_0_comp_nf, 53600, 0x00000000 }, /* ADD */
+{ op_d168_0_comp_nf, 53608, 0x00000002 }, /* ADD */
+{ op_d170_0_comp_nf, 53616, 0x00000002 }, /* ADD */
+{ op_d178_0_comp_nf, 53624, 0x00000002 }, /* ADD */
+{ op_d179_0_comp_nf, 53625, 0x00000002 }, /* ADD */
+{ op_d180_0_comp_nf, 53632, 0x00000008 }, /* ADDX */
+{ op_d188_0_comp_nf, 53640, 0x00000008 }, /* ADDX */
+{ op_d190_0_comp_nf, 53648, 0x00000000 }, /* ADD */
+{ op_d198_0_comp_nf, 53656, 0x00000000 }, /* ADD */
+{ op_d1a0_0_comp_nf, 53664, 0x00000000 }, /* ADD */
+{ op_d1a8_0_comp_nf, 53672, 0x00000002 }, /* ADD */
+{ op_d1b0_0_comp_nf, 53680, 0x00000002 }, /* ADD */
+{ op_d1b8_0_comp_nf, 53688, 0x00000002 }, /* ADD */
+{ op_d1b9_0_comp_nf, 53689, 0x00000002 }, /* ADD */
+{ op_d1c0_0_comp_nf, 53696, 0x00000000 }, /* ADDA */
+{ op_d1c8_0_comp_nf, 53704, 0x00000000 }, /* ADDA */
+{ op_d1d0_0_comp_nf, 53712, 0x00000000 }, /* ADDA */
+{ op_d1d8_0_comp_nf, 53720, 0x00000000 }, /* ADDA */
+{ op_d1e0_0_comp_nf, 53728, 0x00000000 }, /* ADDA */
+{ op_d1e8_0_comp_nf, 53736, 0x00000002 }, /* ADDA */
+{ op_d1f0_0_comp_nf, 53744, 0x00000002 }, /* ADDA */
+{ op_d1f8_0_comp_nf, 53752, 0x00000002 }, /* ADDA */
+{ op_d1f9_0_comp_nf, 53753, 0x00000002 }, /* ADDA */
+{ op_d1fa_0_comp_nf, 53754, 0x00000002 }, /* ADDA */
+{ op_d1fb_0_comp_nf, 53755, 0x00000002 }, /* ADDA */
+{ op_d1fc_0_comp_nf, 53756, 0x00000002 }, /* ADDA */
+{ op_e000_0_comp_nf, 57344, 0x00000000 }, /* ASR */
+{ op_e008_0_comp_nf, 57352, 0x00000000 }, /* LSR */
+{ op_e010_0_comp_nf, 57360, 0x00000008 }, /* ROXR */
+{ op_e018_0_comp_nf, 57368, 0x00000000 }, /* ROR */
+{ op_e020_0_comp_nf, 57376, 0x00000000 }, /* ASR */
+{ op_e028_0_comp_nf, 57384, 0x00000000 }, /* LSR */
+{ op_e030_0_comp_nf, 57392, 0x00000008 }, /* ROXR */
+{ op_e038_0_comp_nf, 57400, 0x00000000 }, /* ROR */
+{ op_e040_0_comp_nf, 57408, 0x00000000 }, /* ASR */
+{ op_e048_0_comp_nf, 57416, 0x00000000 }, /* LSR */
+{ op_e050_0_comp_nf, 57424, 0x00000008 }, /* ROXR */
+{ op_e058_0_comp_nf, 57432, 0x00000000 }, /* ROR */
+{ op_e060_0_comp_nf, 57440, 0x00000000 }, /* ASR */
+{ op_e068_0_comp_nf, 57448, 0x00000000 }, /* LSR */
+{ op_e070_0_comp_nf, 57456, 0x00000008 }, /* ROXR */
+{ op_e078_0_comp_nf, 57464, 0x00000000 }, /* ROR */
+{ op_e080_0_comp_nf, 57472, 0x00000000 }, /* ASR */
+{ op_e088_0_comp_nf, 57480, 0x00000000 }, /* LSR */
+{ op_e090_0_comp_nf, 57488, 0x00000008 }, /* ROXR */
+{ op_e098_0_comp_nf, 57496, 0x00000000 }, /* ROR */
+{ op_e0a0_0_comp_nf, 57504, 0x00000000 }, /* ASR */
+{ op_e0a8_0_comp_nf, 57512, 0x00000000 }, /* LSR */
+{ op_e0b0_0_comp_nf, 57520, 0x00000008 }, /* ROXR */
+{ op_e0b8_0_comp_nf, 57528, 0x00000000 }, /* ROR */
+{ op_e0d0_0_comp_nf, 57552, 0x00000000 }, /* ASRW */
+{ op_e0d8_0_comp_nf, 57560, 0x00000000 }, /* ASRW */
+{ op_e0e0_0_comp_nf, 57568, 0x00000000 }, /* ASRW */
+{ op_e0e8_0_comp_nf, 57576, 0x00000002 }, /* ASRW */
+{ op_e0f0_0_comp_nf, 57584, 0x00000002 }, /* ASRW */
+{ op_e0f8_0_comp_nf, 57592, 0x00000002 }, /* ASRW */
+{ op_e0f9_0_comp_nf, 57593, 0x00000002 }, /* ASRW */
+{ op_e100_0_comp_nf, 57600, 0x00000000 }, /* ASL */
+{ op_e108_0_comp_nf, 57608, 0x00000000 }, /* LSL */
+{ op_e110_0_comp_nf, 57616, 0x00000008 }, /* ROXL */
+{ op_e118_0_comp_nf, 57624, 0x00000000 }, /* ROL */
+{ op_e120_0_comp_nf, 57632, 0x00000000 }, /* ASL */
+{ op_e128_0_comp_nf, 57640, 0x00000000 }, /* LSL */
+{ op_e130_0_comp_nf, 57648, 0x00000008 }, /* ROXL */
+{ op_e138_0_comp_nf, 57656, 0x00000000 }, /* ROL */
+{ op_e140_0_comp_nf, 57664, 0x00000000 }, /* ASL */
+{ op_e148_0_comp_nf, 57672, 0x00000000 }, /* LSL */
+{ op_e150_0_comp_nf, 57680, 0x00000008 }, /* ROXL */
+{ op_e158_0_comp_nf, 57688, 0x00000000 }, /* ROL */
+{ op_e160_0_comp_nf, 57696, 0x00000000 }, /* ASL */
+{ op_e168_0_comp_nf, 57704, 0x00000000 }, /* LSL */
+{ op_e170_0_comp_nf, 57712, 0x00000008 }, /* ROXL */
+{ op_e178_0_comp_nf, 57720, 0x00000000 }, /* ROL */
+{ op_e180_0_comp_nf, 57728, 0x00000000 }, /* ASL */
+{ op_e188_0_comp_nf, 57736, 0x00000000 }, /* LSL */
+{ op_e190_0_comp_nf, 57744, 0x00000008 }, /* ROXL */
+{ op_e198_0_comp_nf, 57752, 0x00000000 }, /* ROL */
+{ op_e1a0_0_comp_nf, 57760, 0x00000000 }, /* ASL */
+{ op_e1a8_0_comp_nf, 57768, 0x00000000 }, /* LSL */
+{ op_e1b0_0_comp_nf, 57776, 0x00000008 }, /* ROXL */
+{ op_e1b8_0_comp_nf, 57784, 0x00000000 }, /* ROL */
+{ op_e1d0_0_comp_nf, 57808, 0x00000000 }, /* ASLW */
+{ op_e1d8_0_comp_nf, 57816, 0x00000000 }, /* ASLW */
+{ op_e1e0_0_comp_nf, 57824, 0x00000000 }, /* ASLW */
+{ op_e1e8_0_comp_nf, 57832, 0x00000002 }, /* ASLW */
+{ op_e1f0_0_comp_nf, 57840, 0x00000002 }, /* ASLW */
+{ op_e1f8_0_comp_nf, 57848, 0x00000002 }, /* ASLW */
+{ op_e1f9_0_comp_nf, 57849, 0x00000002 }, /* ASLW */
+{ op_e2d0_0_comp_nf, 58064, 0x00000000 }, /* LSRW */
+{ op_e2d8_0_comp_nf, 58072, 0x00000000 }, /* LSRW */
+{ op_e2e0_0_comp_nf, 58080, 0x00000000 }, /* LSRW */
+{ op_e2e8_0_comp_nf, 58088, 0x00000002 }, /* LSRW */
+{ op_e2f0_0_comp_nf, 58096, 0x00000002 }, /* LSRW */
+{ op_e2f8_0_comp_nf, 58104, 0x00000002 }, /* LSRW */
+{ op_e2f9_0_comp_nf, 58105, 0x00000002 }, /* LSRW */
+{ op_e3d0_0_comp_nf, 58320, 0x00000000 }, /* LSLW */
+{ op_e3d8_0_comp_nf, 58328, 0x00000000 }, /* LSLW */
+{ op_e3e0_0_comp_nf, 58336, 0x00000000 }, /* LSLW */
+{ op_e3e8_0_comp_nf, 58344, 0x00000002 }, /* LSLW */
+{ op_e3f0_0_comp_nf, 58352, 0x00000002 }, /* LSLW */
+{ op_e3f8_0_comp_nf, 58360, 0x00000002 }, /* LSLW */
+{ op_e3f9_0_comp_nf, 58361, 0x00000002 }, /* LSLW */
+{ NULL, 58576, 0x00000008 }, /* ROXRW */
+{ NULL, 58584, 0x00000008 }, /* ROXRW */
+{ NULL, 58592, 0x00000008 }, /* ROXRW */
+{ NULL, 58600, 0x0000000a }, /* ROXRW */
+{ NULL, 58608, 0x0000000a }, /* ROXRW */
+{ NULL, 58616, 0x0000000a }, /* ROXRW */
+{ NULL, 58617, 0x0000000a }, /* ROXRW */
+{ NULL, 58832, 0x00000008 }, /* ROXLW */
+{ NULL, 58840, 0x00000008 }, /* ROXLW */
+{ NULL, 58848, 0x00000008 }, /* ROXLW */
+{ NULL, 58856, 0x0000000a }, /* ROXLW */
+{ NULL, 58864, 0x0000000a }, /* ROXLW */
+{ NULL, 58872, 0x0000000a }, /* ROXLW */
+{ NULL, 58873, 0x0000000a }, /* ROXLW */
+{ op_e6d0_0_comp_nf, 59088, 0x00000000 }, /* RORW */
+{ op_e6d8_0_comp_nf, 59096, 0x00000000 }, /* RORW */
+{ op_e6e0_0_comp_nf, 59104, 0x00000000 }, /* RORW */
+{ op_e6e8_0_comp_nf, 59112, 0x00000002 }, /* RORW */
+{ op_e6f0_0_comp_nf, 59120, 0x00000002 }, /* RORW */
+{ op_e6f8_0_comp_nf, 59128, 0x00000002 }, /* RORW */
+{ op_e6f9_0_comp_nf, 59129, 0x00000002 }, /* RORW */
+{ op_e7d0_0_comp_nf, 59344, 0x00000000 }, /* ROLW */
+{ op_e7d8_0_comp_nf, 59352, 0x00000000 }, /* ROLW */
+{ op_e7e0_0_comp_nf, 59360, 0x00000000 }, /* ROLW */
+{ op_e7e8_0_comp_nf, 59368, 0x00000002 }, /* ROLW */
+{ op_e7f0_0_comp_nf, 59376, 0x00000002 }, /* ROLW */
+{ op_e7f8_0_comp_nf, 59384, 0x00000002 }, /* ROLW */
+{ op_e7f9_0_comp_nf, 59385, 0x00000002 }, /* ROLW */
+{ NULL, 59584, 0x00000000 }, /* BFTST */
+{ NULL, 59600, 0x00000000 }, /* BFTST */
+{ NULL, 59624, 0x00000000 }, /* BFTST */
+{ NULL, 59632, 0x00000000 }, /* BFTST */
+{ NULL, 59640, 0x00000000 }, /* BFTST */
+{ NULL, 59641, 0x00000000 }, /* BFTST */
+{ NULL, 59642, 0x00000000 }, /* BFTST */
+{ NULL, 59643, 0x00000000 }, /* BFTST */
+{ NULL, 59840, 0x00000000 }, /* BFEXTU */
+{ NULL, 59856, 0x00000000 }, /* BFEXTU */
+{ NULL, 59880, 0x00000000 }, /* BFEXTU */
+{ NULL, 59888, 0x00000000 }, /* BFEXTU */
+{ NULL, 59896, 0x00000000 }, /* BFEXTU */
+{ NULL, 59897, 0x00000000 }, /* BFEXTU */
+{ NULL, 59898, 0x00000000 }, /* BFEXTU */
+{ NULL, 59899, 0x00000000 }, /* BFEXTU */
+{ NULL, 60096, 0x00000000 }, /* BFCHG */
+{ NULL, 60112, 0x00000000 }, /* BFCHG */
+{ NULL, 60136, 0x00000000 }, /* BFCHG */
+{ NULL, 60144, 0x00000000 }, /* BFCHG */
+{ NULL, 60152, 0x00000000 }, /* BFCHG */
+{ NULL, 60153, 0x00000000 }, /* BFCHG */
+{ NULL, 60352, 0x00000000 }, /* BFEXTS */
+{ NULL, 60368, 0x00000000 }, /* BFEXTS */
+{ NULL, 60392, 0x00000000 }, /* BFEXTS */
+{ NULL, 60400, 0x00000000 }, /* BFEXTS */
+{ NULL, 60408, 0x00000000 }, /* BFEXTS */
+{ NULL, 60409, 0x00000000 }, /* BFEXTS */
+{ NULL, 60410, 0x00000000 }, /* BFEXTS */
+{ NULL, 60411, 0x00000000 }, /* BFEXTS */
+{ NULL, 60608, 0x00000000 }, /* BFCLR */
+{ NULL, 60624, 0x00000000 }, /* BFCLR */
+{ NULL, 60648, 0x00000000 }, /* BFCLR */
+{ NULL, 60656, 0x00000000 }, /* BFCLR */
+{ NULL, 60664, 0x00000000 }, /* BFCLR */
+{ NULL, 60665, 0x00000000 }, /* BFCLR */
+{ NULL, 60864, 0x00000000 }, /* BFFFO */
+{ NULL, 60880, 0x00000000 }, /* BFFFO */
+{ NULL, 60904, 0x00000000 }, /* BFFFO */
+{ NULL, 60912, 0x00000000 }, /* BFFFO */
+{ NULL, 60920, 0x00000000 }, /* BFFFO */
+{ NULL, 60921, 0x00000000 }, /* BFFFO */
+{ NULL, 60922, 0x00000000 }, /* BFFFO */
+{ NULL, 60923, 0x00000000 }, /* BFFFO */
+{ NULL, 61120, 0x00000000 }, /* BFSET */
+{ NULL, 61136, 0x00000000 }, /* BFSET */
+{ NULL, 61160, 0x00000000 }, /* BFSET */
+{ NULL, 61168, 0x00000000 }, /* BFSET */
+{ NULL, 61176, 0x00000000 }, /* BFSET */
+{ NULL, 61177, 0x00000000 }, /* BFSET */
+{ op_efc0_0_comp_nf, 61376, 0x00000002 }, /* BFINS */
+{ op_efd0_0_comp_nf, 61392, 0x00000002 }, /* BFINS */
+{ op_efe8_0_comp_nf, 61416, 0x00000002 }, /* BFINS */
+{ op_eff0_0_comp_nf, 61424, 0x00000002 }, /* BFINS */
+{ op_eff8_0_comp_nf, 61432, 0x00000002 }, /* BFINS */
+{ op_eff9_0_comp_nf, 61433, 0x00000002 }, /* BFINS */
+{ NULL, 61440, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61448, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61456, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61464, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61472, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61480, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61488, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61496, 0x00000001 }, /* MMUOP030 */
+{ NULL, 61497, 0x00000001 }, /* MMUOP030 */
+{ op_f200_0_comp_nf, 61952, 0x00000022 }, /* FPP */
+{ op_f208_0_comp_nf, 61960, 0x00000022 }, /* FPP */
+{ op_f210_0_comp_nf, 61968, 0x00000022 }, /* FPP */
+{ op_f218_0_comp_nf, 61976, 0x00000022 }, /* FPP */
+{ op_f220_0_comp_nf, 61984, 0x00000022 }, /* FPP */
+{ op_f228_0_comp_nf, 61992, 0x00000022 }, /* FPP */
+{ op_f230_0_comp_nf, 62000, 0x00000022 }, /* FPP */
+{ op_f238_0_comp_nf, 62008, 0x00000022 }, /* FPP */
+{ op_f239_0_comp_nf, 62009, 0x00000022 }, /* FPP */
+{ op_f23a_0_comp_nf, 62010, 0x00000022 }, /* FPP */
+{ op_f23b_0_comp_nf, 62011, 0x00000022 }, /* FPP */
+{ op_f23c_0_comp_nf, 62012, 0x00000022 }, /* FPP */
+{ op_f240_0_comp_nf, 62016, 0x00000006 }, /* FScc */
+{ NULL, 62024, 0x00000021 }, /* FDBcc */
+{ op_f250_0_comp_nf, 62032, 0x00000006 }, /* FScc */
+{ op_f258_0_comp_nf, 62040, 0x00000006 }, /* FScc */
+{ op_f260_0_comp_nf, 62048, 0x00000006 }, /* FScc */
+{ op_f268_0_comp_nf, 62056, 0x00000006 }, /* FScc */
+{ op_f270_0_comp_nf, 62064, 0x00000006 }, /* FScc */
+{ op_f278_0_comp_nf, 62072, 0x00000006 }, /* FScc */
+{ op_f279_0_comp_nf, 62073, 0x00000006 }, /* FScc */
+{ NULL, 62074, 0x00000021 }, /* FTRAPcc */
+{ NULL, 62075, 0x00000021 }, /* FTRAPcc */
+{ NULL, 62076, 0x00000021 }, /* FTRAPcc */
+{ op_f280_0_comp_nf, 62080, 0x00000005 }, /* FBcc */
+{ op_f2c0_0_comp_nf, 62144, 0x00000005 }, /* FBcc */
+{ NULL, 62224, 0x00000020 }, /* FSAVE */
+{ NULL, 62240, 0x00000020 }, /* FSAVE */
+{ NULL, 62248, 0x00000020 }, /* FSAVE */
+{ NULL, 62256, 0x00000020 }, /* FSAVE */
+{ NULL, 62264, 0x00000020 }, /* FSAVE */
+{ NULL, 62265, 0x00000020 }, /* FSAVE */
+{ NULL, 62288, 0x00000020 }, /* FRESTORE */
+{ NULL, 62296, 0x00000020 }, /* FRESTORE */
+{ NULL, 62312, 0x00000020 }, /* FRESTORE */
+{ NULL, 62320, 0x00000020 }, /* FRESTORE */
+{ NULL, 62328, 0x00000020 }, /* FRESTORE */
+{ NULL, 62329, 0x00000020 }, /* FRESTORE */
+{ NULL, 62330, 0x00000020 }, /* FRESTORE */
+{ NULL, 62331, 0x00000020 }, /* FRESTORE */
+{ NULL, 62472, 0x00000001 }, /* CINVL */
+{ NULL, 62480, 0x00000001 }, /* CINVP */
+{ NULL, 62488, 0x00000001 }, /* CINVA */
+{ NULL, 62489, 0x00000001 }, /* CINVA */
+{ NULL, 62490, 0x00000001 }, /* CINVA */
+{ NULL, 62491, 0x00000001 }, /* CINVA */
+{ NULL, 62492, 0x00000001 }, /* CINVA */
+{ NULL, 62493, 0x00000001 }, /* CINVA */
+{ NULL, 62494, 0x00000001 }, /* CINVA */
+{ NULL, 62495, 0x00000001 }, /* CINVA */
+{ NULL, 62504, 0x00000001 }, /* CPUSHL */
+{ NULL, 62512, 0x00000001 }, /* CPUSHP */
+{ NULL, 62520, 0x00000001 }, /* CPUSHA */
+{ NULL, 62521, 0x00000001 }, /* CPUSHA */
+{ NULL, 62522, 0x00000001 }, /* CPUSHA */
+{ NULL, 62523, 0x00000001 }, /* CPUSHA */
+{ NULL, 62524, 0x00000001 }, /* CPUSHA */
+{ NULL, 62525, 0x00000001 }, /* CPUSHA */
+{ NULL, 62526, 0x00000001 }, /* CPUSHA */
+{ NULL, 62527, 0x00000001 }, /* CPUSHA */
+{ NULL, 62720, 0x00000001 }, /* PFLUSHN */
+{ NULL, 62728, 0x00000001 }, /* PFLUSH */
+{ NULL, 62736, 0x00000001 }, /* PFLUSHAN */
+{ NULL, 62744, 0x00000001 }, /* PFLUSHA */
+{ NULL, 62792, 0x00000001 }, /* PTESTW */
+{ NULL, 62824, 0x00000001 }, /* PTESTR */
+{ op_f600_0_comp_nf, 62976, 0x00000002 }, /* MOVE16 */
+{ op_f608_0_comp_nf, 62984, 0x00000002 }, /* MOVE16 */
+{ op_f610_0_comp_nf, 62992, 0x00000002 }, /* MOVE16 */
+{ op_f618_0_comp_nf, 63000, 0x00000002 }, /* MOVE16 */
+{ op_f620_0_comp_nf, 63008, 0x00000002 }, /* MOVE16 */
+{ 0, 65536, 0 }};
+#endif
diff --git a/jit/arm/comptbl_arm.h b/jit/arm/comptbl_arm.h
new file mode 100644
index 00000000..872e4e0c
--- /dev/null
+++ b/jit/arm/comptbl_arm.h
@@ -0,0 +1,3054 @@
+extern const struct comptbl op_smalltbl_0_comp_nf[];
+extern const struct comptbl op_smalltbl_0_comp_ff[];
+extern compop_func op_0_0_comp_ff;
+extern compop_func op_10_0_comp_ff;
+extern compop_func op_18_0_comp_ff;
+extern compop_func op_20_0_comp_ff;
+extern compop_func op_28_0_comp_ff;
+extern compop_func op_30_0_comp_ff;
+extern compop_func op_38_0_comp_ff;
+extern compop_func op_39_0_comp_ff;
+extern compop_func op_3c_0_comp_ff;
+extern compop_func op_40_0_comp_ff;
+extern compop_func op_50_0_comp_ff;
+extern compop_func op_58_0_comp_ff;
+extern compop_func op_60_0_comp_ff;
+extern compop_func op_68_0_comp_ff;
+extern compop_func op_70_0_comp_ff;
+extern compop_func op_78_0_comp_ff;
+extern compop_func op_79_0_comp_ff;
+extern compop_func op_80_0_comp_ff;
+extern compop_func op_90_0_comp_ff;
+extern compop_func op_98_0_comp_ff;
+extern compop_func op_a0_0_comp_ff;
+extern compop_func op_a8_0_comp_ff;
+extern compop_func op_b0_0_comp_ff;
+extern compop_func op_b8_0_comp_ff;
+extern compop_func op_b9_0_comp_ff;
+extern compop_func op_100_0_comp_ff;
+extern compop_func op_110_0_comp_ff;
+extern compop_func op_118_0_comp_ff;
+extern compop_func op_120_0_comp_ff;
+extern compop_func op_128_0_comp_ff;
+extern compop_func op_130_0_comp_ff;
+extern compop_func op_138_0_comp_ff;
+extern compop_func op_139_0_comp_ff;
+extern compop_func op_13a_0_comp_ff;
+extern compop_func op_13b_0_comp_ff;
+extern compop_func op_13c_0_comp_ff;
+extern compop_func op_140_0_comp_ff;
+extern compop_func op_150_0_comp_ff;
+extern compop_func op_158_0_comp_ff;
+extern compop_func op_160_0_comp_ff;
+extern compop_func op_168_0_comp_ff;
+extern compop_func op_170_0_comp_ff;
+extern compop_func op_178_0_comp_ff;
+extern compop_func op_179_0_comp_ff;
+extern compop_func op_180_0_comp_ff;
+extern compop_func op_190_0_comp_ff;
+extern compop_func op_198_0_comp_ff;
+extern compop_func op_1a0_0_comp_ff;
+extern compop_func op_1a8_0_comp_ff;
+extern compop_func op_1b0_0_comp_ff;
+extern compop_func op_1b8_0_comp_ff;
+extern compop_func op_1b9_0_comp_ff;
+extern compop_func op_1c0_0_comp_ff;
+extern compop_func op_1d0_0_comp_ff;
+extern compop_func op_1d8_0_comp_ff;
+extern compop_func op_1e0_0_comp_ff;
+extern compop_func op_1e8_0_comp_ff;
+extern compop_func op_1f0_0_comp_ff;
+extern compop_func op_1f8_0_comp_ff;
+extern compop_func op_1f9_0_comp_ff;
+extern compop_func op_200_0_comp_ff;
+extern compop_func op_210_0_comp_ff;
+extern compop_func op_218_0_comp_ff;
+extern compop_func op_220_0_comp_ff;
+extern compop_func op_228_0_comp_ff;
+extern compop_func op_230_0_comp_ff;
+extern compop_func op_238_0_comp_ff;
+extern compop_func op_239_0_comp_ff;
+extern compop_func op_23c_0_comp_ff;
+extern compop_func op_240_0_comp_ff;
+extern compop_func op_250_0_comp_ff;
+extern compop_func op_258_0_comp_ff;
+extern compop_func op_260_0_comp_ff;
+extern compop_func op_268_0_comp_ff;
+extern compop_func op_270_0_comp_ff;
+extern compop_func op_278_0_comp_ff;
+extern compop_func op_279_0_comp_ff;
+extern compop_func op_280_0_comp_ff;
+extern compop_func op_290_0_comp_ff;
+extern compop_func op_298_0_comp_ff;
+extern compop_func op_2a0_0_comp_ff;
+extern compop_func op_2a8_0_comp_ff;
+extern compop_func op_2b0_0_comp_ff;
+extern compop_func op_2b8_0_comp_ff;
+extern compop_func op_2b9_0_comp_ff;
+extern compop_func op_400_0_comp_ff;
+extern compop_func op_410_0_comp_ff;
+extern compop_func op_418_0_comp_ff;
+extern compop_func op_420_0_comp_ff;
+extern compop_func op_428_0_comp_ff;
+extern compop_func op_430_0_comp_ff;
+extern compop_func op_438_0_comp_ff;
+extern compop_func op_439_0_comp_ff;
+extern compop_func op_440_0_comp_ff;
+extern compop_func op_450_0_comp_ff;
+extern compop_func op_458_0_comp_ff;
+extern compop_func op_460_0_comp_ff;
+extern compop_func op_468_0_comp_ff;
+extern compop_func op_470_0_comp_ff;
+extern compop_func op_478_0_comp_ff;
+extern compop_func op_479_0_comp_ff;
+extern compop_func op_480_0_comp_ff;
+extern compop_func op_490_0_comp_ff;
+extern compop_func op_498_0_comp_ff;
+extern compop_func op_4a0_0_comp_ff;
+extern compop_func op_4a8_0_comp_ff;
+extern compop_func op_4b0_0_comp_ff;
+extern compop_func op_4b8_0_comp_ff;
+extern compop_func op_4b9_0_comp_ff;
+extern compop_func op_600_0_comp_ff;
+extern compop_func op_610_0_comp_ff;
+extern compop_func op_618_0_comp_ff;
+extern compop_func op_620_0_comp_ff;
+extern compop_func op_628_0_comp_ff;
+extern compop_func op_630_0_comp_ff;
+extern compop_func op_638_0_comp_ff;
+extern compop_func op_639_0_comp_ff;
+extern compop_func op_640_0_comp_ff;
+extern compop_func op_650_0_comp_ff;
+extern compop_func op_658_0_comp_ff;
+extern compop_func op_660_0_comp_ff;
+extern compop_func op_668_0_comp_ff;
+extern compop_func op_670_0_comp_ff;
+extern compop_func op_678_0_comp_ff;
+extern compop_func op_679_0_comp_ff;
+extern compop_func op_680_0_comp_ff;
+extern compop_func op_690_0_comp_ff;
+extern compop_func op_698_0_comp_ff;
+extern compop_func op_6a0_0_comp_ff;
+extern compop_func op_6a8_0_comp_ff;
+extern compop_func op_6b0_0_comp_ff;
+extern compop_func op_6b8_0_comp_ff;
+extern compop_func op_6b9_0_comp_ff;
+extern compop_func op_800_0_comp_ff;
+extern compop_func op_810_0_comp_ff;
+extern compop_func op_818_0_comp_ff;
+extern compop_func op_820_0_comp_ff;
+extern compop_func op_828_0_comp_ff;
+extern compop_func op_830_0_comp_ff;
+extern compop_func op_838_0_comp_ff;
+extern compop_func op_839_0_comp_ff;
+extern compop_func op_83a_0_comp_ff;
+extern compop_func op_83b_0_comp_ff;
+extern compop_func op_840_0_comp_ff;
+extern compop_func op_850_0_comp_ff;
+extern compop_func op_858_0_comp_ff;
+extern compop_func op_860_0_comp_ff;
+extern compop_func op_868_0_comp_ff;
+extern compop_func op_870_0_comp_ff;
+extern compop_func op_878_0_comp_ff;
+extern compop_func op_879_0_comp_ff;
+extern compop_func op_880_0_comp_ff;
+extern compop_func op_890_0_comp_ff;
+extern compop_func op_898_0_comp_ff;
+extern compop_func op_8a0_0_comp_ff;
+extern compop_func op_8a8_0_comp_ff;
+extern compop_func op_8b0_0_comp_ff;
+extern compop_func op_8b8_0_comp_ff;
+extern compop_func op_8b9_0_comp_ff;
+extern compop_func op_8c0_0_comp_ff;
+extern compop_func op_8d0_0_comp_ff;
+extern compop_func op_8d8_0_comp_ff;
+extern compop_func op_8e0_0_comp_ff;
+extern compop_func op_8e8_0_comp_ff;
+extern compop_func op_8f0_0_comp_ff;
+extern compop_func op_8f8_0_comp_ff;
+extern compop_func op_8f9_0_comp_ff;
+extern compop_func op_a00_0_comp_ff;
+extern compop_func op_a10_0_comp_ff;
+extern compop_func op_a18_0_comp_ff;
+extern compop_func op_a20_0_comp_ff;
+extern compop_func op_a28_0_comp_ff;
+extern compop_func op_a30_0_comp_ff;
+extern compop_func op_a38_0_comp_ff;
+extern compop_func op_a39_0_comp_ff;
+extern compop_func op_a3c_0_comp_ff;
+extern compop_func op_a40_0_comp_ff;
+extern compop_func op_a50_0_comp_ff;
+extern compop_func op_a58_0_comp_ff;
+extern compop_func op_a60_0_comp_ff;
+extern compop_func op_a68_0_comp_ff;
+extern compop_func op_a70_0_comp_ff;
+extern compop_func op_a78_0_comp_ff;
+extern compop_func op_a79_0_comp_ff;
+extern compop_func op_a80_0_comp_ff;
+extern compop_func op_a90_0_comp_ff;
+extern compop_func op_a98_0_comp_ff;
+extern compop_func op_aa0_0_comp_ff;
+extern compop_func op_aa8_0_comp_ff;
+extern compop_func op_ab0_0_comp_ff;
+extern compop_func op_ab8_0_comp_ff;
+extern compop_func op_ab9_0_comp_ff;
+extern compop_func op_c00_0_comp_ff;
+extern compop_func op_c10_0_comp_ff;
+extern compop_func op_c18_0_comp_ff;
+extern compop_func op_c20_0_comp_ff;
+extern compop_func op_c28_0_comp_ff;
+extern compop_func op_c30_0_comp_ff;
+extern compop_func op_c38_0_comp_ff;
+extern compop_func op_c39_0_comp_ff;
+extern compop_func op_c3a_0_comp_ff;
+extern compop_func op_c3b_0_comp_ff;
+extern compop_func op_c40_0_comp_ff;
+extern compop_func op_c50_0_comp_ff;
+extern compop_func op_c58_0_comp_ff;
+extern compop_func op_c60_0_comp_ff;
+extern compop_func op_c68_0_comp_ff;
+extern compop_func op_c70_0_comp_ff;
+extern compop_func op_c78_0_comp_ff;
+extern compop_func op_c79_0_comp_ff;
+extern compop_func op_c7a_0_comp_ff;
+extern compop_func op_c7b_0_comp_ff;
+extern compop_func op_c80_0_comp_ff;
+extern compop_func op_c90_0_comp_ff;
+extern compop_func op_c98_0_comp_ff;
+extern compop_func op_ca0_0_comp_ff;
+extern compop_func op_ca8_0_comp_ff;
+extern compop_func op_cb0_0_comp_ff;
+extern compop_func op_cb8_0_comp_ff;
+extern compop_func op_cb9_0_comp_ff;
+extern compop_func op_cba_0_comp_ff;
+extern compop_func op_cbb_0_comp_ff;
+extern compop_func op_1000_0_comp_ff;
+extern compop_func op_1010_0_comp_ff;
+extern compop_func op_1018_0_comp_ff;
+extern compop_func op_1020_0_comp_ff;
+extern compop_func op_1028_0_comp_ff;
+extern compop_func op_1030_0_comp_ff;
+extern compop_func op_1038_0_comp_ff;
+extern compop_func op_1039_0_comp_ff;
+extern compop_func op_103a_0_comp_ff;
+extern compop_func op_103b_0_comp_ff;
+extern compop_func op_103c_0_comp_ff;
+extern compop_func op_1080_0_comp_ff;
+extern compop_func op_1090_0_comp_ff;
+extern compop_func op_1098_0_comp_ff;
+extern compop_func op_10a0_0_comp_ff;
+extern compop_func op_10a8_0_comp_ff;
+extern compop_func op_10b0_0_comp_ff;
+extern compop_func op_10b8_0_comp_ff;
+extern compop_func op_10b9_0_comp_ff;
+extern compop_func op_10ba_0_comp_ff;
+extern compop_func op_10bb_0_comp_ff;
+extern compop_func op_10bc_0_comp_ff;
+extern compop_func op_10c0_0_comp_ff;
+extern compop_func op_10d0_0_comp_ff;
+extern compop_func op_10d8_0_comp_ff;
+extern compop_func op_10e0_0_comp_ff;
+extern compop_func op_10e8_0_comp_ff;
+extern compop_func op_10f0_0_comp_ff;
+extern compop_func op_10f8_0_comp_ff;
+extern compop_func op_10f9_0_comp_ff;
+extern compop_func op_10fa_0_comp_ff;
+extern compop_func op_10fb_0_comp_ff;
+extern compop_func op_10fc_0_comp_ff;
+extern compop_func op_1100_0_comp_ff;
+extern compop_func op_1110_0_comp_ff;
+extern compop_func op_1118_0_comp_ff;
+extern compop_func op_1120_0_comp_ff;
+extern compop_func op_1128_0_comp_ff;
+extern compop_func op_1130_0_comp_ff;
+extern compop_func op_1138_0_comp_ff;
+extern compop_func op_1139_0_comp_ff;
+extern compop_func op_113a_0_comp_ff;
+extern compop_func op_113b_0_comp_ff;
+extern compop_func op_113c_0_comp_ff;
+extern compop_func op_1140_0_comp_ff;
+extern compop_func op_1150_0_comp_ff;
+extern compop_func op_1158_0_comp_ff;
+extern compop_func op_1160_0_comp_ff;
+extern compop_func op_1168_0_comp_ff;
+extern compop_func op_1170_0_comp_ff;
+extern compop_func op_1178_0_comp_ff;
+extern compop_func op_1179_0_comp_ff;
+extern compop_func op_117a_0_comp_ff;
+extern compop_func op_117b_0_comp_ff;
+extern compop_func op_117c_0_comp_ff;
+extern compop_func op_1180_0_comp_ff;
+extern compop_func op_1190_0_comp_ff;
+extern compop_func op_1198_0_comp_ff;
+extern compop_func op_11a0_0_comp_ff;
+extern compop_func op_11a8_0_comp_ff;
+extern compop_func op_11b0_0_comp_ff;
+extern compop_func op_11b8_0_comp_ff;
+extern compop_func op_11b9_0_comp_ff;
+extern compop_func op_11ba_0_comp_ff;
+extern compop_func op_11bb_0_comp_ff;
+extern compop_func op_11bc_0_comp_ff;
+extern compop_func op_11c0_0_comp_ff;
+extern compop_func op_11d0_0_comp_ff;
+extern compop_func op_11d8_0_comp_ff;
+extern compop_func op_11e0_0_comp_ff;
+extern compop_func op_11e8_0_comp_ff;
+extern compop_func op_11f0_0_comp_ff;
+extern compop_func op_11f8_0_comp_ff;
+extern compop_func op_11f9_0_comp_ff;
+extern compop_func op_11fa_0_comp_ff;
+extern compop_func op_11fb_0_comp_ff;
+extern compop_func op_11fc_0_comp_ff;
+extern compop_func op_13c0_0_comp_ff;
+extern compop_func op_13d0_0_comp_ff;
+extern compop_func op_13d8_0_comp_ff;
+extern compop_func op_13e0_0_comp_ff;
+extern compop_func op_13e8_0_comp_ff;
+extern compop_func op_13f0_0_comp_ff;
+extern compop_func op_13f8_0_comp_ff;
+extern compop_func op_13f9_0_comp_ff;
+extern compop_func op_13fa_0_comp_ff;
+extern compop_func op_13fb_0_comp_ff;
+extern compop_func op_13fc_0_comp_ff;
+extern compop_func op_2000_0_comp_ff;
+extern compop_func op_2008_0_comp_ff;
+extern compop_func op_2010_0_comp_ff;
+extern compop_func op_2018_0_comp_ff;
+extern compop_func op_2020_0_comp_ff;
+extern compop_func op_2028_0_comp_ff;
+extern compop_func op_2030_0_comp_ff;
+extern compop_func op_2038_0_comp_ff;
+extern compop_func op_2039_0_comp_ff;
+extern compop_func op_203a_0_comp_ff;
+extern compop_func op_203b_0_comp_ff;
+extern compop_func op_203c_0_comp_ff;
+extern compop_func op_2040_0_comp_ff;
+extern compop_func op_2048_0_comp_ff;
+extern compop_func op_2050_0_comp_ff;
+extern compop_func op_2058_0_comp_ff;
+extern compop_func op_2060_0_comp_ff;
+extern compop_func op_2068_0_comp_ff;
+extern compop_func op_2070_0_comp_ff;
+extern compop_func op_2078_0_comp_ff;
+extern compop_func op_2079_0_comp_ff;
+extern compop_func op_207a_0_comp_ff;
+extern compop_func op_207b_0_comp_ff;
+extern compop_func op_207c_0_comp_ff;
+extern compop_func op_2080_0_comp_ff;
+extern compop_func op_2088_0_comp_ff;
+extern compop_func op_2090_0_comp_ff;
+extern compop_func op_2098_0_comp_ff;
+extern compop_func op_20a0_0_comp_ff;
+extern compop_func op_20a8_0_comp_ff;
+extern compop_func op_20b0_0_comp_ff;
+extern compop_func op_20b8_0_comp_ff;
+extern compop_func op_20b9_0_comp_ff;
+extern compop_func op_20ba_0_comp_ff;
+extern compop_func op_20bb_0_comp_ff;
+extern compop_func op_20bc_0_comp_ff;
+extern compop_func op_20c0_0_comp_ff;
+extern compop_func op_20c8_0_comp_ff;
+extern compop_func op_20d0_0_comp_ff;
+extern compop_func op_20d8_0_comp_ff;
+extern compop_func op_20e0_0_comp_ff;
+extern compop_func op_20e8_0_comp_ff;
+extern compop_func op_20f0_0_comp_ff;
+extern compop_func op_20f8_0_comp_ff;
+extern compop_func op_20f9_0_comp_ff;
+extern compop_func op_20fa_0_comp_ff;
+extern compop_func op_20fb_0_comp_ff;
+extern compop_func op_20fc_0_comp_ff;
+extern compop_func op_2100_0_comp_ff;
+extern compop_func op_2108_0_comp_ff;
+extern compop_func op_2110_0_comp_ff;
+extern compop_func op_2118_0_comp_ff;
+extern compop_func op_2120_0_comp_ff;
+extern compop_func op_2128_0_comp_ff;
+extern compop_func op_2130_0_comp_ff;
+extern compop_func op_2138_0_comp_ff;
+extern compop_func op_2139_0_comp_ff;
+extern compop_func op_213a_0_comp_ff;
+extern compop_func op_213b_0_comp_ff;
+extern compop_func op_213c_0_comp_ff;
+extern compop_func op_2140_0_comp_ff;
+extern compop_func op_2148_0_comp_ff;
+extern compop_func op_2150_0_comp_ff;
+extern compop_func op_2158_0_comp_ff;
+extern compop_func op_2160_0_comp_ff;
+extern compop_func op_2168_0_comp_ff;
+extern compop_func op_2170_0_comp_ff;
+extern compop_func op_2178_0_comp_ff;
+extern compop_func op_2179_0_comp_ff;
+extern compop_func op_217a_0_comp_ff;
+extern compop_func op_217b_0_comp_ff;
+extern compop_func op_217c_0_comp_ff;
+extern compop_func op_2180_0_comp_ff;
+extern compop_func op_2188_0_comp_ff;
+extern compop_func op_2190_0_comp_ff;
+extern compop_func op_2198_0_comp_ff;
+extern compop_func op_21a0_0_comp_ff;
+extern compop_func op_21a8_0_comp_ff;
+extern compop_func op_21b0_0_comp_ff;
+extern compop_func op_21b8_0_comp_ff;
+extern compop_func op_21b9_0_comp_ff;
+extern compop_func op_21ba_0_comp_ff;
+extern compop_func op_21bb_0_comp_ff;
+extern compop_func op_21bc_0_comp_ff;
+extern compop_func op_21c0_0_comp_ff;
+extern compop_func op_21c8_0_comp_ff;
+extern compop_func op_21d0_0_comp_ff;
+extern compop_func op_21d8_0_comp_ff;
+extern compop_func op_21e0_0_comp_ff;
+extern compop_func op_21e8_0_comp_ff;
+extern compop_func op_21f0_0_comp_ff;
+extern compop_func op_21f8_0_comp_ff;
+extern compop_func op_21f9_0_comp_ff;
+extern compop_func op_21fa_0_comp_ff;
+extern compop_func op_21fb_0_comp_ff;
+extern compop_func op_21fc_0_comp_ff;
+extern compop_func op_23c0_0_comp_ff;
+extern compop_func op_23c8_0_comp_ff;
+extern compop_func op_23d0_0_comp_ff;
+extern compop_func op_23d8_0_comp_ff;
+extern compop_func op_23e0_0_comp_ff;
+extern compop_func op_23e8_0_comp_ff;
+extern compop_func op_23f0_0_comp_ff;
+extern compop_func op_23f8_0_comp_ff;
+extern compop_func op_23f9_0_comp_ff;
+extern compop_func op_23fa_0_comp_ff;
+extern compop_func op_23fb_0_comp_ff;
+extern compop_func op_23fc_0_comp_ff;
+extern compop_func op_3000_0_comp_ff;
+extern compop_func op_3008_0_comp_ff;
+extern compop_func op_3010_0_comp_ff;
+extern compop_func op_3018_0_comp_ff;
+extern compop_func op_3020_0_comp_ff;
+extern compop_func op_3028_0_comp_ff;
+extern compop_func op_3030_0_comp_ff;
+extern compop_func op_3038_0_comp_ff;
+extern compop_func op_3039_0_comp_ff;
+extern compop_func op_303a_0_comp_ff;
+extern compop_func op_303b_0_comp_ff;
+extern compop_func op_303c_0_comp_ff;
+extern compop_func op_3040_0_comp_ff;
+extern compop_func op_3048_0_comp_ff;
+extern compop_func op_3050_0_comp_ff;
+extern compop_func op_3058_0_comp_ff;
+extern compop_func op_3060_0_comp_ff;
+extern compop_func op_3068_0_comp_ff;
+extern compop_func op_3070_0_comp_ff;
+extern compop_func op_3078_0_comp_ff;
+extern compop_func op_3079_0_comp_ff;
+extern compop_func op_307a_0_comp_ff;
+extern compop_func op_307b_0_comp_ff;
+extern compop_func op_307c_0_comp_ff;
+extern compop_func op_3080_0_comp_ff;
+extern compop_func op_3088_0_comp_ff;
+extern compop_func op_3090_0_comp_ff;
+extern compop_func op_3098_0_comp_ff;
+extern compop_func op_30a0_0_comp_ff;
+extern compop_func op_30a8_0_comp_ff;
+extern compop_func op_30b0_0_comp_ff;
+extern compop_func op_30b8_0_comp_ff;
+extern compop_func op_30b9_0_comp_ff;
+extern compop_func op_30ba_0_comp_ff;
+extern compop_func op_30bb_0_comp_ff;
+extern compop_func op_30bc_0_comp_ff;
+extern compop_func op_30c0_0_comp_ff;
+extern compop_func op_30c8_0_comp_ff;
+extern compop_func op_30d0_0_comp_ff;
+extern compop_func op_30d8_0_comp_ff;
+extern compop_func op_30e0_0_comp_ff;
+extern compop_func op_30e8_0_comp_ff;
+extern compop_func op_30f0_0_comp_ff;
+extern compop_func op_30f8_0_comp_ff;
+extern compop_func op_30f9_0_comp_ff;
+extern compop_func op_30fa_0_comp_ff;
+extern compop_func op_30fb_0_comp_ff;
+extern compop_func op_30fc_0_comp_ff;
+extern compop_func op_3100_0_comp_ff;
+extern compop_func op_3108_0_comp_ff;
+extern compop_func op_3110_0_comp_ff;
+extern compop_func op_3118_0_comp_ff;
+extern compop_func op_3120_0_comp_ff;
+extern compop_func op_3128_0_comp_ff;
+extern compop_func op_3130_0_comp_ff;
+extern compop_func op_3138_0_comp_ff;
+extern compop_func op_3139_0_comp_ff;
+extern compop_func op_313a_0_comp_ff;
+extern compop_func op_313b_0_comp_ff;
+extern compop_func op_313c_0_comp_ff;
+extern compop_func op_3140_0_comp_ff;
+extern compop_func op_3148_0_comp_ff;
+extern compop_func op_3150_0_comp_ff;
+extern compop_func op_3158_0_comp_ff;
+extern compop_func op_3160_0_comp_ff;
+extern compop_func op_3168_0_comp_ff;
+extern compop_func op_3170_0_comp_ff;
+extern compop_func op_3178_0_comp_ff;
+extern compop_func op_3179_0_comp_ff;
+extern compop_func op_317a_0_comp_ff;
+extern compop_func op_317b_0_comp_ff;
+extern compop_func op_317c_0_comp_ff;
+extern compop_func op_3180_0_comp_ff;
+extern compop_func op_3188_0_comp_ff;
+extern compop_func op_3190_0_comp_ff;
+extern compop_func op_3198_0_comp_ff;
+extern compop_func op_31a0_0_comp_ff;
+extern compop_func op_31a8_0_comp_ff;
+extern compop_func op_31b0_0_comp_ff;
+extern compop_func op_31b8_0_comp_ff;
+extern compop_func op_31b9_0_comp_ff;
+extern compop_func op_31ba_0_comp_ff;
+extern compop_func op_31bb_0_comp_ff;
+extern compop_func op_31bc_0_comp_ff;
+extern compop_func op_31c0_0_comp_ff;
+extern compop_func op_31c8_0_comp_ff;
+extern compop_func op_31d0_0_comp_ff;
+extern compop_func op_31d8_0_comp_ff;
+extern compop_func op_31e0_0_comp_ff;
+extern compop_func op_31e8_0_comp_ff;
+extern compop_func op_31f0_0_comp_ff;
+extern compop_func op_31f8_0_comp_ff;
+extern compop_func op_31f9_0_comp_ff;
+extern compop_func op_31fa_0_comp_ff;
+extern compop_func op_31fb_0_comp_ff;
+extern compop_func op_31fc_0_comp_ff;
+extern compop_func op_33c0_0_comp_ff;
+extern compop_func op_33c8_0_comp_ff;
+extern compop_func op_33d0_0_comp_ff;
+extern compop_func op_33d8_0_comp_ff;
+extern compop_func op_33e0_0_comp_ff;
+extern compop_func op_33e8_0_comp_ff;
+extern compop_func op_33f0_0_comp_ff;
+extern compop_func op_33f8_0_comp_ff;
+extern compop_func op_33f9_0_comp_ff;
+extern compop_func op_33fa_0_comp_ff;
+extern compop_func op_33fb_0_comp_ff;
+extern compop_func op_33fc_0_comp_ff;
+extern compop_func op_4000_0_comp_ff;
+extern compop_func op_4010_0_comp_ff;
+extern compop_func op_4018_0_comp_ff;
+extern compop_func op_4020_0_comp_ff;
+extern compop_func op_4028_0_comp_ff;
+extern compop_func op_4030_0_comp_ff;
+extern compop_func op_4038_0_comp_ff;
+extern compop_func op_4039_0_comp_ff;
+extern compop_func op_4040_0_comp_ff;
+extern compop_func op_4050_0_comp_ff;
+extern compop_func op_4058_0_comp_ff;
+extern compop_func op_4060_0_comp_ff;
+extern compop_func op_4068_0_comp_ff;
+extern compop_func op_4070_0_comp_ff;
+extern compop_func op_4078_0_comp_ff;
+extern compop_func op_4079_0_comp_ff;
+extern compop_func op_4080_0_comp_ff;
+extern compop_func op_4090_0_comp_ff;
+extern compop_func op_4098_0_comp_ff;
+extern compop_func op_40a0_0_comp_ff;
+extern compop_func op_40a8_0_comp_ff;
+extern compop_func op_40b0_0_comp_ff;
+extern compop_func op_40b8_0_comp_ff;
+extern compop_func op_40b9_0_comp_ff;
+extern compop_func op_41d0_0_comp_ff;
+extern compop_func op_41e8_0_comp_ff;
+extern compop_func op_41f0_0_comp_ff;
+extern compop_func op_41f8_0_comp_ff;
+extern compop_func op_41f9_0_comp_ff;
+extern compop_func op_41fa_0_comp_ff;
+extern compop_func op_41fb_0_comp_ff;
+extern compop_func op_4200_0_comp_ff;
+extern compop_func op_4210_0_comp_ff;
+extern compop_func op_4218_0_comp_ff;
+extern compop_func op_4220_0_comp_ff;
+extern compop_func op_4228_0_comp_ff;
+extern compop_func op_4230_0_comp_ff;
+extern compop_func op_4238_0_comp_ff;
+extern compop_func op_4239_0_comp_ff;
+extern compop_func op_4240_0_comp_ff;
+extern compop_func op_4250_0_comp_ff;
+extern compop_func op_4258_0_comp_ff;
+extern compop_func op_4260_0_comp_ff;
+extern compop_func op_4268_0_comp_ff;
+extern compop_func op_4270_0_comp_ff;
+extern compop_func op_4278_0_comp_ff;
+extern compop_func op_4279_0_comp_ff;
+extern compop_func op_4280_0_comp_ff;
+extern compop_func op_4290_0_comp_ff;
+extern compop_func op_4298_0_comp_ff;
+extern compop_func op_42a0_0_comp_ff;
+extern compop_func op_42a8_0_comp_ff;
+extern compop_func op_42b0_0_comp_ff;
+extern compop_func op_42b8_0_comp_ff;
+extern compop_func op_42b9_0_comp_ff;
+extern compop_func op_4400_0_comp_ff;
+extern compop_func op_4410_0_comp_ff;
+extern compop_func op_4418_0_comp_ff;
+extern compop_func op_4420_0_comp_ff;
+extern compop_func op_4428_0_comp_ff;
+extern compop_func op_4430_0_comp_ff;
+extern compop_func op_4438_0_comp_ff;
+extern compop_func op_4439_0_comp_ff;
+extern compop_func op_4440_0_comp_ff;
+extern compop_func op_4450_0_comp_ff;
+extern compop_func op_4458_0_comp_ff;
+extern compop_func op_4460_0_comp_ff;
+extern compop_func op_4468_0_comp_ff;
+extern compop_func op_4470_0_comp_ff;
+extern compop_func op_4478_0_comp_ff;
+extern compop_func op_4479_0_comp_ff;
+extern compop_func op_4480_0_comp_ff;
+extern compop_func op_4490_0_comp_ff;
+extern compop_func op_4498_0_comp_ff;
+extern compop_func op_44a0_0_comp_ff;
+extern compop_func op_44a8_0_comp_ff;
+extern compop_func op_44b0_0_comp_ff;
+extern compop_func op_44b8_0_comp_ff;
+extern compop_func op_44b9_0_comp_ff;
+extern compop_func op_4600_0_comp_ff;
+extern compop_func op_4610_0_comp_ff;
+extern compop_func op_4618_0_comp_ff;
+extern compop_func op_4620_0_comp_ff;
+extern compop_func op_4628_0_comp_ff;
+extern compop_func op_4630_0_comp_ff;
+extern compop_func op_4638_0_comp_ff;
+extern compop_func op_4639_0_comp_ff;
+extern compop_func op_4640_0_comp_ff;
+extern compop_func op_4650_0_comp_ff;
+extern compop_func op_4658_0_comp_ff;
+extern compop_func op_4660_0_comp_ff;
+extern compop_func op_4668_0_comp_ff;
+extern compop_func op_4670_0_comp_ff;
+extern compop_func op_4678_0_comp_ff;
+extern compop_func op_4679_0_comp_ff;
+extern compop_func op_4680_0_comp_ff;
+extern compop_func op_4690_0_comp_ff;
+extern compop_func op_4698_0_comp_ff;
+extern compop_func op_46a0_0_comp_ff;
+extern compop_func op_46a8_0_comp_ff;
+extern compop_func op_46b0_0_comp_ff;
+extern compop_func op_46b8_0_comp_ff;
+extern compop_func op_46b9_0_comp_ff;
+extern compop_func op_4808_0_comp_ff;
+extern compop_func op_4840_0_comp_ff;
+extern compop_func op_4850_0_comp_ff;
+extern compop_func op_4868_0_comp_ff;
+extern compop_func op_4870_0_comp_ff;
+extern compop_func op_4878_0_comp_ff;
+extern compop_func op_4879_0_comp_ff;
+extern compop_func op_487a_0_comp_ff;
+extern compop_func op_487b_0_comp_ff;
+extern compop_func op_4880_0_comp_ff;
+extern compop_func op_4890_0_comp_ff;
+extern compop_func op_48a0_0_comp_ff;
+extern compop_func op_48a8_0_comp_ff;
+extern compop_func op_48b0_0_comp_ff;
+extern compop_func op_48b8_0_comp_ff;
+extern compop_func op_48b9_0_comp_ff;
+extern compop_func op_48c0_0_comp_ff;
+extern compop_func op_48d0_0_comp_ff;
+extern compop_func op_48e0_0_comp_ff;
+extern compop_func op_48e8_0_comp_ff;
+extern compop_func op_48f0_0_comp_ff;
+extern compop_func op_48f8_0_comp_ff;
+extern compop_func op_48f9_0_comp_ff;
+extern compop_func op_49c0_0_comp_ff;
+extern compop_func op_4a00_0_comp_ff;
+extern compop_func op_4a10_0_comp_ff;
+extern compop_func op_4a18_0_comp_ff;
+extern compop_func op_4a20_0_comp_ff;
+extern compop_func op_4a28_0_comp_ff;
+extern compop_func op_4a30_0_comp_ff;
+extern compop_func op_4a38_0_comp_ff;
+extern compop_func op_4a39_0_comp_ff;
+extern compop_func op_4a3a_0_comp_ff;
+extern compop_func op_4a3b_0_comp_ff;
+extern compop_func op_4a3c_0_comp_ff;
+extern compop_func op_4a40_0_comp_ff;
+extern compop_func op_4a48_0_comp_ff;
+extern compop_func op_4a50_0_comp_ff;
+extern compop_func op_4a58_0_comp_ff;
+extern compop_func op_4a60_0_comp_ff;
+extern compop_func op_4a68_0_comp_ff;
+extern compop_func op_4a70_0_comp_ff;
+extern compop_func op_4a78_0_comp_ff;
+extern compop_func op_4a79_0_comp_ff;
+extern compop_func op_4a7a_0_comp_ff;
+extern compop_func op_4a7b_0_comp_ff;
+extern compop_func op_4a7c_0_comp_ff;
+extern compop_func op_4a80_0_comp_ff;
+extern compop_func op_4a88_0_comp_ff;
+extern compop_func op_4a90_0_comp_ff;
+extern compop_func op_4a98_0_comp_ff;
+extern compop_func op_4aa0_0_comp_ff;
+extern compop_func op_4aa8_0_comp_ff;
+extern compop_func op_4ab0_0_comp_ff;
+extern compop_func op_4ab8_0_comp_ff;
+extern compop_func op_4ab9_0_comp_ff;
+extern compop_func op_4aba_0_comp_ff;
+extern compop_func op_4abb_0_comp_ff;
+extern compop_func op_4abc_0_comp_ff;
+extern compop_func op_4c00_0_comp_ff;
+extern compop_func op_4c10_0_comp_ff;
+extern compop_func op_4c18_0_comp_ff;
+extern compop_func op_4c20_0_comp_ff;
+extern compop_func op_4c28_0_comp_ff;
+extern compop_func op_4c30_0_comp_ff;
+extern compop_func op_4c38_0_comp_ff;
+extern compop_func op_4c39_0_comp_ff;
+extern compop_func op_4c3a_0_comp_ff;
+extern compop_func op_4c3b_0_comp_ff;
+extern compop_func op_4c3c_0_comp_ff;
+extern compop_func op_4c40_0_comp_ff;
+extern compop_func op_4c50_0_comp_ff;
+extern compop_func op_4c58_0_comp_ff;
+extern compop_func op_4c60_0_comp_ff;
+extern compop_func op_4c68_0_comp_ff;
+extern compop_func op_4c70_0_comp_ff;
+extern compop_func op_4c78_0_comp_ff;
+extern compop_func op_4c79_0_comp_ff;
+extern compop_func op_4c7a_0_comp_ff;
+extern compop_func op_4c7b_0_comp_ff;
+extern compop_func op_4c7c_0_comp_ff;
+extern compop_func op_4c90_0_comp_ff;
+extern compop_func op_4c98_0_comp_ff;
+extern compop_func op_4ca8_0_comp_ff;
+extern compop_func op_4cb0_0_comp_ff;
+extern compop_func op_4cb8_0_comp_ff;
+extern compop_func op_4cb9_0_comp_ff;
+extern compop_func op_4cba_0_comp_ff;
+extern compop_func op_4cbb_0_comp_ff;
+extern compop_func op_4cd0_0_comp_ff;
+extern compop_func op_4cd8_0_comp_ff;
+extern compop_func op_4ce8_0_comp_ff;
+extern compop_func op_4cf0_0_comp_ff;
+extern compop_func op_4cf8_0_comp_ff;
+extern compop_func op_4cf9_0_comp_ff;
+extern compop_func op_4cfa_0_comp_ff;
+extern compop_func op_4cfb_0_comp_ff;
+extern compop_func op_4e50_0_comp_ff;
+extern compop_func op_4e58_0_comp_ff;
+extern compop_func op_4e71_0_comp_ff;
+extern compop_func op_4e74_0_comp_ff;
+extern compop_func op_4e75_0_comp_ff;
+extern compop_func op_4e90_0_comp_ff;
+extern compop_func op_4ea8_0_comp_ff;
+extern compop_func op_4eb0_0_comp_ff;
+extern compop_func op_4eb8_0_comp_ff;
+extern compop_func op_4eb9_0_comp_ff;
+extern compop_func op_4eba_0_comp_ff;
+extern compop_func op_4ebb_0_comp_ff;
+extern compop_func op_4ed0_0_comp_ff;
+extern compop_func op_4ee8_0_comp_ff;
+extern compop_func op_4ef0_0_comp_ff;
+extern compop_func op_4ef8_0_comp_ff;
+extern compop_func op_4ef9_0_comp_ff;
+extern compop_func op_4efa_0_comp_ff;
+extern compop_func op_4efb_0_comp_ff;
+extern compop_func op_5000_0_comp_ff;
+extern compop_func op_5010_0_comp_ff;
+extern compop_func op_5018_0_comp_ff;
+extern compop_func op_5020_0_comp_ff;
+extern compop_func op_5028_0_comp_ff;
+extern compop_func op_5030_0_comp_ff;
+extern compop_func op_5038_0_comp_ff;
+extern compop_func op_5039_0_comp_ff;
+extern compop_func op_5040_0_comp_ff;
+extern compop_func op_5048_0_comp_ff;
+extern compop_func op_5050_0_comp_ff;
+extern compop_func op_5058_0_comp_ff;
+extern compop_func op_5060_0_comp_ff;
+extern compop_func op_5068_0_comp_ff;
+extern compop_func op_5070_0_comp_ff;
+extern compop_func op_5078_0_comp_ff;
+extern compop_func op_5079_0_comp_ff;
+extern compop_func op_5080_0_comp_ff;
+extern compop_func op_5088_0_comp_ff;
+extern compop_func op_5090_0_comp_ff;
+extern compop_func op_5098_0_comp_ff;
+extern compop_func op_50a0_0_comp_ff;
+extern compop_func op_50a8_0_comp_ff;
+extern compop_func op_50b0_0_comp_ff;
+extern compop_func op_50b8_0_comp_ff;
+extern compop_func op_50b9_0_comp_ff;
+extern compop_func op_50c0_0_comp_ff;
+extern compop_func op_50c8_0_comp_ff;
+extern compop_func op_50d0_0_comp_ff;
+extern compop_func op_50d8_0_comp_ff;
+extern compop_func op_50e0_0_comp_ff;
+extern compop_func op_50e8_0_comp_ff;
+extern compop_func op_50f0_0_comp_ff;
+extern compop_func op_50f8_0_comp_ff;
+extern compop_func op_50f9_0_comp_ff;
+extern compop_func op_5100_0_comp_ff;
+extern compop_func op_5110_0_comp_ff;
+extern compop_func op_5118_0_comp_ff;
+extern compop_func op_5120_0_comp_ff;
+extern compop_func op_5128_0_comp_ff;
+extern compop_func op_5130_0_comp_ff;
+extern compop_func op_5138_0_comp_ff;
+extern compop_func op_5139_0_comp_ff;
+extern compop_func op_5140_0_comp_ff;
+extern compop_func op_5148_0_comp_ff;
+extern compop_func op_5150_0_comp_ff;
+extern compop_func op_5158_0_comp_ff;
+extern compop_func op_5160_0_comp_ff;
+extern compop_func op_5168_0_comp_ff;
+extern compop_func op_5170_0_comp_ff;
+extern compop_func op_5178_0_comp_ff;
+extern compop_func op_5179_0_comp_ff;
+extern compop_func op_5180_0_comp_ff;
+extern compop_func op_5188_0_comp_ff;
+extern compop_func op_5190_0_comp_ff;
+extern compop_func op_5198_0_comp_ff;
+extern compop_func op_51a0_0_comp_ff;
+extern compop_func op_51a8_0_comp_ff;
+extern compop_func op_51b0_0_comp_ff;
+extern compop_func op_51b8_0_comp_ff;
+extern compop_func op_51b9_0_comp_ff;
+extern compop_func op_51c0_0_comp_ff;
+extern compop_func op_51c8_0_comp_ff;
+extern compop_func op_51d0_0_comp_ff;
+extern compop_func op_51d8_0_comp_ff;
+extern compop_func op_51e0_0_comp_ff;
+extern compop_func op_51e8_0_comp_ff;
+extern compop_func op_51f0_0_comp_ff;
+extern compop_func op_51f8_0_comp_ff;
+extern compop_func op_51f9_0_comp_ff;
+extern compop_func op_52c0_0_comp_ff;
+extern compop_func op_52c8_0_comp_ff;
+extern compop_func op_52d0_0_comp_ff;
+extern compop_func op_52d8_0_comp_ff;
+extern compop_func op_52e0_0_comp_ff;
+extern compop_func op_52e8_0_comp_ff;
+extern compop_func op_52f0_0_comp_ff;
+extern compop_func op_52f8_0_comp_ff;
+extern compop_func op_52f9_0_comp_ff;
+extern compop_func op_53c0_0_comp_ff;
+extern compop_func op_53c8_0_comp_ff;
+extern compop_func op_53d0_0_comp_ff;
+extern compop_func op_53d8_0_comp_ff;
+extern compop_func op_53e0_0_comp_ff;
+extern compop_func op_53e8_0_comp_ff;
+extern compop_func op_53f0_0_comp_ff;
+extern compop_func op_53f8_0_comp_ff;
+extern compop_func op_53f9_0_comp_ff;
+extern compop_func op_54c0_0_comp_ff;
+extern compop_func op_54c8_0_comp_ff;
+extern compop_func op_54d0_0_comp_ff;
+extern compop_func op_54d8_0_comp_ff;
+extern compop_func op_54e0_0_comp_ff;
+extern compop_func op_54e8_0_comp_ff;
+extern compop_func op_54f0_0_comp_ff;
+extern compop_func op_54f8_0_comp_ff;
+extern compop_func op_54f9_0_comp_ff;
+extern compop_func op_55c0_0_comp_ff;
+extern compop_func op_55c8_0_comp_ff;
+extern compop_func op_55d0_0_comp_ff;
+extern compop_func op_55d8_0_comp_ff;
+extern compop_func op_55e0_0_comp_ff;
+extern compop_func op_55e8_0_comp_ff;
+extern compop_func op_55f0_0_comp_ff;
+extern compop_func op_55f8_0_comp_ff;
+extern compop_func op_55f9_0_comp_ff;
+extern compop_func op_56c0_0_comp_ff;
+extern compop_func op_56c8_0_comp_ff;
+extern compop_func op_56d0_0_comp_ff;
+extern compop_func op_56d8_0_comp_ff;
+extern compop_func op_56e0_0_comp_ff;
+extern compop_func op_56e8_0_comp_ff;
+extern compop_func op_56f0_0_comp_ff;
+extern compop_func op_56f8_0_comp_ff;
+extern compop_func op_56f9_0_comp_ff;
+extern compop_func op_57c0_0_comp_ff;
+extern compop_func op_57c8_0_comp_ff;
+extern compop_func op_57d0_0_comp_ff;
+extern compop_func op_57d8_0_comp_ff;
+extern compop_func op_57e0_0_comp_ff;
+extern compop_func op_57e8_0_comp_ff;
+extern compop_func op_57f0_0_comp_ff;
+extern compop_func op_57f8_0_comp_ff;
+extern compop_func op_57f9_0_comp_ff;
+extern compop_func op_58c0_0_comp_ff;
+extern compop_func op_58c8_0_comp_ff;
+extern compop_func op_58d0_0_comp_ff;
+extern compop_func op_58d8_0_comp_ff;
+extern compop_func op_58e0_0_comp_ff;
+extern compop_func op_58e8_0_comp_ff;
+extern compop_func op_58f0_0_comp_ff;
+extern compop_func op_58f8_0_comp_ff;
+extern compop_func op_58f9_0_comp_ff;
+extern compop_func op_59c0_0_comp_ff;
+extern compop_func op_59c8_0_comp_ff;
+extern compop_func op_59d0_0_comp_ff;
+extern compop_func op_59d8_0_comp_ff;
+extern compop_func op_59e0_0_comp_ff;
+extern compop_func op_59e8_0_comp_ff;
+extern compop_func op_59f0_0_comp_ff;
+extern compop_func op_59f8_0_comp_ff;
+extern compop_func op_59f9_0_comp_ff;
+extern compop_func op_5ac0_0_comp_ff;
+extern compop_func op_5ac8_0_comp_ff;
+extern compop_func op_5ad0_0_comp_ff;
+extern compop_func op_5ad8_0_comp_ff;
+extern compop_func op_5ae0_0_comp_ff;
+extern compop_func op_5ae8_0_comp_ff;
+extern compop_func op_5af0_0_comp_ff;
+extern compop_func op_5af8_0_comp_ff;
+extern compop_func op_5af9_0_comp_ff;
+extern compop_func op_5bc0_0_comp_ff;
+extern compop_func op_5bc8_0_comp_ff;
+extern compop_func op_5bd0_0_comp_ff;
+extern compop_func op_5bd8_0_comp_ff;
+extern compop_func op_5be0_0_comp_ff;
+extern compop_func op_5be8_0_comp_ff;
+extern compop_func op_5bf0_0_comp_ff;
+extern compop_func op_5bf8_0_comp_ff;
+extern compop_func op_5bf9_0_comp_ff;
+extern compop_func op_5cc0_0_comp_ff;
+extern compop_func op_5cc8_0_comp_ff;
+extern compop_func op_5cd0_0_comp_ff;
+extern compop_func op_5cd8_0_comp_ff;
+extern compop_func op_5ce0_0_comp_ff;
+extern compop_func op_5ce8_0_comp_ff;
+extern compop_func op_5cf0_0_comp_ff;
+extern compop_func op_5cf8_0_comp_ff;
+extern compop_func op_5cf9_0_comp_ff;
+extern compop_func op_5dc0_0_comp_ff;
+extern compop_func op_5dc8_0_comp_ff;
+extern compop_func op_5dd0_0_comp_ff;
+extern compop_func op_5dd8_0_comp_ff;
+extern compop_func op_5de0_0_comp_ff;
+extern compop_func op_5de8_0_comp_ff;
+extern compop_func op_5df0_0_comp_ff;
+extern compop_func op_5df8_0_comp_ff;
+extern compop_func op_5df9_0_comp_ff;
+extern compop_func op_5ec0_0_comp_ff;
+extern compop_func op_5ec8_0_comp_ff;
+extern compop_func op_5ed0_0_comp_ff;
+extern compop_func op_5ed8_0_comp_ff;
+extern compop_func op_5ee0_0_comp_ff;
+extern compop_func op_5ee8_0_comp_ff;
+extern compop_func op_5ef0_0_comp_ff;
+extern compop_func op_5ef8_0_comp_ff;
+extern compop_func op_5ef9_0_comp_ff;
+extern compop_func op_5fc0_0_comp_ff;
+extern compop_func op_5fc8_0_comp_ff;
+extern compop_func op_5fd0_0_comp_ff;
+extern compop_func op_5fd8_0_comp_ff;
+extern compop_func op_5fe0_0_comp_ff;
+extern compop_func op_5fe8_0_comp_ff;
+extern compop_func op_5ff0_0_comp_ff;
+extern compop_func op_5ff8_0_comp_ff;
+extern compop_func op_5ff9_0_comp_ff;
+extern compop_func op_6000_0_comp_ff;
+extern compop_func op_6001_0_comp_ff;
+extern compop_func op_60ff_0_comp_ff;
+extern compop_func op_6100_0_comp_ff;
+extern compop_func op_6101_0_comp_ff;
+extern compop_func op_61ff_0_comp_ff;
+extern compop_func op_6200_0_comp_ff;
+extern compop_func op_6201_0_comp_ff;
+extern compop_func op_62ff_0_comp_ff;
+extern compop_func op_6300_0_comp_ff;
+extern compop_func op_6301_0_comp_ff;
+extern compop_func op_63ff_0_comp_ff;
+extern compop_func op_6400_0_comp_ff;
+extern compop_func op_6401_0_comp_ff;
+extern compop_func op_64ff_0_comp_ff;
+extern compop_func op_6500_0_comp_ff;
+extern compop_func op_6501_0_comp_ff;
+extern compop_func op_65ff_0_comp_ff;
+extern compop_func op_6600_0_comp_ff;
+extern compop_func op_6601_0_comp_ff;
+extern compop_func op_66ff_0_comp_ff;
+extern compop_func op_6700_0_comp_ff;
+extern compop_func op_6701_0_comp_ff;
+extern compop_func op_67ff_0_comp_ff;
+extern compop_func op_6800_0_comp_ff;
+extern compop_func op_6801_0_comp_ff;
+extern compop_func op_68ff_0_comp_ff;
+extern compop_func op_6900_0_comp_ff;
+extern compop_func op_6901_0_comp_ff;
+extern compop_func op_69ff_0_comp_ff;
+extern compop_func op_6a00_0_comp_ff;
+extern compop_func op_6a01_0_comp_ff;
+extern compop_func op_6aff_0_comp_ff;
+extern compop_func op_6b00_0_comp_ff;
+extern compop_func op_6b01_0_comp_ff;
+extern compop_func op_6bff_0_comp_ff;
+extern compop_func op_6c00_0_comp_ff;
+extern compop_func op_6c01_0_comp_ff;
+extern compop_func op_6cff_0_comp_ff;
+extern compop_func op_6d00_0_comp_ff;
+extern compop_func op_6d01_0_comp_ff;
+extern compop_func op_6dff_0_comp_ff;
+extern compop_func op_6e00_0_comp_ff;
+extern compop_func op_6e01_0_comp_ff;
+extern compop_func op_6eff_0_comp_ff;
+extern compop_func op_6f00_0_comp_ff;
+extern compop_func op_6f01_0_comp_ff;
+extern compop_func op_6fff_0_comp_ff;
+extern compop_func op_7000_0_comp_ff;
+extern compop_func op_8000_0_comp_ff;
+extern compop_func op_8010_0_comp_ff;
+extern compop_func op_8018_0_comp_ff;
+extern compop_func op_8020_0_comp_ff;
+extern compop_func op_8028_0_comp_ff;
+extern compop_func op_8030_0_comp_ff;
+extern compop_func op_8038_0_comp_ff;
+extern compop_func op_8039_0_comp_ff;
+extern compop_func op_803a_0_comp_ff;
+extern compop_func op_803b_0_comp_ff;
+extern compop_func op_803c_0_comp_ff;
+extern compop_func op_8040_0_comp_ff;
+extern compop_func op_8050_0_comp_ff;
+extern compop_func op_8058_0_comp_ff;
+extern compop_func op_8060_0_comp_ff;
+extern compop_func op_8068_0_comp_ff;
+extern compop_func op_8070_0_comp_ff;
+extern compop_func op_8078_0_comp_ff;
+extern compop_func op_8079_0_comp_ff;
+extern compop_func op_807a_0_comp_ff;
+extern compop_func op_807b_0_comp_ff;
+extern compop_func op_807c_0_comp_ff;
+extern compop_func op_8080_0_comp_ff;
+extern compop_func op_8090_0_comp_ff;
+extern compop_func op_8098_0_comp_ff;
+extern compop_func op_80a0_0_comp_ff;
+extern compop_func op_80a8_0_comp_ff;
+extern compop_func op_80b0_0_comp_ff;
+extern compop_func op_80b8_0_comp_ff;
+extern compop_func op_80b9_0_comp_ff;
+extern compop_func op_80ba_0_comp_ff;
+extern compop_func op_80bb_0_comp_ff;
+extern compop_func op_80bc_0_comp_ff;
+extern compop_func op_80c0_0_comp_ff;
+extern compop_func op_80d0_0_comp_ff;
+extern compop_func op_80d8_0_comp_ff;
+extern compop_func op_80e0_0_comp_ff;
+extern compop_func op_80e8_0_comp_ff;
+extern compop_func op_80f0_0_comp_ff;
+extern compop_func op_80f8_0_comp_ff;
+extern compop_func op_80f9_0_comp_ff;
+extern compop_func op_80fa_0_comp_ff;
+extern compop_func op_80fb_0_comp_ff;
+extern compop_func op_80fc_0_comp_ff;
+extern compop_func op_8110_0_comp_ff;
+extern compop_func op_8118_0_comp_ff;
+extern compop_func op_8120_0_comp_ff;
+extern compop_func op_8128_0_comp_ff;
+extern compop_func op_8130_0_comp_ff;
+extern compop_func op_8138_0_comp_ff;
+extern compop_func op_8139_0_comp_ff;
+extern compop_func op_8150_0_comp_ff;
+extern compop_func op_8158_0_comp_ff;
+extern compop_func op_8160_0_comp_ff;
+extern compop_func op_8168_0_comp_ff;
+extern compop_func op_8170_0_comp_ff;
+extern compop_func op_8178_0_comp_ff;
+extern compop_func op_8179_0_comp_ff;
+extern compop_func op_8190_0_comp_ff;
+extern compop_func op_8198_0_comp_ff;
+extern compop_func op_81a0_0_comp_ff;
+extern compop_func op_81a8_0_comp_ff;
+extern compop_func op_81b0_0_comp_ff;
+extern compop_func op_81b8_0_comp_ff;
+extern compop_func op_81b9_0_comp_ff;
+extern compop_func op_81c0_0_comp_ff;
+extern compop_func op_81d0_0_comp_ff;
+extern compop_func op_81d8_0_comp_ff;
+extern compop_func op_81e0_0_comp_ff;
+extern compop_func op_81e8_0_comp_ff;
+extern compop_func op_81f0_0_comp_ff;
+extern compop_func op_81f8_0_comp_ff;
+extern compop_func op_81f9_0_comp_ff;
+extern compop_func op_81fa_0_comp_ff;
+extern compop_func op_81fb_0_comp_ff;
+extern compop_func op_81fc_0_comp_ff;
+extern compop_func op_9000_0_comp_ff;
+extern compop_func op_9010_0_comp_ff;
+extern compop_func op_9018_0_comp_ff;
+extern compop_func op_9020_0_comp_ff;
+extern compop_func op_9028_0_comp_ff;
+extern compop_func op_9030_0_comp_ff;
+extern compop_func op_9038_0_comp_ff;
+extern compop_func op_9039_0_comp_ff;
+extern compop_func op_903a_0_comp_ff;
+extern compop_func op_903b_0_comp_ff;
+extern compop_func op_903c_0_comp_ff;
+extern compop_func op_9040_0_comp_ff;
+extern compop_func op_9048_0_comp_ff;
+extern compop_func op_9050_0_comp_ff;
+extern compop_func op_9058_0_comp_ff;
+extern compop_func op_9060_0_comp_ff;
+extern compop_func op_9068_0_comp_ff;
+extern compop_func op_9070_0_comp_ff;
+extern compop_func op_9078_0_comp_ff;
+extern compop_func op_9079_0_comp_ff;
+extern compop_func op_907a_0_comp_ff;
+extern compop_func op_907b_0_comp_ff;
+extern compop_func op_907c_0_comp_ff;
+extern compop_func op_9080_0_comp_ff;
+extern compop_func op_9088_0_comp_ff;
+extern compop_func op_9090_0_comp_ff;
+extern compop_func op_9098_0_comp_ff;
+extern compop_func op_90a0_0_comp_ff;
+extern compop_func op_90a8_0_comp_ff;
+extern compop_func op_90b0_0_comp_ff;
+extern compop_func op_90b8_0_comp_ff;
+extern compop_func op_90b9_0_comp_ff;
+extern compop_func op_90ba_0_comp_ff;
+extern compop_func op_90bb_0_comp_ff;
+extern compop_func op_90bc_0_comp_ff;
+extern compop_func op_90c0_0_comp_ff;
+extern compop_func op_90c8_0_comp_ff;
+extern compop_func op_90d0_0_comp_ff;
+extern compop_func op_90d8_0_comp_ff;
+extern compop_func op_90e0_0_comp_ff;
+extern compop_func op_90e8_0_comp_ff;
+extern compop_func op_90f0_0_comp_ff;
+extern compop_func op_90f8_0_comp_ff;
+extern compop_func op_90f9_0_comp_ff;
+extern compop_func op_90fa_0_comp_ff;
+extern compop_func op_90fb_0_comp_ff;
+extern compop_func op_90fc_0_comp_ff;
+extern compop_func op_9100_0_comp_ff;
+extern compop_func op_9108_0_comp_ff;
+extern compop_func op_9110_0_comp_ff;
+extern compop_func op_9118_0_comp_ff;
+extern compop_func op_9120_0_comp_ff;
+extern compop_func op_9128_0_comp_ff;
+extern compop_func op_9130_0_comp_ff;
+extern compop_func op_9138_0_comp_ff;
+extern compop_func op_9139_0_comp_ff;
+extern compop_func op_9140_0_comp_ff;
+extern compop_func op_9148_0_comp_ff;
+extern compop_func op_9150_0_comp_ff;
+extern compop_func op_9158_0_comp_ff;
+extern compop_func op_9160_0_comp_ff;
+extern compop_func op_9168_0_comp_ff;
+extern compop_func op_9170_0_comp_ff;
+extern compop_func op_9178_0_comp_ff;
+extern compop_func op_9179_0_comp_ff;
+extern compop_func op_9180_0_comp_ff;
+extern compop_func op_9188_0_comp_ff;
+extern compop_func op_9190_0_comp_ff;
+extern compop_func op_9198_0_comp_ff;
+extern compop_func op_91a0_0_comp_ff;
+extern compop_func op_91a8_0_comp_ff;
+extern compop_func op_91b0_0_comp_ff;
+extern compop_func op_91b8_0_comp_ff;
+extern compop_func op_91b9_0_comp_ff;
+extern compop_func op_91c0_0_comp_ff;
+extern compop_func op_91c8_0_comp_ff;
+extern compop_func op_91d0_0_comp_ff;
+extern compop_func op_91d8_0_comp_ff;
+extern compop_func op_91e0_0_comp_ff;
+extern compop_func op_91e8_0_comp_ff;
+extern compop_func op_91f0_0_comp_ff;
+extern compop_func op_91f8_0_comp_ff;
+extern compop_func op_91f9_0_comp_ff;
+extern compop_func op_91fa_0_comp_ff;
+extern compop_func op_91fb_0_comp_ff;
+extern compop_func op_91fc_0_comp_ff;
+extern compop_func op_b000_0_comp_ff;
+extern compop_func op_b010_0_comp_ff;
+extern compop_func op_b018_0_comp_ff;
+extern compop_func op_b020_0_comp_ff;
+extern compop_func op_b028_0_comp_ff;
+extern compop_func op_b030_0_comp_ff;
+extern compop_func op_b038_0_comp_ff;
+extern compop_func op_b039_0_comp_ff;
+extern compop_func op_b03a_0_comp_ff;
+extern compop_func op_b03b_0_comp_ff;
+extern compop_func op_b03c_0_comp_ff;
+extern compop_func op_b040_0_comp_ff;
+extern compop_func op_b048_0_comp_ff;
+extern compop_func op_b050_0_comp_ff;
+extern compop_func op_b058_0_comp_ff;
+extern compop_func op_b060_0_comp_ff;
+extern compop_func op_b068_0_comp_ff;
+extern compop_func op_b070_0_comp_ff;
+extern compop_func op_b078_0_comp_ff;
+extern compop_func op_b079_0_comp_ff;
+extern compop_func op_b07a_0_comp_ff;
+extern compop_func op_b07b_0_comp_ff;
+extern compop_func op_b07c_0_comp_ff;
+extern compop_func op_b080_0_comp_ff;
+extern compop_func op_b088_0_comp_ff;
+extern compop_func op_b090_0_comp_ff;
+extern compop_func op_b098_0_comp_ff;
+extern compop_func op_b0a0_0_comp_ff;
+extern compop_func op_b0a8_0_comp_ff;
+extern compop_func op_b0b0_0_comp_ff;
+extern compop_func op_b0b8_0_comp_ff;
+extern compop_func op_b0b9_0_comp_ff;
+extern compop_func op_b0ba_0_comp_ff;
+extern compop_func op_b0bb_0_comp_ff;
+extern compop_func op_b0bc_0_comp_ff;
+extern compop_func op_b0c0_0_comp_ff;
+extern compop_func op_b0c8_0_comp_ff;
+extern compop_func op_b0d0_0_comp_ff;
+extern compop_func op_b0d8_0_comp_ff;
+extern compop_func op_b0e0_0_comp_ff;
+extern compop_func op_b0e8_0_comp_ff;
+extern compop_func op_b0f0_0_comp_ff;
+extern compop_func op_b0f8_0_comp_ff;
+extern compop_func op_b0f9_0_comp_ff;
+extern compop_func op_b0fa_0_comp_ff;
+extern compop_func op_b0fb_0_comp_ff;
+extern compop_func op_b0fc_0_comp_ff;
+extern compop_func op_b100_0_comp_ff;
+extern compop_func op_b108_0_comp_ff;
+extern compop_func op_b110_0_comp_ff;
+extern compop_func op_b118_0_comp_ff;
+extern compop_func op_b120_0_comp_ff;
+extern compop_func op_b128_0_comp_ff;
+extern compop_func op_b130_0_comp_ff;
+extern compop_func op_b138_0_comp_ff;
+extern compop_func op_b139_0_comp_ff;
+extern compop_func op_b140_0_comp_ff;
+extern compop_func op_b148_0_comp_ff;
+extern compop_func op_b150_0_comp_ff;
+extern compop_func op_b158_0_comp_ff;
+extern compop_func op_b160_0_comp_ff;
+extern compop_func op_b168_0_comp_ff;
+extern compop_func op_b170_0_comp_ff;
+extern compop_func op_b178_0_comp_ff;
+extern compop_func op_b179_0_comp_ff;
+extern compop_func op_b180_0_comp_ff;
+extern compop_func op_b188_0_comp_ff;
+extern compop_func op_b190_0_comp_ff;
+extern compop_func op_b198_0_comp_ff;
+extern compop_func op_b1a0_0_comp_ff;
+extern compop_func op_b1a8_0_comp_ff;
+extern compop_func op_b1b0_0_comp_ff;
+extern compop_func op_b1b8_0_comp_ff;
+extern compop_func op_b1b9_0_comp_ff;
+extern compop_func op_b1c0_0_comp_ff;
+extern compop_func op_b1c8_0_comp_ff;
+extern compop_func op_b1d0_0_comp_ff;
+extern compop_func op_b1d8_0_comp_ff;
+extern compop_func op_b1e0_0_comp_ff;
+extern compop_func op_b1e8_0_comp_ff;
+extern compop_func op_b1f0_0_comp_ff;
+extern compop_func op_b1f8_0_comp_ff;
+extern compop_func op_b1f9_0_comp_ff;
+extern compop_func op_b1fa_0_comp_ff;
+extern compop_func op_b1fb_0_comp_ff;
+extern compop_func op_b1fc_0_comp_ff;
+extern compop_func op_c000_0_comp_ff;
+extern compop_func op_c010_0_comp_ff;
+extern compop_func op_c018_0_comp_ff;
+extern compop_func op_c020_0_comp_ff;
+extern compop_func op_c028_0_comp_ff;
+extern compop_func op_c030_0_comp_ff;
+extern compop_func op_c038_0_comp_ff;
+extern compop_func op_c039_0_comp_ff;
+extern compop_func op_c03a_0_comp_ff;
+extern compop_func op_c03b_0_comp_ff;
+extern compop_func op_c03c_0_comp_ff;
+extern compop_func op_c040_0_comp_ff;
+extern compop_func op_c050_0_comp_ff;
+extern compop_func op_c058_0_comp_ff;
+extern compop_func op_c060_0_comp_ff;
+extern compop_func op_c068_0_comp_ff;
+extern compop_func op_c070_0_comp_ff;
+extern compop_func op_c078_0_comp_ff;
+extern compop_func op_c079_0_comp_ff;
+extern compop_func op_c07a_0_comp_ff;
+extern compop_func op_c07b_0_comp_ff;
+extern compop_func op_c07c_0_comp_ff;
+extern compop_func op_c080_0_comp_ff;
+extern compop_func op_c090_0_comp_ff;
+extern compop_func op_c098_0_comp_ff;
+extern compop_func op_c0a0_0_comp_ff;
+extern compop_func op_c0a8_0_comp_ff;
+extern compop_func op_c0b0_0_comp_ff;
+extern compop_func op_c0b8_0_comp_ff;
+extern compop_func op_c0b9_0_comp_ff;
+extern compop_func op_c0ba_0_comp_ff;
+extern compop_func op_c0bb_0_comp_ff;
+extern compop_func op_c0bc_0_comp_ff;
+extern compop_func op_c0c0_0_comp_ff;
+extern compop_func op_c0d0_0_comp_ff;
+extern compop_func op_c0d8_0_comp_ff;
+extern compop_func op_c0e0_0_comp_ff;
+extern compop_func op_c0e8_0_comp_ff;
+extern compop_func op_c0f0_0_comp_ff;
+extern compop_func op_c0f8_0_comp_ff;
+extern compop_func op_c0f9_0_comp_ff;
+extern compop_func op_c0fa_0_comp_ff;
+extern compop_func op_c0fb_0_comp_ff;
+extern compop_func op_c0fc_0_comp_ff;
+extern compop_func op_c110_0_comp_ff;
+extern compop_func op_c118_0_comp_ff;
+extern compop_func op_c120_0_comp_ff;
+extern compop_func op_c128_0_comp_ff;
+extern compop_func op_c130_0_comp_ff;
+extern compop_func op_c138_0_comp_ff;
+extern compop_func op_c139_0_comp_ff;
+extern compop_func op_c140_0_comp_ff;
+extern compop_func op_c148_0_comp_ff;
+extern compop_func op_c150_0_comp_ff;
+extern compop_func op_c158_0_comp_ff;
+extern compop_func op_c160_0_comp_ff;
+extern compop_func op_c168_0_comp_ff;
+extern compop_func op_c170_0_comp_ff;
+extern compop_func op_c178_0_comp_ff;
+extern compop_func op_c179_0_comp_ff;
+extern compop_func op_c188_0_comp_ff;
+extern compop_func op_c190_0_comp_ff;
+extern compop_func op_c198_0_comp_ff;
+extern compop_func op_c1a0_0_comp_ff;
+extern compop_func op_c1a8_0_comp_ff;
+extern compop_func op_c1b0_0_comp_ff;
+extern compop_func op_c1b8_0_comp_ff;
+extern compop_func op_c1b9_0_comp_ff;
+extern compop_func op_c1c0_0_comp_ff;
+extern compop_func op_c1d0_0_comp_ff;
+extern compop_func op_c1d8_0_comp_ff;
+extern compop_func op_c1e0_0_comp_ff;
+extern compop_func op_c1e8_0_comp_ff;
+extern compop_func op_c1f0_0_comp_ff;
+extern compop_func op_c1f8_0_comp_ff;
+extern compop_func op_c1f9_0_comp_ff;
+extern compop_func op_c1fa_0_comp_ff;
+extern compop_func op_c1fb_0_comp_ff;
+extern compop_func op_c1fc_0_comp_ff;
+extern compop_func op_d000_0_comp_ff;
+extern compop_func op_d010_0_comp_ff;
+extern compop_func op_d018_0_comp_ff;
+extern compop_func op_d020_0_comp_ff;
+extern compop_func op_d028_0_comp_ff;
+extern compop_func op_d030_0_comp_ff;
+extern compop_func op_d038_0_comp_ff;
+extern compop_func op_d039_0_comp_ff;
+extern compop_func op_d03a_0_comp_ff;
+extern compop_func op_d03b_0_comp_ff;
+extern compop_func op_d03c_0_comp_ff;
+extern compop_func op_d040_0_comp_ff;
+extern compop_func op_d048_0_comp_ff;
+extern compop_func op_d050_0_comp_ff;
+extern compop_func op_d058_0_comp_ff;
+extern compop_func op_d060_0_comp_ff;
+extern compop_func op_d068_0_comp_ff;
+extern compop_func op_d070_0_comp_ff;
+extern compop_func op_d078_0_comp_ff;
+extern compop_func op_d079_0_comp_ff;
+extern compop_func op_d07a_0_comp_ff;
+extern compop_func op_d07b_0_comp_ff;
+extern compop_func op_d07c_0_comp_ff;
+extern compop_func op_d080_0_comp_ff;
+extern compop_func op_d088_0_comp_ff;
+extern compop_func op_d090_0_comp_ff;
+extern compop_func op_d098_0_comp_ff;
+extern compop_func op_d0a0_0_comp_ff;
+extern compop_func op_d0a8_0_comp_ff;
+extern compop_func op_d0b0_0_comp_ff;
+extern compop_func op_d0b8_0_comp_ff;
+extern compop_func op_d0b9_0_comp_ff;
+extern compop_func op_d0ba_0_comp_ff;
+extern compop_func op_d0bb_0_comp_ff;
+extern compop_func op_d0bc_0_comp_ff;
+extern compop_func op_d0c0_0_comp_ff;
+extern compop_func op_d0c8_0_comp_ff;
+extern compop_func op_d0d0_0_comp_ff;
+extern compop_func op_d0d8_0_comp_ff;
+extern compop_func op_d0e0_0_comp_ff;
+extern compop_func op_d0e8_0_comp_ff;
+extern compop_func op_d0f0_0_comp_ff;
+extern compop_func op_d0f8_0_comp_ff;
+extern compop_func op_d0f9_0_comp_ff;
+extern compop_func op_d0fa_0_comp_ff;
+extern compop_func op_d0fb_0_comp_ff;
+extern compop_func op_d0fc_0_comp_ff;
+extern compop_func op_d100_0_comp_ff;
+extern compop_func op_d108_0_comp_ff;
+extern compop_func op_d110_0_comp_ff;
+extern compop_func op_d118_0_comp_ff;
+extern compop_func op_d120_0_comp_ff;
+extern compop_func op_d128_0_comp_ff;
+extern compop_func op_d130_0_comp_ff;
+extern compop_func op_d138_0_comp_ff;
+extern compop_func op_d139_0_comp_ff;
+extern compop_func op_d140_0_comp_ff;
+extern compop_func op_d148_0_comp_ff;
+extern compop_func op_d150_0_comp_ff;
+extern compop_func op_d158_0_comp_ff;
+extern compop_func op_d160_0_comp_ff;
+extern compop_func op_d168_0_comp_ff;
+extern compop_func op_d170_0_comp_ff;
+extern compop_func op_d178_0_comp_ff;
+extern compop_func op_d179_0_comp_ff;
+extern compop_func op_d180_0_comp_ff;
+extern compop_func op_d188_0_comp_ff;
+extern compop_func op_d190_0_comp_ff;
+extern compop_func op_d198_0_comp_ff;
+extern compop_func op_d1a0_0_comp_ff;
+extern compop_func op_d1a8_0_comp_ff;
+extern compop_func op_d1b0_0_comp_ff;
+extern compop_func op_d1b8_0_comp_ff;
+extern compop_func op_d1b9_0_comp_ff;
+extern compop_func op_d1c0_0_comp_ff;
+extern compop_func op_d1c8_0_comp_ff;
+extern compop_func op_d1d0_0_comp_ff;
+extern compop_func op_d1d8_0_comp_ff;
+extern compop_func op_d1e0_0_comp_ff;
+extern compop_func op_d1e8_0_comp_ff;
+extern compop_func op_d1f0_0_comp_ff;
+extern compop_func op_d1f8_0_comp_ff;
+extern compop_func op_d1f9_0_comp_ff;
+extern compop_func op_d1fa_0_comp_ff;
+extern compop_func op_d1fb_0_comp_ff;
+extern compop_func op_d1fc_0_comp_ff;
+extern compop_func op_e000_0_comp_ff;
+extern compop_func op_e008_0_comp_ff;
+extern compop_func op_e010_0_comp_ff;
+extern compop_func op_e018_0_comp_ff;
+extern compop_func op_e020_0_comp_ff;
+extern compop_func op_e028_0_comp_ff;
+extern compop_func op_e030_0_comp_ff;
+extern compop_func op_e038_0_comp_ff;
+extern compop_func op_e040_0_comp_ff;
+extern compop_func op_e048_0_comp_ff;
+extern compop_func op_e050_0_comp_ff;
+extern compop_func op_e058_0_comp_ff;
+extern compop_func op_e060_0_comp_ff;
+extern compop_func op_e068_0_comp_ff;
+extern compop_func op_e070_0_comp_ff;
+extern compop_func op_e078_0_comp_ff;
+extern compop_func op_e080_0_comp_ff;
+extern compop_func op_e088_0_comp_ff;
+extern compop_func op_e090_0_comp_ff;
+extern compop_func op_e098_0_comp_ff;
+extern compop_func op_e0a0_0_comp_ff;
+extern compop_func op_e0a8_0_comp_ff;
+extern compop_func op_e0b0_0_comp_ff;
+extern compop_func op_e0b8_0_comp_ff;
+extern compop_func op_e0d0_0_comp_ff;
+extern compop_func op_e0d8_0_comp_ff;
+extern compop_func op_e0e0_0_comp_ff;
+extern compop_func op_e0e8_0_comp_ff;
+extern compop_func op_e0f0_0_comp_ff;
+extern compop_func op_e0f8_0_comp_ff;
+extern compop_func op_e0f9_0_comp_ff;
+extern compop_func op_e100_0_comp_ff;
+extern compop_func op_e108_0_comp_ff;
+extern compop_func op_e110_0_comp_ff;
+extern compop_func op_e118_0_comp_ff;
+extern compop_func op_e120_0_comp_ff;
+extern compop_func op_e128_0_comp_ff;
+extern compop_func op_e130_0_comp_ff;
+extern compop_func op_e138_0_comp_ff;
+extern compop_func op_e140_0_comp_ff;
+extern compop_func op_e148_0_comp_ff;
+extern compop_func op_e150_0_comp_ff;
+extern compop_func op_e158_0_comp_ff;
+extern compop_func op_e160_0_comp_ff;
+extern compop_func op_e168_0_comp_ff;
+extern compop_func op_e170_0_comp_ff;
+extern compop_func op_e178_0_comp_ff;
+extern compop_func op_e180_0_comp_ff;
+extern compop_func op_e188_0_comp_ff;
+extern compop_func op_e190_0_comp_ff;
+extern compop_func op_e198_0_comp_ff;
+extern compop_func op_e1a0_0_comp_ff;
+extern compop_func op_e1a8_0_comp_ff;
+extern compop_func op_e1b0_0_comp_ff;
+extern compop_func op_e1b8_0_comp_ff;
+extern compop_func op_e1d0_0_comp_ff;
+extern compop_func op_e1d8_0_comp_ff;
+extern compop_func op_e1e0_0_comp_ff;
+extern compop_func op_e1e8_0_comp_ff;
+extern compop_func op_e1f0_0_comp_ff;
+extern compop_func op_e1f8_0_comp_ff;
+extern compop_func op_e1f9_0_comp_ff;
+extern compop_func op_e2d0_0_comp_ff;
+extern compop_func op_e2d8_0_comp_ff;
+extern compop_func op_e2e0_0_comp_ff;
+extern compop_func op_e2e8_0_comp_ff;
+extern compop_func op_e2f0_0_comp_ff;
+extern compop_func op_e2f8_0_comp_ff;
+extern compop_func op_e2f9_0_comp_ff;
+extern compop_func op_e3d0_0_comp_ff;
+extern compop_func op_e3d8_0_comp_ff;
+extern compop_func op_e3e0_0_comp_ff;
+extern compop_func op_e3e8_0_comp_ff;
+extern compop_func op_e3f0_0_comp_ff;
+extern compop_func op_e3f8_0_comp_ff;
+extern compop_func op_e3f9_0_comp_ff;
+extern compop_func op_e6d0_0_comp_ff;
+extern compop_func op_e6d8_0_comp_ff;
+extern compop_func op_e6e0_0_comp_ff;
+extern compop_func op_e6e8_0_comp_ff;
+extern compop_func op_e6f0_0_comp_ff;
+extern compop_func op_e6f8_0_comp_ff;
+extern compop_func op_e6f9_0_comp_ff;
+extern compop_func op_e7d0_0_comp_ff;
+extern compop_func op_e7d8_0_comp_ff;
+extern compop_func op_e7e0_0_comp_ff;
+extern compop_func op_e7e8_0_comp_ff;
+extern compop_func op_e7f0_0_comp_ff;
+extern compop_func op_e7f8_0_comp_ff;
+extern compop_func op_e7f9_0_comp_ff;
+extern compop_func op_efc0_0_comp_ff;
+extern compop_func op_efd0_0_comp_ff;
+extern compop_func op_efe8_0_comp_ff;
+extern compop_func op_eff0_0_comp_ff;
+extern compop_func op_eff8_0_comp_ff;
+extern compop_func op_eff9_0_comp_ff;
+extern compop_func op_f200_0_comp_ff;
+extern compop_func op_f208_0_comp_ff;
+extern compop_func op_f210_0_comp_ff;
+extern compop_func op_f218_0_comp_ff;
+extern compop_func op_f220_0_comp_ff;
+extern compop_func op_f228_0_comp_ff;
+extern compop_func op_f230_0_comp_ff;
+extern compop_func op_f238_0_comp_ff;
+extern compop_func op_f239_0_comp_ff;
+extern compop_func op_f23a_0_comp_ff;
+extern compop_func op_f23b_0_comp_ff;
+extern compop_func op_f23c_0_comp_ff;
+extern compop_func op_f240_0_comp_ff;
+extern compop_func op_f250_0_comp_ff;
+extern compop_func op_f258_0_comp_ff;
+extern compop_func op_f260_0_comp_ff;
+extern compop_func op_f268_0_comp_ff;
+extern compop_func op_f270_0_comp_ff;
+extern compop_func op_f278_0_comp_ff;
+extern compop_func op_f279_0_comp_ff;
+extern compop_func op_f280_0_comp_ff;
+extern compop_func op_f2c0_0_comp_ff;
+extern compop_func op_f600_0_comp_ff;
+extern compop_func op_f608_0_comp_ff;
+extern compop_func op_f610_0_comp_ff;
+extern compop_func op_f618_0_comp_ff;
+extern compop_func op_f620_0_comp_ff;
+extern compop_func op_0_0_comp_nf;
+extern compop_func op_10_0_comp_nf;
+extern compop_func op_18_0_comp_nf;
+extern compop_func op_20_0_comp_nf;
+extern compop_func op_28_0_comp_nf;
+extern compop_func op_30_0_comp_nf;
+extern compop_func op_38_0_comp_nf;
+extern compop_func op_39_0_comp_nf;
+extern compop_func op_3c_0_comp_nf;
+extern compop_func op_40_0_comp_nf;
+extern compop_func op_50_0_comp_nf;
+extern compop_func op_58_0_comp_nf;
+extern compop_func op_60_0_comp_nf;
+extern compop_func op_68_0_comp_nf;
+extern compop_func op_70_0_comp_nf;
+extern compop_func op_78_0_comp_nf;
+extern compop_func op_79_0_comp_nf;
+extern compop_func op_80_0_comp_nf;
+extern compop_func op_90_0_comp_nf;
+extern compop_func op_98_0_comp_nf;
+extern compop_func op_a0_0_comp_nf;
+extern compop_func op_a8_0_comp_nf;
+extern compop_func op_b0_0_comp_nf;
+extern compop_func op_b8_0_comp_nf;
+extern compop_func op_b9_0_comp_nf;
+extern compop_func op_100_0_comp_nf;
+extern compop_func op_110_0_comp_nf;
+extern compop_func op_118_0_comp_nf;
+extern compop_func op_120_0_comp_nf;
+extern compop_func op_128_0_comp_nf;
+extern compop_func op_130_0_comp_nf;
+extern compop_func op_138_0_comp_nf;
+extern compop_func op_139_0_comp_nf;
+extern compop_func op_13a_0_comp_nf;
+extern compop_func op_13b_0_comp_nf;
+extern compop_func op_13c_0_comp_nf;
+extern compop_func op_140_0_comp_nf;
+extern compop_func op_150_0_comp_nf;
+extern compop_func op_158_0_comp_nf;
+extern compop_func op_160_0_comp_nf;
+extern compop_func op_168_0_comp_nf;
+extern compop_func op_170_0_comp_nf;
+extern compop_func op_178_0_comp_nf;
+extern compop_func op_179_0_comp_nf;
+extern compop_func op_180_0_comp_nf;
+extern compop_func op_190_0_comp_nf;
+extern compop_func op_198_0_comp_nf;
+extern compop_func op_1a0_0_comp_nf;
+extern compop_func op_1a8_0_comp_nf;
+extern compop_func op_1b0_0_comp_nf;
+extern compop_func op_1b8_0_comp_nf;
+extern compop_func op_1b9_0_comp_nf;
+extern compop_func op_1c0_0_comp_nf;
+extern compop_func op_1d0_0_comp_nf;
+extern compop_func op_1d8_0_comp_nf;
+extern compop_func op_1e0_0_comp_nf;
+extern compop_func op_1e8_0_comp_nf;
+extern compop_func op_1f0_0_comp_nf;
+extern compop_func op_1f8_0_comp_nf;
+extern compop_func op_1f9_0_comp_nf;
+extern compop_func op_200_0_comp_nf;
+extern compop_func op_210_0_comp_nf;
+extern compop_func op_218_0_comp_nf;
+extern compop_func op_220_0_comp_nf;
+extern compop_func op_228_0_comp_nf;
+extern compop_func op_230_0_comp_nf;
+extern compop_func op_238_0_comp_nf;
+extern compop_func op_239_0_comp_nf;
+extern compop_func op_23c_0_comp_nf;
+extern compop_func op_240_0_comp_nf;
+extern compop_func op_250_0_comp_nf;
+extern compop_func op_258_0_comp_nf;
+extern compop_func op_260_0_comp_nf;
+extern compop_func op_268_0_comp_nf;
+extern compop_func op_270_0_comp_nf;
+extern compop_func op_278_0_comp_nf;
+extern compop_func op_279_0_comp_nf;
+extern compop_func op_280_0_comp_nf;
+extern compop_func op_290_0_comp_nf;
+extern compop_func op_298_0_comp_nf;
+extern compop_func op_2a0_0_comp_nf;
+extern compop_func op_2a8_0_comp_nf;
+extern compop_func op_2b0_0_comp_nf;
+extern compop_func op_2b8_0_comp_nf;
+extern compop_func op_2b9_0_comp_nf;
+extern compop_func op_400_0_comp_nf;
+extern compop_func op_410_0_comp_nf;
+extern compop_func op_418_0_comp_nf;
+extern compop_func op_420_0_comp_nf;
+extern compop_func op_428_0_comp_nf;
+extern compop_func op_430_0_comp_nf;
+extern compop_func op_438_0_comp_nf;
+extern compop_func op_439_0_comp_nf;
+extern compop_func op_440_0_comp_nf;
+extern compop_func op_450_0_comp_nf;
+extern compop_func op_458_0_comp_nf;
+extern compop_func op_460_0_comp_nf;
+extern compop_func op_468_0_comp_nf;
+extern compop_func op_470_0_comp_nf;
+extern compop_func op_478_0_comp_nf;
+extern compop_func op_479_0_comp_nf;
+extern compop_func op_480_0_comp_nf;
+extern compop_func op_490_0_comp_nf;
+extern compop_func op_498_0_comp_nf;
+extern compop_func op_4a0_0_comp_nf;
+extern compop_func op_4a8_0_comp_nf;
+extern compop_func op_4b0_0_comp_nf;
+extern compop_func op_4b8_0_comp_nf;
+extern compop_func op_4b9_0_comp_nf;
+extern compop_func op_600_0_comp_nf;
+extern compop_func op_610_0_comp_nf;
+extern compop_func op_618_0_comp_nf;
+extern compop_func op_620_0_comp_nf;
+extern compop_func op_628_0_comp_nf;
+extern compop_func op_630_0_comp_nf;
+extern compop_func op_638_0_comp_nf;
+extern compop_func op_639_0_comp_nf;
+extern compop_func op_640_0_comp_nf;
+extern compop_func op_650_0_comp_nf;
+extern compop_func op_658_0_comp_nf;
+extern compop_func op_660_0_comp_nf;
+extern compop_func op_668_0_comp_nf;
+extern compop_func op_670_0_comp_nf;
+extern compop_func op_678_0_comp_nf;
+extern compop_func op_679_0_comp_nf;
+extern compop_func op_680_0_comp_nf;
+extern compop_func op_690_0_comp_nf;
+extern compop_func op_698_0_comp_nf;
+extern compop_func op_6a0_0_comp_nf;
+extern compop_func op_6a8_0_comp_nf;
+extern compop_func op_6b0_0_comp_nf;
+extern compop_func op_6b8_0_comp_nf;
+extern compop_func op_6b9_0_comp_nf;
+extern compop_func op_800_0_comp_nf;
+extern compop_func op_810_0_comp_nf;
+extern compop_func op_818_0_comp_nf;
+extern compop_func op_820_0_comp_nf;
+extern compop_func op_828_0_comp_nf;
+extern compop_func op_830_0_comp_nf;
+extern compop_func op_838_0_comp_nf;
+extern compop_func op_839_0_comp_nf;
+extern compop_func op_83a_0_comp_nf;
+extern compop_func op_83b_0_comp_nf;
+extern compop_func op_840_0_comp_nf;
+extern compop_func op_850_0_comp_nf;
+extern compop_func op_858_0_comp_nf;
+extern compop_func op_860_0_comp_nf;
+extern compop_func op_868_0_comp_nf;
+extern compop_func op_870_0_comp_nf;
+extern compop_func op_878_0_comp_nf;
+extern compop_func op_879_0_comp_nf;
+extern compop_func op_880_0_comp_nf;
+extern compop_func op_890_0_comp_nf;
+extern compop_func op_898_0_comp_nf;
+extern compop_func op_8a0_0_comp_nf;
+extern compop_func op_8a8_0_comp_nf;
+extern compop_func op_8b0_0_comp_nf;
+extern compop_func op_8b8_0_comp_nf;
+extern compop_func op_8b9_0_comp_nf;
+extern compop_func op_8c0_0_comp_nf;
+extern compop_func op_8d0_0_comp_nf;
+extern compop_func op_8d8_0_comp_nf;
+extern compop_func op_8e0_0_comp_nf;
+extern compop_func op_8e8_0_comp_nf;
+extern compop_func op_8f0_0_comp_nf;
+extern compop_func op_8f8_0_comp_nf;
+extern compop_func op_8f9_0_comp_nf;
+extern compop_func op_a00_0_comp_nf;
+extern compop_func op_a10_0_comp_nf;
+extern compop_func op_a18_0_comp_nf;
+extern compop_func op_a20_0_comp_nf;
+extern compop_func op_a28_0_comp_nf;
+extern compop_func op_a30_0_comp_nf;
+extern compop_func op_a38_0_comp_nf;
+extern compop_func op_a39_0_comp_nf;
+extern compop_func op_a3c_0_comp_nf;
+extern compop_func op_a40_0_comp_nf;
+extern compop_func op_a50_0_comp_nf;
+extern compop_func op_a58_0_comp_nf;
+extern compop_func op_a60_0_comp_nf;
+extern compop_func op_a68_0_comp_nf;
+extern compop_func op_a70_0_comp_nf;
+extern compop_func op_a78_0_comp_nf;
+extern compop_func op_a79_0_comp_nf;
+extern compop_func op_a80_0_comp_nf;
+extern compop_func op_a90_0_comp_nf;
+extern compop_func op_a98_0_comp_nf;
+extern compop_func op_aa0_0_comp_nf;
+extern compop_func op_aa8_0_comp_nf;
+extern compop_func op_ab0_0_comp_nf;
+extern compop_func op_ab8_0_comp_nf;
+extern compop_func op_ab9_0_comp_nf;
+extern compop_func op_c00_0_comp_nf;
+extern compop_func op_c10_0_comp_nf;
+extern compop_func op_c18_0_comp_nf;
+extern compop_func op_c20_0_comp_nf;
+extern compop_func op_c28_0_comp_nf;
+extern compop_func op_c30_0_comp_nf;
+extern compop_func op_c38_0_comp_nf;
+extern compop_func op_c39_0_comp_nf;
+extern compop_func op_c3a_0_comp_nf;
+extern compop_func op_c3b_0_comp_nf;
+extern compop_func op_c40_0_comp_nf;
+extern compop_func op_c50_0_comp_nf;
+extern compop_func op_c58_0_comp_nf;
+extern compop_func op_c60_0_comp_nf;
+extern compop_func op_c68_0_comp_nf;
+extern compop_func op_c70_0_comp_nf;
+extern compop_func op_c78_0_comp_nf;
+extern compop_func op_c79_0_comp_nf;
+extern compop_func op_c7a_0_comp_nf;
+extern compop_func op_c7b_0_comp_nf;
+extern compop_func op_c80_0_comp_nf;
+extern compop_func op_c90_0_comp_nf;
+extern compop_func op_c98_0_comp_nf;
+extern compop_func op_ca0_0_comp_nf;
+extern compop_func op_ca8_0_comp_nf;
+extern compop_func op_cb0_0_comp_nf;
+extern compop_func op_cb8_0_comp_nf;
+extern compop_func op_cb9_0_comp_nf;
+extern compop_func op_cba_0_comp_nf;
+extern compop_func op_cbb_0_comp_nf;
+extern compop_func op_1000_0_comp_nf;
+extern compop_func op_1010_0_comp_nf;
+extern compop_func op_1018_0_comp_nf;
+extern compop_func op_1020_0_comp_nf;
+extern compop_func op_1028_0_comp_nf;
+extern compop_func op_1030_0_comp_nf;
+extern compop_func op_1038_0_comp_nf;
+extern compop_func op_1039_0_comp_nf;
+extern compop_func op_103a_0_comp_nf;
+extern compop_func op_103b_0_comp_nf;
+extern compop_func op_103c_0_comp_nf;
+extern compop_func op_1080_0_comp_nf;
+extern compop_func op_1090_0_comp_nf;
+extern compop_func op_1098_0_comp_nf;
+extern compop_func op_10a0_0_comp_nf;
+extern compop_func op_10a8_0_comp_nf;
+extern compop_func op_10b0_0_comp_nf;
+extern compop_func op_10b8_0_comp_nf;
+extern compop_func op_10b9_0_comp_nf;
+extern compop_func op_10ba_0_comp_nf;
+extern compop_func op_10bb_0_comp_nf;
+extern compop_func op_10bc_0_comp_nf;
+extern compop_func op_10c0_0_comp_nf;
+extern compop_func op_10d0_0_comp_nf;
+extern compop_func op_10d8_0_comp_nf;
+extern compop_func op_10e0_0_comp_nf;
+extern compop_func op_10e8_0_comp_nf;
+extern compop_func op_10f0_0_comp_nf;
+extern compop_func op_10f8_0_comp_nf;
+extern compop_func op_10f9_0_comp_nf;
+extern compop_func op_10fa_0_comp_nf;
+extern compop_func op_10fb_0_comp_nf;
+extern compop_func op_10fc_0_comp_nf;
+extern compop_func op_1100_0_comp_nf;
+extern compop_func op_1110_0_comp_nf;
+extern compop_func op_1118_0_comp_nf;
+extern compop_func op_1120_0_comp_nf;
+extern compop_func op_1128_0_comp_nf;
+extern compop_func op_1130_0_comp_nf;
+extern compop_func op_1138_0_comp_nf;
+extern compop_func op_1139_0_comp_nf;
+extern compop_func op_113a_0_comp_nf;
+extern compop_func op_113b_0_comp_nf;
+extern compop_func op_113c_0_comp_nf;
+extern compop_func op_1140_0_comp_nf;
+extern compop_func op_1150_0_comp_nf;
+extern compop_func op_1158_0_comp_nf;
+extern compop_func op_1160_0_comp_nf;
+extern compop_func op_1168_0_comp_nf;
+extern compop_func op_1170_0_comp_nf;
+extern compop_func op_1178_0_comp_nf;
+extern compop_func op_1179_0_comp_nf;
+extern compop_func op_117a_0_comp_nf;
+extern compop_func op_117b_0_comp_nf;
+extern compop_func op_117c_0_comp_nf;
+extern compop_func op_1180_0_comp_nf;
+extern compop_func op_1190_0_comp_nf;
+extern compop_func op_1198_0_comp_nf;
+extern compop_func op_11a0_0_comp_nf;
+extern compop_func op_11a8_0_comp_nf;
+extern compop_func op_11b0_0_comp_nf;
+extern compop_func op_11b8_0_comp_nf;
+extern compop_func op_11b9_0_comp_nf;
+extern compop_func op_11ba_0_comp_nf;
+extern compop_func op_11bb_0_comp_nf;
+extern compop_func op_11bc_0_comp_nf;
+extern compop_func op_11c0_0_comp_nf;
+extern compop_func op_11d0_0_comp_nf;
+extern compop_func op_11d8_0_comp_nf;
+extern compop_func op_11e0_0_comp_nf;
+extern compop_func op_11e8_0_comp_nf;
+extern compop_func op_11f0_0_comp_nf;
+extern compop_func op_11f8_0_comp_nf;
+extern compop_func op_11f9_0_comp_nf;
+extern compop_func op_11fa_0_comp_nf;
+extern compop_func op_11fb_0_comp_nf;
+extern compop_func op_11fc_0_comp_nf;
+extern compop_func op_13c0_0_comp_nf;
+extern compop_func op_13d0_0_comp_nf;
+extern compop_func op_13d8_0_comp_nf;
+extern compop_func op_13e0_0_comp_nf;
+extern compop_func op_13e8_0_comp_nf;
+extern compop_func op_13f0_0_comp_nf;
+extern compop_func op_13f8_0_comp_nf;
+extern compop_func op_13f9_0_comp_nf;
+extern compop_func op_13fa_0_comp_nf;
+extern compop_func op_13fb_0_comp_nf;
+extern compop_func op_13fc_0_comp_nf;
+extern compop_func op_2000_0_comp_nf;
+extern compop_func op_2008_0_comp_nf;
+extern compop_func op_2010_0_comp_nf;
+extern compop_func op_2018_0_comp_nf;
+extern compop_func op_2020_0_comp_nf;
+extern compop_func op_2028_0_comp_nf;
+extern compop_func op_2030_0_comp_nf;
+extern compop_func op_2038_0_comp_nf;
+extern compop_func op_2039_0_comp_nf;
+extern compop_func op_203a_0_comp_nf;
+extern compop_func op_203b_0_comp_nf;
+extern compop_func op_203c_0_comp_nf;
+extern compop_func op_2040_0_comp_nf;
+extern compop_func op_2048_0_comp_nf;
+extern compop_func op_2050_0_comp_nf;
+extern compop_func op_2058_0_comp_nf;
+extern compop_func op_2060_0_comp_nf;
+extern compop_func op_2068_0_comp_nf;
+extern compop_func op_2070_0_comp_nf;
+extern compop_func op_2078_0_comp_nf;
+extern compop_func op_2079_0_comp_nf;
+extern compop_func op_207a_0_comp_nf;
+extern compop_func op_207b_0_comp_nf;
+extern compop_func op_207c_0_comp_nf;
+extern compop_func op_2080_0_comp_nf;
+extern compop_func op_2088_0_comp_nf;
+extern compop_func op_2090_0_comp_nf;
+extern compop_func op_2098_0_comp_nf;
+extern compop_func op_20a0_0_comp_nf;
+extern compop_func op_20a8_0_comp_nf;
+extern compop_func op_20b0_0_comp_nf;
+extern compop_func op_20b8_0_comp_nf;
+extern compop_func op_20b9_0_comp_nf;
+extern compop_func op_20ba_0_comp_nf;
+extern compop_func op_20bb_0_comp_nf;
+extern compop_func op_20bc_0_comp_nf;
+extern compop_func op_20c0_0_comp_nf;
+extern compop_func op_20c8_0_comp_nf;
+extern compop_func op_20d0_0_comp_nf;
+extern compop_func op_20d8_0_comp_nf;
+extern compop_func op_20e0_0_comp_nf;
+extern compop_func op_20e8_0_comp_nf;
+extern compop_func op_20f0_0_comp_nf;
+extern compop_func op_20f8_0_comp_nf;
+extern compop_func op_20f9_0_comp_nf;
+extern compop_func op_20fa_0_comp_nf;
+extern compop_func op_20fb_0_comp_nf;
+extern compop_func op_20fc_0_comp_nf;
+extern compop_func op_2100_0_comp_nf;
+extern compop_func op_2108_0_comp_nf;
+extern compop_func op_2110_0_comp_nf;
+extern compop_func op_2118_0_comp_nf;
+extern compop_func op_2120_0_comp_nf;
+extern compop_func op_2128_0_comp_nf;
+extern compop_func op_2130_0_comp_nf;
+extern compop_func op_2138_0_comp_nf;
+extern compop_func op_2139_0_comp_nf;
+extern compop_func op_213a_0_comp_nf;
+extern compop_func op_213b_0_comp_nf;
+extern compop_func op_213c_0_comp_nf;
+extern compop_func op_2140_0_comp_nf;
+extern compop_func op_2148_0_comp_nf;
+extern compop_func op_2150_0_comp_nf;
+extern compop_func op_2158_0_comp_nf;
+extern compop_func op_2160_0_comp_nf;
+extern compop_func op_2168_0_comp_nf;
+extern compop_func op_2170_0_comp_nf;
+extern compop_func op_2178_0_comp_nf;
+extern compop_func op_2179_0_comp_nf;
+extern compop_func op_217a_0_comp_nf;
+extern compop_func op_217b_0_comp_nf;
+extern compop_func op_217c_0_comp_nf;
+extern compop_func op_2180_0_comp_nf;
+extern compop_func op_2188_0_comp_nf;
+extern compop_func op_2190_0_comp_nf;
+extern compop_func op_2198_0_comp_nf;
+extern compop_func op_21a0_0_comp_nf;
+extern compop_func op_21a8_0_comp_nf;
+extern compop_func op_21b0_0_comp_nf;
+extern compop_func op_21b8_0_comp_nf;
+extern compop_func op_21b9_0_comp_nf;
+extern compop_func op_21ba_0_comp_nf;
+extern compop_func op_21bb_0_comp_nf;
+extern compop_func op_21bc_0_comp_nf;
+extern compop_func op_21c0_0_comp_nf;
+extern compop_func op_21c8_0_comp_nf;
+extern compop_func op_21d0_0_comp_nf;
+extern compop_func op_21d8_0_comp_nf;
+extern compop_func op_21e0_0_comp_nf;
+extern compop_func op_21e8_0_comp_nf;
+extern compop_func op_21f0_0_comp_nf;
+extern compop_func op_21f8_0_comp_nf;
+extern compop_func op_21f9_0_comp_nf;
+extern compop_func op_21fa_0_comp_nf;
+extern compop_func op_21fb_0_comp_nf;
+extern compop_func op_21fc_0_comp_nf;
+extern compop_func op_23c0_0_comp_nf;
+extern compop_func op_23c8_0_comp_nf;
+extern compop_func op_23d0_0_comp_nf;
+extern compop_func op_23d8_0_comp_nf;
+extern compop_func op_23e0_0_comp_nf;
+extern compop_func op_23e8_0_comp_nf;
+extern compop_func op_23f0_0_comp_nf;
+extern compop_func op_23f8_0_comp_nf;
+extern compop_func op_23f9_0_comp_nf;
+extern compop_func op_23fa_0_comp_nf;
+extern compop_func op_23fb_0_comp_nf;
+extern compop_func op_23fc_0_comp_nf;
+extern compop_func op_3000_0_comp_nf;
+extern compop_func op_3008_0_comp_nf;
+extern compop_func op_3010_0_comp_nf;
+extern compop_func op_3018_0_comp_nf;
+extern compop_func op_3020_0_comp_nf;
+extern compop_func op_3028_0_comp_nf;
+extern compop_func op_3030_0_comp_nf;
+extern compop_func op_3038_0_comp_nf;
+extern compop_func op_3039_0_comp_nf;
+extern compop_func op_303a_0_comp_nf;
+extern compop_func op_303b_0_comp_nf;
+extern compop_func op_303c_0_comp_nf;
+extern compop_func op_3040_0_comp_nf;
+extern compop_func op_3048_0_comp_nf;
+extern compop_func op_3050_0_comp_nf;
+extern compop_func op_3058_0_comp_nf;
+extern compop_func op_3060_0_comp_nf;
+extern compop_func op_3068_0_comp_nf;
+extern compop_func op_3070_0_comp_nf;
+extern compop_func op_3078_0_comp_nf;
+extern compop_func op_3079_0_comp_nf;
+extern compop_func op_307a_0_comp_nf;
+extern compop_func op_307b_0_comp_nf;
+extern compop_func op_307c_0_comp_nf;
+extern compop_func op_3080_0_comp_nf;
+extern compop_func op_3088_0_comp_nf;
+extern compop_func op_3090_0_comp_nf;
+extern compop_func op_3098_0_comp_nf;
+extern compop_func op_30a0_0_comp_nf;
+extern compop_func op_30a8_0_comp_nf;
+extern compop_func op_30b0_0_comp_nf;
+extern compop_func op_30b8_0_comp_nf;
+extern compop_func op_30b9_0_comp_nf;
+extern compop_func op_30ba_0_comp_nf;
+extern compop_func op_30bb_0_comp_nf;
+extern compop_func op_30bc_0_comp_nf;
+extern compop_func op_30c0_0_comp_nf;
+extern compop_func op_30c8_0_comp_nf;
+extern compop_func op_30d0_0_comp_nf;
+extern compop_func op_30d8_0_comp_nf;
+extern compop_func op_30e0_0_comp_nf;
+extern compop_func op_30e8_0_comp_nf;
+extern compop_func op_30f0_0_comp_nf;
+extern compop_func op_30f8_0_comp_nf;
+extern compop_func op_30f9_0_comp_nf;
+extern compop_func op_30fa_0_comp_nf;
+extern compop_func op_30fb_0_comp_nf;
+extern compop_func op_30fc_0_comp_nf;
+extern compop_func op_3100_0_comp_nf;
+extern compop_func op_3108_0_comp_nf;
+extern compop_func op_3110_0_comp_nf;
+extern compop_func op_3118_0_comp_nf;
+extern compop_func op_3120_0_comp_nf;
+extern compop_func op_3128_0_comp_nf;
+extern compop_func op_3130_0_comp_nf;
+extern compop_func op_3138_0_comp_nf;
+extern compop_func op_3139_0_comp_nf;
+extern compop_func op_313a_0_comp_nf;
+extern compop_func op_313b_0_comp_nf;
+extern compop_func op_313c_0_comp_nf;
+extern compop_func op_3140_0_comp_nf;
+extern compop_func op_3148_0_comp_nf;
+extern compop_func op_3150_0_comp_nf;
+extern compop_func op_3158_0_comp_nf;
+extern compop_func op_3160_0_comp_nf;
+extern compop_func op_3168_0_comp_nf;
+extern compop_func op_3170_0_comp_nf;
+extern compop_func op_3178_0_comp_nf;
+extern compop_func op_3179_0_comp_nf;
+extern compop_func op_317a_0_comp_nf;
+extern compop_func op_317b_0_comp_nf;
+extern compop_func op_317c_0_comp_nf;
+extern compop_func op_3180_0_comp_nf;
+extern compop_func op_3188_0_comp_nf;
+extern compop_func op_3190_0_comp_nf;
+extern compop_func op_3198_0_comp_nf;
+extern compop_func op_31a0_0_comp_nf;
+extern compop_func op_31a8_0_comp_nf;
+extern compop_func op_31b0_0_comp_nf;
+extern compop_func op_31b8_0_comp_nf;
+extern compop_func op_31b9_0_comp_nf;
+extern compop_func op_31ba_0_comp_nf;
+extern compop_func op_31bb_0_comp_nf;
+extern compop_func op_31bc_0_comp_nf;
+extern compop_func op_31c0_0_comp_nf;
+extern compop_func op_31c8_0_comp_nf;
+extern compop_func op_31d0_0_comp_nf;
+extern compop_func op_31d8_0_comp_nf;
+extern compop_func op_31e0_0_comp_nf;
+extern compop_func op_31e8_0_comp_nf;
+extern compop_func op_31f0_0_comp_nf;
+extern compop_func op_31f8_0_comp_nf;
+extern compop_func op_31f9_0_comp_nf;
+extern compop_func op_31fa_0_comp_nf;
+extern compop_func op_31fb_0_comp_nf;
+extern compop_func op_31fc_0_comp_nf;
+extern compop_func op_33c0_0_comp_nf;
+extern compop_func op_33c8_0_comp_nf;
+extern compop_func op_33d0_0_comp_nf;
+extern compop_func op_33d8_0_comp_nf;
+extern compop_func op_33e0_0_comp_nf;
+extern compop_func op_33e8_0_comp_nf;
+extern compop_func op_33f0_0_comp_nf;
+extern compop_func op_33f8_0_comp_nf;
+extern compop_func op_33f9_0_comp_nf;
+extern compop_func op_33fa_0_comp_nf;
+extern compop_func op_33fb_0_comp_nf;
+extern compop_func op_33fc_0_comp_nf;
+extern compop_func op_4000_0_comp_nf;
+extern compop_func op_4010_0_comp_nf;
+extern compop_func op_4018_0_comp_nf;
+extern compop_func op_4020_0_comp_nf;
+extern compop_func op_4028_0_comp_nf;
+extern compop_func op_4030_0_comp_nf;
+extern compop_func op_4038_0_comp_nf;
+extern compop_func op_4039_0_comp_nf;
+extern compop_func op_4040_0_comp_nf;
+extern compop_func op_4050_0_comp_nf;
+extern compop_func op_4058_0_comp_nf;
+extern compop_func op_4060_0_comp_nf;
+extern compop_func op_4068_0_comp_nf;
+extern compop_func op_4070_0_comp_nf;
+extern compop_func op_4078_0_comp_nf;
+extern compop_func op_4079_0_comp_nf;
+extern compop_func op_4080_0_comp_nf;
+extern compop_func op_4090_0_comp_nf;
+extern compop_func op_4098_0_comp_nf;
+extern compop_func op_40a0_0_comp_nf;
+extern compop_func op_40a8_0_comp_nf;
+extern compop_func op_40b0_0_comp_nf;
+extern compop_func op_40b8_0_comp_nf;
+extern compop_func op_40b9_0_comp_nf;
+extern compop_func op_41d0_0_comp_nf;
+extern compop_func op_41e8_0_comp_nf;
+extern compop_func op_41f0_0_comp_nf;
+extern compop_func op_41f8_0_comp_nf;
+extern compop_func op_41f9_0_comp_nf;
+extern compop_func op_41fa_0_comp_nf;
+extern compop_func op_41fb_0_comp_nf;
+extern compop_func op_4200_0_comp_nf;
+extern compop_func op_4210_0_comp_nf;
+extern compop_func op_4218_0_comp_nf;
+extern compop_func op_4220_0_comp_nf;
+extern compop_func op_4228_0_comp_nf;
+extern compop_func op_4230_0_comp_nf;
+extern compop_func op_4238_0_comp_nf;
+extern compop_func op_4239_0_comp_nf;
+extern compop_func op_4240_0_comp_nf;
+extern compop_func op_4250_0_comp_nf;
+extern compop_func op_4258_0_comp_nf;
+extern compop_func op_4260_0_comp_nf;
+extern compop_func op_4268_0_comp_nf;
+extern compop_func op_4270_0_comp_nf;
+extern compop_func op_4278_0_comp_nf;
+extern compop_func op_4279_0_comp_nf;
+extern compop_func op_4280_0_comp_nf;
+extern compop_func op_4290_0_comp_nf;
+extern compop_func op_4298_0_comp_nf;
+extern compop_func op_42a0_0_comp_nf;
+extern compop_func op_42a8_0_comp_nf;
+extern compop_func op_42b0_0_comp_nf;
+extern compop_func op_42b8_0_comp_nf;
+extern compop_func op_42b9_0_comp_nf;
+extern compop_func op_4400_0_comp_nf;
+extern compop_func op_4410_0_comp_nf;
+extern compop_func op_4418_0_comp_nf;
+extern compop_func op_4420_0_comp_nf;
+extern compop_func op_4428_0_comp_nf;
+extern compop_func op_4430_0_comp_nf;
+extern compop_func op_4438_0_comp_nf;
+extern compop_func op_4439_0_comp_nf;
+extern compop_func op_4440_0_comp_nf;
+extern compop_func op_4450_0_comp_nf;
+extern compop_func op_4458_0_comp_nf;
+extern compop_func op_4460_0_comp_nf;
+extern compop_func op_4468_0_comp_nf;
+extern compop_func op_4470_0_comp_nf;
+extern compop_func op_4478_0_comp_nf;
+extern compop_func op_4479_0_comp_nf;
+extern compop_func op_4480_0_comp_nf;
+extern compop_func op_4490_0_comp_nf;
+extern compop_func op_4498_0_comp_nf;
+extern compop_func op_44a0_0_comp_nf;
+extern compop_func op_44a8_0_comp_nf;
+extern compop_func op_44b0_0_comp_nf;
+extern compop_func op_44b8_0_comp_nf;
+extern compop_func op_44b9_0_comp_nf;
+extern compop_func op_4600_0_comp_nf;
+extern compop_func op_4610_0_comp_nf;
+extern compop_func op_4618_0_comp_nf;
+extern compop_func op_4620_0_comp_nf;
+extern compop_func op_4628_0_comp_nf;
+extern compop_func op_4630_0_comp_nf;
+extern compop_func op_4638_0_comp_nf;
+extern compop_func op_4639_0_comp_nf;
+extern compop_func op_4640_0_comp_nf;
+extern compop_func op_4650_0_comp_nf;
+extern compop_func op_4658_0_comp_nf;
+extern compop_func op_4660_0_comp_nf;
+extern compop_func op_4668_0_comp_nf;
+extern compop_func op_4670_0_comp_nf;
+extern compop_func op_4678_0_comp_nf;
+extern compop_func op_4679_0_comp_nf;
+extern compop_func op_4680_0_comp_nf;
+extern compop_func op_4690_0_comp_nf;
+extern compop_func op_4698_0_comp_nf;
+extern compop_func op_46a0_0_comp_nf;
+extern compop_func op_46a8_0_comp_nf;
+extern compop_func op_46b0_0_comp_nf;
+extern compop_func op_46b8_0_comp_nf;
+extern compop_func op_46b9_0_comp_nf;
+extern compop_func op_4808_0_comp_nf;
+extern compop_func op_4840_0_comp_nf;
+extern compop_func op_4850_0_comp_nf;
+extern compop_func op_4868_0_comp_nf;
+extern compop_func op_4870_0_comp_nf;
+extern compop_func op_4878_0_comp_nf;
+extern compop_func op_4879_0_comp_nf;
+extern compop_func op_487a_0_comp_nf;
+extern compop_func op_487b_0_comp_nf;
+extern compop_func op_4880_0_comp_nf;
+extern compop_func op_4890_0_comp_nf;
+extern compop_func op_48a0_0_comp_nf;
+extern compop_func op_48a8_0_comp_nf;
+extern compop_func op_48b0_0_comp_nf;
+extern compop_func op_48b8_0_comp_nf;
+extern compop_func op_48b9_0_comp_nf;
+extern compop_func op_48c0_0_comp_nf;
+extern compop_func op_48d0_0_comp_nf;
+extern compop_func op_48e0_0_comp_nf;
+extern compop_func op_48e8_0_comp_nf;
+extern compop_func op_48f0_0_comp_nf;
+extern compop_func op_48f8_0_comp_nf;
+extern compop_func op_48f9_0_comp_nf;
+extern compop_func op_49c0_0_comp_nf;
+extern compop_func op_4a00_0_comp_nf;
+extern compop_func op_4a10_0_comp_nf;
+extern compop_func op_4a18_0_comp_nf;
+extern compop_func op_4a20_0_comp_nf;
+extern compop_func op_4a28_0_comp_nf;
+extern compop_func op_4a30_0_comp_nf;
+extern compop_func op_4a38_0_comp_nf;
+extern compop_func op_4a39_0_comp_nf;
+extern compop_func op_4a3a_0_comp_nf;
+extern compop_func op_4a3b_0_comp_nf;
+extern compop_func op_4a3c_0_comp_nf;
+extern compop_func op_4a40_0_comp_nf;
+extern compop_func op_4a48_0_comp_nf;
+extern compop_func op_4a50_0_comp_nf;
+extern compop_func op_4a58_0_comp_nf;
+extern compop_func op_4a60_0_comp_nf;
+extern compop_func op_4a68_0_comp_nf;
+extern compop_func op_4a70_0_comp_nf;
+extern compop_func op_4a78_0_comp_nf;
+extern compop_func op_4a79_0_comp_nf;
+extern compop_func op_4a7a_0_comp_nf;
+extern compop_func op_4a7b_0_comp_nf;
+extern compop_func op_4a7c_0_comp_nf;
+extern compop_func op_4a80_0_comp_nf;
+extern compop_func op_4a88_0_comp_nf;
+extern compop_func op_4a90_0_comp_nf;
+extern compop_func op_4a98_0_comp_nf;
+extern compop_func op_4aa0_0_comp_nf;
+extern compop_func op_4aa8_0_comp_nf;
+extern compop_func op_4ab0_0_comp_nf;
+extern compop_func op_4ab8_0_comp_nf;
+extern compop_func op_4ab9_0_comp_nf;
+extern compop_func op_4aba_0_comp_nf;
+extern compop_func op_4abb_0_comp_nf;
+extern compop_func op_4abc_0_comp_nf;
+extern compop_func op_4c00_0_comp_nf;
+extern compop_func op_4c10_0_comp_nf;
+extern compop_func op_4c18_0_comp_nf;
+extern compop_func op_4c20_0_comp_nf;
+extern compop_func op_4c28_0_comp_nf;
+extern compop_func op_4c30_0_comp_nf;
+extern compop_func op_4c38_0_comp_nf;
+extern compop_func op_4c39_0_comp_nf;
+extern compop_func op_4c3a_0_comp_nf;
+extern compop_func op_4c3b_0_comp_nf;
+extern compop_func op_4c3c_0_comp_nf;
+extern compop_func op_4c40_0_comp_nf;
+extern compop_func op_4c50_0_comp_nf;
+extern compop_func op_4c58_0_comp_nf;
+extern compop_func op_4c60_0_comp_nf;
+extern compop_func op_4c68_0_comp_nf;
+extern compop_func op_4c70_0_comp_nf;
+extern compop_func op_4c78_0_comp_nf;
+extern compop_func op_4c79_0_comp_nf;
+extern compop_func op_4c7a_0_comp_nf;
+extern compop_func op_4c7b_0_comp_nf;
+extern compop_func op_4c7c_0_comp_nf;
+extern compop_func op_4c90_0_comp_nf;
+extern compop_func op_4c98_0_comp_nf;
+extern compop_func op_4ca8_0_comp_nf;
+extern compop_func op_4cb0_0_comp_nf;
+extern compop_func op_4cb8_0_comp_nf;
+extern compop_func op_4cb9_0_comp_nf;
+extern compop_func op_4cba_0_comp_nf;
+extern compop_func op_4cbb_0_comp_nf;
+extern compop_func op_4cd0_0_comp_nf;
+extern compop_func op_4cd8_0_comp_nf;
+extern compop_func op_4ce8_0_comp_nf;
+extern compop_func op_4cf0_0_comp_nf;
+extern compop_func op_4cf8_0_comp_nf;
+extern compop_func op_4cf9_0_comp_nf;
+extern compop_func op_4cfa_0_comp_nf;
+extern compop_func op_4cfb_0_comp_nf;
+extern compop_func op_4e50_0_comp_nf;
+extern compop_func op_4e58_0_comp_nf;
+extern compop_func op_4e71_0_comp_nf;
+extern compop_func op_4e74_0_comp_nf;
+extern compop_func op_4e75_0_comp_nf;
+extern compop_func op_4e90_0_comp_nf;
+extern compop_func op_4ea8_0_comp_nf;
+extern compop_func op_4eb0_0_comp_nf;
+extern compop_func op_4eb8_0_comp_nf;
+extern compop_func op_4eb9_0_comp_nf;
+extern compop_func op_4eba_0_comp_nf;
+extern compop_func op_4ebb_0_comp_nf;
+extern compop_func op_4ed0_0_comp_nf;
+extern compop_func op_4ee8_0_comp_nf;
+extern compop_func op_4ef0_0_comp_nf;
+extern compop_func op_4ef8_0_comp_nf;
+extern compop_func op_4ef9_0_comp_nf;
+extern compop_func op_4efa_0_comp_nf;
+extern compop_func op_4efb_0_comp_nf;
+extern compop_func op_5000_0_comp_nf;
+extern compop_func op_5010_0_comp_nf;
+extern compop_func op_5018_0_comp_nf;
+extern compop_func op_5020_0_comp_nf;
+extern compop_func op_5028_0_comp_nf;
+extern compop_func op_5030_0_comp_nf;
+extern compop_func op_5038_0_comp_nf;
+extern compop_func op_5039_0_comp_nf;
+extern compop_func op_5040_0_comp_nf;
+extern compop_func op_5048_0_comp_nf;
+extern compop_func op_5050_0_comp_nf;
+extern compop_func op_5058_0_comp_nf;
+extern compop_func op_5060_0_comp_nf;
+extern compop_func op_5068_0_comp_nf;
+extern compop_func op_5070_0_comp_nf;
+extern compop_func op_5078_0_comp_nf;
+extern compop_func op_5079_0_comp_nf;
+extern compop_func op_5080_0_comp_nf;
+extern compop_func op_5088_0_comp_nf;
+extern compop_func op_5090_0_comp_nf;
+extern compop_func op_5098_0_comp_nf;
+extern compop_func op_50a0_0_comp_nf;
+extern compop_func op_50a8_0_comp_nf;
+extern compop_func op_50b0_0_comp_nf;
+extern compop_func op_50b8_0_comp_nf;
+extern compop_func op_50b9_0_comp_nf;
+extern compop_func op_50c0_0_comp_nf;
+extern compop_func op_50c8_0_comp_nf;
+extern compop_func op_50d0_0_comp_nf;
+extern compop_func op_50d8_0_comp_nf;
+extern compop_func op_50e0_0_comp_nf;
+extern compop_func op_50e8_0_comp_nf;
+extern compop_func op_50f0_0_comp_nf;
+extern compop_func op_50f8_0_comp_nf;
+extern compop_func op_50f9_0_comp_nf;
+extern compop_func op_5100_0_comp_nf;
+extern compop_func op_5110_0_comp_nf;
+extern compop_func op_5118_0_comp_nf;
+extern compop_func op_5120_0_comp_nf;
+extern compop_func op_5128_0_comp_nf;
+extern compop_func op_5130_0_comp_nf;
+extern compop_func op_5138_0_comp_nf;
+extern compop_func op_5139_0_comp_nf;
+extern compop_func op_5140_0_comp_nf;
+extern compop_func op_5148_0_comp_nf;
+extern compop_func op_5150_0_comp_nf;
+extern compop_func op_5158_0_comp_nf;
+extern compop_func op_5160_0_comp_nf;
+extern compop_func op_5168_0_comp_nf;
+extern compop_func op_5170_0_comp_nf;
+extern compop_func op_5178_0_comp_nf;
+extern compop_func op_5179_0_comp_nf;
+extern compop_func op_5180_0_comp_nf;
+extern compop_func op_5188_0_comp_nf;
+extern compop_func op_5190_0_comp_nf;
+extern compop_func op_5198_0_comp_nf;
+extern compop_func op_51a0_0_comp_nf;
+extern compop_func op_51a8_0_comp_nf;
+extern compop_func op_51b0_0_comp_nf;
+extern compop_func op_51b8_0_comp_nf;
+extern compop_func op_51b9_0_comp_nf;
+extern compop_func op_51c0_0_comp_nf;
+extern compop_func op_51c8_0_comp_nf;
+extern compop_func op_51d0_0_comp_nf;
+extern compop_func op_51d8_0_comp_nf;
+extern compop_func op_51e0_0_comp_nf;
+extern compop_func op_51e8_0_comp_nf;
+extern compop_func op_51f0_0_comp_nf;
+extern compop_func op_51f8_0_comp_nf;
+extern compop_func op_51f9_0_comp_nf;
+extern compop_func op_52c0_0_comp_nf;
+extern compop_func op_52c8_0_comp_nf;
+extern compop_func op_52d0_0_comp_nf;
+extern compop_func op_52d8_0_comp_nf;
+extern compop_func op_52e0_0_comp_nf;
+extern compop_func op_52e8_0_comp_nf;
+extern compop_func op_52f0_0_comp_nf;
+extern compop_func op_52f8_0_comp_nf;
+extern compop_func op_52f9_0_comp_nf;
+extern compop_func op_53c0_0_comp_nf;
+extern compop_func op_53c8_0_comp_nf;
+extern compop_func op_53d0_0_comp_nf;
+extern compop_func op_53d8_0_comp_nf;
+extern compop_func op_53e0_0_comp_nf;
+extern compop_func op_53e8_0_comp_nf;
+extern compop_func op_53f0_0_comp_nf;
+extern compop_func op_53f8_0_comp_nf;
+extern compop_func op_53f9_0_comp_nf;
+extern compop_func op_54c0_0_comp_nf;
+extern compop_func op_54c8_0_comp_nf;
+extern compop_func op_54d0_0_comp_nf;
+extern compop_func op_54d8_0_comp_nf;
+extern compop_func op_54e0_0_comp_nf;
+extern compop_func op_54e8_0_comp_nf;
+extern compop_func op_54f0_0_comp_nf;
+extern compop_func op_54f8_0_comp_nf;
+extern compop_func op_54f9_0_comp_nf;
+extern compop_func op_55c0_0_comp_nf;
+extern compop_func op_55c8_0_comp_nf;
+extern compop_func op_55d0_0_comp_nf;
+extern compop_func op_55d8_0_comp_nf;
+extern compop_func op_55e0_0_comp_nf;
+extern compop_func op_55e8_0_comp_nf;
+extern compop_func op_55f0_0_comp_nf;
+extern compop_func op_55f8_0_comp_nf;
+extern compop_func op_55f9_0_comp_nf;
+extern compop_func op_56c0_0_comp_nf;
+extern compop_func op_56c8_0_comp_nf;
+extern compop_func op_56d0_0_comp_nf;
+extern compop_func op_56d8_0_comp_nf;
+extern compop_func op_56e0_0_comp_nf;
+extern compop_func op_56e8_0_comp_nf;
+extern compop_func op_56f0_0_comp_nf;
+extern compop_func op_56f8_0_comp_nf;
+extern compop_func op_56f9_0_comp_nf;
+extern compop_func op_57c0_0_comp_nf;
+extern compop_func op_57c8_0_comp_nf;
+extern compop_func op_57d0_0_comp_nf;
+extern compop_func op_57d8_0_comp_nf;
+extern compop_func op_57e0_0_comp_nf;
+extern compop_func op_57e8_0_comp_nf;
+extern compop_func op_57f0_0_comp_nf;
+extern compop_func op_57f8_0_comp_nf;
+extern compop_func op_57f9_0_comp_nf;
+extern compop_func op_58c0_0_comp_nf;
+extern compop_func op_58c8_0_comp_nf;
+extern compop_func op_58d0_0_comp_nf;
+extern compop_func op_58d8_0_comp_nf;
+extern compop_func op_58e0_0_comp_nf;
+extern compop_func op_58e8_0_comp_nf;
+extern compop_func op_58f0_0_comp_nf;
+extern compop_func op_58f8_0_comp_nf;
+extern compop_func op_58f9_0_comp_nf;
+extern compop_func op_59c0_0_comp_nf;
+extern compop_func op_59c8_0_comp_nf;
+extern compop_func op_59d0_0_comp_nf;
+extern compop_func op_59d8_0_comp_nf;
+extern compop_func op_59e0_0_comp_nf;
+extern compop_func op_59e8_0_comp_nf;
+extern compop_func op_59f0_0_comp_nf;
+extern compop_func op_59f8_0_comp_nf;
+extern compop_func op_59f9_0_comp_nf;
+extern compop_func op_5ac0_0_comp_nf;
+extern compop_func op_5ac8_0_comp_nf;
+extern compop_func op_5ad0_0_comp_nf;
+extern compop_func op_5ad8_0_comp_nf;
+extern compop_func op_5ae0_0_comp_nf;
+extern compop_func op_5ae8_0_comp_nf;
+extern compop_func op_5af0_0_comp_nf;
+extern compop_func op_5af8_0_comp_nf;
+extern compop_func op_5af9_0_comp_nf;
+extern compop_func op_5bc0_0_comp_nf;
+extern compop_func op_5bc8_0_comp_nf;
+extern compop_func op_5bd0_0_comp_nf;
+extern compop_func op_5bd8_0_comp_nf;
+extern compop_func op_5be0_0_comp_nf;
+extern compop_func op_5be8_0_comp_nf;
+extern compop_func op_5bf0_0_comp_nf;
+extern compop_func op_5bf8_0_comp_nf;
+extern compop_func op_5bf9_0_comp_nf;
+extern compop_func op_5cc0_0_comp_nf;
+extern compop_func op_5cc8_0_comp_nf;
+extern compop_func op_5cd0_0_comp_nf;
+extern compop_func op_5cd8_0_comp_nf;
+extern compop_func op_5ce0_0_comp_nf;
+extern compop_func op_5ce8_0_comp_nf;
+extern compop_func op_5cf0_0_comp_nf;
+extern compop_func op_5cf8_0_comp_nf;
+extern compop_func op_5cf9_0_comp_nf;
+extern compop_func op_5dc0_0_comp_nf;
+extern compop_func op_5dc8_0_comp_nf;
+extern compop_func op_5dd0_0_comp_nf;
+extern compop_func op_5dd8_0_comp_nf;
+extern compop_func op_5de0_0_comp_nf;
+extern compop_func op_5de8_0_comp_nf;
+extern compop_func op_5df0_0_comp_nf;
+extern compop_func op_5df8_0_comp_nf;
+extern compop_func op_5df9_0_comp_nf;
+extern compop_func op_5ec0_0_comp_nf;
+extern compop_func op_5ec8_0_comp_nf;
+extern compop_func op_5ed0_0_comp_nf;
+extern compop_func op_5ed8_0_comp_nf;
+extern compop_func op_5ee0_0_comp_nf;
+extern compop_func op_5ee8_0_comp_nf;
+extern compop_func op_5ef0_0_comp_nf;
+extern compop_func op_5ef8_0_comp_nf;
+extern compop_func op_5ef9_0_comp_nf;
+extern compop_func op_5fc0_0_comp_nf;
+extern compop_func op_5fc8_0_comp_nf;
+extern compop_func op_5fd0_0_comp_nf;
+extern compop_func op_5fd8_0_comp_nf;
+extern compop_func op_5fe0_0_comp_nf;
+extern compop_func op_5fe8_0_comp_nf;
+extern compop_func op_5ff0_0_comp_nf;
+extern compop_func op_5ff8_0_comp_nf;
+extern compop_func op_5ff9_0_comp_nf;
+extern compop_func op_6000_0_comp_nf;
+extern compop_func op_6001_0_comp_nf;
+extern compop_func op_60ff_0_comp_nf;
+extern compop_func op_6100_0_comp_nf;
+extern compop_func op_6101_0_comp_nf;
+extern compop_func op_61ff_0_comp_nf;
+extern compop_func op_6200_0_comp_nf;
+extern compop_func op_6201_0_comp_nf;
+extern compop_func op_62ff_0_comp_nf;
+extern compop_func op_6300_0_comp_nf;
+extern compop_func op_6301_0_comp_nf;
+extern compop_func op_63ff_0_comp_nf;
+extern compop_func op_6400_0_comp_nf;
+extern compop_func op_6401_0_comp_nf;
+extern compop_func op_64ff_0_comp_nf;
+extern compop_func op_6500_0_comp_nf;
+extern compop_func op_6501_0_comp_nf;
+extern compop_func op_65ff_0_comp_nf;
+extern compop_func op_6600_0_comp_nf;
+extern compop_func op_6601_0_comp_nf;
+extern compop_func op_66ff_0_comp_nf;
+extern compop_func op_6700_0_comp_nf;
+extern compop_func op_6701_0_comp_nf;
+extern compop_func op_67ff_0_comp_nf;
+extern compop_func op_6800_0_comp_nf;
+extern compop_func op_6801_0_comp_nf;
+extern compop_func op_68ff_0_comp_nf;
+extern compop_func op_6900_0_comp_nf;
+extern compop_func op_6901_0_comp_nf;
+extern compop_func op_69ff_0_comp_nf;
+extern compop_func op_6a00_0_comp_nf;
+extern compop_func op_6a01_0_comp_nf;
+extern compop_func op_6aff_0_comp_nf;
+extern compop_func op_6b00_0_comp_nf;
+extern compop_func op_6b01_0_comp_nf;
+extern compop_func op_6bff_0_comp_nf;
+extern compop_func op_6c00_0_comp_nf;
+extern compop_func op_6c01_0_comp_nf;
+extern compop_func op_6cff_0_comp_nf;
+extern compop_func op_6d00_0_comp_nf;
+extern compop_func op_6d01_0_comp_nf;
+extern compop_func op_6dff_0_comp_nf;
+extern compop_func op_6e00_0_comp_nf;
+extern compop_func op_6e01_0_comp_nf;
+extern compop_func op_6eff_0_comp_nf;
+extern compop_func op_6f00_0_comp_nf;
+extern compop_func op_6f01_0_comp_nf;
+extern compop_func op_6fff_0_comp_nf;
+extern compop_func op_7000_0_comp_nf;
+extern compop_func op_8000_0_comp_nf;
+extern compop_func op_8010_0_comp_nf;
+extern compop_func op_8018_0_comp_nf;
+extern compop_func op_8020_0_comp_nf;
+extern compop_func op_8028_0_comp_nf;
+extern compop_func op_8030_0_comp_nf;
+extern compop_func op_8038_0_comp_nf;
+extern compop_func op_8039_0_comp_nf;
+extern compop_func op_803a_0_comp_nf;
+extern compop_func op_803b_0_comp_nf;
+extern compop_func op_803c_0_comp_nf;
+extern compop_func op_8040_0_comp_nf;
+extern compop_func op_8050_0_comp_nf;
+extern compop_func op_8058_0_comp_nf;
+extern compop_func op_8060_0_comp_nf;
+extern compop_func op_8068_0_comp_nf;
+extern compop_func op_8070_0_comp_nf;
+extern compop_func op_8078_0_comp_nf;
+extern compop_func op_8079_0_comp_nf;
+extern compop_func op_807a_0_comp_nf;
+extern compop_func op_807b_0_comp_nf;
+extern compop_func op_807c_0_comp_nf;
+extern compop_func op_8080_0_comp_nf;
+extern compop_func op_8090_0_comp_nf;
+extern compop_func op_8098_0_comp_nf;
+extern compop_func op_80a0_0_comp_nf;
+extern compop_func op_80a8_0_comp_nf;
+extern compop_func op_80b0_0_comp_nf;
+extern compop_func op_80b8_0_comp_nf;
+extern compop_func op_80b9_0_comp_nf;
+extern compop_func op_80ba_0_comp_nf;
+extern compop_func op_80bb_0_comp_nf;
+extern compop_func op_80bc_0_comp_nf;
+extern compop_func op_80c0_0_comp_nf;
+extern compop_func op_80d0_0_comp_nf;
+extern compop_func op_80d8_0_comp_nf;
+extern compop_func op_80e0_0_comp_nf;
+extern compop_func op_80e8_0_comp_nf;
+extern compop_func op_80f0_0_comp_nf;
+extern compop_func op_80f8_0_comp_nf;
+extern compop_func op_80f9_0_comp_nf;
+extern compop_func op_80fa_0_comp_nf;
+extern compop_func op_80fb_0_comp_nf;
+extern compop_func op_80fc_0_comp_nf;
+extern compop_func op_8110_0_comp_nf;
+extern compop_func op_8118_0_comp_nf;
+extern compop_func op_8120_0_comp_nf;
+extern compop_func op_8128_0_comp_nf;
+extern compop_func op_8130_0_comp_nf;
+extern compop_func op_8138_0_comp_nf;
+extern compop_func op_8139_0_comp_nf;
+extern compop_func op_8150_0_comp_nf;
+extern compop_func op_8158_0_comp_nf;
+extern compop_func op_8160_0_comp_nf;
+extern compop_func op_8168_0_comp_nf;
+extern compop_func op_8170_0_comp_nf;
+extern compop_func op_8178_0_comp_nf;
+extern compop_func op_8179_0_comp_nf;
+extern compop_func op_8190_0_comp_nf;
+extern compop_func op_8198_0_comp_nf;
+extern compop_func op_81a0_0_comp_nf;
+extern compop_func op_81a8_0_comp_nf;
+extern compop_func op_81b0_0_comp_nf;
+extern compop_func op_81b8_0_comp_nf;
+extern compop_func op_81b9_0_comp_nf;
+extern compop_func op_81c0_0_comp_nf;
+extern compop_func op_81d0_0_comp_nf;
+extern compop_func op_81d8_0_comp_nf;
+extern compop_func op_81e0_0_comp_nf;
+extern compop_func op_81e8_0_comp_nf;
+extern compop_func op_81f0_0_comp_nf;
+extern compop_func op_81f8_0_comp_nf;
+extern compop_func op_81f9_0_comp_nf;
+extern compop_func op_81fa_0_comp_nf;
+extern compop_func op_81fb_0_comp_nf;
+extern compop_func op_81fc_0_comp_nf;
+extern compop_func op_9000_0_comp_nf;
+extern compop_func op_9010_0_comp_nf;
+extern compop_func op_9018_0_comp_nf;
+extern compop_func op_9020_0_comp_nf;
+extern compop_func op_9028_0_comp_nf;
+extern compop_func op_9030_0_comp_nf;
+extern compop_func op_9038_0_comp_nf;
+extern compop_func op_9039_0_comp_nf;
+extern compop_func op_903a_0_comp_nf;
+extern compop_func op_903b_0_comp_nf;
+extern compop_func op_903c_0_comp_nf;
+extern compop_func op_9040_0_comp_nf;
+extern compop_func op_9048_0_comp_nf;
+extern compop_func op_9050_0_comp_nf;
+extern compop_func op_9058_0_comp_nf;
+extern compop_func op_9060_0_comp_nf;
+extern compop_func op_9068_0_comp_nf;
+extern compop_func op_9070_0_comp_nf;
+extern compop_func op_9078_0_comp_nf;
+extern compop_func op_9079_0_comp_nf;
+extern compop_func op_907a_0_comp_nf;
+extern compop_func op_907b_0_comp_nf;
+extern compop_func op_907c_0_comp_nf;
+extern compop_func op_9080_0_comp_nf;
+extern compop_func op_9088_0_comp_nf;
+extern compop_func op_9090_0_comp_nf;
+extern compop_func op_9098_0_comp_nf;
+extern compop_func op_90a0_0_comp_nf;
+extern compop_func op_90a8_0_comp_nf;
+extern compop_func op_90b0_0_comp_nf;
+extern compop_func op_90b8_0_comp_nf;
+extern compop_func op_90b9_0_comp_nf;
+extern compop_func op_90ba_0_comp_nf;
+extern compop_func op_90bb_0_comp_nf;
+extern compop_func op_90bc_0_comp_nf;
+extern compop_func op_90c0_0_comp_nf;
+extern compop_func op_90c8_0_comp_nf;
+extern compop_func op_90d0_0_comp_nf;
+extern compop_func op_90d8_0_comp_nf;
+extern compop_func op_90e0_0_comp_nf;
+extern compop_func op_90e8_0_comp_nf;
+extern compop_func op_90f0_0_comp_nf;
+extern compop_func op_90f8_0_comp_nf;
+extern compop_func op_90f9_0_comp_nf;
+extern compop_func op_90fa_0_comp_nf;
+extern compop_func op_90fb_0_comp_nf;
+extern compop_func op_90fc_0_comp_nf;
+extern compop_func op_9100_0_comp_nf;
+extern compop_func op_9108_0_comp_nf;
+extern compop_func op_9110_0_comp_nf;
+extern compop_func op_9118_0_comp_nf;
+extern compop_func op_9120_0_comp_nf;
+extern compop_func op_9128_0_comp_nf;
+extern compop_func op_9130_0_comp_nf;
+extern compop_func op_9138_0_comp_nf;
+extern compop_func op_9139_0_comp_nf;
+extern compop_func op_9140_0_comp_nf;
+extern compop_func op_9148_0_comp_nf;
+extern compop_func op_9150_0_comp_nf;
+extern compop_func op_9158_0_comp_nf;
+extern compop_func op_9160_0_comp_nf;
+extern compop_func op_9168_0_comp_nf;
+extern compop_func op_9170_0_comp_nf;
+extern compop_func op_9178_0_comp_nf;
+extern compop_func op_9179_0_comp_nf;
+extern compop_func op_9180_0_comp_nf;
+extern compop_func op_9188_0_comp_nf;
+extern compop_func op_9190_0_comp_nf;
+extern compop_func op_9198_0_comp_nf;
+extern compop_func op_91a0_0_comp_nf;
+extern compop_func op_91a8_0_comp_nf;
+extern compop_func op_91b0_0_comp_nf;
+extern compop_func op_91b8_0_comp_nf;
+extern compop_func op_91b9_0_comp_nf;
+extern compop_func op_91c0_0_comp_nf;
+extern compop_func op_91c8_0_comp_nf;
+extern compop_func op_91d0_0_comp_nf;
+extern compop_func op_91d8_0_comp_nf;
+extern compop_func op_91e0_0_comp_nf;
+extern compop_func op_91e8_0_comp_nf;
+extern compop_func op_91f0_0_comp_nf;
+extern compop_func op_91f8_0_comp_nf;
+extern compop_func op_91f9_0_comp_nf;
+extern compop_func op_91fa_0_comp_nf;
+extern compop_func op_91fb_0_comp_nf;
+extern compop_func op_91fc_0_comp_nf;
+extern compop_func op_b000_0_comp_nf;
+extern compop_func op_b010_0_comp_nf;
+extern compop_func op_b018_0_comp_nf;
+extern compop_func op_b020_0_comp_nf;
+extern compop_func op_b028_0_comp_nf;
+extern compop_func op_b030_0_comp_nf;
+extern compop_func op_b038_0_comp_nf;
+extern compop_func op_b039_0_comp_nf;
+extern compop_func op_b03a_0_comp_nf;
+extern compop_func op_b03b_0_comp_nf;
+extern compop_func op_b03c_0_comp_nf;
+extern compop_func op_b040_0_comp_nf;
+extern compop_func op_b048_0_comp_nf;
+extern compop_func op_b050_0_comp_nf;
+extern compop_func op_b058_0_comp_nf;
+extern compop_func op_b060_0_comp_nf;
+extern compop_func op_b068_0_comp_nf;
+extern compop_func op_b070_0_comp_nf;
+extern compop_func op_b078_0_comp_nf;
+extern compop_func op_b079_0_comp_nf;
+extern compop_func op_b07a_0_comp_nf;
+extern compop_func op_b07b_0_comp_nf;
+extern compop_func op_b07c_0_comp_nf;
+extern compop_func op_b080_0_comp_nf;
+extern compop_func op_b088_0_comp_nf;
+extern compop_func op_b090_0_comp_nf;
+extern compop_func op_b098_0_comp_nf;
+extern compop_func op_b0a0_0_comp_nf;
+extern compop_func op_b0a8_0_comp_nf;
+extern compop_func op_b0b0_0_comp_nf;
+extern compop_func op_b0b8_0_comp_nf;
+extern compop_func op_b0b9_0_comp_nf;
+extern compop_func op_b0ba_0_comp_nf;
+extern compop_func op_b0bb_0_comp_nf;
+extern compop_func op_b0bc_0_comp_nf;
+extern compop_func op_b0c0_0_comp_nf;
+extern compop_func op_b0c8_0_comp_nf;
+extern compop_func op_b0d0_0_comp_nf;
+extern compop_func op_b0d8_0_comp_nf;
+extern compop_func op_b0e0_0_comp_nf;
+extern compop_func op_b0e8_0_comp_nf;
+extern compop_func op_b0f0_0_comp_nf;
+extern compop_func op_b0f8_0_comp_nf;
+extern compop_func op_b0f9_0_comp_nf;
+extern compop_func op_b0fa_0_comp_nf;
+extern compop_func op_b0fb_0_comp_nf;
+extern compop_func op_b0fc_0_comp_nf;
+extern compop_func op_b100_0_comp_nf;
+extern compop_func op_b108_0_comp_nf;
+extern compop_func op_b110_0_comp_nf;
+extern compop_func op_b118_0_comp_nf;
+extern compop_func op_b120_0_comp_nf;
+extern compop_func op_b128_0_comp_nf;
+extern compop_func op_b130_0_comp_nf;
+extern compop_func op_b138_0_comp_nf;
+extern compop_func op_b139_0_comp_nf;
+extern compop_func op_b140_0_comp_nf;
+extern compop_func op_b148_0_comp_nf;
+extern compop_func op_b150_0_comp_nf;
+extern compop_func op_b158_0_comp_nf;
+extern compop_func op_b160_0_comp_nf;
+extern compop_func op_b168_0_comp_nf;
+extern compop_func op_b170_0_comp_nf;
+extern compop_func op_b178_0_comp_nf;
+extern compop_func op_b179_0_comp_nf;
+extern compop_func op_b180_0_comp_nf;
+extern compop_func op_b188_0_comp_nf;
+extern compop_func op_b190_0_comp_nf;
+extern compop_func op_b198_0_comp_nf;
+extern compop_func op_b1a0_0_comp_nf;
+extern compop_func op_b1a8_0_comp_nf;
+extern compop_func op_b1b0_0_comp_nf;
+extern compop_func op_b1b8_0_comp_nf;
+extern compop_func op_b1b9_0_comp_nf;
+extern compop_func op_b1c0_0_comp_nf;
+extern compop_func op_b1c8_0_comp_nf;
+extern compop_func op_b1d0_0_comp_nf;
+extern compop_func op_b1d8_0_comp_nf;
+extern compop_func op_b1e0_0_comp_nf;
+extern compop_func op_b1e8_0_comp_nf;
+extern compop_func op_b1f0_0_comp_nf;
+extern compop_func op_b1f8_0_comp_nf;
+extern compop_func op_b1f9_0_comp_nf;
+extern compop_func op_b1fa_0_comp_nf;
+extern compop_func op_b1fb_0_comp_nf;
+extern compop_func op_b1fc_0_comp_nf;
+extern compop_func op_c000_0_comp_nf;
+extern compop_func op_c010_0_comp_nf;
+extern compop_func op_c018_0_comp_nf;
+extern compop_func op_c020_0_comp_nf;
+extern compop_func op_c028_0_comp_nf;
+extern compop_func op_c030_0_comp_nf;
+extern compop_func op_c038_0_comp_nf;
+extern compop_func op_c039_0_comp_nf;
+extern compop_func op_c03a_0_comp_nf;
+extern compop_func op_c03b_0_comp_nf;
+extern compop_func op_c03c_0_comp_nf;
+extern compop_func op_c040_0_comp_nf;
+extern compop_func op_c050_0_comp_nf;
+extern compop_func op_c058_0_comp_nf;
+extern compop_func op_c060_0_comp_nf;
+extern compop_func op_c068_0_comp_nf;
+extern compop_func op_c070_0_comp_nf;
+extern compop_func op_c078_0_comp_nf;
+extern compop_func op_c079_0_comp_nf;
+extern compop_func op_c07a_0_comp_nf;
+extern compop_func op_c07b_0_comp_nf;
+extern compop_func op_c07c_0_comp_nf;
+extern compop_func op_c080_0_comp_nf;
+extern compop_func op_c090_0_comp_nf;
+extern compop_func op_c098_0_comp_nf;
+extern compop_func op_c0a0_0_comp_nf;
+extern compop_func op_c0a8_0_comp_nf;
+extern compop_func op_c0b0_0_comp_nf;
+extern compop_func op_c0b8_0_comp_nf;
+extern compop_func op_c0b9_0_comp_nf;
+extern compop_func op_c0ba_0_comp_nf;
+extern compop_func op_c0bb_0_comp_nf;
+extern compop_func op_c0bc_0_comp_nf;
+extern compop_func op_c0c0_0_comp_nf;
+extern compop_func op_c0d0_0_comp_nf;
+extern compop_func op_c0d8_0_comp_nf;
+extern compop_func op_c0e0_0_comp_nf;
+extern compop_func op_c0e8_0_comp_nf;
+extern compop_func op_c0f0_0_comp_nf;
+extern compop_func op_c0f8_0_comp_nf;
+extern compop_func op_c0f9_0_comp_nf;
+extern compop_func op_c0fa_0_comp_nf;
+extern compop_func op_c0fb_0_comp_nf;
+extern compop_func op_c0fc_0_comp_nf;
+extern compop_func op_c110_0_comp_nf;
+extern compop_func op_c118_0_comp_nf;
+extern compop_func op_c120_0_comp_nf;
+extern compop_func op_c128_0_comp_nf;
+extern compop_func op_c130_0_comp_nf;
+extern compop_func op_c138_0_comp_nf;
+extern compop_func op_c139_0_comp_nf;
+extern compop_func op_c140_0_comp_nf;
+extern compop_func op_c148_0_comp_nf;
+extern compop_func op_c150_0_comp_nf;
+extern compop_func op_c158_0_comp_nf;
+extern compop_func op_c160_0_comp_nf;
+extern compop_func op_c168_0_comp_nf;
+extern compop_func op_c170_0_comp_nf;
+extern compop_func op_c178_0_comp_nf;
+extern compop_func op_c179_0_comp_nf;
+extern compop_func op_c188_0_comp_nf;
+extern compop_func op_c190_0_comp_nf;
+extern compop_func op_c198_0_comp_nf;
+extern compop_func op_c1a0_0_comp_nf;
+extern compop_func op_c1a8_0_comp_nf;
+extern compop_func op_c1b0_0_comp_nf;
+extern compop_func op_c1b8_0_comp_nf;
+extern compop_func op_c1b9_0_comp_nf;
+extern compop_func op_c1c0_0_comp_nf;
+extern compop_func op_c1d0_0_comp_nf;
+extern compop_func op_c1d8_0_comp_nf;
+extern compop_func op_c1e0_0_comp_nf;
+extern compop_func op_c1e8_0_comp_nf;
+extern compop_func op_c1f0_0_comp_nf;
+extern compop_func op_c1f8_0_comp_nf;
+extern compop_func op_c1f9_0_comp_nf;
+extern compop_func op_c1fa_0_comp_nf;
+extern compop_func op_c1fb_0_comp_nf;
+extern compop_func op_c1fc_0_comp_nf;
+extern compop_func op_d000_0_comp_nf;
+extern compop_func op_d010_0_comp_nf;
+extern compop_func op_d018_0_comp_nf;
+extern compop_func op_d020_0_comp_nf;
+extern compop_func op_d028_0_comp_nf;
+extern compop_func op_d030_0_comp_nf;
+extern compop_func op_d038_0_comp_nf;
+extern compop_func op_d039_0_comp_nf;
+extern compop_func op_d03a_0_comp_nf;
+extern compop_func op_d03b_0_comp_nf;
+extern compop_func op_d03c_0_comp_nf;
+extern compop_func op_d040_0_comp_nf;
+extern compop_func op_d048_0_comp_nf;
+extern compop_func op_d050_0_comp_nf;
+extern compop_func op_d058_0_comp_nf;
+extern compop_func op_d060_0_comp_nf;
+extern compop_func op_d068_0_comp_nf;
+extern compop_func op_d070_0_comp_nf;
+extern compop_func op_d078_0_comp_nf;
+extern compop_func op_d079_0_comp_nf;
+extern compop_func op_d07a_0_comp_nf;
+extern compop_func op_d07b_0_comp_nf;
+extern compop_func op_d07c_0_comp_nf;
+extern compop_func op_d080_0_comp_nf;
+extern compop_func op_d088_0_comp_nf;
+extern compop_func op_d090_0_comp_nf;
+extern compop_func op_d098_0_comp_nf;
+extern compop_func op_d0a0_0_comp_nf;
+extern compop_func op_d0a8_0_comp_nf;
+extern compop_func op_d0b0_0_comp_nf;
+extern compop_func op_d0b8_0_comp_nf;
+extern compop_func op_d0b9_0_comp_nf;
+extern compop_func op_d0ba_0_comp_nf;
+extern compop_func op_d0bb_0_comp_nf;
+extern compop_func op_d0bc_0_comp_nf;
+extern compop_func op_d0c0_0_comp_nf;
+extern compop_func op_d0c8_0_comp_nf;
+extern compop_func op_d0d0_0_comp_nf;
+extern compop_func op_d0d8_0_comp_nf;
+extern compop_func op_d0e0_0_comp_nf;
+extern compop_func op_d0e8_0_comp_nf;
+extern compop_func op_d0f0_0_comp_nf;
+extern compop_func op_d0f8_0_comp_nf;
+extern compop_func op_d0f9_0_comp_nf;
+extern compop_func op_d0fa_0_comp_nf;
+extern compop_func op_d0fb_0_comp_nf;
+extern compop_func op_d0fc_0_comp_nf;
+extern compop_func op_d100_0_comp_nf;
+extern compop_func op_d108_0_comp_nf;
+extern compop_func op_d110_0_comp_nf;
+extern compop_func op_d118_0_comp_nf;
+extern compop_func op_d120_0_comp_nf;
+extern compop_func op_d128_0_comp_nf;
+extern compop_func op_d130_0_comp_nf;
+extern compop_func op_d138_0_comp_nf;
+extern compop_func op_d139_0_comp_nf;
+extern compop_func op_d140_0_comp_nf;
+extern compop_func op_d148_0_comp_nf;
+extern compop_func op_d150_0_comp_nf;
+extern compop_func op_d158_0_comp_nf;
+extern compop_func op_d160_0_comp_nf;
+extern compop_func op_d168_0_comp_nf;
+extern compop_func op_d170_0_comp_nf;
+extern compop_func op_d178_0_comp_nf;
+extern compop_func op_d179_0_comp_nf;
+extern compop_func op_d180_0_comp_nf;
+extern compop_func op_d188_0_comp_nf;
+extern compop_func op_d190_0_comp_nf;
+extern compop_func op_d198_0_comp_nf;
+extern compop_func op_d1a0_0_comp_nf;
+extern compop_func op_d1a8_0_comp_nf;
+extern compop_func op_d1b0_0_comp_nf;
+extern compop_func op_d1b8_0_comp_nf;
+extern compop_func op_d1b9_0_comp_nf;
+extern compop_func op_d1c0_0_comp_nf;
+extern compop_func op_d1c8_0_comp_nf;
+extern compop_func op_d1d0_0_comp_nf;
+extern compop_func op_d1d8_0_comp_nf;
+extern compop_func op_d1e0_0_comp_nf;
+extern compop_func op_d1e8_0_comp_nf;
+extern compop_func op_d1f0_0_comp_nf;
+extern compop_func op_d1f8_0_comp_nf;
+extern compop_func op_d1f9_0_comp_nf;
+extern compop_func op_d1fa_0_comp_nf;
+extern compop_func op_d1fb_0_comp_nf;
+extern compop_func op_d1fc_0_comp_nf;
+extern compop_func op_e000_0_comp_nf;
+extern compop_func op_e008_0_comp_nf;
+extern compop_func op_e010_0_comp_nf;
+extern compop_func op_e018_0_comp_nf;
+extern compop_func op_e020_0_comp_nf;
+extern compop_func op_e028_0_comp_nf;
+extern compop_func op_e030_0_comp_nf;
+extern compop_func op_e038_0_comp_nf;
+extern compop_func op_e040_0_comp_nf;
+extern compop_func op_e048_0_comp_nf;
+extern compop_func op_e050_0_comp_nf;
+extern compop_func op_e058_0_comp_nf;
+extern compop_func op_e060_0_comp_nf;
+extern compop_func op_e068_0_comp_nf;
+extern compop_func op_e070_0_comp_nf;
+extern compop_func op_e078_0_comp_nf;
+extern compop_func op_e080_0_comp_nf;
+extern compop_func op_e088_0_comp_nf;
+extern compop_func op_e090_0_comp_nf;
+extern compop_func op_e098_0_comp_nf;
+extern compop_func op_e0a0_0_comp_nf;
+extern compop_func op_e0a8_0_comp_nf;
+extern compop_func op_e0b0_0_comp_nf;
+extern compop_func op_e0b8_0_comp_nf;
+extern compop_func op_e0d0_0_comp_nf;
+extern compop_func op_e0d8_0_comp_nf;
+extern compop_func op_e0e0_0_comp_nf;
+extern compop_func op_e0e8_0_comp_nf;
+extern compop_func op_e0f0_0_comp_nf;
+extern compop_func op_e0f8_0_comp_nf;
+extern compop_func op_e0f9_0_comp_nf;
+extern compop_func op_e100_0_comp_nf;
+extern compop_func op_e108_0_comp_nf;
+extern compop_func op_e110_0_comp_nf;
+extern compop_func op_e118_0_comp_nf;
+extern compop_func op_e120_0_comp_nf;
+extern compop_func op_e128_0_comp_nf;
+extern compop_func op_e130_0_comp_nf;
+extern compop_func op_e138_0_comp_nf;
+extern compop_func op_e140_0_comp_nf;
+extern compop_func op_e148_0_comp_nf;
+extern compop_func op_e150_0_comp_nf;
+extern compop_func op_e158_0_comp_nf;
+extern compop_func op_e160_0_comp_nf;
+extern compop_func op_e168_0_comp_nf;
+extern compop_func op_e170_0_comp_nf;
+extern compop_func op_e178_0_comp_nf;
+extern compop_func op_e180_0_comp_nf;
+extern compop_func op_e188_0_comp_nf;
+extern compop_func op_e190_0_comp_nf;
+extern compop_func op_e198_0_comp_nf;
+extern compop_func op_e1a0_0_comp_nf;
+extern compop_func op_e1a8_0_comp_nf;
+extern compop_func op_e1b0_0_comp_nf;
+extern compop_func op_e1b8_0_comp_nf;
+extern compop_func op_e1d0_0_comp_nf;
+extern compop_func op_e1d8_0_comp_nf;
+extern compop_func op_e1e0_0_comp_nf;
+extern compop_func op_e1e8_0_comp_nf;
+extern compop_func op_e1f0_0_comp_nf;
+extern compop_func op_e1f8_0_comp_nf;
+extern compop_func op_e1f9_0_comp_nf;
+extern compop_func op_e2d0_0_comp_nf;
+extern compop_func op_e2d8_0_comp_nf;
+extern compop_func op_e2e0_0_comp_nf;
+extern compop_func op_e2e8_0_comp_nf;
+extern compop_func op_e2f0_0_comp_nf;
+extern compop_func op_e2f8_0_comp_nf;
+extern compop_func op_e2f9_0_comp_nf;
+extern compop_func op_e3d0_0_comp_nf;
+extern compop_func op_e3d8_0_comp_nf;
+extern compop_func op_e3e0_0_comp_nf;
+extern compop_func op_e3e8_0_comp_nf;
+extern compop_func op_e3f0_0_comp_nf;
+extern compop_func op_e3f8_0_comp_nf;
+extern compop_func op_e3f9_0_comp_nf;
+extern compop_func op_e6d0_0_comp_nf;
+extern compop_func op_e6d8_0_comp_nf;
+extern compop_func op_e6e0_0_comp_nf;
+extern compop_func op_e6e8_0_comp_nf;
+extern compop_func op_e6f0_0_comp_nf;
+extern compop_func op_e6f8_0_comp_nf;
+extern compop_func op_e6f9_0_comp_nf;
+extern compop_func op_e7d0_0_comp_nf;
+extern compop_func op_e7d8_0_comp_nf;
+extern compop_func op_e7e0_0_comp_nf;
+extern compop_func op_e7e8_0_comp_nf;
+extern compop_func op_e7f0_0_comp_nf;
+extern compop_func op_e7f8_0_comp_nf;
+extern compop_func op_e7f9_0_comp_nf;
+extern compop_func op_efc0_0_comp_nf;
+extern compop_func op_efd0_0_comp_nf;
+extern compop_func op_efe8_0_comp_nf;
+extern compop_func op_eff0_0_comp_nf;
+extern compop_func op_eff8_0_comp_nf;
+extern compop_func op_eff9_0_comp_nf;
+extern compop_func op_f200_0_comp_nf;
+extern compop_func op_f208_0_comp_nf;
+extern compop_func op_f210_0_comp_nf;
+extern compop_func op_f218_0_comp_nf;
+extern compop_func op_f220_0_comp_nf;
+extern compop_func op_f228_0_comp_nf;
+extern compop_func op_f230_0_comp_nf;
+extern compop_func op_f238_0_comp_nf;
+extern compop_func op_f239_0_comp_nf;
+extern compop_func op_f23a_0_comp_nf;
+extern compop_func op_f23b_0_comp_nf;
+extern compop_func op_f23c_0_comp_nf;
+extern compop_func op_f240_0_comp_nf;
+extern compop_func op_f250_0_comp_nf;
+extern compop_func op_f258_0_comp_nf;
+extern compop_func op_f260_0_comp_nf;
+extern compop_func op_f268_0_comp_nf;
+extern compop_func op_f270_0_comp_nf;
+extern compop_func op_f278_0_comp_nf;
+extern compop_func op_f279_0_comp_nf;
+extern compop_func op_f280_0_comp_nf;
+extern compop_func op_f2c0_0_comp_nf;
+extern compop_func op_f600_0_comp_nf;
+extern compop_func op_f608_0_comp_nf;
+extern compop_func op_f610_0_comp_nf;
+extern compop_func op_f618_0_comp_nf;
+extern compop_func op_f620_0_comp_nf;
diff --git a/jit/arm/flags_arm.h b/jit/arm/flags_arm.h
new file mode 100644
index 00000000..ce7686ca
--- /dev/null
+++ b/jit/arm/flags_arm.h
@@ -0,0 +1,68 @@
+/*
+ *  compiler/flags_arm.h - Native flags definitions for ARM
+ *
+ * Copyright (c) 2013 Jens Heitmann of ARAnyM dev team (see AUTHORS)
+ *
+ * Inspired by Christian Bauer's Basilisk II
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2002 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef NATIVE_FLAGS_ARM_H
+#define NATIVE_FLAGS_ARM_H
+
+/* Native integer code conditions */
+enum
+{
+	NATIVE_CC_EQ = 0,
+	NATIVE_CC_NE = 1,
+	NATIVE_CC_CS = 2,
+	NATIVE_CC_CC = 3,
+	NATIVE_CC_MI = 4,
+	NATIVE_CC_PL = 5,
+	NATIVE_CC_VS = 6,
+	NATIVE_CC_VC = 7,
+	NATIVE_CC_HI = 8,
+	NATIVE_CC_LS = 9,
+	NATIVE_CC_GE = 10,
+	NATIVE_CC_LT = 11,
+	NATIVE_CC_GT = 12,
+	NATIVE_CC_LE = 13,
+	NATIVE_CC_AL = 14,
+
+	// For FBcc, we need some pseudo condition codes
+	NATIVE_CC_F_OGT = 16 + 2,
+	NATIVE_CC_F_OGE = 16 + 3,
+	NATIVE_CC_F_OLT = 16 + 4,
+	NATIVE_CC_F_OLE = 16 + 5,
+	NATIVE_CC_F_OGL = 16 + 6,
+	NATIVE_CC_F_OR = 16 + 7,
+	NATIVE_CC_F_UN = 16 + 8,
+	NATIVE_CC_F_UEQ = 16 + 9,
+	NATIVE_CC_F_UGT = 16 + 10,
+	NATIVE_CC_F_UGE = 16 + 11,
+	NATIVE_CC_F_ULT = 16 + 12,
+	NATIVE_CC_F_ULE = 16 + 13,
+	NATIVE_CC_F_NEVER = 32
+};
+
+#endif /* NATIVE_FLAGS_ARM_H */
diff --git a/jit/arm/gencomp_arm.c b/jit/arm/gencomp_arm.c
new file mode 100644
index 00000000..63d60fc1
--- /dev/null
+++ b/jit/arm/gencomp_arm.c
@@ -0,0 +1,5111 @@
+/*
+ *  compiler/gencomp_arm2.c - MC680x0 compilation generator (ARM Adaption JIT v1 & JIT v2)
+ *
+ *  Based on work Copyright 1995, 1996 Bernd Schmidt
+ *  Changes for UAE-JIT Copyright 2000 Bernd Meyer
+ *
+ *  Adaptation for ARAnyM/ARM, copyright 2001-2015
+ *    Milan Jurik, Jens Heitmann
+ *
+ *  Basilisk II (C) 1997-2005 Christian Bauer
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Notes
+ *  =====
+ *
+ *  Advantages of JIT v2
+ *  	- Processor independent style
+ *  	- Reduced overhead
+ *  	- Easier to understand / read
+ *  	- Easier to optimize
+ *  	- More precise flag handling
+ *  	- Better optimization for different CPU version ARM, ARMv6 etc..
+ *
+ *  Disadvantages of JIT v2
+ *  	- Less generated
+ *  	- Requires more code implementation by hand (MidFunc)
+ *  	- MIDFUNCS are more CPU minded (closer to raw)
+ *  	- Separate code for each instruction (but this could be also an advantage, because you can concentrate on it)
+ *
+ * Additional note:
+ *  	- current using jnf_xxx calls for non-flag operations and
+ *  	  jff_xxx for flag operations
+ *
+ * Still todo:
+ * 		- Optimize genamode, genastore, gen_writeXXX, gen_readXXX, genmovemXXX
+ *
+ */
+
+#define CC_FOR_BUILD 1
+#include "sysconfig.h"
+
+#include "sysdeps.h"
+#include "readcpu.h"
+
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <ctype.h>
+#undef abort
+
+#define BOOL_TYPE		"int"
+#define failure			global_failure=1
+#define FAILURE			global_failure=1
+#define isjump			global_isjump=1
+#define is_const_jump	global_iscjump=1
+#define isaddx			global_isaddx=1
+#define uses_cmov		global_cmov=1
+#define mayfail			global_mayfail=1
+#define uses_fpu		global_fpu=1
+
+int hack_opcode;
+
+static int global_failure;
+static int global_isjump;
+static int global_iscjump;
+static int global_isaddx;
+static int global_cmov;
+static int long_opcode;
+static int global_mayfail;
+static int global_fpu;
+
+static char endstr[1000];
+static char lines[100000];
+static int comp_index = 0;
+
+#include "flags_arm.h"
+
+#ifndef __attribute__
+#  ifndef __GNUC__
+#    define __attribute__(x)
+#  endif
+#endif
+
+
+static int cond_codes[] = { //
+		NATIVE_CC_AL, -1, //
+				NATIVE_CC_HI, NATIVE_CC_LS, //
+				NATIVE_CC_CC, NATIVE_CC_CS, //
+				NATIVE_CC_NE, NATIVE_CC_EQ, //
+				NATIVE_CC_VC, NATIVE_CC_VS, //
+				NATIVE_CC_PL, NATIVE_CC_MI, //
+				NATIVE_CC_GE, NATIVE_CC_LT, //
+				NATIVE_CC_GT, NATIVE_CC_LE //
+		};
+
+__attribute__((format(printf, 1, 2)))
+static void comprintf(const char *format, ...)
+{
+	va_list args;
+
+	va_start(args, format);
+	comp_index += vsprintf(lines + comp_index, format, args);
+	va_end(args);
+}
+
+static void com_discard(void)
+{
+	comp_index = 0;
+}
+
+static void com_flush(void)
+{
+	int i;
+	for (i = 0; i < comp_index; i++)
+		putchar(lines[i]);
+	com_discard();
+}
+
+
+static FILE *headerfile;
+static FILE *stblfile;
+
+static int using_prefetch;
+static int using_exception_3;
+static int cpu_level;
+static int noflags;
+
+/* For the current opcode, the next lower level that will have different code.
+ * Initialized to -1 for each opcode. If it remains unchanged, indicates we
+ * are done with that opcode.  */
+static int next_cpu_level;
+
+static int *opcode_map;
+static int *opcode_next_clev;
+static int *opcode_last_postfix;
+static unsigned long *counts;
+
+static void read_counts(void)
+{
+	FILE *file;
+	unsigned long opcode, count, total;
+	char name[20];
+	int nr = 0;
+	memset(counts, 0, 65536 * sizeof *counts);
+
+	file = fopen("frequent.68k", "r");
+	if (file) {
+		if (fscanf(file, "Total: %lu\n", &total) != 1)
+		{
+			assert(0);
+		}
+		while (fscanf(file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
+			opcode_next_clev[nr] = 4;
+			opcode_last_postfix[nr] = -1;
+			opcode_map[nr++] = opcode;
+			counts[opcode] = count;
+		}
+		fclose(file);
+	}
+	if (nr == nr_cpuop_funcs)
+		return;
+	for (opcode = 0; opcode < 0x10000; opcode++) {
+		if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
+				&& counts[opcode] == 0) {
+			opcode_next_clev[nr] = 4;
+			opcode_last_postfix[nr] = -1;
+			opcode_map[nr++] = opcode;
+			counts[opcode] = count;
+		}
+	}
+    assert (nr == nr_cpuop_funcs);
+}
+
+static int n_braces = 0;
+static int insn_n_cycles;
+
+static void start_brace(void) {
+	n_braces++;
+	comprintf("{");
+}
+
+static void close_brace(void) {
+	assert(n_braces > 0);
+	n_braces--;
+	comprintf("}");
+}
+
+static void finish_braces(void) {
+	while (n_braces > 0)
+		close_brace();
+}
+
+static inline void gen_update_next_handler(void) {
+	return; /* Can anything clever be done here? */
+}
+
+static void gen_writebyte(const char *address, const char *source)
+{
+	comprintf("\twritebyte(%s, %s, scratchie);\n", address, source);
+}
+
+static void gen_writeword(const char *address, const char *source)
+{
+	comprintf("\twriteword(%s, %s, scratchie);\n", address, source);
+}
+
+static void gen_writelong(const char *address, const char *source)
+{
+	comprintf("\twritelong(%s, %s, scratchie);\n", address, source);
+}
+
+static void gen_readbyte(const char *address, const char* dest)
+{
+	comprintf("\treadbyte(%s, %s, scratchie);\n", address, dest);
+}
+
+static void gen_readword(const char *address, const char *dest)
+{
+	comprintf("\treadword(%s,%s,scratchie);\n", address, dest);
+}
+
+static void gen_readlong(const char *address, const char *dest)
+{
+	comprintf("\treadlong(%s, %s, scratchie);\n", address, dest);
+}
+
+static const char *
+gen_nextilong(void) {
+	static char buffer[80];
+
+	sprintf(buffer, "comp_get_ilong((m68k_pc_offset+=4)-4)");
+	insn_n_cycles += 4;
+
+	long_opcode = 1;
+	return buffer;
+}
+
+static const char *
+gen_nextiword(void) {
+	static char buffer[80];
+
+	sprintf(buffer, "comp_get_iword((m68k_pc_offset+=2)-2)");
+	insn_n_cycles += 2;
+
+	long_opcode = 1;
+	return buffer;
+}
+
+static const char *
+gen_nextibyte(void) {
+	static char buffer[80];
+
+	sprintf(buffer, "comp_get_ibyte((m68k_pc_offset+=2)-2)");
+	insn_n_cycles += 2;
+
+	long_opcode = 1;
+	return buffer;
+}
+
+#if defined(USE_JIT_FPU)
+// Only used by FPU (future), get rid of unused warning
+static void
+swap_opcode (void)
+{
+	comprintf("#if defined(HAVE_GET_WORD_UNSWAPPED) && !defined(FULLMMU)\n");
+	comprintf("\topcode = do_byteswap_16(opcode);\n");
+	comprintf("#endif\n");
+}
+#endif
+
+static void sync_m68k_pc(void) {
+	comprintf("\t if (m68k_pc_offset>SYNC_PC_OFFSET) sync_m68k_pc();\n");
+}
+
+/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
+ * the calling routine handles Apdi and Aipi modes.
+ * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
+static void genamode(amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem)
+{
+	start_brace();
+	switch (mode)
+	{
+	case Dreg: /* Do we need to check dodgy here? */
+		assert (!movem);
+		if (getv == 1 || getv == 2)
+		{
+			/* We generate the variable even for getv==2, so we can use
+			 it as a destination for MOVE */
+			comprintf("\tint %s = %s;\n", name, reg);
+		}
+		return;
+
+	case Areg:
+		assert (!movem);
+		if (getv == 1 || getv == 2)
+		{
+			/* see above */
+			comprintf("\tint %s = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+			if (getv == 1)
+			{
+				comprintf("\tif (dodgy) \n");
+				comprintf("\t\tmov_l_rr(%s, %s + 8);\n", name, reg);
+			}
+		}
+		return;
+
+	case Aind:
+		comprintf("\tint %sa = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+		comprintf("\tif (dodgy)\n");
+		comprintf("\t\tmov_l_rr(%sa, %s + 8);\n", name, reg);
+		break;
+	case Aipi:
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tmov_l_rr(%sa, %s + 8);\n", name, reg);
+		break;
+	case Apdi:
+		switch (size)
+		{
+		case sz_byte:
+			if (movem)
+			{
+				comprintf("\tint %sa = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+				comprintf("\tif (dodgy)\n");
+				comprintf("\t\tmov_l_rr(%sa, 8 + %s);\n", name, reg);
+			} else
+			{
+				start_brace();
+				comprintf("\tint %sa = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+				comprintf("\tlea_l_brr(%s + 8, %s + 8, (uae_s32)-areg_byteinc[%s]);\n", reg, reg, reg);
+				comprintf("\tif (dodgy)\n");
+				comprintf("\t\tmov_l_rr(%sa, 8 + %s);\n", name, reg);
+			}
+			break;
+		case sz_word:
+			if (movem)
+			{
+				comprintf("\tint %sa=dodgy?scratchie++:%s+8;\n", name, reg);
+				comprintf("\tif (dodgy) \n");
+				comprintf("\tmov_l_rr(%sa,8+%s);\n", name, reg);
+			} else
+			{
+				start_brace();
+				comprintf("\tint %sa = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+				comprintf("\tlea_l_brr(%s + 8, %s + 8, -2);\n", reg, reg);
+				comprintf("\tif (dodgy)\n");
+				comprintf("\t\tmov_l_rr(%sa, 8 + %s);\n", name, reg);
+			}
+			break;
+		case sz_long:
+			if (movem)
+			{
+				comprintf("\tint %sa = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+				comprintf("\tif (dodgy)\n");
+				comprintf("\t\tmov_l_rr(%sa, 8 + %s);\n", name, reg);
+			} else
+			{
+				start_brace();
+				comprintf("\tint %sa = dodgy ? scratchie++ : %s + 8;\n", name, reg);
+				comprintf("\tlea_l_brr(%s + 8, %s + 8, -4);\n", reg, reg);
+				comprintf("\tif (dodgy)\n");
+				comprintf("\t\tmov_l_rr(%sa, 8 + %s);\n", name, reg);
+			}
+			break;
+		default:
+			assert(0);
+			break;
+		}
+		break;
+	case Ad16:
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tmov_l_rr(%sa, 8 + %s);\n", name, reg);
+		comprintf("\tlea_l_brr(%sa, %sa, (uae_s32)(uae_s16)%s);\n", name, name, gen_nextiword());
+		break;
+	case Ad8r:
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tcalc_disp_ea_020(%s + 8, %s, %sa, scratchie);\n", reg, gen_nextiword(), name);
+		break;
+
+	case PC16:
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tuae_u32 address = start_pc + ((char *)comp_pc_p - (char *)start_pc_p) + m68k_pc_offset;\n");
+		comprintf("\tuae_s32 PC16off = (uae_s32)(uae_s16)%s;\n", gen_nextiword());
+		comprintf("\tmov_l_ri(%sa, address + PC16off);\n", name);
+		break;
+
+	case PC8r:
+		comprintf("\tint pctmp = scratchie++;\n");
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tuae_u32 address = start_pc + ((char *)comp_pc_p - (char *)start_pc_p) + m68k_pc_offset;\n");
+		start_brace();
+		comprintf("\tmov_l_ri(pctmp,address);\n");
+
+		comprintf("\tcalc_disp_ea_020(pctmp, %s, %sa, scratchie);\n", gen_nextiword(), name);
+		break;
+	case absw:
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tmov_l_ri(%sa, (uae_s32)(uae_s16)%s);\n", name, gen_nextiword());
+		break;
+	case absl:
+		comprintf("\tint %sa = scratchie++;\n", name);
+		comprintf("\tmov_l_ri(%sa, %s); /* absl */\n", name, gen_nextilong());
+		break;
+	case imm:
+		assert (getv == 1);
+		switch (size)
+		{
+		case sz_byte:
+			comprintf("\tint %s = scratchie++;\n", name);
+			comprintf("\tmov_l_ri(%s, (uae_s32)(uae_s8)%s);\n", name, gen_nextibyte());
+			break;
+		case sz_word:
+			comprintf("\tint %s = scratchie++;\n", name);
+			comprintf("\tmov_l_ri(%s, (uae_s32)(uae_s16)%s);\n", name, gen_nextiword());
+			break;
+		case sz_long:
+			comprintf("\tint %s = scratchie++;\n", name);
+			comprintf("\tmov_l_ri(%s, %s);\n", name, gen_nextilong());
+			break;
+		default:
+			assert(0);
+			break;
+		}
+		return;
+	case imm0:
+		assert (getv == 1);
+		comprintf("\tint %s = scratchie++;\n", name);
+		comprintf("\tmov_l_ri(%s, (uae_s32)(uae_s8)%s);\n", name, gen_nextibyte());
+		return;
+	case imm1:
+		assert (getv == 1);
+		comprintf("\tint %s = scratchie++;\n", name);
+		comprintf("\tmov_l_ri(%s, (uae_s32)(uae_s16)%s);\n", name, gen_nextiword());
+		return;
+	case imm2:
+		assert (getv == 1);
+		comprintf("\tint %s = scratchie++;\n", name);
+		comprintf("\tmov_l_ri(%s, %s);\n", name, gen_nextilong());
+		return;
+	case immi:
+		assert (getv == 1);
+		comprintf("\tint %s = scratchie++;\n", name);
+		comprintf("\tmov_l_ri(%s, %s);\n", name, reg);
+		return;
+	default:
+		assert(0);
+		break;
+	}
+
+	/* We get here for all non-reg non-immediate addressing modes to
+	 * actually fetch the value. */
+	if (getv == 1)
+	{
+		char astring[80];
+		sprintf(astring, "%sa", name);
+		switch (size)
+		{
+		case sz_byte:
+			insn_n_cycles += 2;
+			break;
+		case sz_word:
+			insn_n_cycles += 2;
+			break;
+		case sz_long:
+			insn_n_cycles += 4;
+			break;
+		default:
+			assert(0);
+			break;
+		}
+		start_brace();
+		comprintf("\tint %s = scratchie++;\n", name);
+		switch (size)
+		{
+		case sz_byte:
+			gen_readbyte(astring, name);
+			break;
+		case sz_word:
+			gen_readword(astring, name);
+			break;
+		case sz_long:
+			gen_readlong(astring, name);
+			break;
+		default:
+			assert(0);
+			break;
+		}
+	}
+
+	/* We now might have to fix up the register for pre-dec or post-inc
+	 * addressing modes. */
+	if (!movem)
+	{
+		switch (mode)
+		{
+		case Aipi:
+			switch (size)
+			{
+			case sz_byte:
+				comprintf("\tlea_l_brr(%s + 8,%s + 8, areg_byteinc[%s]);\n", reg, reg, reg);
+				break;
+			case sz_word:
+				comprintf("\tlea_l_brr(%s + 8, %s + 8, 2);\n", reg, reg);
+				break;
+			case sz_long:
+				comprintf("\tlea_l_brr(%s + 8, %s + 8, 4);\n", reg, reg);
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			break;
+		case Apdi:
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+static void genastore(const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
+{
+	switch (mode)
+	{
+	case Dreg:
+		switch (size)
+		{
+		case sz_byte:
+			comprintf("\tif(%s != %s)\n", reg, from);
+			comprintf("\t\tmov_b_rr(%s, %s);\n", reg, from);
+			break;
+		case sz_word:
+			comprintf("\tif(%s != %s)\n", reg, from);
+			comprintf("\t\tmov_w_rr(%s, %s);\n", reg, from);
+			break;
+		case sz_long:
+			comprintf("\tif(%s != %s)\n", reg, from);
+			comprintf("\t\tmov_l_rr(%s, %s);\n", reg, from);
+			break;
+		default:
+			assert(0);
+			break;
+		}
+		break;
+	case Areg:
+		switch (size)
+		{
+		case sz_word:
+			comprintf("\tif(%s + 8 != %s)\n", reg, from);
+			comprintf("\t\tmov_w_rr(%s + 8, %s);\n", reg, from);
+			break;
+		case sz_long:
+			comprintf("\tif(%s + 8 != %s)\n", reg, from);
+			comprintf("\t\tmov_l_rr(%s + 8, %s);\n", reg, from);
+			break;
+		default:
+			assert(0);
+			break;
+		}
+		break;
+
+	case Apdi:
+	case absw:
+	case PC16:
+	case PC8r:
+	case Ad16:
+	case Ad8r:
+	case Aipi:
+	case Aind:
+	case absl:
+	{
+		char astring[80];
+		sprintf(astring, "%sa", to);
+
+		switch (size)
+		{
+		case sz_byte:
+			insn_n_cycles += 2;
+			gen_writebyte(astring, from);
+			break;
+		case sz_word:
+			insn_n_cycles += 2;
+			gen_writeword(astring, from);
+			break;
+		case sz_long:
+			insn_n_cycles += 4;
+			gen_writelong(astring, from);
+			break;
+		default:
+			assert(0);
+			break;
+		}
+	}
+		break;
+	case imm:
+	case imm0:
+	case imm1:
+	case imm2:
+	case immi:
+		assert(0);
+		break;
+	default:
+		assert(0);
+		break;
+	}
+}
+
+static void gen_move16(uae_u32 opcode, struct instr *curi) {
+#if defined(USE_JIT2)
+	comprintf("\tint src=scratchie++;\n");
+	comprintf("\tint dst=scratchie++;\n");
+
+	uae_u32 masked_op = (opcode & 0xfff8);
+	if (masked_op == 0xf620) {
+		// POSTINCREMENT SOURCE AND DESTINATION version
+		comprintf("\t uae_u16 dstreg = ((%s)>>12) & 0x07;\n", gen_nextiword());
+		comprintf("\t jnf_MOVE(src, srcreg + 8);");
+		comprintf("\t jnf_MOVE(dst, dstreg + 8);");
+		comprintf("\t if (srcreg != dstreg)\n");
+		comprintf("\t   jnf_ADD_imm(srcreg + 8, srcreg + 8, 16);");
+		comprintf("\t jnf_ADD_imm(dstreg + 8, dstreg + 8, 16);");
+	} else {
+		/* Other variants */
+		genamode(curi->smode, "srcreg", curi->size, "src", 0, 2);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 0, 2);
+		switch (masked_op) {
+			case 0xf600:
+			comprintf("\t jnf_ADD_imm(srcreg + 8, srcreg + 8, 16);");
+			break;
+			case 0xf608:
+			comprintf("\t jnf_ADD_imm(dstreg + 8, dstreg + 8, 16);");
+			break;
+		}
+	}
+	comprintf("\t jnf_MOVE16(dst, src);");
+#else
+	comprintf("\tint src=scratchie++;\n");
+	comprintf("\tint dst=scratchie++;\n");
+
+	if ((opcode & 0xfff8) == 0xf620) {
+		/* MOVE16 (Ax)+,(Ay)+ */
+		comprintf("\tuae_u16 dstreg=((%s)>>12)&0x07;\n", gen_nextiword());
+		comprintf("\tmov_l_rr(src,8+srcreg);\n");
+		comprintf("\tmov_l_rr(dst,8+dstreg);\n");
+	} else {
+		/* Other variants */
+		genamode(curi->smode, "srcreg", curi->size, "src", 0, 2);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 0, 2);
+		comprintf("\tmov_l_rr(src,srca);\n");
+		comprintf("\tmov_l_rr(dst,dsta);\n");
+	}
+
+	/* Align on 16-byte boundaries */
+	comprintf("\tand_l_ri(src,~15);\n");
+	comprintf("\tand_l_ri(dst,~15);\n");
+
+	if ((opcode & 0xfff8) == 0xf620) {
+		comprintf("\tif (srcreg != dstreg)\n");
+		comprintf("\tarm_ADD_l_ri8(srcreg+8,16);\n");
+		comprintf("\tarm_ADD_l_ri8(dstreg+8,16);\n");
+	} else if ((opcode & 0xfff8) == 0xf600)
+		comprintf("\tarm_ADD_l_ri8(srcreg+8,16);\n");
+	else if ((opcode & 0xfff8) == 0xf608)
+		comprintf("\tarm_ADD_l_ri8(dstreg+8,16);\n");
+
+	start_brace();
+	comprintf("\tint tmp=scratchie;\n");
+	comprintf("\tscratchie+=4;\n");
+
+	comprintf("\tget_n_addr(src,src,scratchie);\n"
+			"\tget_n_addr(dst,dst,scratchie);\n"
+			"\tmov_l_rR(tmp+0,src,0);\n"
+			"\tmov_l_rR(tmp+1,src,4);\n"
+			"\tmov_l_rR(tmp+2,src,8);\n"
+			"\tmov_l_rR(tmp+3,src,12);\n"
+			"\tmov_l_Rr(dst,tmp+0,0);\n"
+			"\tforget_about(tmp+0);\n"
+			"\tmov_l_Rr(dst,tmp+1,4);\n"
+			"\tforget_about(tmp+1);\n"
+			"\tmov_l_Rr(dst,tmp+2,8);\n"
+			"\tforget_about(tmp+2);\n"
+			"\tmov_l_Rr(dst,tmp+3,12);\n");
+	close_brace();
+#endif
+}
+
+static void genmovemel(uae_u16 opcode) {
+	comprintf("\tuae_u16 mask = %s;\n", gen_nextiword());
+	comprintf("\tint native=scratchie++;\n");
+	comprintf("\tint i;\n");
+	comprintf("\tsigned char offset=0;\n");
+	genamode(table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2,
+			1);
+	comprintf("\tget_n_addr(srca,native,scratchie);\n");
+
+	comprintf("\tfor (i=0;i<16;i++) {\n"
+			"\t\tif ((mask>>i)&1) {\n");
+	switch (table68k[opcode].size) {
+	case sz_long:
+		comprintf("\t\t\tmov_l_rR(i,native,offset);\n"
+				"\t\t\tmid_bswap_32(i);\n"
+				"\t\t\toffset+=4;\n");
+		break;
+	case sz_word:
+		comprintf("\t\t\tmov_w_rR(i,native,offset);\n"
+				"\t\t\tmid_bswap_16(i);\n"
+				"\t\t\tsign_extend_16_rr(i,i);\n"
+				"\t\t\toffset+=2;\n");
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	comprintf("\t\t}\n"
+			"\t}");
+	if (table68k[opcode].dmode == Aipi) {
+		comprintf("\t\t\tlea_l_brr(8+dstreg,srca,offset);\n");
+	}
+}
+
+static void genmovemle(uae_u16 opcode) {
+	comprintf("\tuae_u16 mask = %s;\n", gen_nextiword());
+	comprintf("\tint native=scratchie++;\n");
+	comprintf("\tint i;\n");
+	comprintf("\tint tmp=scratchie++;\n");
+	comprintf("\tsigned char offset=0;\n");
+	genamode(table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2,
+			1);
+
+	comprintf("\tget_n_addr(srca,native,scratchie);\n");
+
+	if (table68k[opcode].dmode != Apdi) {
+		comprintf("\tfor (i=0;i<16;i++) {\n"
+				"\t\tif ((mask>>i)&1) {\n");
+		switch (table68k[opcode].size) {
+		case sz_long:
+			comprintf("\t\t\tmov_l_rr(tmp,i);\n"
+					"\t\t\tmid_bswap_32(tmp);\n"
+					"\t\t\tmov_l_Rr(native,tmp,offset);\n"
+					"\t\t\toffset+=4;\n");
+			break;
+		case sz_word:
+			comprintf("\t\t\tmov_l_rr(tmp,i);\n"
+					"\t\t\tmid_bswap_16(tmp);\n"
+					"\t\t\tmov_w_Rr(native,tmp,offset);\n"
+					"\t\t\toffset+=2;\n");
+			break;
+		default:
+			assert(0);
+			break;
+		}
+	} else { /* Pre-decrement */
+		comprintf("\tfor (i=0;i<16;i++) {\n"
+				"\t\tif ((mask>>i)&1) {\n");
+		switch (table68k[opcode].size) {
+		case sz_long:
+			comprintf("\t\t\toffset-=4;\n"
+					"\t\t\tmov_l_rr(tmp,15-i);\n"
+					"\t\t\tmid_bswap_32(tmp);\n"
+					"\t\t\tmov_l_Rr(native,tmp,offset);\n");
+			break;
+		case sz_word:
+			comprintf("\t\t\toffset-=2;\n"
+					"\t\t\tmov_l_rr(tmp,15-i);\n"
+					"\t\t\tmid_bswap_16(tmp);\n"
+					"\t\t\tmov_w_Rr(native,tmp,offset);\n");
+			break;
+		default:
+			assert(0);
+			break;
+		}
+	}
+
+	comprintf("\t\t}\n"
+			"\t}");
+	if (table68k[opcode].dmode == Apdi) {
+		comprintf("\t\t\tlea_l_brr(8+dstreg,srca,(uae_s32)offset);\n");
+	}
+}
+
+static void duplicate_carry(void) {
+	comprintf("\tif (needed_flags&FLAG_X) duplicate_carry();\n");
+}
+
+typedef enum {
+	flag_logical_noclobber,
+	flag_logical,
+	flag_add,
+	flag_sub,
+	flag_cmp,
+	flag_addx,
+	flag_subx,
+	flag_zn,
+	flag_av,
+	flag_sv,
+	flag_and,
+	flag_or,
+	flag_eor,
+	flag_mov
+} flagtypes;
+
+#if !defined(USE_JIT2)
+static void genflags(flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
+{
+	if (noflags) {
+		switch (type) {
+		case flag_cmp:
+			comprintf("\tdont_care_flags();\n");
+			comprintf("/* Weird --- CMP with noflags ;-) */\n");
+			return;
+		case flag_add:
+		case flag_sub:
+			comprintf("\tdont_care_flags();\n");
+			{
+				const char* op;
+				switch (type) {
+				case flag_add:
+					op = "add";
+					break; // nf
+				case flag_sub:
+					op = "sub";
+					break; // nf
+				default:
+					assert(0);
+					break;
+				}
+				switch (size) {
+				case sz_byte:
+					comprintf("\t%s_b(%s,%s);\n", op, dst, src);
+					break;
+				case sz_word:
+					comprintf("\t%s_w(%s,%s);\n", op, dst, src);
+					break;
+				case sz_long:
+					comprintf("\t%s_l(%s,%s);\n", op, dst, src);
+					break;
+				}
+				return;
+			}
+			break;
+
+		case flag_and:
+			comprintf("\tdont_care_flags();\n");
+			switch (size) {
+			case sz_byte:
+				comprintf("if (kill_rodent(dst)) {\n");
+				comprintf("\tzero_extend_8_rr(scratchie,%s);\n", src);
+				comprintf("\tor_l_ri(scratchie,0xffffff00);\n"); // nf
+				comprintf("\tarm_AND_l(%s,scratchie);\n", dst);
+				comprintf("\tforget_about(scratchie);\n");
+				comprintf("\t} else \n"
+						"\tarm_AND_b(%s,%s);\n", dst, src);
+				break;
+			case sz_word:
+				comprintf("if (kill_rodent(dst)) {\n");
+				comprintf("\tzero_extend_16_rr(scratchie,%s);\n", src);
+				comprintf("\tor_l_ri(scratchie,0xffff0000);\n"); // nf
+				comprintf("\tarm_AND_l(%s,scratchie);\n", dst);
+				comprintf("\tforget_about(scratchie);\n");
+				comprintf("\t} else \n"
+						"\tarm_AND_w(%s,%s);\n", dst, src);
+				break;
+			case sz_long:
+				comprintf("\tarm_AND_l(%s,%s);\n", dst, src);
+				break;
+			}
+			return;
+
+		case flag_mov:
+			comprintf("\tdont_care_flags();\n");
+			switch (size) {
+			case sz_byte:
+				comprintf("if (kill_rodent(dst)) {\n");
+				comprintf("\tzero_extend_8_rr(scratchie,%s);\n", src);
+				comprintf("\tand_l_ri(%s,0xffffff00);\n", dst); // nf
+				comprintf("\tarm_ORR_l(%s,scratchie);\n", dst);
+				comprintf("\tforget_about(scratchie);\n");
+				comprintf("\t} else \n"
+						"\tmov_b_rr(%s,%s);\n", dst, src);
+				break;
+			case sz_word:
+				comprintf("if (kill_rodent(dst)) {\n");
+				comprintf("\tzero_extend_16_rr(scratchie,%s);\n", src);
+				comprintf("\tand_l_ri(%s,0xffff0000);\n", dst); // nf
+				comprintf("\tarm_ORR_l(%s,scratchie);\n", dst);
+				comprintf("\tforget_about(scratchie);\n");
+				comprintf("\t} else \n"
+						"\tmov_w_rr(%s,%s);\n", dst, src);
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(%s,%s);\n", dst, src);
+				break;
+			}
+			return;
+
+		case flag_or:
+		case flag_eor:
+			comprintf("\tdont_care_flags();\n");
+			start_brace();
+			{
+				const char* op;
+				switch (type) {
+				case flag_or:
+					op = "ORR";
+					break; // nf
+				case flag_eor:
+					op = "EOR";
+					break; // nf
+				default:
+					assert(0);
+					break;
+				}
+				switch (size) {
+				case sz_byte:
+					comprintf("if (kill_rodent(dst)) {\n");
+					comprintf("\tzero_extend_8_rr(scratchie,%s);\n", src);
+					comprintf("\tarm_%s_l(%s,scratchie);\n", op, dst);
+					comprintf("\tforget_about(scratchie);\n");
+					comprintf("\t} else \n"
+							"\tarm_%s_b(%s,%s);\n", op, dst, src);
+					break;
+				case sz_word:
+					comprintf("if (kill_rodent(dst)) {\n");
+					comprintf("\tzero_extend_16_rr(scratchie,%s);\n", src);
+					comprintf("\tarm_%s_l(%s,scratchie);\n", op, dst);
+					comprintf("\tforget_about(scratchie);\n");
+					comprintf("\t} else \n"
+							"\tarm_%s_w(%s,%s);\n", op, dst, src);
+					break;
+				case sz_long:
+					comprintf("\tarm_%s_l(%s,%s);\n", op, dst, src);
+					break;
+				}
+				close_brace();
+				return;
+			}
+
+		case flag_addx:
+		case flag_subx:
+			comprintf("\tdont_care_flags();\n");
+			{
+				const char* op;
+				switch (type) {
+				case flag_addx:
+					op = "adc";
+					break;
+				case flag_subx:
+					op = "sbb";
+					break;
+				default:
+					assert(0);
+					break;
+				}
+				comprintf("\trestore_carry();\n"); /* Reload the X flag into C */
+				switch (size) {
+				case sz_byte:
+					comprintf("\t%s_b(%s,%s);\n", op, dst, src);
+					break;
+				case sz_word:
+					comprintf("\t%s_w(%s,%s);\n", op, dst, src);
+					break;
+				case sz_long:
+					comprintf("\t%s_l(%s,%s);\n", op, dst, src);
+					break;
+				}
+				return;
+			}
+			break;
+		default:
+			return;
+		}
+	}
+
+	/* Need the flags, but possibly not all of them */
+	switch (type) {
+	case flag_logical_noclobber:
+		failure;
+		/* fall through */
+
+	case flag_and:
+	case flag_or:
+	case flag_eor:
+		comprintf("\tdont_care_flags();\n");
+		start_brace();
+		{
+			const char* op;
+			switch (type) {
+			case flag_and:
+				op = "and";
+				break;
+			case flag_or:
+				op = "or";
+				break;
+			case flag_eor:
+				op = "xor";
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			switch (size) {
+			case sz_byte:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_b(%s,%s);\n", op, dst, src);
+				break;
+			case sz_word:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_w(%s,%s);\n", op, dst, src);
+				break;
+			case sz_long:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_l(%s,%s);\n", op, dst, src);
+				break;
+			}
+			comprintf("\tlive_flags();\n");
+			comprintf("\tend_needflags();\n");
+			close_brace();
+			return;
+		}
+
+	case flag_mov:
+		comprintf("\tdont_care_flags();\n");
+		start_brace();
+		{
+			switch (size) {
+			case sz_byte:
+				comprintf("\tif (%s!=%s) {\n", src, dst);
+				comprintf("\tmov_b_ri(%s,0);\n"
+						"\tstart_needflags();\n", dst);
+				comprintf("\tor_b(%s,%s);\n", dst, src);
+				comprintf("\t} else {\n");
+				comprintf("\tmov_b_rr(%s,%s);\n", dst, src);
+				comprintf("\ttest_b_rr(%s,%s);\n", dst, dst);
+				comprintf("\t}\n");
+				break;
+			case sz_word:
+				comprintf("\tif (%s!=%s) {\n", src, dst);
+				comprintf("\tmov_w_ri(%s,0);\n"
+						"\tstart_needflags();\n", dst);
+				comprintf("\tor_w(%s,%s);\n", dst, src);
+				comprintf("\t} else {\n");
+				comprintf("\tmov_w_rr(%s,%s);\n", dst, src);
+				comprintf("\ttest_w_rr(%s,%s);\n", dst, dst);
+				comprintf("\t}\n");
+				break;
+			case sz_long:
+				comprintf("\tif (%s!=%s) {\n", src, dst);
+				comprintf("\tmov_l_ri(%s,0);\n"
+						"\tstart_needflags();\n", dst);
+				comprintf("\tor_l(%s,%s);\n", dst, src);
+				comprintf("\t} else {\n");
+				comprintf("\tmov_l_rr(%s,%s);\n", dst, src);
+				comprintf("\ttest_l_rr(%s,%s);\n", dst, dst);
+				comprintf("\t}\n");
+				break;
+			}
+			comprintf("\tlive_flags();\n");
+			comprintf("\tend_needflags();\n");
+			close_brace();
+			return;
+		}
+
+	case flag_logical:
+		comprintf("\tdont_care_flags();\n");
+		start_brace();
+		switch (size) {
+		case sz_byte:
+			comprintf("\tstart_needflags();\n"
+					"\ttest_b_rr(%s,%s);\n", value, value);
+			break;
+		case sz_word:
+			comprintf("\tstart_needflags();\n"
+					"\ttest_w_rr(%s,%s);\n", value, value);
+			break;
+		case sz_long:
+			comprintf("\tstart_needflags();\n"
+					"\ttest_l_rr(%s,%s);\n", value, value);
+			break;
+		}
+		comprintf("\tlive_flags();\n");
+		comprintf("\tend_needflags();\n");
+		close_brace();
+		return;
+
+	case flag_add:
+	case flag_sub:
+	case flag_cmp:
+		comprintf("\tdont_care_flags();\n");
+		{
+			const char* op;
+			switch (type) {
+			case flag_add:
+				op = "add";
+				break;
+			case flag_sub:
+				op = "sub";
+				break;
+			case flag_cmp:
+				op = "cmp";
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			switch (size) {
+			case sz_byte:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_b(%s,%s);\n", op, dst, src);
+				break;
+			case sz_word:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_w(%s,%s);\n", op, dst, src);
+				break;
+			case sz_long:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_l(%s,%s);\n", op, dst, src);
+				break;
+			}
+			comprintf("\tlive_flags();\n");
+			comprintf("\tend_needflags();\n");
+			if (type != flag_cmp) {
+				duplicate_carry();
+			}
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+
+			return;
+		}
+
+	case flag_addx:
+	case flag_subx:
+		uses_cmov;
+		comprintf("\tdont_care_flags();\n");
+		{
+			const char* op;
+			switch (type) {
+			case flag_addx:
+				op = "adc";
+				break;
+			case flag_subx:
+				op = "sbb";
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			start_brace();
+			comprintf("\tint zero=scratchie++;\n"
+					"\tint one=scratchie++;\n"
+					"\tif (needed_flags&FLAG_Z) {\n"
+					"\tmov_l_ri(zero,0);\n"
+					"\tmov_l_ri(one,-1);\n"
+					"\tmake_flags_live();\n"
+					"\tcmov_l_rr(zero,one,%d);\n"
+					"\t}\n", NATIVE_CC_NE);
+			comprintf("\trestore_carry();\n"); /* Reload the X flag into C */
+			switch (size) {
+			case sz_byte:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_b(%s,%s);\n", op, dst, src);
+				break;
+			case sz_word:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_w(%s,%s);\n", op, dst, src);
+				break;
+			case sz_long:
+				comprintf("\tstart_needflags();\n"
+						"\t%s_l(%s,%s);\n", op, dst, src);
+				break;
+			}
+			comprintf("\tlive_flags();\n");
+			comprintf("\tif (needed_flags&FLAG_Z) {\n"
+					"\tcmov_l_rr(zero,one,%d);\n"
+					"\tset_zero(zero, one);\n" /* No longer need one */
+					"\tlive_flags();\n"
+					"\t}\n", NATIVE_CC_NE);
+			comprintf("\tend_needflags();\n");
+			duplicate_carry();
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+			return;
+		}
+	default:
+		failure;
+		break;
+	}
+}
+#endif
+
+static void gen_abcd(uae_u32 opcode, struct instr *curi, const char* ssize) {
+#if 0
+#else
+	(void) opcode;
+	(void) curi;
+	(void) ssize;
+	failure;
+	/* No BCD maths for me.... */
+#endif
+}
+
+static void gen_add(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	// Use tmp register to avoid destroying upper part in .B., .W cases
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ADD_%s(tmp,dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+		comprintf(
+				"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t jnf_ADD(tmp,dst,src);\n");
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags(flag_add, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_adda(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\t jnf_ADDA_%s(dst, src);\n", ssize);
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n");
+	switch (curi->size) {
+	case sz_byte:
+		comprintf("\tsign_extend_8_rr(tmp,src);\n");
+		break;
+	case sz_word:
+		comprintf("\tsign_extend_16_rr(tmp,src);\n");
+		break;
+	case sz_long:
+		comprintf("\ttmp=src;\n");
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	comprintf("\tarm_ADD_l(dst,tmp);\n");
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#endif
+}
+
+static void gen_addx(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	isaddx;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+
+	// Use tmp register to avoid destroying upper part in .B., .W cases
+	comprintf("\t dont_care_flags();\n");
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ADDX_%s(tmp,dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+		comprintf("\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_ADDX(tmp,dst,src);\n");
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	isaddx;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	genflags(flag_addx, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_and(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+
+	comprintf("\t dont_care_flags();\n");
+	comprintf("\t int tmp=scratchie++;\n");
+	start_brace();
+	if (!noflags) {
+		comprintf("\t jff_AND_%s(tmp,dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_AND(tmp,dst,src);\n");
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags(flag_and, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_andsr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ANDSR(ARM_CCR_MAP[src & 0xF], (src & 0x10));\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	}
+#else
+	(void) curi;
+	failure;
+	isjump;
+#endif
+}
+
+static void gen_asl(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\t dont_care_flags();\n");
+	comprintf("\t int tmp=scratchie++;\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+
+	if (curi->smode != immi) {
+		if (!noflags) {
+			start_brace();
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_ASL_%s_reg(tmp,data,cnt);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		} else {
+			start_brace();
+			comprintf("\t jnf_LSL_reg(tmp,data,cnt);\n");
+		}
+	} else {
+		start_brace();
+		if (!noflags) {
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_ASL_%s_imm(tmp,data,srcreg);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		} else {
+			comprintf("\t jnf_LSL_imm(tmp,data,srcreg);\n");
+		}
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) ssize;
+
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+	/* Except for the handling of the V flag, this is identical to
+	 LSL. The handling of V is, uhm, unpleasant, so if it's needed,
+	 let the normal emulation handle it. Shoulders of giants kinda
+	 thing ;-) */
+	comprintf("if (needed_flags & FLAG_V) {\n"
+			"  FAIL(1);\n"
+			"  return;\n"
+			"} \n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode != immi) {
+		if (!noflags) {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n"
+					"\tint cdata=scratchie++;\n"
+					"\tint tmpcnt=scratchie++;\n");
+			comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+					"\tand_l_ri(tmpcnt,63);\n"
+					"\tmov_l_ri(cdata,0);\n"
+					"\tcmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
+			/* cdata is now either data (for shift count!=0) or
+			 0 (for shift count==0) */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshll_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n");
+				break;
+			case sz_word:
+				comprintf("\tshll_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n");
+				break;
+			case sz_long:
+				comprintf("\tshll_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(scratchie,data,%d);\n", NATIVE_CC_EQ);
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tmov_b_rr(data,scratchie);\n");
+				break;
+			case sz_word:
+				comprintf("\tmov_w_rr(data,scratchie);\n");
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(data,scratchie);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			/* Result of shift is now in data. Now we need to determine
+			 the carry by shifting cdata one less */
+			comprintf("\tsub_l_ri(tmpcnt,1);\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshll_b_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_word:
+				comprintf("\tshll_w_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_long:
+				comprintf("\tshll_l_rr(cdata,tmpcnt);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(tmpcnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(cdata,scratchie,%d);\n", NATIVE_CC_NE);
+			/* And create the flags */
+			comprintf("\tstart_needflags();\n");
+
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				comprintf("\t bt_l_ri(cdata,7);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				comprintf("\t bt_l_ri(cdata,15);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				comprintf("\t bt_l_ri(cdata,31);\n");
+				break;
+			}
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		} else {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshll_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n");
+				break;
+			case sz_word:
+				comprintf("\tshll_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n");
+				break;
+			case sz_long:
+				comprintf("\tshll_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(scratchie,data,%d);\n", NATIVE_CC_EQ);
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tmov_b_rr(data,scratchie);\n");
+				break;
+			case sz_word:
+				comprintf("\tmov_w_rr(data,scratchie);\n");
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(data,scratchie);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		}
+	} else {
+		start_brace();
+		comprintf("\tint tmp=scratchie++;\n"
+				"\tint bp;\n"
+				"\tmov_l_rr(tmp,data);\n");
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\tshll_b_ri(data,srcreg);\n"
+					"\tbp=8-srcreg;\n");
+			break;
+		case sz_word:
+			comprintf("\tshll_w_ri(data,srcreg);\n"
+					"\tbp=16-srcreg;\n");
+			break;
+		case sz_long:
+			comprintf("\tshll_l_ri(data,srcreg);\n"
+					"\tbp=32-srcreg;\n");
+			break;
+		default:
+			assert(0);
+			break;
+		}
+
+		if (!noflags) {
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				break;
+			}
+			comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		}
+		genastore("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+#endif
+}
+
+static void gen_aslw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ASLW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_ASLW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_asr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+#if defined(USE_JIT2)
+	(void)opcode;
+
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\t dont_care_flags();\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (curi->smode != immi) {
+		if (!noflags) {
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_ASR_%s_reg(tmp,data,cnt);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		} else {
+			comprintf("\t jnf_ASR_%s_reg(tmp,data,cnt);\n", ssize);
+		}
+	} else {
+		char *op;
+		if (!noflags) {
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			op = "ff";
+		} else
+		op = "nf";
+
+		comprintf("\t j%s_ASR_%s_imm(tmp,data,srcreg);\n", op, ssize);
+		if (!noflags) {
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		}
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) opcode;
+	(void) ssize;
+
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode != immi) {
+		if (!noflags) {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n"
+					"\tint width;\n"
+					"\tint cdata=scratchie++;\n"
+					"\tint tmpcnt=scratchie++;\n"
+					"\tint highshift=scratchie++;\n");
+			comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+					"\tand_l_ri(tmpcnt,63);\n"
+					"\tmov_l_ri(cdata,0);\n"
+					"\tcmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
+			/* cdata is now either data (for shift count!=0) or
+			 0 (for shift count==0) */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n"
+						"\twidth=8;\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n"
+						"\twidth=16;\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n"
+						"\twidth=32;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(highshift,0);\n"
+					"mov_l_ri(scratchie,width/2);\n"
+					"cmov_l_rr(highshift,scratchie,%d);\n", NATIVE_CC_NE);
+			/* The x86 masks out bits, so we now make sure that things
+			 really get shifted as much as planned */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(data,highshift);\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(data,highshift);\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(data,highshift);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			/* And again */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(data,highshift);\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(data,highshift);\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(data,highshift);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+
+			/* Result of shift is now in data. Now we need to determine
+			 the carry by shifting cdata one less */
+			comprintf("\tsub_l_ri(tmpcnt,1);\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(cdata,tmpcnt);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			/* If the shift count was higher than the width, we need
+			 to pick up the sign from data */
+			comprintf("test_l_ri(tmpcnt,highmask);\n"
+					"cmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
+			/* And create the flags */
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				break;
+			}
+			comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		} else {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n"
+					"\tint width;\n"
+					"\tint highshift=scratchie++;\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n"
+						"\twidth=8;\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n"
+						"\twidth=16;\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n"
+						"\twidth=32;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(highshift,0);\n"
+					"mov_l_ri(scratchie,width/2);\n"
+					"cmov_l_rr(highshift,scratchie,%d);\n", NATIVE_CC_NE);
+			/* The x86 masks out bits, so we now make sure that things
+			 really get shifted as much as planned */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(data,highshift);\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(data,highshift);\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(data,highshift);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			/* And again */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshra_b_rr(data,highshift);\n");
+				break;
+			case sz_word:
+				comprintf("\tshra_w_rr(data,highshift);\n");
+				break;
+			case sz_long:
+				comprintf("\tshra_l_rr(data,highshift);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		}
+	} else {
+		start_brace();
+		comprintf("\tint tmp=scratchie++;\n"
+				"\tint bp;\n"
+				"\tmov_l_rr(tmp,data);\n");
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\tshra_b_ri(data,srcreg);\n"
+					"\tbp=srcreg-1;\n");
+			break;
+		case sz_word:
+			comprintf("\tshra_w_ri(data,srcreg);\n"
+					"\tbp=srcreg-1;\n");
+			break;
+		case sz_long:
+			comprintf("\tshra_l_ri(data,srcreg);\n"
+					"\tbp=srcreg-1;\n");
+			break;
+		default:
+			assert(0);
+			break;
+		}
+
+		if (!noflags) {
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				break;
+			}
+			comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		}
+		genastore("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+#endif
+}
+
+static void gen_asrw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp = scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ASRW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_ASRW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_bchg(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_BCHG_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_BCHG_%s(dst,src);\n", ssize);
+		comprintf("\t dont_care_flags();\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint s=scratchie++;\n"
+			"\tint tmp=scratchie++;\n"
+			"\tmov_l_rr(s,src);\n");
+	if (curi->size == sz_byte)
+		comprintf("\tand_l_ri(s,7);\n");
+	else
+		comprintf("\tand_l_ri(s,31);\n");
+
+	comprintf("\tbtc_l_rr(dst,s);\n" /* Answer now in C */
+			"\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
+			"\tmake_flags_live();\n" /* Get the flags back */
+			"\tdont_care_flags();\n");
+	if (!noflags) {
+		comprintf("\tstart_needflags();\n"
+				"\tset_zero(s,tmp);\n"
+				"\tlive_flags();\n"
+				"\tend_needflags();\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_bclr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_BCLR_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_BCLR_%s(dst,src);\n", ssize);
+		comprintf("\t dont_care_flags();\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint s=scratchie++;\n"
+			"\tint tmp=scratchie++;\n"
+			"\tmov_l_rr(s,src);\n");
+	if (curi->size == sz_byte)
+		comprintf("\tand_l_ri(s,7);\n");
+	else
+		comprintf("\tand_l_ri(s,31);\n");
+
+	comprintf("\tbtr_l_rr(dst,s);\n" /* Answer now in C */
+			"\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
+			"\tmake_flags_live();\n" /* Get the flags back */
+			"\tdont_care_flags();\n");
+	if (!noflags) {
+		comprintf("\tstart_needflags();\n"
+				"\tset_zero(s,tmp);\n"
+				"\tlive_flags();\n"
+				"\tend_needflags();\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_bset(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_BSET_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_BSET_%s(dst,src);\n", ssize);
+		comprintf("\t dont_care_flags();\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint s=scratchie++;\n"
+			"\tint tmp=scratchie++;\n"
+			"\tmov_l_rr(s,src);\n");
+	if (curi->size == sz_byte)
+		comprintf("\tand_l_ri(s,7);\n");
+	else
+		comprintf("\tand_l_ri(s,31);\n");
+
+	comprintf("\tbts_l_rr(dst,s);\n" /* Answer now in C */
+			"\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
+			"\tmake_flags_live();\n" /* Get the flags back */
+			"\tdont_care_flags();\n");
+	if (!noflags) {
+		comprintf("\tstart_needflags();\n"
+				"\tset_zero(s,tmp);\n"
+				"\tlive_flags();\n"
+				"\tend_needflags();\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_btst(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+
+	// If we are not interested in flags it is not necessary to do
+	// anything with the data
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_BTST_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t dont_care_flags();\n");
+	}
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint s=scratchie++;\n"
+			"\tint tmp=scratchie++;\n"
+			"\tmov_l_rr(s,src);\n");
+	if (curi->size == sz_byte)
+		comprintf("\tand_l_ri(s,7);\n");
+	else
+		comprintf("\tand_l_ri(s,31);\n");
+
+	comprintf("\tbt_l_rr(dst,s);\n" /* Answer now in C */
+			"\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
+			"\tmake_flags_live();\n" /* Get the flags back */
+			"\tdont_care_flags();\n");
+	if (!noflags) {
+		comprintf("\tstart_needflags();\n"
+				"\tset_zero(s,tmp);\n"
+				"\tlive_flags();\n"
+				"\tend_needflags();\n");
+	}
+#endif
+}
+
+static void gen_clr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 2, 0);
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_CLR(tmp);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_CLR(tmp);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	genamode(curi->smode, "srcreg", curi->size, "src", 2, 0);
+	start_brace();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0);\n");
+	genflags(flag_logical, curi->size, "dst", "", "");
+	genastore("dst", curi->smode, "srcreg", curi->size, "src");
+#endif
+}
+
+static void gen_cmp(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\t dont_care_flags();\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_CMP_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("/* Weird --- CMP with noflags ;-) */\n");
+	}
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	genflags(flag_cmp, curi->size, "", "src", "dst");
+#endif
+}
+
+static void gen_cmpa(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if  defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	if (!noflags) {
+		comprintf("\t dont_care_flags();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_CMPA_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\tdont_care_flags();\n");
+		comprintf("/* Weird --- CMP with noflags ;-) */\n");
+	}
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmps=scratchie++;\n");
+	switch (curi->size) {
+	case sz_byte:
+		comprintf("\tsign_extend_8_rr(tmps,src);\n");
+		break;
+	case sz_word:
+		comprintf("\tsign_extend_16_rr(tmps,src);\n");
+		break;
+	case sz_long:
+		comprintf("tmps=src;\n");
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	genflags(flag_cmp, sz_long, "", "tmps", "dst");
+#endif
+}
+
+static void gen_dbcc(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if 0
+	isjump;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "offs", 1, 0);
+
+	comprintf("uae_u32 voffs;\n");
+	comprintf("voffs = get_const(offs);\n");
+	/* That offs is an immediate, so we can clobber it with abandon */
+	switch (curi->size) {
+		case sz_word:
+		comprintf("\t voffs = (uae_s32)((uae_s16)voffs);\n");
+		break;
+		default:
+		assert(0); /* Seems this only comes in word flavour */
+		break;
+	}
+	comprintf("\t voffs -= m68k_pc_offset - m68k_pc_offset_thisinst - 2;\n");
+	comprintf("\t voffs += (uintptr)comp_pc_p + m68k_pc_offset;\n");
+
+	comprintf("\t add_const_v(PC_P, m68k_pc_offset);\n");
+	comprintf("\t m68k_pc_offset = 0;\n");
+
+	start_brace();
+
+	if (curi->cc >= 2) {
+		comprintf("\t make_flags_live();\n"); /* Load the flags */
+	}
+
+	assert(curi->size == sz_word);
+
+	switch (curi->cc) {
+		case 0: /* This is an elaborate nop? */
+		break;
+		case 1:
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 8:
+		case 9:
+		case 10:
+		case 11:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jnf_DBcc(src,voffs,%d);\n", curi->cc);
+		comprintf("\t end_needflags();\n");
+		break;
+		default:
+		assert(0);
+		break;
+	}
+	genastore("src", curi->smode, "srcreg", curi->size, "src");
+	gen_update_next_handler();
+#else
+	isjump;
+	uses_cmov;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "offs", 1, 0);
+
+	/* That offs is an immediate, so we can clobber it with abandon */
+	switch (curi->size) {
+	case sz_word:
+		comprintf("\tsign_extend_16_rr(offs,offs);\n");
+		break;
+	default:
+		assert(0); /* Seems this only comes in word flavour */
+		break;
+	}
+	comprintf("\tsub_l_ri(offs,m68k_pc_offset-m68k_pc_offset_thisinst-2);\n");
+	comprintf("\tarm_ADD_l_ri(offs,(uintptr)comp_pc_p);\n");
+	/* New PC,
+	 once the
+	 offset_68k is
+	 * also added */
+	/* Let's fold in the m68k_pc_offset at this point */
+	comprintf("\tarm_ADD_l_ri(offs,m68k_pc_offset);\n");
+	comprintf("\tarm_ADD_l_ri(PC_P,m68k_pc_offset);\n");
+	comprintf("\tm68k_pc_offset=0;\n");
+
+	start_brace();
+	comprintf("\tint nsrc=scratchie++;\n");
+
+	if (curi->cc >= 2) {
+		comprintf("\tmake_flags_live();\n"); /* Load the flags */
+	}
+
+	assert (curi->size == sz_word);
+
+	switch (curi->cc) {
+	case 0: /* This is an elaborate nop? */
+		break;
+	case 1:
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tsub_w_ri(src,1);\n");
+		comprintf("\t end_needflags();\n");
+		start_brace();
+		comprintf("\tuintptr v2,v;\n"
+				"\tuintptr v1=get_const(PC_P);\n");
+		comprintf("\tv2=get_const(offs);\n"
+				"\tregister_branch(v1,v2,%d);\n", NATIVE_CC_CC);
+		break;
+
+	case 8:
+		failure;
+		break; /* Work out details! FIXME */
+	case 9:
+		failure;
+		break; /* Not critical, though! */
+
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+		comprintf("\tmov_l_rr(nsrc,src);\n");
+		comprintf("\tlea_l_brr(scratchie,src,(uae_s32)-1);\n"
+				"\tmov_w_rr(src,scratchie);\n");
+		comprintf("\tcmov_l_rr(offs,PC_P,%d);\n", cond_codes[curi->cc]);
+		comprintf("\tcmov_l_rr(src,nsrc,%d);\n", cond_codes[curi->cc]);
+		/* OK, now for cc=true, we have src==nsrc and offs==PC_P,
+		 so whether we move them around doesn't matter. However,
+		 if cc=false, we have offs==jump_pc, and src==nsrc-1 */
+
+		comprintf("\t start_needflags();\n");
+		comprintf("\ttest_w_rr(nsrc,nsrc);\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\tcmov_l_rr(PC_P,offs,%d);\n", NATIVE_CC_NE);
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	genastore("src", curi->smode, "srcreg", curi->size, "src");
+	gen_update_next_handler();
+#endif
+}
+
+static void gen_eor(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t jff_EOR_%s(tmp,dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_EOR(tmp,dst,src);\n");
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags(flag_eor, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_eorsr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_EORSR(ARM_CCR_MAP[src & 0xF], ((src & 0x10) >> 4));\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	}
+#else
+	(void) curi;
+	failure;
+	isjump;
+#endif
+}
+
+static void gen_exg(uae_u32 opcode, struct instr *curi, const char* ssize) {
+#if 0
+#else
+	(void) opcode;
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n"
+			"\tmov_l_rr(tmp,src);\n");
+	genastore("dst", curi->smode, "srcreg", curi->size, "src");
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_ext(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", sz_long, "src", 1, 0);
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_EXT_%s(tmp,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_EXT_%s(tmp,src);\n", ssize);
+	}
+	genastore("tmp", curi->smode, "srcreg",
+			curi->size == sz_word ? sz_word : sz_long, "src");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", sz_long, "src", 1, 0);
+	comprintf("\tdont_care_flags();\n");
+	start_brace();
+	switch (curi->size) {
+	case sz_byte:
+		comprintf("\tint dst = src;\n"
+				"\tsign_extend_8_rr(src,src);\n");
+		break;
+	case sz_word:
+		comprintf("\tint dst = scratchie++;\n"
+				"\tsign_extend_8_rr(dst,src);\n");
+		break;
+	case sz_long:
+		comprintf("\tint dst = src;\n"
+				"\tsign_extend_16_rr(src,src);\n");
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	genflags(flag_logical, curi->size == sz_word ? sz_word : sz_long, "dst", "",
+			"");
+	genastore("dst", curi->smode, "srcreg",
+			curi->size == sz_word ? sz_word : sz_long, "src");
+#endif
+}
+
+static void gen_lsl(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	comprintf("\t int tmp=scratchie++;\n");
+	if (curi->smode != immi) {
+		if (!noflags) {
+			start_brace();
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_LSL_%s_reg(tmp,data,cnt);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		} else {
+			start_brace();
+			comprintf("\t jnf_LSL_reg(tmp,data,cnt);\n");
+		}
+	} else {
+		start_brace();
+		if (!noflags) {
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_LSL_%s_imm(tmp,data,srcreg);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		} else {
+			comprintf("\t jnf_LSL_imm(tmp,data,srcreg);\n");
+		}
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode != immi) {
+		if (!noflags) {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n"
+					"\tint cdata=scratchie++;\n"
+					"\tint tmpcnt=scratchie++;\n");
+			comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+					"\tand_l_ri(tmpcnt,63);\n"
+					"\tmov_l_ri(cdata,0);\n"
+					"\tcmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
+			/* cdata is now either data (for shift count!=0) or
+			 0 (for shift count==0) */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshll_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n");
+				break;
+			case sz_word:
+				comprintf("\tshll_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n");
+				break;
+			case sz_long:
+				comprintf("\tshll_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(scratchie,data,%d);\n", NATIVE_CC_EQ);
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tmov_b_rr(data,scratchie);\n");
+				break;
+			case sz_word:
+				comprintf("\tmov_w_rr(data,scratchie);\n");
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(data,scratchie);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			/* Result of shift is now in data. Now we need to determine
+			 the carry by shifting cdata one less */
+			comprintf("\tsub_l_ri(tmpcnt,1);\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshll_b_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_word:
+				comprintf("\tshll_w_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_long:
+				comprintf("\tshll_l_rr(cdata,tmpcnt);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(tmpcnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(cdata,scratchie,%d);\n", NATIVE_CC_NE);
+			/* And create the flags */
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				comprintf("\t bt_l_ri(cdata,7);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				comprintf("\t bt_l_ri(cdata,15);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				comprintf("\t bt_l_ri(cdata,31);\n");
+				break;
+			}
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		} else {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshll_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n");
+				break;
+			case sz_word:
+				comprintf("\tshll_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n");
+				break;
+			case sz_long:
+				comprintf("\tshll_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(scratchie,data,%d);\n", NATIVE_CC_EQ);
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tmov_b_rr(data,scratchie);\n");
+				break;
+			case sz_word:
+				comprintf("\tmov_w_rr(data,scratchie);\n");
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(data,scratchie);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		}
+	} else {
+		start_brace();
+		comprintf("\tint tmp=scratchie++;\n"
+				"\tint bp;\n"
+				"\tmov_l_rr(tmp,data);\n");
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\tshll_b_ri(data,srcreg);\n"
+					"\tbp=8-srcreg;\n");
+			break;
+		case sz_word:
+			comprintf("\tshll_w_ri(data,srcreg);\n"
+					"\tbp=16-srcreg;\n");
+			break;
+		case sz_long:
+			comprintf("\tshll_l_ri(data,srcreg);\n"
+					"\tbp=32-srcreg;\n");
+			break;
+		default:
+			assert(0);
+			break;
+		}
+
+		if (!noflags) {
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				break;
+			}
+			comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		}
+		genastore("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+#endif
+}
+
+static void gen_lslw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_LSLW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_LSLW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_lsr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\t dont_care_flags();\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	comprintf("\t int tmp=scratchie++;\n");
+	if (curi->smode != immi) {
+		if (!noflags) {
+			start_brace();
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_LSR_%s_reg(tmp,data,cnt);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		} else {
+			start_brace();
+			comprintf("\t jnf_LSR_%s_reg(tmp,data,cnt);\n", ssize);
+		}
+	} else {
+		start_brace();
+		char *op;
+		if (!noflags) {
+			comprintf("\t make_flags_live();\n");
+			comprintf("\t start_needflags();\n");
+			op = "ff";
+		} else
+		op = "nf";
+
+		comprintf("\t j%s_LSR_%s_imm(tmp,data,srcreg);\n", op, ssize);
+
+		if (!noflags) {
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf(
+					"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		}
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) ssize;
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode != immi) {
+		if (!noflags) {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n"
+					"\tint cdata=scratchie++;\n"
+					"\tint tmpcnt=scratchie++;\n");
+			comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+					"\tand_l_ri(tmpcnt,63);\n"
+					"\tmov_l_ri(cdata,0);\n"
+					"\tcmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
+			/* cdata is now either data (for shift count!=0) or
+			 0 (for shift count==0) */
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshrl_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n");
+				break;
+			case sz_word:
+				comprintf("\tshrl_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n");
+				break;
+			case sz_long:
+				comprintf("\tshrl_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(scratchie,data,%d);\n", NATIVE_CC_EQ);
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tmov_b_rr(data,scratchie);\n");
+				break;
+			case sz_word:
+				comprintf("\tmov_w_rr(data,scratchie);\n");
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(data,scratchie);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			/* Result of shift is now in data. Now we need to determine
+			 the carry by shifting cdata one less */
+			comprintf("\tsub_l_ri(tmpcnt,1);\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshrl_b_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_word:
+				comprintf("\tshrl_w_rr(cdata,tmpcnt);\n");
+				break;
+			case sz_long:
+				comprintf("\tshrl_l_rr(cdata,tmpcnt);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(tmpcnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(cdata,scratchie,%d);\n", NATIVE_CC_NE);
+			/* And create the flags */
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				break;
+			}
+			comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		} else {
+			uses_cmov;
+			start_brace();
+			comprintf("\tint highmask;\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tshrl_b_rr(data,cnt);\n"
+						"\thighmask=0x38;\n");
+				break;
+			case sz_word:
+				comprintf("\tshrl_w_rr(data,cnt);\n"
+						"\thighmask=0x30;\n");
+				break;
+			case sz_long:
+				comprintf("\tshrl_l_rr(data,cnt);\n"
+						"\thighmask=0x20;\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			comprintf("test_l_ri(cnt,highmask);\n"
+					"mov_l_ri(scratchie,0);\n"
+					"cmov_l_rr(scratchie,data,%d);\n", NATIVE_CC_EQ);
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\tmov_b_rr(data,scratchie);\n");
+				break;
+			case sz_word:
+				comprintf("\tmov_w_rr(data,scratchie);\n");
+				break;
+			case sz_long:
+				comprintf("\tmov_l_rr(data,scratchie);\n");
+				break;
+			default:
+				assert(0);
+				break;
+			}
+			genastore("data", curi->dmode, "dstreg", curi->size, "data");
+		}
+	} else {
+		start_brace();
+		comprintf("\tint tmp=scratchie++;\n"
+				"\tint bp;\n"
+				"\tmov_l_rr(tmp,data);\n");
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\tshrl_b_ri(data,srcreg);\n"
+					"\tbp=srcreg-1;\n");
+			break;
+		case sz_word:
+			comprintf("\tshrl_w_ri(data,srcreg);\n"
+					"\tbp=srcreg-1;\n");
+			break;
+		case sz_long:
+			comprintf("\tshrl_l_ri(data,srcreg);\n"
+					"\tbp=srcreg-1;\n");
+			break;
+		default:
+			assert(0);
+			break;
+		}
+
+		if (!noflags) {
+			comprintf("\tstart_needflags();\n");
+			comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+			switch (curi->size) {
+			case sz_byte:
+				comprintf("\t  test_b_rr(data,data);\n");
+				break;
+			case sz_word:
+				comprintf("\t  test_w_rr(data,data);\n");
+				break;
+			case sz_long:
+				comprintf("\t  test_l_rr(data,data);\n");
+				break;
+			}
+			comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+			comprintf("\t duplicate_carry();\n");
+			comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		}
+		genastore("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+#endif
+}
+
+static void gen_lsrw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp = scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_LSRW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_LSRW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_move(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	switch (curi->dmode) {
+		case Dreg:
+		case Areg:
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+		comprintf("\t dont_care_flags();\n");
+		start_brace();
+		comprintf("\t int tmp=scratchie++;\n");
+		if (!noflags && curi->dmode == Dreg) {
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_MOVE_%s(tmp, src);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+		} else {
+			comprintf("\t tmp = src;\n");
+		}
+		genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+
+		default: /* It goes to memory, not a register */
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+		comprintf("\t dont_care_flags();\n");
+		start_brace();
+		if (!noflags) {
+			comprintf("\t start_needflags();\n");
+			comprintf("\t jff_TST_%s(src);\n", ssize);
+			comprintf("\t live_flags();\n");
+			comprintf("\t end_needflags();\n");
+		}
+		genastore("src", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	}
+#else
+	(void) ssize;
+
+	switch (curi->dmode) {
+	case Dreg:
+	case Areg:
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+		genflags(flag_mov, curi->size, "", "src", "dst");
+		genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	default: /* It goes to memory, not a register */
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+		genflags(flag_logical, curi->size, "src", "", "");
+		genastore("src", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	}
+#endif
+}
+
+static void gen_movea(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+
+	start_brace();
+	comprintf("\t jnf_MOVEA_%s(dst, src);\n", ssize);
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#else
+	(void) ssize;
+
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+
+	start_brace();
+	comprintf("\tint tmps=scratchie++;\n");
+	switch (curi->size) {
+	case sz_word:
+		comprintf("\tsign_extend_16_rr(dst,src);\n");
+		break;
+	case sz_long:
+		comprintf("\tmov_l_rr(dst,src);\n");
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#endif
+}
+
+static void gen_mull(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t uae_u16 extra=%s;\n", gen_nextiword());
+	comprintf("\t int r2=(extra>>12)&7;\n"
+			"\t int tmp=scratchie++;\n");
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	/* The two operands are in dst and r2 */
+	if (!noflags) {
+		comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit result */
+		comprintf("\t   int r3=(extra & 7);\n");
+		comprintf("\t   mov_l_rr(r3,dst);\n"); /* operands now in r3 and r2 */
+		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
+		comprintf("\t\t	  jff_MULS64(r2,r3);\n");
+		comprintf("\t	} else { \n");
+		comprintf("\t\t	  jff_MULU64(r2,r3);\n");
+		comprintf("\t	} \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
+		comprintf("\t } else {\n"); /* Only want 32 bit result */
+		/* operands in dst and r2, result goes into r2 */
+		/* shouldn't matter whether it's signed or unsigned?!? */
+		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
+		comprintf("\t     jff_MULS32(r2,dst);\n");
+		comprintf("\t	} else { \n");
+		comprintf("\t\t	  jff_MULU32(r2,dst);\n");
+		comprintf("\t	} \n"); /* The result is in r2, with r2 holding the lower 32 bits */
+		comprintf("\t }\n");
+	} else {
+		comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit result */
+		comprintf("\t   int r3=(extra & 7);\n");
+		comprintf("\t   mov_l_rr(r3,dst);\n"); /* operands now in r3 and r2 */
+		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
+		comprintf("\t\t	  jnf_MULS64(r2,r3);\n");
+		comprintf("\t	} else { \n");
+		comprintf("\t\t	  jnf_MULU64(r2,r3);\n");
+		comprintf("\t	} \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
+		comprintf("\t } else {\n"); /* Only want 32 bit result */
+		/* operands in dst and r2, result foes into r2 */
+		/* shouldn't matter whether it's signed or unsigned?!? */
+		comprintf("\t   if (extra & 0x0800) { \n"); /* signed */
+		comprintf("\t     jnf_MULS32(r2,dst);\n");
+		comprintf("\t	} else { \n");
+		comprintf("\t\t	  jnf_MULU32(r2,dst);\n");
+		comprintf("\t	} \n"); /* The result is in r2, with r2 holding the lower 32 bits */
+		comprintf("\t }\n");
+	}
+#else
+	if (!noflags) {
+		failure;
+		return;
+	}
+	comprintf("\tuae_u16 extra=%s;\n", gen_nextiword());
+	comprintf("\tint r2=(extra>>12)&7;\n"
+			"\tint tmp=scratchie++;\n");
+
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	/* The two operands are in dst and r2 */
+	comprintf("\tif (extra&0x0400) {\n" /* Need full 64 bit result */
+			"\tint r3=(extra&7);\n"
+			"\tmov_l_rr(r3,dst);\n"); /* operands now in r3 and r2 */
+	comprintf("\tif (extra&0x0800) { \n" /* signed */
+			"\t\timul_64_32(r2,r3);\n"
+			"\t} else { \n"
+			"\t\tmul_64_32(r2,r3);\n"
+			"\t} \n");
+	/* The result is in r2/tmp, with r2 holding the lower 32 bits */
+	comprintf("\t} else {\n"); /* Only want 32 bit result */
+	/* operands in dst and r2, result foes into r2 */
+	/* shouldn't matter whether it's signed or unsigned?!? */
+	comprintf("\timul_32_32(r2,dst);\n"
+			"\t}\n");
+#endif
+}
+
+static void gen_muls(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", sz_word, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+	start_brace();
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_MULS(dst,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_MULS(dst,src);\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#else
+	comprintf("\tdont_care_flags();\n");
+	genamode(curi->smode, "srcreg", sz_word, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+	comprintf("\tsign_extend_16_rr(scratchie,src);\n"
+			"\tsign_extend_16_rr(dst,dst);\n"
+			"\timul_32_32(dst,scratchie);\n");
+	genflags(flag_logical, sz_long, "dst", "", "");
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#endif
+}
+
+static void gen_mulu(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", sz_word, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+	start_brace();
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_MULU(dst,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_MULU(dst,src);\n");
+	}
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#else
+	comprintf("\tdont_care_flags();\n");
+	genamode(curi->smode, "srcreg", sz_word, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+	/* To do 16x16 unsigned multiplication, we actually use
+	 32x32 signed, and zero-extend the registers first.
+	 That solves the problem of MUL needing dedicated registers
+	 on the x86 */
+	comprintf("\tzero_extend_16_rr(scratchie,src);\n"
+			"\tzero_extend_16_rr(dst,dst);\n"
+			"\timul_32_32(dst,scratchie);\n");
+	genflags(flag_logical, sz_long, "dst", "", "");
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+
+#endif
+}
+
+static void gen_nbcd(uae_u32 opcode, struct instr *curi, const char* ssize) {
+#if 0
+#else
+	(void) opcode;
+	(void) curi;
+	(void) ssize;
+	failure;
+	/* Nope! */
+#endif
+}
+
+static void gen_neg(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_NEG_%s(tmp,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+		comprintf("\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t jnf_NEG(tmp,src);\n");
+	}
+
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0);\n");
+	genflags(flag_sub, curi->size, "", "src", "dst");
+	genastore("dst", curi->smode, "srcreg", curi->size, "src");
+#endif
+}
+
+static void gen_negx(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	isaddx;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int dst=scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_inverted_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_NEGX_%s(dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+		comprintf("\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t restore_inverted_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_NEGX(dst,src);\n");
+	}
+
+	genastore("dst", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) ssize;
+	isaddx;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0);\n");
+	genflags(flag_subx, curi->size, "", "src", "dst");
+	genastore("dst", curi->smode, "srcreg", curi->size, "src");
+#endif
+}
+
+static void gen_not(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_NOT_%s(tmp,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_NOT(tmp,src);\n", ssize);
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0xffffffff);\n");
+	genflags(flag_eor, curi->size, "", "src", "dst");
+	genastore("dst", curi->smode, "srcreg", curi->size, "src");
+#endif
+}
+
+static void gen_or(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t jff_OR_%s(tmp, dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_OR(tmp, dst,src);\n");
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags(flag_or, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_orsr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ORSR(ARM_CCR_MAP[src & 0xF], ((src & 0x10) >> 4));\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	}
+#else
+	(void) curi;
+	failure;
+	isjump;
+#endif
+}
+
+static void gen_rol(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROL_%s(tmp,data,cnt);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_ROL_%s(tmp,data,cnt);\n", ssize);
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) ssize;
+
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace();
+
+	switch (curi->size) {
+	case sz_long:
+		comprintf("\t rol_l_rr(data,cnt);\n");
+		break;
+	case sz_word:
+		comprintf("\t rol_w_rr(data,cnt);\n");
+		break;
+	case sz_byte:
+		comprintf("\t rol_b_rr(data,cnt);\n");
+		break;
+	}
+
+	if (!noflags) {
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\t  test_b_rr(data,data);\n");
+			break;
+		case sz_word:
+			comprintf("\t  test_w_rr(data,data);\n");
+			break;
+		case sz_long:
+			comprintf("\t  test_l_rr(data,data);\n");
+			break;
+		}
+		comprintf("\t bt_l_ri(data,0x00);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	}
+	genastore("data", curi->dmode, "dstreg", curi->size, "data");
+#endif
+}
+
+static void gen_rolw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp = scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROLW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_ROLW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_ror(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROR_%s(tmp,data,cnt);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_ROR_%s(tmp,data,cnt);\n", ssize);
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) ssize;
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace();
+
+	switch (curi->size) {
+	case sz_long:
+		comprintf("\t ror_l_rr(data,cnt);\n");
+		break;
+	case sz_word:
+		comprintf("\t ror_w_rr(data,cnt);\n");
+		break;
+	case sz_byte:
+		comprintf("\t ror_b_rr(data,cnt);\n");
+		break;
+	}
+
+	if (!noflags) {
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\t  test_b_rr(data,data);\n");
+			break;
+		case sz_word:
+			comprintf("\t  test_w_rr(data,data);\n");
+			break;
+		case sz_long:
+			comprintf("\t  test_l_rr(data,data);\n");
+			break;
+		}
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\t bt_l_ri(data,0x07);\n");
+			break;
+		case sz_word:
+			comprintf("\t bt_l_ri(data,0x0f);\n");
+			break;
+		case sz_long:
+			comprintf("\t bt_l_ri(data,0x1f);\n");
+			break;
+		}
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	}
+	genastore("data", curi->dmode, "dstreg", curi->size, "data");
+#endif
+}
+
+static void gen_rorw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp = scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_RORW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	} else {
+		comprintf("\t jnf_RORW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_roxl(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	isaddx;
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROXL_%s(tmp,data,cnt);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+	} else {
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_ROXL_%s(tmp,data,cnt);\n", ssize);
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) curi;
+	(void) ssize;
+	failure;
+#endif
+}
+
+static void gen_roxlw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	isaddx;
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp = scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROXLW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+	} else {
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_ROXLW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_roxr(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	mayfail;
+	if (curi->smode == Dreg) {
+		comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+				"  FAIL(1);\n"
+				"  return;\n"
+				"} \n");
+		start_brace();
+	}
+	isaddx;
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace();
+	comprintf("\t int tmp=scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROXR_%s(tmp,data,cnt);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+	} else {
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_ROXR_%s(tmp,data,cnt);\n", ssize);
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "data");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_roxrw(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	isaddx;
+	comprintf("\t dont_care_flags();\n");
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace();
+	comprintf("\t int tmp = scratchie++;\n");
+
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_ROXRW(tmp,src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+	} else {
+		comprintf("\t restore_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_ROXRW(tmp,src);\n");
+	}
+	genastore("tmp", curi->smode, "srcreg", curi->size, "src");
+#else
+	(void) curi;
+	failure;
+#endif
+}
+
+static void gen_sbcd(uae_u32 opcode, struct instr *curi, const char* ssize) {
+#if 0
+#else
+	(void) opcode;
+	(void) curi;
+	(void) ssize;
+	failure;
+	/* I don't think so! */
+#endif
+}
+
+static void gen_scc(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if 0
+	genamode(curi->smode, "srcreg", curi->size, "src", 2, 0);
+	start_brace();
+	comprintf("\t int val = scratchie++;\n");
+	switch (curi->cc) {
+		case 0: /* Unconditional set */
+		case 1:
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 8:
+		case 9:
+		case 10:
+		case 11:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+		comprintf("\t make_flags_live();\n"); /* Load the flags */
+		comprintf("\t jnf_Scc_ri(val,%d);\n", curi->cc);
+		break;
+		default:
+		assert(0);
+		break;
+	}
+	genastore("val", curi->smode, "srcreg", curi->size, "src");
+#else
+	genamode(curi->smode, "srcreg", curi->size, "src", 2, 0);
+	start_brace();
+	comprintf("\tint val = scratchie++;\n");
+
+	/* We set val to 0 if we really should use 255, and to 1 for real 0 */
+	switch (curi->cc) {
+	case 0: /* Unconditional set */
+		comprintf("\tmov_l_ri(val,0);\n");
+		break;
+	case 1:
+		/* Unconditional not-set */
+		comprintf("\tmov_l_ri(val,1);\n");
+		break;
+	case 8:
+		failure;
+		break; /* Work out details! FIXME */
+	case 9:
+		failure;
+		break; /* Not critical, though! */
+
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+	case 10:
+	case 11:
+	case 12:
+	case 13:
+	case 14:
+	case 15:
+		comprintf("\tmake_flags_live();\n"); /* Load the flags */
+		/* All condition codes can be inverted by changing the LSB */
+		comprintf("\tsetcc(val,%d);\n", cond_codes[curi->cc] ^ 1);
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	comprintf("\tsub_b_ri(val,1);\n");
+	genastore("val", curi->smode, "srcreg", curi->size, "src");
+#endif
+}
+
+static void gen_sub(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+	// Use tmp register to avoid destroying upper part in .B., .W cases
+	comprintf("\t int tmp=scratchie++;\n");
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_SUB_%s(tmp,dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+		comprintf(
+				"\t if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t jnf_SUB_%s(tmp,dst,src);\n", ssize);
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags(flag_sub, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_suba(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\t jnf_SUBA_%s(dst, src);\n", ssize);
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#else
+	(void) ssize;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n");
+	switch (curi->size) {
+	case sz_byte:
+		comprintf("\tsign_extend_8_rr(tmp,src);\n");
+		break;
+	case sz_word:
+		comprintf("\tsign_extend_16_rr(tmp,src);\n");
+		break;
+	case sz_long:
+		comprintf("\ttmp=src;\n");
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	comprintf("\tsub_l(dst,tmp);\n");
+	genastore("dst", curi->dmode, "dstreg", sz_long, "dst");
+#endif
+}
+
+static void gen_subx(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+#if defined(USE_JIT2)
+	isaddx;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n");
+	comprintf("\tdont_care_flags();\n");
+	if (!noflags) {
+		comprintf("\t make_flags_live();\n");
+		comprintf("\t restore_inverted_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_SUBX_%s(tmp,dst,src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		duplicate_carry();
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t restore_inverted_carry();\n"); /* Reload the X flag into C */
+		comprintf("\t jnf_SUBX(tmp,dst,src);\n");
+	}
+	genastore("tmp", curi->dmode, "dstreg", curi->size, "dst");
+#else
+	(void) ssize;
+	isaddx;
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags(flag_subx, curi->size, "", "src", "dst");
+	genastore("dst", curi->dmode, "dstreg", curi->size, "dst");
+#endif
+}
+
+static void gen_swap(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", sz_long, "src", 1, 0);
+	comprintf("\t dont_care_flags();\n");
+	start_brace();
+
+	if (!noflags) {
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_SWAP(src);\n");
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	} else {
+		comprintf("\t jnf_SWAP(src);\n");
+	}
+	genastore("src", curi->smode, "srcreg", sz_long, "src");
+#else
+	genamode(curi->smode, "srcreg", sz_long, "src", 1, 0);
+	comprintf("\tdont_care_flags();\n");
+	comprintf("\tarm_ROR_l_ri8(src,16);\n");
+	genflags(flag_logical, sz_long, "src", "", "");
+	genastore("src", curi->smode, "srcreg", sz_long, "src");
+#endif
+}
+
+static void gen_tst(uae_u32 opcode, struct instr *curi, const char* ssize) {
+	(void) opcode;
+	(void) ssize;
+#if defined(USE_JIT2)
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	comprintf("\t dont_care_flags();\n");
+	if (!noflags) {
+		start_brace();
+		comprintf("\t start_needflags();\n");
+		comprintf("\t jff_TST_%s(src);\n", ssize);
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+	}
+#else
+	genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genflags(flag_logical, curi->size, "src", "", "");
+#endif
+}
+
+static int /* returns zero for success, non-zero for failure */
+gen_opcode(unsigned long int opcode) {
+	struct instr *curi = table68k + opcode;
+	const char* ssize = NULL;
+
+	insn_n_cycles = 2;
+	global_failure = 0;
+	long_opcode = 0;
+	global_isjump = 0;
+	global_iscjump = 0;
+	global_isaddx = 0;
+	global_cmov = 0;
+	global_fpu = 0;
+	global_mayfail = 0;
+	hack_opcode = opcode;
+	endstr[0] = 0;
+
+	start_brace();
+	comprintf("\tuae_u8 scratchie=S1;\n");
+	switch (curi->plev) {
+	case 0: /* not privileged */
+		break;
+	case 1: /* unprivileged only on 68000 */
+		if (cpu_level == 0)
+			break;
+		if (next_cpu_level < 0)
+			next_cpu_level = 0;
+
+		/* fall through */
+	case 2: /* priviledged */
+		failure; /* Easy ones first */
+		break;
+	case 3: /* privileged if size == word */
+		if (curi->size == sz_byte)
+			break;
+		failure;
+		break;
+	}
+	switch (curi->size) {
+	case sz_byte:
+		ssize = "b";
+		break;
+	case sz_word:
+		ssize = "w";
+		break;
+	case sz_long:
+		ssize = "l";
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	(void) ssize;
+
+	switch (curi->mnemo) {
+	case i_AND:
+		gen_and(opcode, curi, ssize);
+		break;
+
+	case i_OR:
+		gen_or(opcode, curi, ssize);
+		break;
+
+	case i_EOR:
+		gen_eor(opcode, curi, ssize);
+		break;
+
+	case i_ORSR:
+		gen_orsr(opcode, curi, ssize);
+		break;
+
+	case i_EORSR:
+		gen_eorsr(opcode, curi, ssize);
+		break;
+
+	case i_ANDSR:
+		gen_andsr(opcode, curi, ssize);
+		break;
+
+	case i_SUB:
+		gen_sub(opcode, curi, ssize);
+		break;
+
+	case i_SUBA:
+		gen_suba(opcode, curi, ssize);
+		break;
+
+	case i_SUBX:
+		gen_subx(opcode, curi, ssize);
+		break;
+
+	case i_SBCD:
+		gen_sbcd(opcode, curi, ssize);
+		break;
+
+	case i_ADD:
+		gen_add(opcode, curi, ssize);
+		break;
+
+	case i_ADDA:
+		gen_adda(opcode, curi, ssize);
+		break;
+
+	case i_ADDX:
+		gen_addx(opcode, curi, ssize);
+		break;
+
+	case i_ABCD:
+		gen_abcd(opcode, curi, ssize);
+		break;
+
+	case i_NEG:
+		gen_neg(opcode, curi, ssize);
+		break;
+
+	case i_NEGX:
+		gen_negx(opcode, curi, ssize);
+		break;
+
+	case i_NBCD:
+		gen_nbcd(opcode, curi, ssize);
+		break;
+
+	case i_CLR:
+		gen_clr(opcode, curi, ssize);
+		break;
+
+	case i_NOT:
+		gen_not(opcode, curi, ssize);
+		break;
+
+	case i_TST:
+		gen_tst(opcode, curi, ssize);
+		break;
+
+	case i_BCHG:
+		gen_bchg(opcode, curi, ssize);
+		break;
+
+	case i_BCLR:
+		gen_bclr(opcode, curi, ssize);
+		break;
+
+	case i_BSET:
+		gen_bset(opcode, curi, ssize);
+		break;
+
+	case i_BTST:
+		gen_btst(opcode, curi, ssize);
+		break;
+
+	case i_CMPM:
+	case i_CMP:
+		gen_cmp(opcode, curi, ssize);
+		break;
+
+	case i_CMPA:
+		gen_cmpa(opcode, curi, ssize);
+		break;
+
+		/* The next two are coded a little unconventional, but they are doing
+		 * weird things... */
+	case i_MVPRM:
+		isjump;
+		failure;
+		break;
+
+	case i_MVPMR:
+		isjump;
+		failure;
+		break;
+
+	case i_MOVE:
+		gen_move(opcode, curi, ssize);
+		break;
+
+	case i_MOVEA:
+		gen_movea(opcode, curi, ssize);
+		break;
+
+	case i_MVSR2:
+		isjump;
+		failure;
+		break;
+
+	case i_MV2SR:
+		isjump;
+		failure;
+		break;
+
+	case i_SWAP:
+		gen_swap(opcode, curi, ssize);
+		break;
+
+	case i_EXG:
+		gen_exg(opcode, curi, ssize);
+		break;
+
+	case i_EXT:
+		gen_ext(opcode, curi, ssize);
+		break;
+
+	case i_MVMEL:
+		genmovemel(opcode);
+		break;
+
+	case i_MVMLE:
+		genmovemle(opcode);
+		break;
+
+	case i_TRAP:
+		isjump;
+		failure;
+		break;
+
+	case i_MVR2USP:
+		isjump;
+		failure;
+		break;
+
+	case i_MVUSP2R:
+		isjump;
+		failure;
+		break;
+
+	case i_RESET:
+		isjump;
+		failure;
+		break;
+
+	case i_NOP:
+		break;
+
+	case i_STOP:
+		isjump;
+		failure;
+		break;
+
+	case i_RTE:
+		isjump;
+		failure;
+		break;
+
+	case i_RTD:
+		genamode(curi->smode, "srcreg", curi->size, "offs", 1, 0);
+		/* offs is constant */
+		comprintf("\tarm_ADD_l_ri8(offs,4);\n");
+		start_brace();
+		comprintf("\tint newad=scratchie++;\n"
+				"\treadlong(15,newad,scratchie);\n"
+				"\tmov_l_mr((uintptr)&regs.pc,newad);\n"
+				"\tget_n_addr_jmp(newad,PC_P,scratchie);\n"
+				"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
+				"\tm68k_pc_offset=0;\n"
+				"\tarm_ADD_l(15,offs);\n");
+		gen_update_next_handler();
+		isjump;
+		break;
+
+	case i_LINK:
+		genamode(curi->smode, "srcreg", sz_long, "src", 1, 0);
+		genamode(curi->dmode, "dstreg", curi->size, "offs", 1, 0);
+		comprintf("\tsub_l_ri(15,4);\n"
+				"\twritelong_clobber(15,src,scratchie);\n"
+				"\tmov_l_rr(src,15);\n");
+		if (curi->size == sz_word)
+			comprintf("\tsign_extend_16_rr(offs,offs);\n");
+		comprintf("\tarm_ADD_l(15,offs);\n");
+		genastore("src", curi->smode, "srcreg", sz_long, "src");
+		break;
+
+	case i_UNLK:
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		comprintf("\tmov_l_rr(15,src);\n"
+				"\treadlong(15,src,scratchie);\n"
+				"\tarm_ADD_l_ri8(15,4);\n");
+		genastore("src", curi->smode, "srcreg", curi->size, "src");
+		break;
+
+	case i_RTS:
+		comprintf("\tint newad=scratchie++;\n"
+				"\treadlong(15,newad,scratchie);\n"
+				"\tmov_l_mr((uintptr)&regs.pc,newad);\n"
+				"\tget_n_addr_jmp(newad,PC_P,scratchie);\n"
+				"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
+				"\tm68k_pc_offset=0;\n"
+				"\tlea_l_brr(15,15,4);\n");
+		gen_update_next_handler();
+		isjump;
+		break;
+
+	case i_TRAPV:
+		isjump;
+		failure;
+		break;
+
+	case i_RTR:
+		isjump;
+		failure;
+		break;
+
+	case i_JSR:
+		isjump;
+		genamode(curi->smode, "srcreg", curi->size, "src", 0, 0);
+		start_brace();
+		comprintf(
+				"\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
+		comprintf("\tint ret=scratchie++;\n"
+				"\tmov_l_ri(ret,retadd);\n"
+				"\tsub_l_ri(15,4);\n"
+				"\twritelong_clobber(15,ret,scratchie);\n");
+		comprintf("\tmov_l_mr((uintptr)&regs.pc,srca);\n"
+				"\tget_n_addr_jmp(srca,PC_P,scratchie);\n"
+				"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
+				"\tm68k_pc_offset=0;\n");
+		gen_update_next_handler();
+		break;
+
+	case i_JMP:
+		isjump;
+		genamode(curi->smode, "srcreg", curi->size, "src", 0, 0);
+		comprintf("\tmov_l_mr((uintptr)&regs.pc,srca);\n"
+				"\tget_n_addr_jmp(srca,PC_P,scratchie);\n"
+				"\tmov_l_mr((uintptr)&regs.pc_oldp,PC_P);\n"
+				"\tm68k_pc_offset=0;\n");
+		gen_update_next_handler();
+		break;
+
+	case i_BSR:
+		is_const_jump;
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		if (curi->size == sz_long) {
+			/* Sign-extend 32-bit long displacement to native pointer width.
+			 * comp_get_ilong returns uae_u32 which zero-extends to uintptr on
+			 * 64-bit platforms, but BSR displacement is signed. Without this,
+			 * backward branches corrupt comp_pc_p (upper bits overflow). */
+			comprintf("\tif (isconst(src)) live.state[src].val = (uintptr)(uae_s32)(uae_u32)live.state[src].val;\n");
+		}
+		start_brace();
+		comprintf(
+				"\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
+		comprintf("\tint ret=scratchie++;\n"
+				"\tmov_l_ri(ret,retadd);\n"
+				"\tsub_l_ri(15,4);\n"
+				"\twritelong_clobber(15,ret,scratchie);\n");
+		comprintf("\tarm_ADD_l_ri(src,m68k_pc_offset_thisinst+2);\n");
+		comprintf("\tm68k_pc_offset=0;\n");
+		comprintf("\tarm_ADD_l(PC_P,src);\n");
+		comprintf("\tcomp_pc_p=(uae_u8*)get_const(PC_P);\n");
+		break;
+
+	case i_Bcc:
+		comprintf("\tuintptr v,v1,v2;\n");
+		genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
+		/* That source is an immediate, so we can clobber it with abandon */
+		switch (curi->size) {
+		case sz_byte:
+			comprintf("\tsign_extend_8_rr(src,src);\n");
+			break;
+		case sz_word:
+			comprintf("\tsign_extend_16_rr(src,src);\n");
+			break;
+		case sz_long:
+			/* Sign-extend 32-bit long displacement to native pointer width.
+			 * comp_get_ilong returns uae_u32 which zero-extends to uintptr on
+			 * 64-bit platforms, but Bcc displacement is signed. Without this,
+			 * backward branches compute wrong target addresses (upper bits overflow). */
+			comprintf("\tif (isconst(src)) live.state[src].val = (uintptr)(uae_s32)(uae_u32)live.state[src].val;\n");
+			break;
+		}
+		comprintf(
+				"\tsub_l_ri(src,m68k_pc_offset-m68k_pc_offset_thisinst-2);\n");
+		/* Leave the following as "add" --- it will allow it to be optimized
+		 away due to src being a constant ;-) */
+		comprintf("\tarm_ADD_l_ri(src,(uintptr)comp_pc_p);\n");
+		comprintf("\tmov_l_ri(PC_P,(uintptr)comp_pc_p);\n");
+		/* Now they are both constant. Might as well fold in m68k_pc_offset */
+		comprintf("\tarm_ADD_l_ri(src,m68k_pc_offset);\n");
+		comprintf("\tarm_ADD_l_ri(PC_P,m68k_pc_offset);\n");
+		comprintf("\tm68k_pc_offset=0;\n");
+
+		if (curi->cc >= 2) {
+			comprintf("\tv1=get_const(PC_P);\n"
+					"\tv2=get_const(src);\n"
+					"\tregister_branch(v1,v2,%d);\n", cond_codes[curi->cc]);
+			comprintf("\tmake_flags_live();\n"); /* Load the flags */
+			isjump;
+		} else {
+			is_const_jump;
+		}
+
+		switch (curi->cc) {
+		case 0: /* Unconditional jump */
+			comprintf("\tmov_l_rr(PC_P,src);\n");
+			comprintf("\tcomp_pc_p=(uae_u8*)get_const(PC_P);\n");
+			break;
+		case 1:
+			break; /* This is silly! */
+		case 8:
+			failure;
+			break; /* Work out details! FIXME */
+		case 9:
+			failure;
+			break; /* Not critical, though! */
+
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 10:
+		case 11:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+			break;
+		default:
+			assert(0);
+			break;
+		}
+		break;
+
+	case i_LEA:
+		genamode(curi->smode, "srcreg", curi->size, "src", 0, 0);
+		genamode(curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+		genastore("srca", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+
+	case i_PEA:
+		if (table68k[opcode].smode == Areg || table68k[opcode].smode == Aind
+				|| table68k[opcode].smode == Aipi
+				|| table68k[opcode].smode == Apdi
+				|| table68k[opcode].smode == Ad16
+				|| table68k[opcode].smode == Ad8r)
+			comprintf("if (srcreg==7) dodgy=1;\n");
+
+		genamode(curi->smode, "srcreg", curi->size, "src", 0, 0);
+		genamode(Apdi, "7", sz_long, "dst", 2, 0);
+		genastore("srca", Apdi, "7", sz_long, "dst");
+		break;
+
+	case i_DBcc:
+		gen_dbcc(opcode, curi, ssize);
+		break;
+
+	case i_Scc:
+		gen_scc(opcode, curi, ssize);
+		break;
+
+	case i_DIVU:
+		isjump;
+		failure;
+		break;
+
+	case i_DIVS:
+		isjump;
+		failure;
+		break;
+
+	case i_MULU:
+		gen_mulu(opcode, curi, ssize);
+		break;
+
+	case i_MULS:
+		gen_muls(opcode, curi, ssize);
+		break;
+
+	case i_CHK:
+		isjump;
+		failure;
+		break;
+
+	case i_CHK2:
+		isjump;
+		failure;
+		break;
+
+	case i_ASR:
+		gen_asr(opcode, curi, ssize);
+		break;
+
+	case i_ASL:
+		gen_asl(opcode, curi, ssize);
+		break;
+
+	case i_LSR:
+		gen_lsr(opcode, curi, ssize);
+		break;
+
+	case i_LSL:
+		gen_lsl(opcode, curi, ssize);
+		break;
+
+	case i_ROL:
+		gen_rol(opcode, curi, ssize);
+		break;
+
+	case i_ROR:
+		gen_ror(opcode, curi, ssize);
+		break;
+
+	case i_ROXL:
+		gen_roxl(opcode, curi, ssize);
+		break;
+
+	case i_ROXR:
+		gen_roxr(opcode, curi, ssize);
+		break;
+
+	case i_ASRW:
+		gen_asrw(opcode, curi, ssize);
+		break;
+
+	case i_ASLW:
+		gen_aslw(opcode, curi, ssize);
+		break;
+
+	case i_LSRW:
+		gen_lsrw(opcode, curi, ssize);
+		break;
+
+	case i_LSLW:
+		gen_lslw(opcode, curi, ssize);
+		break;
+
+	case i_ROLW:
+		gen_rolw(opcode, curi, ssize);
+		break;
+
+	case i_RORW:
+		gen_rorw(opcode, curi, ssize);
+		break;
+
+	case i_ROXLW:
+		gen_roxlw(opcode, curi, ssize);
+		break;
+
+	case i_ROXRW:
+		gen_roxrw(opcode, curi, ssize);
+		break;
+
+	case i_MOVEC2:
+		isjump;
+		failure;
+		break;
+
+	case i_MOVE2C:
+		isjump;
+		failure;
+		break;
+
+	case i_CAS:
+		failure;
+		break;
+
+	case i_CAS2:
+		failure;
+		break;
+
+	case i_MOVES:
+		/* ignore DFC and SFC because we have no MMU */
+		isjump;
+		failure;
+		break;
+
+	case i_BKPT:
+		/* only needed for hardware emulators */
+		isjump;
+		failure;
+		break;
+
+	case i_CALLM:
+		/* not present in 68030 */
+		isjump;
+		failure;
+		break;
+
+	case i_RTM:
+		/* not present in 68030 */
+		isjump;
+		failure;
+		break;
+
+	case i_TRAPcc:
+		isjump;
+		failure;
+		break;
+
+	case i_DIVL:
+		isjump;
+		failure;
+		break;
+
+	case i_MULL:
+		gen_mull(opcode, curi, ssize);
+		break;
+
+	case i_BFTST:
+	case i_BFEXTU:
+	case i_BFCHG:
+	case i_BFEXTS:
+	case i_BFCLR:
+	case i_BFFFO:
+	case i_BFSET:
+	case i_BFINS:
+		failure;
+		break;
+	case i_PACK:
+		failure;
+		break;
+	case i_UNPK:
+		failure;
+		break;
+	case i_TAS:
+		failure;
+		break;
+	case i_FPP:
+		uses_fpu;
+#ifdef USE_JIT_FPU
+		mayfail;
+		comprintf("\tuae_u16 extra=%s;\n",gen_nextiword());
+		swap_opcode();
+		comprintf("\tcomp_fpp_opp(opcode,extra);\n");
+#else
+		failure;
+#endif
+		break;
+	case i_FBcc:
+		uses_fpu;
+#ifdef USE_JIT_FPU
+		isjump;
+		uses_cmov;
+		mayfail;
+		swap_opcode();
+		comprintf("\tcomp_fbcc_opp(opcode);\n");
+#else
+		isjump;
+		failure;
+#endif
+		break;
+	case i_FDBcc:
+		uses_fpu;
+		isjump;
+		failure;
+		break;
+	case i_FScc:
+		uses_fpu;
+#ifdef USE_JIT_FPU
+		mayfail;
+		uses_cmov;
+		comprintf("\tuae_u16 extra=%s;\n",gen_nextiword());
+		swap_opcode();
+		comprintf("\tcomp_fscc_opp(opcode,extra);\n");
+#else
+		failure;
+#endif
+		break;
+	case i_FTRAPcc:
+		uses_fpu;
+		isjump;
+		failure;
+		break;
+	case i_FSAVE:
+		uses_fpu;
+		failure;
+		break;
+	case i_FRESTORE:
+		uses_fpu;
+		failure;
+		break;
+
+	case i_CINVL:
+	case i_CINVP:
+	case i_CINVA:
+		isjump; /* Not really, but it's probably a good idea to stop
+		 translating at this point */
+		failure;
+		comprintf("\tflush_icache();\n"); /* Differentiate a bit more? */
+		break;
+	case i_CPUSHL:
+	case i_CPUSHP:
+	case i_CPUSHA:
+		isjump; /* Not really, but it's probably a good idea to stop
+		 translating at this point */
+		failure;
+		break;
+
+	case i_MOVE16:
+		gen_move16(opcode, curi);
+		break;
+
+#ifdef UAE
+	case i_MMUOP030:
+	case i_PFLUSHN:
+	case i_PFLUSH:
+	case i_PFLUSHAN:
+	case i_PFLUSHA:
+	case i_PLPAR:
+	case i_PLPAW:
+	case i_PTESTR:
+	case i_PTESTW:
+	case i_LPSTOP:
+	case i_PULSE:
+	case i_HALT:
+		isjump;
+		failure;
+		break;
+#endif
+	case i_EMULOP_RETURN:
+		isjump;
+		failure;
+		break;
+
+	case i_EMULOP:
+		failure;
+		break;
+
+	case i_NATFEAT_ID:
+	case i_NATFEAT_CALL:
+		failure;
+		break;
+
+	case i_MMUOP:
+		isjump;
+		failure;
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	comprintf("%s", endstr);
+	finish_braces();
+	sync_m68k_pc();
+	if (global_mayfail)
+		comprintf("\tif (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;\n");
+	return global_failure;
+}
+
+static void generate_includes(FILE * f) {
+	fprintf(f, "#include \"sysdeps.h\"\n");
+	fprintf(f, "#include \"machdep/m68k.h\"\n");
+	fprintf(f, "#include \"memory-uae.h\"\n");
+	fprintf(f, "#include \"readcpu.h\"\n");
+	fprintf(f, "#include \"newcpu.h\"\n");
+	fprintf(f, "#include \"comptbl.h\"\n");
+	fprintf(f, "#include \"debug.h\"\n");
+}
+
+static int postfix;
+
+static char *decodeEA (amodes mode, wordsizes size)
+{
+	static char buffer[80];
+
+	buffer[0] = 0;
+	switch (mode){
+	case Dreg:
+		strcpy (buffer,"Dn");
+		break;
+	case Areg:
+		strcpy (buffer,"An");
+		break;
+	case Aind:
+		strcpy (buffer,"(An)");
+		break;
+	case Aipi:
+		strcpy (buffer,"(An)+");
+		break;
+	case Apdi:
+		strcpy (buffer,"-(An)");
+		break;
+	case Ad16:
+		strcpy (buffer,"(d16,An)");
+		break;
+	case Ad8r:
+		strcpy (buffer,"(d8,An,Xn)");
+		break;
+	case PC16:
+		strcpy (buffer,"(d16,PC)");
+		break;
+	case PC8r:
+		strcpy (buffer,"(d8,PC,Xn)");
+		break;
+	case absw:
+		strcpy (buffer,"(xxx).W");
+		break;
+	case absl:
+		strcpy (buffer,"(xxx).L");
+		break;
+	case imm:
+		switch (size){
+		case sz_byte:
+			strcpy (buffer,"#<data>.B");
+			break;
+		case sz_word:
+			strcpy (buffer,"#<data>.W");
+			break;
+		case sz_long:
+			strcpy (buffer,"#<data>.L");
+			break;
+		default:
+			break;
+		}
+		break;
+	case imm0:
+		strcpy (buffer,"#<data>.B");
+		break;
+	case imm1:
+		strcpy (buffer,"#<data>.W");
+		break;
+	case imm2:
+		strcpy (buffer,"#<data>.L");
+		break;
+	case immi:
+		strcpy (buffer,"#<data>");
+		break;
+
+	default:
+		break;
+	}
+	return buffer;
+}
+
+static char *outopcode (const char *name, int opcode)
+{
+	static char out[100];
+	struct instr *ins;
+
+	ins = &table68k[opcode];
+	strcpy (out, name);
+	if (ins->smode == immi)
+		strcat (out, "Q");
+	if (ins->size == sz_byte)
+		strcat (out,".B");
+	if (ins->size == sz_word)
+		strcat (out,".W");
+	if (ins->size == sz_long)
+		strcat (out,".L");
+	strcat (out," ");
+	if (ins->suse)
+		strcat (out, decodeEA (ins->smode, ins->size));
+	if (ins->duse) {
+		if (ins->suse) strcat (out,",");
+		strcat (out, decodeEA (ins->dmode, ins->size));
+	}
+	return out;
+}
+
+
+static void generate_one_opcode(int rp, int noflags) {
+	int i;
+	uae_u16 smsk, dmsk;
+	int opcode = opcode_map[rp];
+	int aborted = 0;
+	int have_srcreg = 0;
+	int have_dstreg = 0;
+	const char *name;
+
+	if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
+		return;
+
+	for (i = 0; lookuptab[i].name[0]; i++) {
+		if (table68k[opcode].mnemo == lookuptab[i].mnemo)
+			break;
+	}
+
+	if (table68k[opcode].handler != -1)
+		return;
+
+	switch (table68k[opcode].stype) {
+	case 0:
+		smsk = 7;
+		break;
+	case 1:
+		smsk = 255;
+		break;
+	case 2:
+		smsk = 15;
+		break;
+	case 3:
+		smsk = 7;
+		break;
+	case 4:
+		smsk = 7;
+		break;
+	case 5:
+		smsk = 63;
+		break;
+	case 6:
+		smsk = 255;
+		break;
+	case 7:
+		smsk = 3;
+		break;
+	default:
+		assert(0);
+		break;
+	}
+	dmsk = 7;
+
+	next_cpu_level = -1;
+	if (table68k[opcode].suse && table68k[opcode].smode != imm
+			&& table68k[opcode].smode != imm0 && table68k[opcode].smode != imm1
+			&& table68k[opcode].smode != imm2 && table68k[opcode].smode != absw
+			&& table68k[opcode].smode != absl && table68k[opcode].smode != PC8r
+			&& table68k[opcode].smode != PC16) {
+		have_srcreg = 1;
+		if (table68k[opcode].spos == -1) {
+			if (((int) table68k[opcode].sreg) >= 128)
+				comprintf("\tuae_s32 srcreg = (uae_s32)(uae_s8)%d;\n",
+						(int) table68k[opcode].sreg);
+			else
+				comprintf("\tuae_s32 srcreg = %d;\n",
+						(int) table68k[opcode].sreg);
+		} else {
+			char source[100];
+			int pos = table68k[opcode].spos;
+
+			comprintf(
+					"#if defined(HAVE_GET_WORD_UNSWAPPED) && !defined(FULLMMU)\n");
+
+			if (pos < 8 && (smsk >> (8 - pos)) != 0)
+				sprintf(source, "(((opcode >> %d) | (opcode << %d)) & %d)",
+						pos ^ 8, 8 - pos, dmsk);
+			else if (pos != 8)
+				sprintf(source, "((opcode >> %d) & %d)", pos ^ 8, smsk);
+			else
+				sprintf(source, "(opcode & %d)", smsk);
+
+			if (table68k[opcode].stype == 3)
+				comprintf("\tuae_u32 srcreg = imm8_table[%s];\n", source);
+			else if (table68k[opcode].stype == 1)
+				comprintf("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
+			else
+				comprintf("\tuae_u32 srcreg = %s;\n", source);
+
+			comprintf("#else\n");
+
+			if (pos)
+				sprintf(source, "((opcode >> %d) & %d)", pos, smsk);
+			else
+				sprintf(source, "(opcode & %d)", smsk);
+
+			if (table68k[opcode].stype == 3)
+				comprintf("\tuae_s32 srcreg = imm8_table[%s];\n", source);
+			else if (table68k[opcode].stype == 1)
+				comprintf("\tuae_s32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
+			else
+				comprintf("\tuae_s32 srcreg = %s;\n", source);
+
+			comprintf("#endif\n");
+		}
+	}
+	if (table68k[opcode].duse
+	/* Yes, the dmode can be imm, in case of LINK or DBcc */
+	&& table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
+			&& table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
+			&& table68k[opcode].dmode != absw
+			&& table68k[opcode].dmode != absl) {
+		have_dstreg = 1;
+		if (table68k[opcode].dpos == -1) {
+			if (((int) table68k[opcode].dreg) >= 128)
+				comprintf("\tuae_s32 dstreg = (uae_s32)(uae_s8)%d;\n",
+						(int) table68k[opcode].dreg);
+			else
+				comprintf("\tuae_s32 dstreg = %d;\n",
+						(int) table68k[opcode].dreg);
+		} else {
+			int pos = table68k[opcode].dpos;
+
+			comprintf(
+					"#if defined(HAVE_GET_WORD_UNSWAPPED) && !defined(FULLMMU)\n");
+
+			if (pos < 8 && (dmsk >> (8 - pos)) != 0)
+				comprintf(
+						"\tuae_u32 dstreg = ((opcode >> %d) | (opcode << %d)) & %d;\n",
+						pos ^ 8, 8 - pos, dmsk);
+			else if (pos != 8)
+				comprintf("\tuae_u32 dstreg = (opcode >> %d) & %d;\n", pos ^ 8,
+						dmsk);
+			else
+				comprintf("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
+
+			comprintf("#else\n");
+
+			if (pos)
+				comprintf("\tuae_u32 dstreg = (opcode >> %d) & %d;\n", pos,
+						dmsk);
+			else
+				comprintf("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
+
+			comprintf("#endif\n");
+		}
+	}
+
+	if (have_srcreg && have_dstreg
+			&& (table68k[opcode].dmode == Areg || table68k[opcode].dmode == Aind
+					|| table68k[opcode].dmode == Aipi
+					|| table68k[opcode].dmode == Apdi
+					|| table68k[opcode].dmode == Ad16
+					|| table68k[opcode].dmode == Ad8r)
+			&& (table68k[opcode].smode == Areg || table68k[opcode].smode == Aind
+					|| table68k[opcode].smode == Aipi
+					|| table68k[opcode].smode == Apdi
+					|| table68k[opcode].smode == Ad16
+					|| table68k[opcode].smode == Ad8r)) {
+		comprintf("\tuae_u32 dodgy=(srcreg==(uae_s32)dstreg);\n");
+	} else {
+		comprintf("\tuae_u32 dodgy=0;\n");
+	}
+	comprintf("\tuae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;\n");
+	comprintf("\tm68k_pc_offset+=2;\n");
+
+	aborted = gen_opcode(opcode);
+	{
+		int flags = 0;
+		if (global_isjump)
+			flags |= 1;
+		if (long_opcode)
+			flags |= 2;
+		if (global_cmov)
+			flags |= 4;
+		if (global_isaddx)
+			flags |= 8;
+		if (global_iscjump)
+			flags |= 16;
+		if (global_fpu)
+			flags |= 32;
+
+		comprintf("}\n");
+
+		name = lookuptab[i].name;
+		if (aborted) {
+			fprintf(stblfile, "{ NULL, 0x%08x, %d }, /* %s */\n", opcode, flags, name);
+			com_discard();
+		} else {
+			const char *tbl = noflags ? "nf" : "ff";
+			fprintf(stblfile,
+					"{ op_%x_%d_comp_%s, %d, 0x%08x }, /* %s */\n",
+					opcode, postfix, tbl, opcode, flags, name);
+			fprintf(headerfile, "extern compop_func op_%x_%d_comp_%s;\n",
+					opcode, postfix, tbl);
+			printf ("/* %s */\n", outopcode (name, opcode));
+			printf(
+					"void REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode) /* %s */\n{\n",
+					opcode, postfix, tbl, name);
+			com_flush();
+		}
+	}
+	opcode_next_clev[rp] = next_cpu_level;
+	opcode_last_postfix[rp] = postfix;
+}
+
+static void generate_func(int noflags) {
+	int i, j, rp;
+	const char *tbl = noflags ? "nf" : "ff";
+
+	using_prefetch = 0;
+	using_exception_3 = 0;
+	for (i = 0; i < 1; i++) /* We only do one level! */
+	{
+		cpu_level = 4 - i;
+		postfix = i;
+
+		fprintf(stblfile, "const struct comptbl op_smalltbl_%d_comp_%s[] = {\n",
+				postfix, tbl);
+
+		/* sam: this is for people with low memory (eg. me :)) */
+		printf("\n"
+				"#if !defined(PART_1) && !defined(PART_2) && "
+				"!defined(PART_3) && !defined(PART_4) && "
+				"!defined(PART_5) && !defined(PART_6) && "
+				"!defined(PART_7) && !defined(PART_8)"
+				"\n"
+				"#define PART_1 1\n"
+				"#define PART_2 1\n"
+				"#define PART_3 1\n"
+				"#define PART_4 1\n"
+				"#define PART_5 1\n"
+				"#define PART_6 1\n"
+				"#define PART_7 1\n"
+				"#define PART_8 1\n"
+				"#endif\n\n");
+
+		rp = 0;
+		for (j = 1; j <= 8; ++j) {
+			int k = (j * nr_cpuop_funcs) / 8;
+			printf("#ifdef PART_%d\n", j);
+			for (; rp < k; rp++)
+				generate_one_opcode(rp, noflags);
+			printf("#endif\n\n");
+		}
+
+		fprintf(stblfile, "{ 0, 65536, 0 }};\n");
+	}
+
+}
+
+#if (defined(OS_cygwin) || defined(OS_mingw)) && defined(EXTENDED_SIGSEGV)
+void cygwin_mingw_abort()
+{
+#undef abort
+	abort();
+}
+#endif
+
+int main(void)
+{
+	init_table68k();
+
+	opcode_map = (int *) malloc(sizeof(int) * nr_cpuop_funcs);
+	opcode_last_postfix = (int *) malloc(sizeof(int) * nr_cpuop_funcs);
+	opcode_next_clev = (int *) malloc(sizeof(int) * nr_cpuop_funcs);
+	counts = (unsigned long *) malloc(65536 * sizeof(unsigned long));
+	read_counts();
+
+	/* It would be a lot nicer to put all in one file (we'd also get rid of
+	 * cputbl.h that way), but cpuopti can't cope.  That could be fixed, but
+	 * I don't dare to touch the 68k version.  */
+
+	headerfile = fopen("comptbl.h", "wb");
+	fprintf (headerfile, ""
+		"extern const struct comptbl op_smalltbl_0_comp_nf[];\n"
+		"extern const struct comptbl op_smalltbl_0_comp_ff[];\n"
+		"");
+
+	stblfile = fopen("compstbl_arm.cpp", "wb");
+	if (freopen("compemu_arm.cpp", "wb", stdout) == NULL)
+	{
+		assert(0);
+	}
+
+	generate_includes(stdout);
+	generate_includes(stblfile);
+
+	printf("#include \"jit/compemu.h\"\n");
+
+	noflags = 0;
+	generate_func(noflags);
+
+	free(opcode_map);
+	free(opcode_last_postfix);
+	free(opcode_next_clev);
+	free(counts);
+
+	opcode_map = (int *) malloc(sizeof(int) * nr_cpuop_funcs);
+	opcode_last_postfix = (int *) malloc(sizeof(int) * nr_cpuop_funcs);
+	opcode_next_clev = (int *) malloc(sizeof(int) * nr_cpuop_funcs);
+	counts = (unsigned long *) malloc(65536 * sizeof(unsigned long));
+	read_counts();
+	noflags = 1;
+	generate_func(noflags);
+
+	free(opcode_map);
+	free(opcode_last_postfix);
+	free(opcode_next_clev);
+	free(counts);
+
+	free(table68k);
+	fclose(stblfile);
+	fclose(headerfile);
+	return 0;
+}
diff --git a/jit/codegen_x86.cpp b/jit/codegen_x86.cpp
index d1ff6784..b49753f3 100644
--- a/jit/codegen_x86.cpp
+++ b/jit/codegen_x86.cpp
@@ -59,6 +59,9 @@
 #define R13_INDEX 13
 #define R14_INDEX 14
 #define R15_INDEX 15
+/* Dedicated register holding natmem_offset, analogous to ARM64's R27 (R_MEMSTART).
+   Used in [R_MEMSTART + m68k_addr] addressing to avoid disp32 sign-extension. */
+#define R_MEMSTART R15_INDEX
 #endif
 /* XXX this has to match X86_Reg8H_Base + 4 */
 #define AH_INDEX (0x10+4+EAX_INDEX)
@@ -111,12 +114,12 @@
  * since r/m bits 100 implies SIB byte. Simplest fix is to not use these
  * registers. Also note that these registers are listed in the freescratch
  * function as well. */
-uae_s8 always_used[] = { ESP_INDEX, R12_INDEX, -1 };
+uae_s8 always_used[] = { ESP_INDEX, R12_INDEX, R_MEMSTART, -1 };
 #else
 uae_s8 always_used[] = { ESP_INDEX, -1 };
 #endif
-uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
-uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
+uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,-1};
+uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,-1};
 #else
 uae_s8 always_used[] = { ESP_INDEX, -1 };
 uae_s8 can_byte[]={0,1,2,3,-1};
@@ -198,10 +201,19 @@ static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,1,1};
 
 #if defined(CPU_x86_64)
 #define X86_TARGET_64BIT		1
-/* The address override prefix causes a 5 cycles penalty on Intel Core
-   processors. Another solution would be to decompose the load in an LEA,
-   MOV (to zero-extend), MOV (from memory): is it better? */
-#define ADDR32					x86_emit_byte(0x67),
+/* ADDR32 removed: the address override prefix (0x67) caused a 5-cycle penalty
+   on Intel Core processors and forced 32-bit addressing. With the JIT now
+   64-bit pointer-clean, we use the default 64-bit addressing mode which
+   allows RIP-relative access (via _r_X macro) for addresses within 2GB
+   of the JIT code. This is both faster and supports natmem above 4GB.
+   FreeBSD exception: JIT cache is placed by ASLR mmap so RIP-relative
+   encoding of raw 32-bit addresses is incorrect. Restore 0x67 prefix to
+   force 32-bit absolute addressing. The 5-cycle penalty is acceptable. */
+#if defined(__FreeBSD__)
+#define ADDR32  x86_emit_byte(0x67),
+#else
+#define ADDR32
+#endif
 #else
 #define ADDR32
 #endif
@@ -703,31 +715,74 @@ LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index,
 	ADDR32 MOVBmr(base, baser, index, factor, d);
 }
 
-LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
-{
-	ADDR32 MOVLmr(base, X86_NOREG, index, factor, d);
+LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, MEMR base, R4 index, IMM factor))
+{
+#if X86_TARGET_64BIT
+	/* x86-64: [disp32 + index*scale] can't reach addresses above +/-2GB.
+	   Load 64-bit base into a scratch, then read from [scratch + index*factor].
+	   All callers read pointer arrays (baseaddr[], mem_banks[], cache_tags[]),
+	   so use MOVQmr (64-bit load) to get the full pointer width.
+	   If d == index, we must use a DIFFERENT scratch register so MOVQir
+	   doesn't destroy the index value.
+	   Compare _rR() to get 4-bit hardware register number regardless of
+	   register class (X86_EAX=0x40 and X86_RAX=0x50 are the same register). */
+	if (d == index) {
+		int scratch = (_rR(d) == 0) ? X86_RCX : X86_RAX;
+		PUSHQr(scratch);
+		MOVQir(base, scratch);
+		MOVQmr(0, scratch, index, factor, d);
+		POPQr(scratch);
+	} else {
+		MOVQir(base, d);
+		MOVQmr(0, d, index, factor, d);
+	}
+#else
+	MOVLmr(base, X86_NOREG, index, factor, d);
+#endif
 }
 
-LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
+LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, MEMR base, R4 index, IMM factor, IMM cond))
 {
+#if X86_TARGET_64BIT
+	/* x86-64: [disp32 + index*scale] can't reach 64-bit addresses.
+	   Emulate CMOV as: JCC_not skip; MOV d,[base+index*factor]; skip:
+	   If d == index, use a scratch register to hold the base (preserved
+	   via PUSH/POP) to avoid overwriting the index value. */
+	{
+		uae_s8 *target_p = (uae_s8 *)x86_get_target() + 1;
+		JCCSii(cond^1, 0);
+		if (d == index) {
+			int scratch = (_rR(d) == 0) ? X86_RCX : X86_RAX;
+			PUSHQr(scratch);
+			MOVQir(base, scratch);
+			MOVQmr(0, scratch, index, factor, d);
+			POPQr(scratch);
+		} else {
+			MOVQir(base, d);
+			MOVQmr(0, d, index, factor, d);
+		}
+		*target_p = (uae_s8)(JITPTR x86_get_target() - (JITPTR target_p + 1));
+	}
+#else
 	if (have_cmov)
-		ADDR32 CMOVLmr(cond, base, X86_NOREG, index, factor, d);
+		CMOVLmr(cond, base, X86_NOREG, index, factor, d);
 	else { /* replacement using branch and mov */
 		uae_s8 *target_p = (uae_s8 *)x86_get_target() + 1;
 		JCCSii(cond^1, 0);
-		ADDR32 MOVLmr(base, X86_NOREG, index, factor, d);
+		MOVLmr(base, X86_NOREG, index, factor, d);
 		*target_p = JITPTR x86_get_target() - (JITPTR target_p + 1);
 	}
+#endif
 }
 
-LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, MEMR mem, IMM cond))
 {
 	if (have_cmov)
 		CMOVLmr(cond, mem, X86_NOREG, X86_NOREG, 1, d);
 	else { /* replacement using branch and mov */
 		uae_s8 *target_p = (uae_s8 *)x86_get_target() + 1;
 		JCCSii(cond^1, 0);
-		ADDR32 MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d);
+		MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d);
 		*target_p = JITPTR x86_get_target() - (JITPTR target_p + 1);
 	}
 }
@@ -737,6 +792,15 @@ LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
 	ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d);
 }
 
+#if X86_TARGET_64BIT
+/* 64-bit register-relative load: d = *(uint64_t*)(s + offset).
+   Used for reading pointer-sized values (e.g., function pointers from addrbank). */
+static inline void raw_mov_q_rR(int d, int s, int offset)
+{
+	MOVQmr(offset, s, X86_NOREG, 1, d);
+}
+#endif
+
 LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
 {
 	ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d);
@@ -749,17 +813,52 @@ LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
 
 LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
 {
+#if X86_TARGET_64BIT
+	/* Use LEA+MOV to ensure M68K 32-bit address wrapping.
+	   x86-64 [base + index + disp32] computes in 64-bit, so when the
+	   M68K register + displacement wraps past 32 bits, the host address
+	   is 4GB off.  LEA r32,[r64+disp32] truncates to 32 bits (zeroing
+	   the upper half), giving the correct M68K effective address.
+	   Skip the LEA when offset==0 - the register already holds the
+	   full M68K address and no wrapping is possible. */
+	if (offset != 0) {
+		LEALmr(offset, s, X86_NOREG, 1, d);
+		MOVLmr(0, R_MEMSTART, d, 1, d);
+	} else {
+		MOVLmr(0, R_MEMSTART, s, 1, d);
+	}
+#else
 	ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d);
+#endif
 }
 
 LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
 {
+#if X86_TARGET_64BIT
+	/* See raw_mov_l_brR for the LEA+MOV rationale. */
+	if (offset != 0) {
+		LEALmr(offset, s, X86_NOREG, 1, d);
+		MOVWmr(0, R_MEMSTART, d, 1, d);
+	} else {
+		MOVWmr(0, R_MEMSTART, s, 1, d);
+	}
+#else
 	ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d);
+#endif
 }
 
 LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
 {
+#if X86_TARGET_64BIT
+	if (offset != 0) {
+		LEALmr(offset, s, X86_NOREG, 1, d);
+		MOVBmr(0, R_MEMSTART, d, 1, d);
+	} else {
+		MOVBmr(0, R_MEMSTART, s, 1, d);
+	}
+#else
 	ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d);
+#endif
 }
 
 LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
@@ -794,7 +893,13 @@ LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
 
 LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
 {
-	ADDR32 LEALmr(offset, s, X86_NOREG, 1, d);
+	/* On x86-64 without ADDR32: LEA r32, [r64 + disp32_signext].
+	   The 32-bit operand size truncates the result correctly even when
+	   disp32 sign-extends (e.g. MEMBaseDiff=0x80000000 -> -2GB + addr
+	   wraps around in 64-bit, but 32-bit truncation gives correct result).
+	   This works for both natmem translation (MEMBaseDiff offset) and
+	   general register arithmetic (small offsets like 2, 4, -2, -4). */
+	LEALmr(offset, s, X86_NOREG, 1, d);
 }
 
 LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
@@ -814,17 +919,30 @@ LOWFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor))
 
 LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
 {
+#if X86_TARGET_64BIT
+	/* Use [R_MEMSTART + d + offset] - see raw_mov_l_brR comment. */
+	MOVLrm(s, offset, R_MEMSTART, d, 1);
+#else
 	ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1);
+#endif
 }
 
 LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
 {
+#if X86_TARGET_64BIT
+	MOVWrm(s, offset, R_MEMSTART, d, 1);
+#else
 	ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1);
+#endif
 }
 
 LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
 {
+#if X86_TARGET_64BIT
+	MOVBrm(s, offset, R_MEMSTART, d, 1);
+#else
 	ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1);
+#endif
 }
 
 LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
@@ -842,27 +960,27 @@ LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
 	MOVLrr(s, d);
 }
 
-LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(MEMW d, R4 s))
 {
 	ADDR32 MOVLrm(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
-LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(MEMW d, R2 s))
 {
 	ADDR32 MOVWrm(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
-LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, MEMR s))
 {
 	ADDR32 MOVWmr(s, X86_NOREG, X86_NOREG, 1, d);
 }
 
-LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(MEMW d, R1 s))
 {
 	ADDR32 MOVBrm(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
-LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, MEMR s))
 {
 	ADDR32 MOVBmr(s, X86_NOREG, X86_NOREG, 1, d);
 }
@@ -872,6 +990,40 @@ LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
 	MOVLir(s, d);
 }
 
+#if X86_TARGET_64BIT
+/* 64-bit immediate -> register (movabs r64, imm64).
+   Used for PC_P which holds a 64-bit host pointer. */
+LOWFUNC(NONE,NONE,2,raw_mov_q_ri,(W4 d, uintptr s))
+{
+	MOVQir(s, d);
+}
+
+/* 64-bit value -> memory via scratch register.
+   x86_64 has no MOV [mem], imm64 instruction, so we use
+   movabs rax, imm64; then store via RIP-relative or register-indirect. */
+static inline void raw_mov_q_mi(uintptr d, uintptr s)
+{
+	MOVQir(s, X86_RAX);  /* movabs rax, imm64 (value to store) */
+	/* Let _r_X handle RIP-relative vs fallback automatically.
+	   _r_X sees d as uintptr, computes RIP-relative if within +/-2GB. */
+	MOVQrm(X86_RAX, d, X86_NOREG, X86_NOREG, 1);  /* mov [d], rax */
+}
+
+/* 64-bit load from memory -> register.
+   Used for reloading PC_P from its home slot. */
+static inline void raw_mov_q_rm(int d, uintptr s)
+{
+	MOVQmr(s, X86_NOREG, X86_NOREG, 1, d);  /* mov d, [s] via RIP-relative */
+}
+
+/* 64-bit store from register -> memory.
+   Used for flushing PC_P from hardware register to its home slot. */
+static inline void raw_mov_q_mr(uintptr d, int s)
+{
+	MOVQrm(s, d, X86_NOREG, X86_NOREG, 1);  /* mov [d], s via RIP-relative */
+}
+#endif
+
 LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
 {
 	MOVWir(s, d);
@@ -887,17 +1039,17 @@ LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
 	ADDR32 ADCLim(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
-LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) 
+LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(MEMRW d, IMM s))
 {
 	ADDR32 ADDLim(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
-LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) 
+LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(MEMRW d, IMM s))
 {
 	ADDR32 ADDWim(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
-LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) 
+LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(MEMRW d, IMM s))
 {
 	ADDR32 ADDBim(s, d, X86_NOREG, X86_NOREG, 1);
 }
@@ -922,7 +1074,7 @@ LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
 	TESTBrr(s, d);
 }
 
-LOWFUNC(WRITE,READ,2,raw_test_b_mi,(IMM d, IMM s))
+LOWFUNC(WRITE,READ,2,raw_test_b_mi,(MEMR d, IMM s))
 {
 	ADDR32 TESTBim(s, d, X86_NOREG, X86_NOREG, 1);
 }
@@ -1122,6 +1274,15 @@ LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
 	ADDR32 CMPLim(s, d, X86_NOREG, X86_NOREG, 1);
 }
 
+#if X86_TARGET_64BIT
+/* CMP [mem64], r64  - compare 8-byte memory value against 64-bit register.
+   Sets flags from [mem] - reg. */
+static inline void raw_cmp_q_mr(uintptr mem, R4 r)
+{
+	CMPQrm(r, mem, X86_NOREG, X86_NOREG, 1);
+}
+#endif
+
 LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
 {
 	XCHGLrr(r2, r1);
@@ -1168,28 +1329,58 @@ static inline void raw_jmp_r(R4 r)
 	JMPsr(r);
 }
 
-static inline void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
+static inline void raw_jmp_m_indexed(uintptr base, uae_u32 r, uae_u32 m)
 {
-	ADDR32 JMPsm(base, X86_NOREG, r, m);
+#if X86_TARGET_64BIT
+	/* x86-64: load 64-bit base into RAX, then JMP [RAX + r*m].
+	   Caller must ensure r != EAX_INDEX (currently always true:
+	   r = REG_PC_TMP = ECX_INDEX). */
+	MOVQir(base, X86_RAX);
+	JMPsm(0, X86_RAX, r, m);
+#else
+	JMPsm(base, X86_NOREG, r, m);
+#endif
 }
 
-static inline void raw_jmp_m(uae_u32 base)
+static inline void raw_jmp_m(uintptr base)
 {
+#if X86_TARGET_64BIT
+	/* x86-64: load 64-bit address into RAX, then JMP [RAX] */
+	MOVQir(base, X86_RAX);
+	JMPsm(0, X86_RAX, X86_NOREG, 1);
+#else
 	emit_byte(0xff);
 	emit_byte(0x25);
 	emit_long(base);
+#endif
 }
 
 
+#if X86_TARGET_64BIT
+static inline void raw_call(uintptr t)
+{
+	/* 64-bit: load target into scratch register, call via register */
+	MOVQir(t, X86_RAX);
+	CALLsr(X86_RAX);
+}
+
+static inline void raw_jmp(uintptr t)
+{
+	/* 64-bit: load target into scratch register, jump via register */
+	MOVQir(t, X86_RAX);
+	JMPsr(X86_RAX);
+}
+#else
 static inline void raw_call(uae_u32 t)
 {
-	ADDR32 CALLm(t);
+	CALLm(t);
 }
 
 static inline void raw_jmp(uae_u32 t)
 {
-	ADDR32 JMPm(t);
+	JMPm(t);
 }
+#endif
 
 static inline void raw_jcc_l_oponly(int cc)
 {
@@ -1207,22 +1398,22 @@ static inline void raw_jnz_l_oponly(void)
 	raw_jcc_l_oponly(NATIVE_CC_NE);
 }
 
-static inline void raw_jl(uae_u32 t)
+static inline void raw_jl(uintptr t)
 {
 	raw_jcc_l_oponly(NATIVE_CC_LT);
-	emit_long(t-(uae_u32)JITPTR target-4);
+	emit_long((uae_u32)(t-(uintptr)target-4));
 }
 
-static inline void raw_jz(uae_u32 t)
+static inline void raw_jz(uintptr t)
 {
 	raw_jz_l_oponly();
-	emit_long(t-(uae_u32)JITPTR target-4);
+	emit_long((uae_u32)(t-(uintptr)target-4));
 }
 
-static inline void raw_jnz(uae_u32 t)
+static inline void raw_jnz(uintptr t)
 {
 	raw_jnz_l_oponly();
-	emit_long(t-(uae_u32)JITPTR target-4);
+	emit_long((uae_u32)(t-(uintptr)target-4));
 }
 
 static inline void raw_jcc_b_oponly(int cc)
@@ -2232,12 +2423,24 @@ LOWFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
 	}
 }
 
-LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base))
+LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, MEMR base))
 {
+#if X86_TARGET_64BIT
+	/* x86-64: [index + disp32] can't reach 64-bit addresses.
+	   Load base into RAX, use FLDCW [RAX + index*1] via SIB encoding. */
+	MOVQir(base, X86_RAX);
+	x86_64_prefix(false, false, NULL, &index, NULL);
+	emit_byte(0xd9);
+	/* ModRM: mod=00, reg=5 (FLDCW), rm=100 (SIB follows) */
+	emit_byte(0x2c);
+	/* SIB: scale=00 (x1), index=index_reg, base=RAX (000) */
+	emit_byte((_r(index) << 3) | 0x00);
+#else
 	x86_64_prefix(true, false, NULL, NULL, &index);
 	emit_byte(0xd9);
 	emit_byte(0xa8 + index);
 	emit_long(base);
+#endif
 }
 
 LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
diff --git a/jit/codegen_x86.h b/jit/codegen_x86.h
index cf4b4193..fb4f1230 100644
--- a/jit/codegen_x86.h
+++ b/jit/codegen_x86.h
@@ -1627,6 +1627,7 @@ enum {
 /*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
 
 #define LEALmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_O_r_X		(0x8d		     ,_r4(RD)		,MD,MB,MI,MS		))
+#define LEAQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_O_r_X		(0x8d		     ,_r8(RD)		,MD,MB,MI,MS		))
 
 #define BSWAPLr(R)			(_REXLrr(0, R),			_OOr		(0x0fc8,_r4(R)							))
 #define BSWAPQr(R)			(_REXQrr(0, R),			_OOr		(0x0fc8,_r8(R)							))
diff --git a/jit/compemu.cpp b/jit/compemu.cpp
index f5d1979a..42ffd3a0 100644
--- a/jit/compemu.cpp
+++ b/jit/compemu.cpp
@@ -1,3 +1,6 @@
+#if defined(CPU_AARCH64)
+#include "arm/compemu_arm.cpp"
+#else
 #include "sysconfig.h"
 #if defined(JIT)
 #include "sysdeps.h"
@@ -20,6 +23,7 @@
 #define PART_7 1
 #define PART_8 1
 #endif
+#endif /* CPU_AARCH64 */
 
 #ifdef USE_JIT_FPU
 extern void comp_fpp_opp();
diff --git a/jit/compemu.h b/jit/compemu.h
index 53837d32..09c4e21a 100644
--- a/jit/compemu.h
+++ b/jit/compemu.h
@@ -1,3 +1,6 @@
+#if defined(CPU_AARCH64)
+#include "arm/compemu_arm.h"
+#else
 /*
  * compiler/compemu.h - Public interface and definitions
  *
@@ -46,10 +49,14 @@ typedef uae_u32 uintptr;
 #define USE_JIT
 #endif
 
-#define JITPTR (uae_u32)(uintptr)
+#define JITPTR (uintptr)
 
 #ifdef USE_JIT
 
+/* Allocate memory near the JIT cache / .data segment for RIP-relative access.
+ * options=0 uses anchor-based allocation; options=1 forces low 2GB (MAP_32BIT). */
+extern void *jit_vm_acquire(uae_u32 size, int options = 0);
+
 #ifdef JIT_DEBUG
 /* dump some information (m68k block, x86 block addresses) about the compiler state */
 extern void compiler_dumpstate(void);
@@ -86,7 +93,7 @@ union cacheline {
 #error implementation in progress
 #endif
 
-/* (gb) When on, this option can save save up to 30% compilation time
+/* (gb) When on, this option can save up to 30% compilation time
  *  when many lazy flushes occur (e.g. apps in MacOS 8.x).
  */
 #define USE_SEPARATE_BIA 1
@@ -97,7 +104,7 @@ union cacheline {
 /* Use code inlining, aka follow-up of constant jumps */
 #define USE_INLINING 1
 
-/* Inlining requires the chained checksuming information */
+/* Inlining requires the chained checksum information */
 #if USE_INLINING
 #undef  USE_CHECKSUM_INFO
 #define USE_CHECKSUM_INFO 1
@@ -176,6 +183,9 @@ extern void (*flush_icache)(int);
 #endif
 extern void alloc_cache(void);
 extern int check_for_cache_miss(void);
+#ifdef UAE
+extern void disable_jit_on_runtime_alloc_failure(const char *what);
+#endif
 
 /* JIT FPU compilation */
 struct jit_disable_opcodes {
@@ -253,7 +263,7 @@ extern void* pushall_call_handler;
 
 typedef struct {
   uae_u32* mem;
-  uae_u32 val;
+  uintptr val;  /* Must be pointer-width: PC_P holds a host pointer (64-bit on x86_64) */
   uae_u8 is_swapped;
   uae_u8 status;
   uae_s8 realreg; /* gb-- realreg can hold -1 */
@@ -348,6 +358,7 @@ typedef struct {
 extern int touchcnt;
 
 #define IMM  uae_s32
+#define IMPTR uintptr
 #define RR1  uae_u32
 #define RR2  uae_u32
 #define RR4  uae_u32
@@ -363,9 +374,9 @@ extern int touchcnt;
 #define RW1 uae_u32
 #define RW2 uae_u32
 #define RW4 uae_u32
-#define MEMR uae_u32
-#define MEMW uae_u32
-#define MEMRW    uae_u32
+#define MEMR uintptr
+#define MEMW uintptr
+#define MEMRW    uintptr
 #define MEMPTR   uintptr
 #define MEMPTRR  MEMPTR
 #define MEMPTRW  MEMPTR
@@ -383,15 +394,6 @@ extern int touchcnt;
 /* What we expose to the outside */
 #define DECLARE_MIDFUNC(func) extern void func
 
-#if defined(CPU_arm)
-
-#include "compemu_midfunc_arm.h"
-
-#if defined(USE_JIT2)
-#include "compemu_midfunc_arm2.h"
-#endif
-#endif
-
 #if defined(CPU_i386) || defined(CPU_x86_64)
 #include "compemu_midfunc_x86.h"
 #endif
@@ -419,9 +421,9 @@ extern void set_zero(int r, int tmp);
 extern int kill_rodent(int r);
 #define SYNC_PC_OFFSET 100
 extern void sync_m68k_pc(void);
-extern uae_u32 get_const(int r);
+extern uintptr get_const(int r);
 extern int  is_const(int r);
-extern void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond);
+extern void register_branch(uintptr not_taken, uintptr taken, uae_u8 cond);
 void compemu_make_sr(int sr, int tmp);
 void compemu_enter_super(int sr);
 void compemu_exc_make_frame(int format, int sr, int currpc, int nr, int tmp);
@@ -569,18 +571,12 @@ void jit_abort(const char *format,...) __attribute__((format(printf, 1, 2))) __a
 
 #endif /* UAE */
 
-#ifdef CPU_64_BIT
-static inline uae_u32 check_uae_p32(uintptr address, const char *file, int line)
-{
-	if (address > (uintptr_t) 0xffffffff) {
-		jit_abort("JIT: 64-bit pointer (0x%llx) at %s:%d (fatal)",
-			(unsigned long long)address, file, line);
-	}
-	return (uae_u32) address;
-}
-#define uae_p32(x) (check_uae_p32((uintptr)(x), __FILE__, __LINE__))
-#else
-#define uae_p32(x) ((uae_u32)(x))
-#endif
+/* x86_64 JIT is now 64-bit pointer-clean. uae_p32() is no longer needed
+   for pointer truncation. It now passes through the full uintptr value.
+   The debug check remains to catch any leftover code that still assumes
+   32-bit pointers where it shouldn't. */
+#define uae_p32(x) ((uintptr)(x))
 
 #endif /* COMPEMU_H */
+
+#endif /* CPU_AARCH64 */
diff --git a/jit/compemu_fpp.cpp b/jit/compemu_fpp.cpp
index 575c4a7b..c1c0576b 100644
--- a/jit/compemu_fpp.cpp
+++ b/jit/compemu_fpp.cpp
@@ -1,3 +1,6 @@
+#if defined(CPU_AARCH64)
+#include "arm/compemu_fpp_arm.cpp"
+#else
 /*
  * compiler/compemu_fpp.cpp - Dynamic translation of FPU instructions
  *
@@ -54,7 +57,7 @@
 //#include "fpu/exceptions.h"
 //#include "fpu/rounding.h"
 
-#define DEBUG 0
+//#define DEBUG 0
 #include "debug.h"
 
 struct jit_disable_opcodes jit_disable;
@@ -616,6 +619,11 @@ void comp_fscc_opp(uae_u32 opcode, uae_u16 extra)
 {
 	int reg;
 
+	if (!currprefs.compfpu)
+	{
+		FAIL(1);
+		return;
+	}
 	if (jit_disable.fscc)
 	{
 		FAIL(1);
@@ -730,14 +738,16 @@ void comp_ftrapcc_opp (uae_u32 /* opcode */, uaecptr /* oldpc */)
 void comp_fbcc_opp(uae_u32 opcode)
 {
 	uae_u32 start_68k_offset = m68k_pc_offset;
-	uae_u32 off;
-	uae_u32 v1;
-	uae_u32 v2;
+	uae_s32 off;
+	uintptr v1;
+	uintptr v2;
 	int cc;
 
-	// comp_pc_p is expected to be bound to 32-bit addresses
-	assert((uintptr) comp_pc_p <= 0xffffffffUL);
-
+	if (!currprefs.compfpu)
+	{
+		FAIL(1);
+		return;
+	}
 	if (jit_disable.fbcc)
 	{
 		FAIL(1);
@@ -753,9 +763,16 @@ void comp_fbcc_opp(uae_u32 opcode)
 		off = (uae_s32) (uae_s16) comp_get_iword((m68k_pc_offset += 2) - 2);
 	} else
 	{
-		off = comp_get_ilong((m68k_pc_offset += 4) - 4);
+		off = (uae_s32) comp_get_ilong((m68k_pc_offset += 4) - 4);
+	}
+	/* Match the ARM64 FBcc fix: keep the signed displacement separate
+	 * from the 64-bit host pointer so non-PC_P set_const paths do not
+	 * lose pointer width or zero-extend backward branches. */
+	{
+		uae_s32 displacement = off - (uae_s32)(m68k_pc_offset - start_68k_offset);
+		mov_l_ri(S1, (uintptr)(uae_s32)displacement);
+		add_l_ri(S1, (uintptr)comp_pc_p);
 	}
-	mov_l_ri(S1, JITPTR (comp_pc_p + off - (m68k_pc_offset - start_68k_offset)));
 	mov_l_ri(PC_P, JITPTR comp_pc_p);
 
 	/* Now they are both constant. Might as well fold in m68k_pc_offset */
@@ -1112,6 +1129,16 @@ void comp_fpp_opp(uae_u32 opcode, uae_u16 extra)
 	int reg;
 	int src;
 
+	if (special_mem)
+	{
+		FAIL(1);
+		return;
+	}
+	if (!currprefs.compfpu)
+	{
+		FAIL(1);
+		return;
+	}
 	switch ((extra >> 13) & 0x7)
 	{
 	case 1:							/* illegal */
@@ -2113,3 +2140,5 @@ void comp_fpp_opp(uae_u32 opcode, uae_u16 extra)
 }
 
 #endif
+
+#endif /* CPU_AARCH64 */
diff --git a/jit/compemu_midfunc_x86.cpp b/jit/compemu_midfunc_x86.cpp
index 38573d87..87bf3171 100644
--- a/jit/compemu_midfunc_x86.cpp
+++ b/jit/compemu_midfunc_x86.cpp
@@ -342,7 +342,7 @@ MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b))
 	unlock2(b);
 }
 
-MIDFUNC(2,mov_l_rm,(W4 d, IMM s))
+MIDFUNC(2,mov_l_rm,(W4 d, MEMR s))
 {
 	CLOBBER_MOV;
 	d=writereg(d,4);
@@ -359,25 +359,25 @@ MIDFUNC(1,call_r,(RR4 r)) /* Clobbering is implicit */
 	unlock2(r);
 }
 
-MIDFUNC(2,sub_l_mi,(IMM d, IMM s))
+MIDFUNC(2,sub_l_mi,(MEMRW d, IMM s))
 {
 	CLOBBER_SUB;
 	raw_sub_l_mi(d,s) ;
 }
 
-MIDFUNC(2,mov_l_mi,(IMM d, IMM s))
+MIDFUNC(2,mov_l_mi,(MEMW d, IMM s))
 {
 	CLOBBER_MOV;
 	raw_mov_l_mi(d,s) ;
 }
 
-MIDFUNC(2,mov_w_mi,(IMM d, IMM s))
+MIDFUNC(2,mov_w_mi,(MEMW d, IMM s))
 {
 	CLOBBER_MOV;
 	raw_mov_w_mi(d,s) ;
 }
 
-MIDFUNC(2,mov_b_mi,(IMM d, IMM s))
+MIDFUNC(2,mov_b_mi,(MEMW d, IMM s))
 {
 	CLOBBER_MOV;
 	raw_mov_b_mi(d,s) ;
@@ -821,17 +821,24 @@ MIDFUNC(2,setcc_m,(IMM d, IMM cc))
 
 MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc))
 {
+	int dreg=d;
+	int sreg=s;
 	if (d==s)
 		return;
 	CLOBBER_CMOV;
 	s=readreg(s,4);
 	d=rmw(d,4,4);
+#if X86_TARGET_64BIT
+	if (dreg == PC_P || sreg == PC_P) {
+		CMOVQrr(cc,s,d);
+	} else
+#endif
 	raw_cmov_l_rr(d,s,cc);
 	unlock2(s);
 	unlock2(d);
 }
 
-MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
+MIDFUNC(3,cmov_l_rm,(RW4 d, MEMR s, IMM cc))
 {
 	CLOBBER_CMOV;
 	d=rmw(d,4,4);
@@ -1288,7 +1295,7 @@ MIDFUNC(5,mov_b_brrm_indexed,(W1 d, IMM base, RR4 baser, RR4 index, IMM factor))
 }
 
 /* Read a long from base+factor*index */
-MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor))
+MIDFUNC(4,mov_l_rm_indexed,(W4 d, MEMR base, RR4 index, IMM factor))
 {
 	int indexreg=index;
 
@@ -1310,10 +1317,15 @@ MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor))
 /* read the long at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset))
 {
+#if !X86_TARGET_64BIT
+	/* On x86-64, s may hold a natmem-translated address (via get_n_addr)
+	   that is unreachable via RIP-relative encoding.  Use register-indirect
+	   path instead. */
 	if (isconst(s)) {
 		COMPCALL(mov_l_rm)(d,live.state[s].val+offset);
 		return;
 	}
+#endif
 	CLOBBER_MOV;
 	s=readreg(s,4);
 	d=writereg(d,4);
@@ -1323,13 +1335,30 @@ MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset))
 	unlock2(s);
 }
 
+#if X86_TARGET_64BIT
+/* read a 64-bit (pointer-width) value at the address contained in s+offset and store in d.
+   Used for reading function pointers from addrbank structs on x86-64. */
+MIDFUNC(3,mov_q_rR,(W4 d, RR4 s, IMM offset))
+{
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=writereg(d,4);
+
+	raw_mov_q_rR(d,s,offset);
+	unlock2(d);
+	unlock2(s);
+}
+#endif
+
 /* read the word at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset))
 {
+#if !X86_TARGET_64BIT
 	if (isconst(s)) {
 		COMPCALL(mov_w_rm)(d,live.state[s].val+offset);
 		return;
 	}
+#endif
 	CLOBBER_MOV;
 	s=readreg(s,4);
 	d=writereg(d,2);
@@ -1342,10 +1371,12 @@ MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset))
 /* read the word at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_b_rR,(W1 d, RR4 s, IMM offset))
 {
+#if !X86_TARGET_64BIT
 	if (isconst(s)) {
 		COMPCALL(mov_b_rm)(d,live.state[s].val+offset);
 		return;
 	}
+#endif
 	CLOBBER_MOV;
 	s=readreg(s,4);
 	d=writereg(d,1);
@@ -1356,57 +1387,81 @@ MIDFUNC(3,mov_b_rR,(W1 d, RR4 s, IMM offset))
 }
 
 /* read the long at the address contained in s+offset and store in d */
-MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset))
+MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMPTR offset))
 {
 	int sreg=s;
+#if !X86_TARGET_64BIT
+	/* On x86-64, natmem addresses are unreachable via RIP-relative encoding
+	   (natmem at ~0x80000000 is far from JIT code at ~0x7FFxxxxxxxxx).
+	   Skip the isconst shortcut; the normal path uses [R_MEMSTART + reg]. */
 	if (isconst(s)) {
 		COMPCALL(mov_l_rm)(d,live.state[s].val+offset);
 		return;
 	}
+#endif
 	CLOBBER_MOV;
 	s=readreg_offset(s,4);
+#if X86_TARGET_64BIT
+	/* R_MEMSTART already holds natmem_offset, so strip only MEMBaseDiff
+	   while preserving the caller's displacement (for example vector
+	   offsets such as MEMBaseDiff + trapno * 4). */
+	offset=offset - MEMBaseDiff + get_offset(sreg);
+#else
 	offset+=get_offset(sreg);
+#endif
 	d=writereg(d,4);
 
-	raw_mov_l_brR(d,s,offset);
+	raw_mov_l_brR(d,s,(IMM)offset);
 	unlock2(d);
 	unlock2(s);
 }
 
 /* read the word at the address contained in s+offset and store in d */
-MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset))
+MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMPTR offset))
 {
 	int sreg=s;
+#if !X86_TARGET_64BIT
 	if (isconst(s)) {
 		COMPCALL(mov_w_rm)(d,live.state[s].val+offset);
 		return;
 	}
+#endif
 	CLOBBER_MOV;
 	remove_offset(d,-1);
 	s=readreg_offset(s,4);
+#if X86_TARGET_64BIT
+	offset=offset - MEMBaseDiff + get_offset(sreg);
+#else
 	offset+=get_offset(sreg);
+#endif
 	d=writereg(d,2);
 
-	raw_mov_w_brR(d,s,offset);
+	raw_mov_w_brR(d,s,(IMM)offset);
 	unlock2(d);
 	unlock2(s);
 }
 
 /* read the word at the address contained in s+offset and store in d */
-MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset))
+MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMPTR offset))
 {
 	int sreg=s;
+#if !X86_TARGET_64BIT
 	if (isconst(s)) {
 		COMPCALL(mov_b_rm)(d,live.state[s].val+offset);
 		return;
 	}
+#endif
 	CLOBBER_MOV;
 	remove_offset(d,-1);
 	s=readreg_offset(s,4);
+#if X86_TARGET_64BIT
+	offset=offset - MEMBaseDiff + get_offset(sreg);
+#else
 	offset+=get_offset(sreg);
+#endif
 	d=writereg(d,1);
 
-	raw_mov_b_brR(d,s,offset);
+	raw_mov_b_brR(d,s,(IMM)offset);
 	unlock2(d);
 	unlock2(s);
 }
@@ -1414,10 +1469,12 @@ MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset))
 MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset))
 {
 	int dreg=d;
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_l_mi)(live.state[d].val+offset,i);
 		return;
 	}
+#endif
 
 	CLOBBER_MOV;
 	d=readreg_offset(d,4);
@@ -1429,10 +1486,12 @@ MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset))
 MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset))
 {
 	int dreg=d;
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_w_mi)(live.state[d].val+offset,i);
 		return;
 	}
+#endif
 
 	CLOBBER_MOV;
 	d=readreg_offset(d,4);
@@ -1444,10 +1503,12 @@ MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset))
 MIDFUNC(3,mov_b_Ri,(RR4 d, IMM i, IMM offset))
 {
 	int dreg=d;
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_b_mi)(live.state[d].val+offset,i);
 		return;
 	}
+#endif
 
 	CLOBBER_MOV;
 	d=readreg_offset(d,4);
@@ -1459,10 +1520,15 @@ MIDFUNC(3,mov_b_Ri,(RR4 d, IMM i, IMM offset))
 /* Warning! OFFSET is byte sized only! */
 MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset))
 {
+#if !X86_TARGET_64BIT
+	/* On x86-64, d may hold a natmem-translated address (via get_n_addr)
+	   that is unreachable via RIP-relative encoding.  Use register-indirect
+	   path instead. */
 	if (isconst(d)) {
 		COMPCALL(mov_l_mr)(live.state[d].val+offset,s);
 		return;
 	}
+#endif
 	if (isconst(s)) {
 		COMPCALL(mov_l_Ri)(d,live.state[s].val,offset);
 		return;
@@ -1479,10 +1545,12 @@ MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset))
 
 MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset))
 {
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_w_mr)(live.state[d].val+offset,s);
 		return;
 	}
+#endif
 	if (isconst(s)) {
 		COMPCALL(mov_w_Ri)(d,(uae_u16)live.state[s].val,offset);
 		return;
@@ -1498,10 +1566,12 @@ MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset))
 
 MIDFUNC(3,mov_b_Rr,(RR4 d, RR1 s, IMM offset))
 {
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_b_mr)(live.state[d].val+offset,s);
 		return;
 	}
+#endif
 	if (isconst(s)) {
 		COMPCALL(mov_b_Ri)(d,(uae_u8)live.state[s].val,offset);
 		return;
@@ -1566,56 +1636,74 @@ MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
 }
 
 /* write d to the long at the address contained in s+offset */
-MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset))
+MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMPTR offset))
 {
 	int dreg=d;
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_l_mr)(live.state[d].val+offset,s);
 		return;
 	}
+#endif
 
 	CLOBBER_MOV;
 	s=readreg(s,4);
 	d=readreg_offset(d,4);
+#if X86_TARGET_64BIT
+	offset=offset - MEMBaseDiff + get_offset(dreg);
+#else
 	offset+=get_offset(dreg);
+#endif
 
-	raw_mov_l_bRr(d,s,offset);
+	raw_mov_l_bRr(d,s,(IMM)offset);
 	unlock2(d);
 	unlock2(s);
 }
 
 /* write the word at the address contained in s+offset and store in d */
-MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset))
+MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMPTR offset))
 {
 	int dreg=d;
 
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_w_mr)(live.state[d].val+offset,s);
 		return;
 	}
+#endif
 
 	CLOBBER_MOV;
 	s=readreg(s,2);
 	d=readreg_offset(d,4);
+#if X86_TARGET_64BIT
+	offset=offset - MEMBaseDiff + get_offset(dreg);
+#else
 	offset+=get_offset(dreg);
-	raw_mov_w_bRr(d,s,offset);
+#endif
+	raw_mov_w_bRr(d,s,(IMM)offset);
 	unlock2(d);
 	unlock2(s);
 }
 
-MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset))
+MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMPTR offset))
 {
 	int dreg=d;
+#if !X86_TARGET_64BIT
 	if (isconst(d)) {
 		COMPCALL(mov_b_mr)(live.state[d].val+offset,s);
 		return;
 	}
+#endif
 
 	CLOBBER_MOV;
 	s=readreg(s,1);
 	d=readreg_offset(d,4);
+#if X86_TARGET_64BIT
+	offset=offset - MEMBaseDiff + get_offset(dreg);
+#else
 	offset+=get_offset(dreg);
-	raw_mov_b_bRr(d,s,offset);
+#endif
+	raw_mov_b_bRr(d,s,(IMM)offset);
 	unlock2(d);
 	unlock2(s);
 }
@@ -1660,9 +1748,29 @@ MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
 		return;
 	}
 	if (isconst(s)) {
+#if X86_TARGET_64BIT
+		if (s == PC_P) {
+			CLOBBER_MOV;
+			d=writereg(d,4);
+			raw_mov_q_ri(d,live.state[s].val);
+			unlock2(d);
+			return;
+		}
+#endif
 		COMPCALL(mov_l_ri)(d,live.state[s].val);
 		return;
 	}
+#if X86_TARGET_64BIT
+	if (d == PC_P || s == PC_P) {
+		CLOBBER_MOV;
+		s=readreg(s,4);
+		d=writereg(d,4);
+		MOVQrr(s,d);
+		unlock2(d);
+		unlock2(s);
+		return;
+	}
+#endif
 	olds=s;
 	disassociate(d);
 	s=readreg_offset(s,4);
@@ -1680,8 +1788,22 @@ MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
 	unlock2(s);
 }
 
-MIDFUNC(2,mov_l_mr,(IMM d, RR4 s))
+MIDFUNC(2,mov_l_mr,(MEMW d, RR4 s))
 {
+#if X86_TARGET_64BIT
+	if (s == PC_P) {
+		/* PC_P holds a 64-bit host pointer and needs allocator-aware scratch use. */
+		if (isconst(s)) {
+			store_const_q_mi(d, live.state[s].val);
+		} else {
+			CLOBBER_MOV;
+			s=readreg(s,4);
+			raw_mov_q_mr(d, s);
+			unlock2(s);
+		}
+		return;
+	}
+#endif
 	if (isconst(s)) {
 		COMPCALL(mov_l_mi)(d,live.state[s].val);
 		return;
@@ -1694,7 +1816,7 @@ MIDFUNC(2,mov_l_mr,(IMM d, RR4 s))
 }
 
 
-MIDFUNC(2,mov_w_mr,(IMM d, RR2 s))
+MIDFUNC(2,mov_w_mr,(MEMW d, RR2 s))
 {
 	if (isconst(s)) {
 		COMPCALL(mov_w_mi)(d,(uae_u16)live.state[s].val);
@@ -1707,7 +1829,7 @@ MIDFUNC(2,mov_w_mr,(IMM d, RR2 s))
 	unlock2(s);
 }
 
-MIDFUNC(2,mov_w_rm,(W2 d, IMM s))
+MIDFUNC(2,mov_w_rm,(W2 d, MEMR s))
 {
 	CLOBBER_MOV;
 	d=writereg(d,2);
@@ -1716,7 +1838,7 @@ MIDFUNC(2,mov_w_rm,(W2 d, IMM s))
 	unlock2(d);
 }
 
-MIDFUNC(2,mov_b_mr,(IMM d, RR1 s))
+MIDFUNC(2,mov_b_mr,(MEMW d, RR1 s))
 {
 	if (isconst(s)) {
 		COMPCALL(mov_b_mi)(d,(uae_u8)live.state[s].val);
@@ -1730,7 +1852,7 @@ MIDFUNC(2,mov_b_mr,(IMM d, RR1 s))
 	unlock2(s);
 }
 
-MIDFUNC(2,mov_b_rm,(W1 d, IMM s))
+MIDFUNC(2,mov_b_rm,(W1 d, MEMR s))
 {
 	CLOBBER_MOV;
 	d=writereg(d,1);
@@ -1739,7 +1861,7 @@ MIDFUNC(2,mov_b_rm,(W1 d, IMM s))
 	unlock2(d);
 }
 
-MIDFUNC(2,mov_l_ri,(W4 d, IMM s))
+MIDFUNC(2,mov_l_ri,(W4 d, IMPTR s))
 {
 	set_const(d,s);
 	return;
@@ -1763,19 +1885,19 @@ MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
 	unlock2(d);
 }
 
-MIDFUNC(2,add_l_mi,(IMM d, IMM s))
+MIDFUNC(2,add_l_mi,(MEMRW d, IMM s))
 {
 	CLOBBER_ADD;
 	raw_add_l_mi(d,s);
 }
 
-MIDFUNC(2,add_w_mi,(IMM d, IMM s))
+MIDFUNC(2,add_w_mi,(MEMRW d, IMM s))
 {
 	CLOBBER_ADD;
 	raw_add_w_mi(d,s);
 }
 
-MIDFUNC(2,add_b_mi,(IMM d, IMM s))
+MIDFUNC(2,add_b_mi,(MEMRW d, IMM s))
 {
 	CLOBBER_ADD;
 	raw_add_b_mi(d,s);
@@ -1823,7 +1945,7 @@ MIDFUNC(2,test_b_rr,(RR1 d, RR1 s))
 	unlock2(s);
 }
 
-MIDFUNC(2,test_b_mi,(IMM d, IMM s))
+MIDFUNC(2,test_b_mi,(MEMR d, IMM s))
 {
 	CLOBBER_TEST;
 	raw_test_b_mi(d,s);
@@ -1972,6 +2094,7 @@ MIDFUNC(2,adc_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,add_l,(RW4 d, RR4 s))
 {
+	int dreg=d;
 	if (isconst(s)) {
 		COMPCALL(add_l_ri)(d,live.state[s].val);
 		return;
@@ -1981,6 +2104,14 @@ MIDFUNC(2,add_l,(RW4 d, RR4 s))
 	s=readreg(s,4);
 	d=rmw(d,4,4);
 
+#if X86_TARGET_64BIT
+	if (dreg == PC_P) {
+		const int scratch = get_unlocked_scratch_nreg_excluding(d, s);
+		free_nreg(scratch);
+		raw_sign_extend_32_rr(scratch,s);
+		ADDQrr(scratch,d);
+	} else
+#endif
 	raw_add_l(d,s);
 
 	unlock2(d);
@@ -2066,23 +2197,56 @@ MIDFUNC(2,sub_b_ri,(RW1 d, IMM i))
 	unlock2(d);
 }
 
-MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
+#if X86_TARGET_64BIT
+static inline uintptr sign_extend_pc_disp(uintptr i)
+{
+	if (i <= static_cast<uintptr>(0xffffffffULL) && (i & static_cast<uintptr>(0x80000000ULL)))
+		return static_cast<uintptr>(static_cast<uae_s64>(static_cast<uae_s32>(i)));
+	return i;
+}
+#endif
+
+MIDFUNC(2,add_l_ri,(RW4 d, IMPTR i))
 {
+	int dreg=d;
 	if (!i && !needflags)
 		return;
 	if (isconst(d) && !needflags) {
-		live.state[d].val+=i;
+#if X86_TARGET_64BIT
+		if (d == PC_P) {
+			live.state[d].val += sign_extend_pc_disp(static_cast<uintptr>(i));
+		} else if (i > static_cast<IMPTR>(0xffffffffULL) ||
+			live.state[d].val > static_cast<uintptr>(0xffffffffULL)) {
+			uintptr val = live.state[d].val;
+			if (val <= static_cast<uintptr>(0xffffffffULL) &&
+				i > static_cast<IMPTR>(0xffffffffULL)) {
+				val = static_cast<uintptr>(static_cast<uae_s64>(static_cast<uae_s32>(val)));
+			}
+			live.state[d].val = val + i;
+		} else
+#endif
+		{
+			live.state[d].val=static_cast<uae_u32>(live.state[d].val + i);
+		}
 		return;
 	}
 #if USE_OFFSET
 	if (!needflags) {
-		add_offset(d,i);
+		add_offset(d,(uintptr)i);
 		return;
 	}
 #endif
 	CLOBBER_ADD;
 	d=rmw(d,4,4);
-	raw_add_l_ri(d,i);
+#if X86_TARGET_64BIT
+	if (dreg == PC_P) {
+		x86_add_q_ri_ptr(d, sign_extend_pc_disp(static_cast<uintptr>(i)));
+	} else if (i > static_cast<IMPTR>(0xffffffffULL)) {
+		raw_sign_extend_32_rr(d,d);
+		x86_add_q_ri_ptr(d, static_cast<uintptr>(i));
+	} else
+#endif
+	raw_add_l_ri(d,(IMM)i);
 	unlock2(d);
 }
 
@@ -2516,7 +2680,7 @@ MIDFUNC(2,fmov_rr,(FW d, FR s))
 #endif
 }
 
-MIDFUNC(2,fldcw_m_indexed,(RR4 index, IMM base))
+MIDFUNC(2,fldcw_m_indexed,(RR4 index, MEMR base))
 {
 	index=readreg(index,4);
 
diff --git a/jit/compemu_midfunc_x86.h b/jit/compemu_midfunc_x86.h
index a25102ed..2b04e647 100644
--- a/jit/compemu_midfunc_x86.h
+++ b/jit/compemu_midfunc_x86.h
@@ -39,12 +39,12 @@ DECLARE_MIDFUNC(bts_l_ri(RW4 r, IMM i));
 DECLARE_MIDFUNC(bts_l_rr(RW4 r, RR4 b));
 DECLARE_MIDFUNC(btr_l_ri(RW4 r, IMM i));
 DECLARE_MIDFUNC(btr_l_rr(RW4 r, RR4 b));
-DECLARE_MIDFUNC(mov_l_rm(W4 d, IMM s));
+DECLARE_MIDFUNC(mov_l_rm(W4 d, MEMR s));
 DECLARE_MIDFUNC(call_r(RR4 r));
-DECLARE_MIDFUNC(sub_l_mi(IMM d, IMM s));
-DECLARE_MIDFUNC(mov_l_mi(IMM d, IMM s));
-DECLARE_MIDFUNC(mov_w_mi(IMM d, IMM s));
-DECLARE_MIDFUNC(mov_b_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(sub_l_mi(MEMRW d, IMM s));
+DECLARE_MIDFUNC(mov_l_mi(MEMW d, IMM s));
+DECLARE_MIDFUNC(mov_w_mi(MEMW d, IMM s));
+DECLARE_MIDFUNC(mov_b_mi(MEMW d, IMM s));
 DECLARE_MIDFUNC(rol_b_ri(RW1 r, IMM i));
 DECLARE_MIDFUNC(rol_w_ri(RW2 r, IMM i));
 DECLARE_MIDFUNC(rol_l_ri(RW4 r, IMM i));
@@ -78,7 +78,7 @@ DECLARE_MIDFUNC(shra_b_ri(RW1 r, IMM i));
 DECLARE_MIDFUNC(setcc(W1 d, IMM cc));
 DECLARE_MIDFUNC(setcc_m(IMM d, IMM cc));
 DECLARE_MIDFUNC(cmov_l_rr(RW4 d, RR4 s, IMM cc));
-DECLARE_MIDFUNC(cmov_l_rm(RW4 d, IMM s, IMM cc));
+DECLARE_MIDFUNC(cmov_l_rm(RW4 d, MEMR s, IMM cc));
 DECLARE_MIDFUNC(bsf_l_rr(W4 d, RR4 s));
 DECLARE_MIDFUNC(pop_m(IMM d));
 DECLARE_MIDFUNC(push_m(IMM d));
@@ -111,13 +111,16 @@ DECLARE_MIDFUNC(mov_b_bmrr_indexed(IMM base, RR4 baser, RR4 index, IMM factor, R
 DECLARE_MIDFUNC(mov_l_brrm_indexed(W4 d, IMM base, RR4 baser, RR4 index, IMM factor));
 DECLARE_MIDFUNC(mov_w_brrm_indexed(W2 d, IMM base, RR4 baser, RR4 index, IMM factor));
 DECLARE_MIDFUNC(mov_b_brrm_indexed(W1 d, IMM base, RR4 baser, RR4 index, IMM factor));
-DECLARE_MIDFUNC(mov_l_rm_indexed(W4 d, IMM base, RR4 index, IMM factor));
+DECLARE_MIDFUNC(mov_l_rm_indexed(W4 d, MEMR base, RR4 index, IMM factor));
 DECLARE_MIDFUNC(mov_l_rR(W4 d, RR4 s, IMM offset));
+#if X86_TARGET_64BIT
+DECLARE_MIDFUNC(mov_q_rR(W4 d, RR4 s, IMM offset));
+#endif
 DECLARE_MIDFUNC(mov_w_rR(W2 d, RR4 s, IMM offset));
 DECLARE_MIDFUNC(mov_b_rR(W1 d, RR4 s, IMM offset));
-DECLARE_MIDFUNC(mov_l_brR(W4 d, RR4 s, IMM offset));
-DECLARE_MIDFUNC(mov_w_brR(W2 d, RR4 s, IMM offset));
-DECLARE_MIDFUNC(mov_b_brR(W1 d, RR4 s, IMM offset));
+DECLARE_MIDFUNC(mov_l_brR(W4 d, RR4 s, IMPTR offset));
+DECLARE_MIDFUNC(mov_w_brR(W2 d, RR4 s, IMPTR offset));
+DECLARE_MIDFUNC(mov_b_brR(W1 d, RR4 s, IMPTR offset));
 DECLARE_MIDFUNC(mov_l_Ri(RR4 d, IMM i, IMM offset));
 DECLARE_MIDFUNC(mov_w_Ri(RR4 d, IMM i, IMM offset));
 DECLARE_MIDFUNC(mov_b_Ri(RR4 d, IMM i, IMM offset));
@@ -127,28 +130,28 @@ DECLARE_MIDFUNC(mov_b_Rr(RR4 d, RR1 s, IMM offset));
 DECLARE_MIDFUNC(lea_l_brr(W4 d, RR4 s, IMM offset));
 DECLARE_MIDFUNC(lea_l_brr_indexed(W4 d, RR4 s, RR4 index, IMM factor, IMM offset));
 DECLARE_MIDFUNC(lea_l_rr_indexed(W4 d, RR4 s, RR4 index, IMM factor));
-DECLARE_MIDFUNC(mov_l_bRr(RR4 d, RR4 s, IMM offset));
-DECLARE_MIDFUNC(mov_w_bRr(RR4 d, RR2 s, IMM offset));
-DECLARE_MIDFUNC(mov_b_bRr(RR4 d, RR1 s, IMM offset));
+DECLARE_MIDFUNC(mov_l_bRr(RR4 d, RR4 s, IMPTR offset));
+DECLARE_MIDFUNC(mov_w_bRr(RR4 d, RR2 s, IMPTR offset));
+DECLARE_MIDFUNC(mov_b_bRr(RR4 d, RR1 s, IMPTR offset));
 DECLARE_MIDFUNC(mid_bswap_32(RW4 r));
 DECLARE_MIDFUNC(mid_bswap_16(RW2 r));
 DECLARE_MIDFUNC(mov_l_rr(W4 d, RR4 s));
-DECLARE_MIDFUNC(mov_l_mr(IMM d, RR4 s));
-DECLARE_MIDFUNC(mov_w_mr(IMM d, RR2 s));
-DECLARE_MIDFUNC(mov_w_rm(W2 d, IMM s));
-DECLARE_MIDFUNC(mov_b_mr(IMM d, RR1 s));
-DECLARE_MIDFUNC(mov_b_rm(W1 d, IMM s));
-DECLARE_MIDFUNC(mov_l_ri(W4 d, IMM s));
+DECLARE_MIDFUNC(mov_l_mr(MEMW d, RR4 s));
+DECLARE_MIDFUNC(mov_w_mr(MEMW d, RR2 s));
+DECLARE_MIDFUNC(mov_w_rm(W2 d, MEMR s));
+DECLARE_MIDFUNC(mov_b_mr(MEMW d, RR1 s));
+DECLARE_MIDFUNC(mov_b_rm(W1 d, MEMR s));
+DECLARE_MIDFUNC(mov_l_ri(W4 d, IMPTR s));
 DECLARE_MIDFUNC(mov_w_ri(W2 d, IMM s));
 DECLARE_MIDFUNC(mov_b_ri(W1 d, IMM s));
-DECLARE_MIDFUNC(add_l_mi(IMM d, IMM s));
-DECLARE_MIDFUNC(add_w_mi(IMM d, IMM s));
-DECLARE_MIDFUNC(add_b_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(add_l_mi(MEMRW d, IMM s));
+DECLARE_MIDFUNC(add_w_mi(MEMRW d, IMM s));
+DECLARE_MIDFUNC(add_b_mi(MEMRW d, IMM s));
 DECLARE_MIDFUNC(test_l_ri(RR4 d, IMM i));
 DECLARE_MIDFUNC(test_l_rr(RR4 d, RR4 s));
 DECLARE_MIDFUNC(test_w_rr(RR2 d, RR2 s));
 DECLARE_MIDFUNC(test_b_rr(RR1 d, RR1 s));
-DECLARE_MIDFUNC(test_b_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(test_b_mi(MEMR d, IMM s));
 DECLARE_MIDFUNC(and_l_ri(RW4 d, IMM i));
 DECLARE_MIDFUNC(and_l(RW4 d, RR4 s));
 DECLARE_MIDFUNC(and_w(RW2 d, RR2 s));
@@ -167,7 +170,7 @@ DECLARE_MIDFUNC(add_b(RW1 d, RR1 s));
 DECLARE_MIDFUNC(sub_l_ri(RW4 d, IMM i));
 DECLARE_MIDFUNC(sub_w_ri(RW2 d, IMM i));
 DECLARE_MIDFUNC(sub_b_ri(RW1 d, IMM i));
-DECLARE_MIDFUNC(add_l_ri(RW4 d, IMM i));
+DECLARE_MIDFUNC(add_l_ri(RW4 d, IMPTR i));
 DECLARE_MIDFUNC(add_w_ri(RW2 d, IMM i));
 DECLARE_MIDFUNC(add_b_ri(RW1 d, IMM i));
 DECLARE_MIDFUNC(sbb_l(RW4 d, RR4 s));
@@ -217,7 +220,7 @@ DECLARE_MIDFUNC(fcut_r(FRW r));
 DECLARE_MIDFUNC(fmov_ext_mr(MEMPTRW m, FR r));
 DECLARE_MIDFUNC(fmov_ext_rm(FW r, MEMPTRR m));
 DECLARE_MIDFUNC(fmov_rr(FW d, FR s));
-DECLARE_MIDFUNC(fldcw_m_indexed(RR4 index, IMM base));
+DECLARE_MIDFUNC(fldcw_m_indexed(RR4 index, MEMR base));
 DECLARE_MIDFUNC(ftst_r(FR r));
 DECLARE_MIDFUNC(dont_care_fflags(void));
 DECLARE_MIDFUNC(fsqrt_rr(FW d, FR s));
diff --git a/jit/compemu_support.cpp b/jit/compemu_support.cpp
index 5645f97a..a56a1a7d 100644
--- a/jit/compemu_support.cpp
+++ b/jit/compemu_support.cpp
@@ -1,3 +1,6 @@
+#if defined(CPU_AARCH64)
+#include "arm/compemu_support_arm.cpp"
+#else
 /*
  * compiler/compemu_support.cpp - Core dynamic translation engine
  *
@@ -28,6 +31,7 @@
  * along with ARAnyM; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+#include "sysdeps.h"
 
 #ifdef UAE
 
@@ -48,8 +52,8 @@
  * code is not 64-bit clean and (ii) it's faster to resolve branches
  * that way.
  */
-#if !defined(CPU_i386) && !defined(CPU_x86_64) && !defined(CPU_arm)
-#error "Only IA-32, X86-64 and ARM v6 targets are supported with the JIT Compiler"
+#if !defined(CPU_i386) && !defined(CPU_x86_64) && !defined(CPU_arm) && !defined(CPU_AARCH64)
+#error "Only IA-32, X86-64, ARM and ARM64 targets are supported with the JIT Compiler"
 #endif
 #endif
 
@@ -102,23 +106,446 @@ static void build_comp(void);
 #endif
 #include "uae/log.h"
 
-#if defined(__pie__) || defined (__PIE__)
-#error Position-independent code (PIE) cannot be used with JIT
-#endif
+/* PIE is now supported on x86-64: the anchor-based JIT allocator
+ * keeps code within RIP-relative range of globals. FreeBSD still
+ * requires -fno-pie (ADDR32+MAP_32BIT strategy). */
 
 #include "uae/vm.h"
+#if defined(CPU_x86_64) && !defined(_WIN32)
+#include <sys/mman.h>
+#endif
+#if defined(CPU_x86_64) && defined(__APPLE__)
+#include <mach/mach.h>
+#include <mach/mach_vm.h>
+#include <mach/vm_region.h>
+#endif
 #define VM_PAGE_READ UAE_VM_READ
 #define VM_PAGE_WRITE UAE_VM_WRITE
 #define VM_PAGE_EXECUTE UAE_VM_EXECUTE
 #define VM_MAP_FAILED UAE_VM_ALLOC_FAILED
-#define VM_MAP_DEFAULT 1
-#define VM_MAP_32BIT 1
+#define VM_MAP_DEFAULT 0
+#define VM_MAP_32BIT   1
 #define vm_protect(address, size, protect) uae_vm_protect(address, size, protect)
 #define vm_release(address, size) uae_vm_free(address, size)
 
-static inline void *vm_acquire(uae_u32 size, int options = VM_MAP_DEFAULT)
+#if defined(CPU_x86_64)
+/*
+ * JIT cache allocation strategy (PIE-compatible):
+ *
+ * x86-64 JIT uses RIP-relative [RIP+disp32] addressing to access globals
+ * (regs, regflags, etc.) via the _r_X() macro. This requires the JIT code
+ * cache to be within +/-2GB of .data.
+ *
+ * Under non-PIE, .data is at a fixed low address and MAP_32BIT suffices.
+ * Under PIE+ASLR, .data can be anywhere in the 47-bit VA space.
+ *
+ * We use an anchor-based probe: &data_anchor is a reference point in .data,
+ * and we search outward from it for a free VA range. This mirrors the
+ * Windows strategy (VirtualQuery walk from data_anchor).
+ *
+ * The probe covers +/-1.75GB at 2MB intervals, well within the +/-2GB
+ * RIP-relative limit.
+ */
+
+/* jit_vm_acquire() uses this as the RIP-relative allocation anchor.
+ * Set to the JIT cache base after alloc_cache() succeeds.
+ * All x86-64 platforms need this since RIP-relative addressing
+ * requires JIT allocations within +/-2GB of both code and globals. */
+static uae_u8* vm_acquire_anchor = NULL;
+#endif
+
+static inline bool jit_vm_alloc_failed(const void *ptr)
+{
+	return ptr == NULL || ptr == VM_MAP_FAILED;
+}
+
+#if defined(CPU_x86_64) && defined(__linux__)
+/* VMA-aware near-address allocator - Linux equivalent of the Windows
+ * VirtualQuery walk.  Parses /proc/self/maps to find the closest gap
+ * to `base` that can hold `size` bytes within `range`.
+ * Returns mmap'd pointer on success, NULL on failure. */
+static void *find_nearest_gap(uintptr base, uae_u32 size, uintptr range)
 {
-	assert(options == (VM_MAP_DEFAULT | VM_MAP_32BIT));
+	FILE *maps = fopen("/proc/self/maps", "r");
+	if (!maps)
+		return NULL;
+
+	const uintptr granularity = 0x10000;  /* 64KB, matches Windows path */
+	uintptr lo = (base > range) ? (base - range) : granularity;
+	uintptr hi = base + range;
+
+	void *best = NULL;
+	uintptr best_dist = UINTPTR_MAX;
+	uintptr prev_end = 0;
+
+	char line[512];
+	while (fgets(line, sizeof(line), maps)) {
+		unsigned long vma_start, vma_end;
+		if (sscanf(line, "%lx-%lx", &vma_start, &vma_end) != 2)
+			continue;
+
+		/* Check the gap between prev_end and this VMA's start */
+		if (vma_start > prev_end && prev_end > 0) {
+			uintptr gap_start = prev_end;
+			uintptr gap_end = vma_start;
+			uintptr gap_size = gap_end - gap_start;
+
+			if (gap_size >= size && gap_start < hi && gap_end > lo) {
+				/* Find the address in this gap closest to base */
+				uintptr alloc_at;
+				if (base >= gap_start && base + size <= gap_end) {
+					/* Gap contains base - ideal */
+					alloc_at = base & ~(granularity - 1);
+				} else if (gap_end <= base) {
+					/* Gap is below base - use highest aligned addr */
+					alloc_at = (gap_end - size) & ~(granularity - 1);
+				} else {
+					/* Gap is above base - use lowest aligned addr */
+					alloc_at = (gap_start + granularity - 1) & ~(granularity - 1);
+				}
+
+				if (alloc_at >= gap_start && alloc_at + size <= gap_end &&
+					alloc_at >= lo && alloc_at + size <= hi) {
+					uintptr dist = (alloc_at >= base)
+						? (alloc_at - base) : (base - alloc_at);
+					if (dist < best_dist) {
+						best = (void *)alloc_at;
+						best_dist = dist;
+					}
+				}
+			}
+		}
+		prev_end = vma_end;
+	}
+	fclose(maps);
+
+	if (!best)
+		return NULL;
+
+	/* Try atomic claim with MAP_FIXED_NOREPLACE first */
+#ifdef MAP_FIXED_NOREPLACE
+	void *result = mmap(best, size, PROT_READ | PROT_WRITE,
+		MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED_NOREPLACE, -1, 0);
+	if (result != MAP_FAILED)
+		return result;
+#endif
+	/* Fallback: hint-based (kernel may slide it) */
+	void *result2 = mmap(best, size, PROT_READ | PROT_WRITE,
+		MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	if (result2 != MAP_FAILED) {
+		uintptr dist = ((uintptr)result2 >= base)
+			? ((uintptr)result2 - base) : (base - (uintptr)result2);
+		if (dist < range)
+			return result2;
+		munmap(result2, size);
+	}
+	return NULL;
+}
+#endif /* CPU_x86_64 && __linux__ */
+
+#if defined(CPU_x86_64) && defined(__APPLE__)
+#ifndef VM_FLAGS_FIXED
+#define VM_FLAGS_FIXED 0
+#endif
+
+static void *mach_vm_allocate_fixed(uintptr try_addr, uae_u32 size)
+{
+	mach_vm_address_t address = (mach_vm_address_t)try_addr;
+	const kern_return_t kr = mach_vm_allocate(
+		mach_task_self(), &address, size, VM_FLAGS_FIXED);
+	if (kr != KERN_SUCCESS)
+		return NULL;
+	if ((uintptr)address == try_addr)
+		return (void *)address;
+	mach_vm_deallocate(mach_task_self(), address, size);
+	return NULL;
+}
+
+static void *mach_vm_try_gap(uintptr gap_start, uintptr gap_end, uintptr base,
+	uae_u32 size, uintptr page, void *best, uintptr *best_dist)
+{
+	if (gap_end <= gap_start || gap_end - gap_start < size)
+		return best;
+
+	uintptr alloc_at;
+	if (base >= gap_start && base + size <= gap_end) {
+		alloc_at = base & ~(page - 1);
+		if (alloc_at < gap_start)
+			alloc_at += page;
+	} else if (gap_end <= base) {
+		alloc_at = (gap_end - size) & ~(page - 1);
+	} else {
+		alloc_at = (gap_start + page - 1) & ~(page - 1);
+	}
+	if (alloc_at < gap_start || alloc_at + size > gap_end)
+		return best;
+
+	const uintptr dist = (alloc_at >= base) ? (alloc_at - base) : (base - alloc_at);
+	if (dist >= *best_dist)
+		return best;
+
+	void *candidate = mach_vm_allocate_fixed(alloc_at, size);
+	if (!candidate)
+		return best;
+	if (best)
+		mach_vm_deallocate(mach_task_self(), (mach_vm_address_t)best, size);
+	*best_dist = dist;
+	return candidate;
+}
+
+static void *mach_vm_acquire_near(uintptr base, uae_u32 size, uintptr range)
+{
+	const uintptr page = (uintptr)uae_vm_page_size();
+	const uintptr lo = (base > range) ? (base - range) : page;
+	const uintptr hi = base + range;
+	const uintptr rounded_size = (size + page - 1) & ~(page - 1);
+
+	void *best = NULL;
+	uintptr best_dist = UINTPTR_MAX;
+	uintptr prev_end = lo;
+	mach_vm_address_t address = (mach_vm_address_t)lo;
+
+	while ((uintptr)address < hi) {
+		mach_vm_size_t region_size = 0;
+		natural_t depth = 0;
+		vm_region_submap_info_data_64_t info;
+		mach_msg_type_number_t count = VM_REGION_SUBMAP_INFO_COUNT_64;
+		const kern_return_t kr = mach_vm_region_recurse(
+			mach_task_self(), &address, &region_size, &depth,
+			(vm_region_recurse_info_t)&info, &count);
+		if (kr != KERN_SUCCESS)
+			break;
+
+		uintptr region_start = (uintptr)address;
+		uintptr region_end = region_start + (uintptr)region_size;
+		if (region_start > hi)
+			region_start = hi;
+		if (region_start > prev_end) {
+			best = mach_vm_try_gap(prev_end, region_start, base,
+				(uae_u32)rounded_size, page, best, &best_dist);
+			if (best_dist == 0)
+				return best;
+		}
+		if (region_end <= prev_end)
+			region_end = prev_end + page;
+		prev_end = region_end;
+		address = (mach_vm_address_t)region_end;
+	}
+
+	if (prev_end < hi) {
+		best = mach_vm_try_gap(prev_end, hi, base,
+			(uae_u32)rounded_size, page, best, &best_dist);
+	}
+	if (best)
+		return best;
+
+	const uintptr stride = rounded_size > 0x10000 ? 0x10000 : page;
+	for (uintptr offset = 0; offset < range; offset += stride) {
+		for (int dir = 0; dir < 2; dir++) {
+			if (offset == 0 && dir == 1)
+				continue;
+			if (dir == 1 && base <= offset)
+				continue;
+			uintptr try_addr = dir == 0 ? base + offset : base - offset;
+			try_addr &= ~(page - 1);
+			if (try_addr < lo || try_addr + rounded_size > hi)
+				continue;
+			void *candidate = mach_vm_allocate_fixed(try_addr, (uae_u32)rounded_size);
+			if (candidate)
+				return candidate;
+		}
+	}
+	return best;
+}
+#endif /* CPU_x86_64 && __APPLE__ */
+
+void *jit_vm_acquire(uae_u32 size, int options)
+{
+#if defined(CPU_x86_64)
+	if (!(options & VM_MAP_32BIT)) {
+#ifdef _WIN32
+		/* RIP-relative addressing (the _r_X macro in codegen_x86.h)
+		 * requires all targets within +/-2GB of the JIT code that
+		 * references them.  Anchor at compiled_code (JIT cache base)
+		 * when available; fall back to a .data anchor for the first
+		 * allocation (the JIT cache itself).
+		 * Use VirtualQuery to find the closest free region within
+		 * +/-1.75GB - this avoids the blind 16MB-step probe that
+		 * exhausts in congested ASLR address spaces. */
+		uintptr base;
+		if (vm_acquire_anchor) {
+			base = (uintptr)vm_acquire_anchor;
+		} else {
+			static int anchor;
+			base = (uintptr)&anchor;
+		}
+		base &= ~(uintptr)0xFFFF;
+		const uintptr range = 0x70000000ULL;  /* 1.75GB */
+		const uintptr granularity = 0x10000;  /* Windows 64KB alloc granularity */
+		uintptr lo = (base > range) ? (base - range) : 0;
+		uintptr hi = base + range;
+
+		/* Walk the address space with VirtualQuery to find the
+		 * closest free region large enough for this allocation. */
+		void *best = NULL;
+		uintptr best_dist = UINTPTR_MAX;
+		uintptr addr = lo;
+		while (addr < hi) {
+			MEMORY_BASIC_INFORMATION mbi;
+			if (VirtualQuery((void *)addr, &mbi, sizeof(mbi)) == 0)
+				break;
+			uintptr region_base = (uintptr)mbi.BaseAddress;
+			uintptr region_end = region_base + mbi.RegionSize;
+			if (mbi.State == MEM_FREE && mbi.RegionSize >= size) {
+				/* Pick the address in this region closest to base */
+				uintptr alloc_at;
+				if (base >= region_base && base < region_end) {
+					/* Region contains base - ideal */
+					alloc_at = base & ~(granularity - 1);
+				} else if (region_end <= base) {
+					/* Region is below base - use highest aligned addr */
+					alloc_at = (region_end - size) & ~(granularity - 1);
+				} else {
+					/* Region is above base - use lowest aligned addr */
+					alloc_at = (region_base + granularity - 1) & ~(granularity - 1);
+				}
+				if (alloc_at >= region_base && alloc_at + size <= region_end &&
+					alloc_at >= lo && alloc_at + size <= hi) {
+					uintptr dist = (alloc_at >= base) ? (alloc_at - base) : (base - alloc_at);
+					if (dist < best_dist) {
+						best = (void *)alloc_at;
+						best_dist = dist;
+					}
+				}
+			}
+			/* Advance to next region */
+			if (region_end <= addr) break;  /* overflow protection */
+			addr = region_end;
+		}
+		void *result = NULL;
+		if (best) {
+			result = VirtualAlloc(best, size, MEM_COMMIT | MEM_RESERVE, PAGE_READWRITE);
+		}
+		if (!result) {
+			/* Last resort: OS choice - range-check the result to avoid
+			 * silent RIP-relative overflow in pool allocations that
+			 * bypass alloc_cache()'s post-hoc distance check. */
+			result = VirtualAlloc(NULL, size, MEM_COMMIT | MEM_RESERVE, PAGE_READWRITE);
+			if (result) {
+				intptr_t dist = (intptr_t)result - (intptr_t)base;
+				if (llabs(dist) >= (intptr_t)range) {
+					VirtualFree(result, 0, MEM_RELEASE);
+					result = NULL;
+				}
+			}
+		}
+		return result;
+#else
+#if defined(__FreeBSD__)
+		/* FreeBSD: ASLR defeats anchor-based hints. Delegate to
+		 * uae_vm_alloc with UAE_VM_32BIT (MAP_32BIT), guaranteeing
+		 * allocation below 2GB where ADDR32 absolute addressing works. */
+		return uae_vm_alloc(size, UAE_VM_32BIT, UAE_VM_READ_WRITE);
+#else
+		/* Linux/POSIX x86-64: RIP-relative addressing (the _r_X macro)
+		 * requires all JIT allocations within +/-2GB of both the JIT code
+		 * and global variables in the .data segment. Use compiled_code
+		 * as anchor when available, otherwise a .data section anchor.
+		 * Try mmap with hints near the anchor; fall back to unanchored. */
+		static int data_anchor;
+		uintptr base = vm_acquire_anchor
+			? (uintptr)vm_acquire_anchor
+			: (uintptr)&data_anchor;
+		base &= ~(uintptr)0xFFFF;
+		const uintptr range = 0x70000000ULL;  /* 1.75GB */
+
+		uintptr lo = (base > range) ? (base - range) : 0x10000;
+		uintptr hi = base + range;
+		void *result = NULL;
+
+#ifdef __linux__
+		result = find_nearest_gap(base, size, range);
+		if (result)
+			return result;
+#endif
+#ifdef __APPLE__
+		result = mach_vm_acquire_near(base, size, range);
+		if (result)
+			return result;
+#endif
+
+#ifdef MAP_FIXED_NOREPLACE
+		int extra_flags = MAP_FIXED_NOREPLACE;
+#else
+		int extra_flags = 0;
+#endif
+
+		uintptr stride = (size + 0xFFFF) & ~(uintptr)0xFFFF;
+		if (stride < 0x10000)
+			stride = 0x10000;
+
+		for (uintptr offset = 0; offset < range && !result; offset += stride) {
+			/* Try above anchor */
+			uintptr try_addr = base + offset;
+			if (try_addr >= lo && try_addr + size <= hi) {
+				result = mmap((void *)try_addr, size, PROT_READ | PROT_WRITE,
+					MAP_PRIVATE | MAP_ANONYMOUS | extra_flags, -1, 0);
+				if (result != MAP_FAILED) {
+					uintptr dist = ((uintptr)result >= base)
+						? ((uintptr)result - base) : (base - (uintptr)result);
+					if (dist < range)
+						break;
+					munmap(result, size);
+					result = NULL;
+				} else {
+					result = NULL;
+				}
+			}
+			if (offset == 0)
+				continue;
+			/* Try below anchor */
+			if (base > offset) {
+				try_addr = base - offset;
+				if (try_addr >= lo && try_addr + size <= hi) {
+					result = mmap((void *)try_addr, size, PROT_READ | PROT_WRITE,
+						MAP_PRIVATE | MAP_ANONYMOUS | extra_flags, -1, 0);
+					if (result != MAP_FAILED) {
+						uintptr dist = ((uintptr)result >= base)
+							? ((uintptr)result - base) : (base - (uintptr)result);
+						if (dist < range)
+							break;
+						munmap(result, size);
+						result = NULL;
+					} else {
+						result = NULL;
+					}
+				}
+			}
+		}
+		if (!result) {
+			for (int attempt = 0; attempt < 2 && !result; attempt++) {
+				void *try_alloc = (attempt == 0)
+					? uae_vm_alloc(size, UAE_VM_32BIT, UAE_VM_READ_WRITE)
+					: uae_vm_alloc(size, 0, UAE_VM_READ_WRITE);
+				if (jit_vm_alloc_failed(try_alloc))
+					continue;
+				intptr_t dist = (intptr_t)try_alloc - (intptr_t)base;
+				if (llabs(dist) >= (intptr_t)range) {
+					uae_vm_free(try_alloc, size);
+					continue;
+				}
+				result = try_alloc;
+			}
+			if (!result) {
+				write_log("JIT: WARNING: could not allocate within 2GB of globals "
+					"(anchor=%p)\n", (void *)base);
+			}
+		}
+		return result;
+#endif /* !__FreeBSD__ */
+#endif /* !_WIN32 */
+	}
+#endif
 	return uae_vm_alloc(size, UAE_VM_32BIT, UAE_VM_READ_WRITE);
 }
 
@@ -126,10 +553,10 @@ static inline void *vm_acquire(uae_u32 size, int options = VM_MAP_DEFAULT)
 #include "uae.h"
 #include "uae/log.h"
 #define jit_log(format, ...) \
-	uae_log("JIT: " format "\n", ##__VA_ARGS__);
+	write_log("JIT: " format "\n", ##__VA_ARGS__);
 #define jit_log2(format, ...)
 
-#define MEMBaseDiff uae_p32(NATMEM_OFFSET)
+#define MEMBaseDiff ((uintptr)NATMEM_OFFSET)
 
 #ifdef NATMEM_OFFSET
 #define FIXED_ADDRESSING 1
@@ -137,6 +564,8 @@ static inline void *vm_acquire(uae_u32 size, int options = VM_MAP_DEFAULT)
 
 // %%% BRIAN KING WAS HERE %%%
 extern bool canbang;
+extern int jit_n_addr_unsafe;
+extern int jit_n_addr_bank_unsafe;
 
 #include "compemu_prefs.cpp"
 
@@ -182,6 +611,16 @@ static inline int distrust_addr(void)
 	return distrust_check(currprefs.comptrustnaddr);
 }
 
+static inline bool jit_use_memory_helpers(void)
+{
+	return jit_n_addr_bank_unsafe || (jit_n_addr_unsafe && !canbang);
+}
+
+static inline bool jit_use_compile_fallbacks(void)
+{
+	return jit_n_addr_bank_unsafe;
+}
+
 #else
 #define DEBUG 0
 #include "debug.h"
@@ -240,7 +679,7 @@ static int reg_count_compare(const void *ap, const void *bp)
 #ifdef PROFILE_COMPILE_TIME
 #include <time.h>
 static uae_u32 compile_count	= 0;
-static clock_t compile_time		= 0;
+static clock_t compile_time	= 0;
 static clock_t emul_start_time	= 0;
 static clock_t emul_end_time	= 0;
 #endif
@@ -340,6 +779,16 @@ static inline bool is_const_jump(uae_u32 opcode)
 	return (prop[opcode].cflow == fl_const_jump);
 }
 
+static inline bool is_dbcc_opcode(uae_u32 opcode)
+{
+	return (opcode & 0xf0f8) == 0x50c8;
+}
+
+static inline bool is_cmp_w_an_postinc_dn_opcode(uae_u32 opcode)
+{
+	return (opcode & 0xf1f8) == 0xb058;
+}
+
 #if 0
 static inline bool may_trap(uae_u32 opcode)
 {
@@ -366,7 +815,7 @@ static inline unsigned int cft_map (unsigned int f)
 
 uae_u8* start_pc_p;
 uae_u32 start_pc;
-uae_u32 current_block_pc_p;
+uintptr current_block_pc_p;
 static uintptr current_block_start_target;
 uae_u32 needed_flags;
 static uintptr next_pc_p;
@@ -415,6 +864,21 @@ static void flush_icache_lazy(int);
 static void flush_icache_none(int);
 //void (*flush_icache)(int) = flush_icache_none;
 
+#ifdef UAE
+void disable_jit_on_runtime_alloc_failure(const char *what)
+{
+	if (!cache_enabled && currprefs.cachesize == 0 && changed_prefs.cachesize == 0)
+		return;
+
+	write_log("JIT: WARNING: %s\n", what);
+	write_log("JIT: WARNING: Disabling JIT and falling back to the interpreter.\n");
+
+	cache_enabled = 0;
+	currprefs.cachesize = 0;
+	changed_prefs.cachesize = 0;
+}
+#endif
+
 static bigstate live;
 static smallstate empty_ss;
 static smallstate default_ss;
@@ -716,7 +1180,7 @@ static inline void invalidate_block(blockinfo* bi)
 	remove_deps(bi);
 }
 
-static inline void create_jmpdep(blockinfo* bi, int i, uae_u32* jmpaddr, uae_u32 target)
+static inline void create_jmpdep(blockinfo* bi, int i, uae_u32* jmpaddr, uintptr target)
 {
 	blockinfo*  tbi=get_blockinfo_addr((void*)(uintptr)target);
 
@@ -803,7 +1267,12 @@ static inline blockinfo* get_blockinfo_addr_new(void* addr, int /* setstate */)
 		}
 	}
 	if (!bi) {
+#ifdef UAE
+		disable_jit_on_runtime_alloc_failure("Looking for blockinfo, can't find free one");
+		return NULL;
+#else
 		jit_abort("Looking for blockinfo, can't find free one");
+#endif
 	}
 	return bi;
 }
@@ -869,9 +1338,20 @@ T * LazyBlockAllocator<T>::acquire()
 	if (!mChunks) {
 		// There is no chunk left, allocate a new pool and link the
 		// chunks into the free list
-		Pool * newPool = (Pool *)vm_acquire(sizeof(Pool), VM_MAP_DEFAULT | VM_MAP_32BIT);
-		if (newPool == VM_MAP_FAILED) {
+#if defined(CPU_x86_64) && defined(__FreeBSD__)
+		Pool * newPool = (Pool *)jit_vm_acquire(sizeof(Pool), VM_MAP_DEFAULT | VM_MAP_32BIT);
+#elif defined(CPU_x86_64)
+		Pool * newPool = (Pool *)jit_vm_acquire(sizeof(Pool), VM_MAP_DEFAULT);
+#else
+		Pool * newPool = (Pool *)jit_vm_acquire(sizeof(Pool), VM_MAP_DEFAULT | VM_MAP_32BIT);
+#endif
+		if (jit_vm_alloc_failed(newPool)) {
+#ifdef UAE
+			disable_jit_on_runtime_alloc_failure("Could not allocate block pool!");
+			return NULL;
+#else
 			jit_abort("Could not allocate block pool!");
+#endif
 		}
 		for (T * chunk = &newPool->chunk[0]; chunk < &newPool->chunk[kPoolSize]; chunk++) {
 			chunk->next = mChunks;
@@ -918,12 +1398,16 @@ static HardBlockAllocator<checksum_info> ChecksumInfoAllocator;
 static inline checksum_info *alloc_checksum_info(void)
 {
 	checksum_info *csi = ChecksumInfoAllocator.acquire();
+	if (!csi)
+		return NULL;
 	csi->next = NULL;
 	return csi;
 }
 
 static inline void free_checksum_info(checksum_info *csi)
 {
+	if (!csi)
+		return;
 	csi->next = NULL;
 	ChecksumInfoAllocator.release(csi);
 }
@@ -940,6 +1424,8 @@ static inline void free_checksum_info_chain(checksum_info *csi)
 static inline blockinfo *alloc_blockinfo(void)
 {
 	blockinfo *bi = BlockInfoAllocator.acquire();
+	if (!bi)
+		return NULL;
 #if USE_CHECKSUM_INFO
 	bi->csi = NULL;
 #endif
@@ -948,6 +1434,8 @@ static inline blockinfo *alloc_blockinfo(void)
 
 static inline void free_blockinfo(blockinfo *bi)
 {
+	if (!bi)
+		return;
 #if USE_CHECKSUM_INFO
 	free_checksum_info_chain(bi->csi);
 	bi->csi = NULL;
@@ -955,17 +1443,20 @@ static inline void free_blockinfo(blockinfo *bi)
 	BlockInfoAllocator.release(bi);
 }
 
-static inline void alloc_blockinfos(void)
+static inline bool alloc_blockinfos(void)
 {
 	int i;
 	blockinfo* bi;
 
 	for (i=0;i<MAX_HOLD_BI;i++) {
 		if (hold_bi[i])
-			return;
+			return true;
 		bi=hold_bi[i]=alloc_blockinfo();
+		if (!bi)
+			return false;
 		prepare_block(bi);
 	}
+	return true;
 }
 
 /********************************************************************
@@ -1517,6 +2008,12 @@ static inline void do_load_reg(int n, int r)
 		raw_load_flagreg(n);
 	else if (r == FLAGX)
 		raw_load_flagx(n);
+#if X86_TARGET_64BIT
+	else if (r == PC_P) {
+		/* PC_P holds a 64-bit host pointer - must use 64-bit load */
+		raw_mov_q_rm(n, (uintptr)live.state[r].mem);
+	}
+#endif
 	else
 		compemu_raw_mov_l_rm(n, JITPTR  live.state[r].mem);
 }
@@ -1610,13 +2107,94 @@ static inline int isinreg(int r)
 	return live.state[r].status==CLEAN || live.state[r].status==DIRTY;
 }
 
-static inline void adjust_nreg(int r, uae_u32 val)
+static inline void adjust_nreg(int r, uintptr val)
 {
 	if (!val)
 		return;
 	compemu_raw_lea_l_brr(r,r,val);
 }
 
+#if X86_TARGET_64BIT
+static inline void free_nreg(int r);
+
+static inline bool x86_imm_fits_s32(uintptr i)
+{
+	const intptr_t si = static_cast<intptr_t>(i);
+	return si >= static_cast<intptr_t>(-2147483647 - 1) &&
+		si <= static_cast<intptr_t>(2147483647);
+}
+
+static inline int get_unlocked_scratch_nreg_excluding(int avoid1, int avoid2)
+{
+	static const int candidates[] = {
+		R11_INDEX, R10_INDEX, R9_INDEX, R8_INDEX,
+		EAX_INDEX, ECX_INDEX, EDX_INDEX, EBX_INDEX,
+		EBP_INDEX, ESI_INDEX, EDI_INDEX, R13_INDEX, R14_INDEX
+	};
+
+	for (int r : candidates) {
+		if (r != avoid1 && r != avoid2 && !live.nat[r].locked)
+			return r;
+	}
+
+	jit_abort("No unlocked scratch register for 64-bit pointer operation");
+	return R11_INDEX;
+}
+
+static inline int get_unlocked_scratch_nreg(void)
+{
+	return get_unlocked_scratch_nreg_excluding(-1, -1);
+}
+
+static inline void x86_add_q_ri_ptr(int d, uintptr i, int avoid = -1)
+{
+	if (x86_imm_fits_s32(i)) {
+		ADDQir(static_cast<IMM>(i), d);
+	} else {
+		const int scratch = get_unlocked_scratch_nreg_excluding(d, avoid);
+		free_nreg(scratch);
+		MOVQir(i, scratch);
+		ADDQrr(scratch, d);
+	}
+}
+
+static inline void copy_vreg_nreg(int vreg, int dst, int src)
+{
+	if (vreg == PC_P) {
+		MOVQrr(src, dst);
+	} else {
+		compemu_raw_mov_l_rr(dst, src);
+	}
+}
+
+static inline void adjust_vreg_nreg(int vreg, int nreg, uintptr val)
+{
+	if (!val)
+		return;
+	if (vreg == PC_P) {
+		const intptr_t svalue = static_cast<intptr_t>(val);
+		if (svalue >= static_cast<intptr_t>(-2147483647 - 1) &&
+			svalue <= static_cast<intptr_t>(2147483647)) {
+			LEAQmr(static_cast<IMM>(svalue), nreg, X86_NOREG, 1, nreg);
+		} else {
+			x86_add_q_ri_ptr(nreg, val);
+		}
+	} else {
+		adjust_nreg(nreg, val);
+	}
+}
+#else
+static inline void copy_vreg_nreg(int /* vreg */, int dst, int src)
+{
+	compemu_raw_mov_l_rr(dst, src);
+}
+
+static inline void adjust_vreg_nreg(int /* vreg */, int nreg, uintptr val)
+{
+	adjust_nreg(nreg, val);
+}
+#endif
+
 static void tomem(int r)
 {
 	int rr=live.state[r].realreg;
@@ -1625,7 +2203,7 @@ static void tomem(int r)
 		if (live.state[r].val && live.nat[rr].nholds==1
 			&& !live.nat[rr].locked) {
 			jit_log2("RemovingA offset %x from reg %d (%d) at %p", live.state[r].val,r,rr,target);
-			adjust_nreg(rr,live.state[r].val);
+			adjust_vreg_nreg(r,rr,live.state[r].val);
 			live.state[r].val=0;
 			live.state[r].dirtysize=4;
 			set_status(r,DIRTY);
@@ -1636,7 +2214,17 @@ static void tomem(int r)
 		switch (live.state[r].dirtysize) {
 		case 1: compemu_raw_mov_b_mr(JITPTR live.state[r].mem,rr); break;
 		case 2: compemu_raw_mov_w_mr(JITPTR live.state[r].mem,rr); break;
-		case 4: compemu_raw_mov_l_mr(JITPTR live.state[r].mem,rr); break;
+		case 4:
+#if X86_TARGET_64BIT
+			if (r == PC_P) {
+				/* PC_P holds a 64-bit host pointer - must use 64-bit store */
+				raw_mov_q_mr((uintptr)live.state[r].mem, rr);
+			} else
+#endif
+			{
+				compemu_raw_mov_l_mr(JITPTR live.state[r].mem, rr);
+			}
+			break;
 		default: abort();
 		}
 		log_vwrite(r);
@@ -1650,6 +2238,16 @@ static inline int isconst(int r)
 	return live.state[r].status==ISCONST;
 }
 
+#if X86_TARGET_64BIT
+static inline void store_const_q_mi(uintptr d, uintptr s)
+{
+	int scratch = get_unlocked_scratch_nreg();
+	free_nreg(scratch);
+	raw_mov_q_ri(scratch, s);
+	raw_mov_q_mr(d, scratch);
+}
+#endif
+
 int is_const(int r)
 {
 	return isconst(r);
@@ -1663,7 +2261,15 @@ static inline void writeback_const(int r)
 		jit_abort("Trying to write back constant NF_HANDLER!");
 	}
 
-	compemu_raw_mov_l_mi(JITPTR live.state[r].mem,live.state[r].val);
+#if X86_TARGET_64BIT
+	if (r == PC_P) {
+		/* PC_P holds a 64-bit host pointer and needs allocator-aware scratch use. */
+		store_const_q_mi((uintptr)live.state[r].mem, live.state[r].val);
+	} else
+#endif
+	{
+		compemu_raw_mov_l_mi(JITPTR live.state[r].mem, live.state[r].val);
+	}
 	log_vwrite(r);
 	live.state[r].val=0;
 	set_status(r,INMEM);
@@ -1737,10 +2343,15 @@ static inline void disassociate(int r)
 	evict(r);
 }
 
-/* XXFIXME: val may be 64bit address for PC_P */
-static inline void set_const(int r, uae_u32 val)
+static inline void set_const(int r, uintptr val)
 {
 	disassociate(r);
+#if X86_TARGET_64BIT
+	/* Guest Dn/An/flag virtual registers are 32-bit M68K values.
+	   PC_P is the only virtual register that may hold a 64-bit host pointer. */
+	if (r != PC_P)
+		val = (uae_u32)val;
+#endif
 	live.state[r].val=val;
 	set_status(r,ISCONST);
 }
@@ -1815,7 +2426,15 @@ static int alloc_reg_hinted(int r, int size, int willclobber, int hint)
 	if (!willclobber) {
 		if (live.state[r].status!=UNDEF) {
 			if (isconst(r)) {
-				compemu_raw_mov_l_ri(bestreg,live.state[r].val);
+#if X86_TARGET_64BIT
+				if (r == PC_P || live.state[r].val > (uintptr)0xffffffff) {
+					/* PC_P and temporary host pointers need the full 64-bit value. */
+					raw_mov_q_ri(bestreg, live.state[r].val);
+				} else
+#endif
+				{
+					compemu_raw_mov_l_ri(bestreg, live.state[r].val);
+				}
 				live.state[r].val=0;
 				live.state[r].dirtysize=4;
 				set_status(r,DIRTY);
@@ -1852,8 +2471,16 @@ static int alloc_reg_hinted(int r, int size, int willclobber, int hint)
 			}
 		}
 		else {
-			if (live.state[r].status!=UNDEF)
-				compemu_raw_mov_l_ri(bestreg,live.state[r].val);
+			if (live.state[r].status!=UNDEF) {
+#if X86_TARGET_64BIT
+				if (r == PC_P || live.state[r].val > (uintptr)0xffffffff) {
+					raw_mov_q_ri(bestreg, live.state[r].val);
+				} else
+#endif
+				{
+					compemu_raw_mov_l_ri(bestreg, live.state[r].val);
+				}
+			}
 			live.state[r].val=0;
 			live.state[r].validsize=4;
 			live.state[r].dirtysize=4;
@@ -1974,20 +2601,19 @@ static inline void make_exclusive(int r, int size, int spec)
 	live.state[r].realind=nind;
 
 	if (size<live.state[r].validsize) {
+		copy_vreg_nreg(r,nr,rr);
 		if (live.state[r].val) {
-			/* Might as well compensate for the offset now */
-			compemu_raw_lea_l_brr(nr,rr,oldstate.val);
+			/* Split first, then compensate for the deferred offset. */
+			adjust_vreg_nreg(r,nr,oldstate.val);
 			live.state[r].val=0;
 			live.state[r].dirtysize=4;
 			set_status(r,DIRTY);
 		}
-		else
-			compemu_raw_mov_l_rr(nr,rr);  /* Make another copy */
 	}
 	unlock2(rr);
 }
 
-static inline void add_offset(int r, uae_u32 off)
+static inline void add_offset(int r, uintptr off)
 {
 	live.state[r].val+=off;
 }
@@ -2018,7 +2644,7 @@ static inline void remove_offset(int r, int spec)
 
 	if (live.nat[rr].nholds==1) {
 		jit_log2("RemovingB offset %x from reg %d (%d) at %p", live.state[r].val,r,rr,target);
-		adjust_nreg(rr,live.state[r].val);
+		adjust_vreg_nreg(r,rr,live.state[r].val);
 		live.state[r].dirtysize=4;
 		live.state[r].val=0;
 		set_status(r,DIRTY);
@@ -2306,11 +2932,15 @@ static void bt_l_ri_noclobber(RR4 r, IMM i)
 static void f_tomem(int r)
 {
 	if (live.fate[r].status==DIRTY) {
+#ifdef USE_LONG_DOUBLE
 		if (use_long_double) {
 			raw_fmov_ext_mr((uintptr)live.fate[r].mem, live.fate[r].realreg);
 		} else {
+#endif
 			raw_fmov_mr((uintptr)live.fate[r].mem, live.fate[r].realreg);
+#ifdef USE_LONG_DOUBLE
 		}
+#endif
 		live.fate[r].status=CLEAN;
 	}
 }
@@ -2318,11 +2948,15 @@ static void f_tomem(int r)
 static void f_tomem_drop(int r)
 {
 	if (live.fate[r].status==DIRTY) {
+#ifdef USE_LONG_DOUBLE
 		if (use_long_double) {
 			raw_fmov_ext_mr_drop((uintptr)live.fate[r].mem, live.fate[r].realreg);
 		} else {
+#endif
 			raw_fmov_mr_drop((uintptr)live.fate[r].mem,live.fate[r].realreg);
+#ifdef USE_LONG_DOUBLE
 		}
+#endif
 		live.fate[r].status=INMEM;
 	}
 }
@@ -2426,11 +3060,15 @@ static int f_alloc_reg(int r, int willclobber)
 
 	if (!willclobber) {
 		if (live.fate[r].status!=UNDEF) {
+#ifdef USE_LONG_DOUBLE
 			if (use_long_double) {
 				raw_fmov_ext_rm(bestreg, (uintptr)live.fate[r].mem);
 			} else {
+#endif
 				raw_fmov_rm(bestreg,(uintptr)live.fate[r].mem);
+#ifdef USE_LONG_DOUBLE
 			}
+#endif
 		}
 		live.fate[r].status=CLEAN;
 	}
@@ -2576,8 +3214,16 @@ static void align_target(uae_u32 a)
 static inline int isinrom(uintptr addr)
 {
 #ifdef UAE
-	return (addr >= uae_p32(kickmem_bank.baseaddr) &&
-			addr < uae_p32(kickmem_bank.baseaddr + 8 * 65536));
+	if (addr >= (uintptr)kickmem_bank.baseaddr &&
+		addr < (uintptr)kickmem_bank.baseaddr + 8 * 65536) {
+		return 1;
+	}
+	if (rtarea_bank.baseaddr &&
+		addr >= (uintptr)rtarea_bank.baseaddr &&
+		addr < (uintptr)rtarea_bank.baseaddr + 65536) {
+		return 1;
+	}
+	return 0;
 #else
 	return ((addr >= (uintptr)ROMBaseHost) && (addr < (uintptr)ROMBaseHost + ROMSize));
 #endif
@@ -2602,7 +3248,7 @@ static void flush_all(void)
 }
 
 /* Make sure all registers that will get clobbered by a call are
-   save and sound in memory */
+   safe and sound in memory */
 static void prepare_for_call_1(void)
 {
 	flush_all();  /* If there are registers that don't get clobbered,
@@ -2663,7 +3309,7 @@ int kill_rodent(int r)
 		 live.state[r].dirtysize==4);
 }
 
-uae_u32 get_const(int r)
+uintptr get_const(int r)
 {
 	Dif (!isconst(r)) {
 		jit_abort("Register %d should be constant, but isn't",r);
@@ -2680,6 +3326,43 @@ void sync_m68k_pc(void)
 	}
 }
 
+static inline uae_u32 get_virtual_compile_pc(uintptr native_pc)
+{
+	uae_u32 m68k_pc = (uae_u32)(start_pc + ((char*)native_pc - (char*)start_pc_p));
+#ifdef NATMEM_OFFSET
+	if (natmem_offset && native_pc >= (uintptr)natmem_offset &&
+		native_pc < (uintptr)natmem_offset + (uintptr)0x100000000ULL) {
+		m68k_pc = (uae_u32)(native_pc - (uintptr)natmem_offset);
+	}
+#endif
+	return m68k_pc;
+}
+
+static uintptr compiled_exception_native_pc;
+static uae_u32 compiled_exception_opcode;
+static bool compiled_exception_state_valid;
+static bool compiled_exception_state_emitted;
+
+static inline void prepare_compiled_exception_state(uintptr native_pc, uae_u32 opcode)
+{
+	compiled_exception_native_pc = native_pc;
+	compiled_exception_opcode = opcode;
+	compiled_exception_state_valid = true;
+	compiled_exception_state_emitted = false;
+}
+
+static inline void sync_compiled_exception_state(void)
+{
+	if (!compiled_exception_state_valid || compiled_exception_state_emitted)
+		return;
+
+	uae_u32 m68k_pc = get_virtual_compile_pc(compiled_exception_native_pc);
+	raw_mov_l_mi((uintptr)&regs.instruction_pc, m68k_pc);
+	raw_mov_w_mi((uintptr)&regs.opcode, compiled_exception_opcode);
+	raw_mov_w_mi((uintptr)&regs.ir, compiled_exception_opcode);
+	compiled_exception_state_emitted = true;
+}
+
 /* for building exception frames */
 void compemu_exc_make_frame(int format, int sr, int ret, int nr, int tmp)
 {
@@ -3114,6 +3797,17 @@ void flush_reg(int reg)
 		case INMEM:
 			if (live.state[reg].val)
 			{
+#if X86_TARGET_64BIT
+				if (reg == PC_P) {
+					/* PC_P is a 64-bit pointer - must use 64-bit load/add/store.
+					   compemu_raw_add_l_mi is only 32-bit and would leave
+					   upper 32 bits of regs.pc_p unmodified. */
+					int r_tmp = REG_PC_TMP;
+					raw_mov_q_rm(r_tmp, (uintptr)live.state[reg].mem);
+					x86_add_q_ri_ptr(r_tmp, live.state[reg].val);
+					raw_mov_q_mr((uintptr)live.state[reg].mem, r_tmp);
+				} else
+#endif
 				compemu_raw_add_l_mi(JITPTR live.state[reg].mem, live.state[reg].val);
 				log_vwrite(reg);
 				live.state[reg].val = 0;
@@ -3220,6 +3914,7 @@ static void freescratch(void)
 		if (live.nat[i].locked && i != ESP_INDEX
 #if defined(UAE) && defined(CPU_x86_64)
 			&& i != R12_INDEX
+			&& i != R_MEMSTART
 #endif
 			)
 #endif
@@ -3242,7 +3937,7 @@ static void freescratch(void)
  * Memory access and related functions, CREATE time                 *
  ********************************************************************/
 
-void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond)
+void register_branch(uintptr not_taken, uintptr taken, uae_u8 cond)
 {
 	next_pc_p=not_taken;
 	taken_pc_p=taken;
@@ -3313,23 +4008,69 @@ static inline void writemem(int address, int source, int offset, int size, int t
 {
 	int f=tmp;
 
+#if X86_TARGET_64BIT
+	/* x86-64: The register allocator only spills/reloads 32-bit values,
+	   so 64-bit pointers (addrbank ptr, function ptr) must NOT be stored
+	   in virtual registers.  Instead, compute the 32-bit bank index via
+	   the allocator, do all register setup for the call, then perform
+	   the 64-bit pointer chase with raw instructions after
+	   prepare_for_call_2() when all allocator bookkeeping is done but
+	   hardware register contents are still valid. */
+
+	/* Step 1: Compute bank index (32-bit, safe in virtual register) */
+	mov_l_rr(f, address);
+	shrl_l_ri(f, 16);
+
+	/* Step 2: Call setup (adapted from call_r_02 internals) */
+	clobber_flags();
+	remove_all_offsets();
+
+	int hw_addr = readreg_specific(address, 4, REG_PAR1);
+	int hw_src = readreg_specific(source, size, REG_PAR2);
+	int hw_f = readreg(f, 4);
+
+	prepare_for_call_1();
+	unlock2(hw_f);
+	unlock2(hw_addr);
+	unlock2(hw_src);
+	prepare_for_call_2();
+
+	/* Step 3: 64-bit pointer chase with raw instructions.
+	   hw_f still holds the bank index, REG_PAR1/PAR2 hold call args.
+	   Use a scratch register for the mem_banks base address. */
+	{
+		int scratch = (hw_f != R11_INDEX) ? R11_INDEX : R10_INDEX;
+		MOVQir((uintptr)mem_banks, scratch);
+		MOVQmr(0, scratch, hw_f, SIZEOF_VOID_P, hw_f);
+		/* hw_f now holds 64-bit addrbank pointer */
+		MOVQmr(offset, hw_f, X86_NOREG, 1, hw_f);
+		/* hw_f now holds 64-bit function pointer */
+	}
+
+	/* Step 4: Call */
+	raw_dec_sp(STACK_SHADOW_SPACE);
+	raw_call_r(hw_f);
+	raw_inc_sp(STACK_SHADOW_SPACE);
+
+	forget_about(tmp);
+#else
 	mov_l_rr(f,address);
-	shrl_l_ri(f,16);   /* The index into the mem bank table */
-	mov_l_rm_indexed(f,uae_p32(mem_banks),f,SIZEOF_VOID_P); /* FIXME: is SIZEOF_VOID_P correct? */
-	/* Now f holds a pointer to the actual membank */
+	shrl_l_ri(f,16);
+	mov_l_rm_indexed(f,uae_p32(mem_banks),f,SIZEOF_VOID_P);
 	mov_l_rR(f,f,offset);
-	/* Now f holds the address of the b/w/lput function */
 	call_r_02(f,address,source,4,size);
 	forget_about(tmp);
+#endif
 }
 #endif
 
 void writebyte(int address, int source, int tmp)
 {
 #ifdef UAE
-	if ((special_mem & S_WRITE) || distrust_byte())
+	if ((special_mem & S_WRITE) || distrust_byte() || jit_use_memory_helpers()) {
+		sync_compiled_exception_state();
 		writemem_special(address, source, 5 * SIZEOF_VOID_P, 1, tmp);
-	else
+	} else
 #endif
 		writemem_real(address,source,1,tmp,0);
 }
@@ -3338,9 +4079,10 @@ static inline void writeword_general(int address, int source, int tmp,
 	int clobber)
 {
 #ifdef UAE
-	if ((special_mem & S_WRITE) || distrust_word())
+	if ((special_mem & S_WRITE) || distrust_word() || jit_use_memory_helpers()) {
+		sync_compiled_exception_state();
 		writemem_special(address, source, 4 * SIZEOF_VOID_P, 2, tmp);
-	else
+	} else
 #endif
 		writemem_real(address,source,2,tmp,clobber);
 }
@@ -3359,9 +4101,10 @@ static inline void writelong_general(int address, int source, int tmp,
 	int clobber)
 {
 #ifdef UAE
-	if ((special_mem & S_WRITE) || distrust_long())
+	if ((special_mem & S_WRITE) || distrust_long() || jit_use_memory_helpers()) {
+		sync_compiled_exception_state();
 		writemem_special(address, source, 3 * SIZEOF_VOID_P, 4, tmp);
-	else
+	} else
 #endif
 		writemem_real(address,source,4,tmp,clobber);
 }
@@ -3424,23 +4167,80 @@ static inline void readmem(int address, int dest, int offset, int size, int tmp)
 {
 	int f=tmp;
 
+#if X86_TARGET_64BIT
+	/* x86-64: Same approach as writemem - keep 64-bit pointers out of
+	   virtual registers.  Compute 32-bit bank index via allocator, then
+	   do 64-bit pointer chase with raw instructions after call setup. */
+
+	/* Step 1: Compute bank index (32-bit, safe in virtual register) */
+	mov_l_rr(f, address);
+	shrl_l_ri(f, 16);
+
+	/* Step 2: Call setup (adapted from call_r_11 internals) */
+	clobber_flags();
+	remove_all_offsets();
+	if (size == 4) {
+		if (dest != address && dest != f) {
+			forget_about(dest);
+		}
+	} else {
+		tomem_c(dest);
+	}
+
+	int hw_addr = readreg_specific(address, 4, REG_PAR1);
+	int hw_f = readreg(f, 4);
+
+	prepare_for_call_1();
+	unlock2(hw_addr);
+	unlock2(hw_f);
+	prepare_for_call_2();
+
+	/* Step 3: 64-bit pointer chase with raw instructions */
+	{
+		int scratch = (hw_f != R11_INDEX) ? R11_INDEX : R10_INDEX;
+		MOVQir((uintptr)mem_banks, scratch);
+		MOVQmr(0, scratch, hw_f, SIZEOF_VOID_P, hw_f);
+		/* hw_f now holds 64-bit addrbank pointer */
+		MOVQmr(offset, hw_f, X86_NOREG, 1, hw_f);
+		/* hw_f now holds 64-bit function pointer */
+	}
+
+	/* Step 4: Call */
+	raw_dec_sp(STACK_SHADOW_SPACE);
+	raw_call_r(hw_f);
+	raw_inc_sp(STACK_SHADOW_SPACE);
+
+	/* Step 5: Record result (same as call_r_11 epilogue) */
+	live.nat[REG_RESULT].holds[0] = dest;
+	live.nat[REG_RESULT].nholds = 1;
+	live.nat[REG_RESULT].touched = touchcnt++;
+
+	live.state[dest].realreg = REG_RESULT;
+	live.state[dest].realind = 0;
+	live.state[dest].val = 0;
+	live.state[dest].validsize = size;
+	live.state[dest].dirtysize = size;
+	set_status(dest, DIRTY);
+
+	forget_about(tmp);
+#else
 	mov_l_rr(f,address);
-	shrl_l_ri(f,16);   /* The index into the mem bank table */
-	mov_l_rm_indexed(f,uae_p32(mem_banks),f,SIZEOF_VOID_P); /* FIXME: is SIZEOF_VOID_P correct? */
-	/* Now f holds a pointer to the actual membank */
+	shrl_l_ri(f,16);
+	mov_l_rm_indexed(f,uae_p32(mem_banks),f,SIZEOF_VOID_P);
 	mov_l_rR(f,f,offset);
-	/* Now f holds the address of the b/w/lget function */
 	call_r_11(dest,f,address,size,4);
 	forget_about(tmp);
+#endif
 }
 #endif
 
 void readbyte(int address, int dest, int tmp)
 {
 #ifdef UAE
-	if ((special_mem & S_READ) || distrust_byte())
+	if ((special_mem & S_READ) || distrust_byte() || jit_use_memory_helpers()) {
+		sync_compiled_exception_state();
 		readmem_special(address, dest, 2 * SIZEOF_VOID_P, 1, tmp);
-	else
+	} else
 #endif
 		readmem_real(address,dest,1,tmp);
 }
@@ -3448,9 +4248,10 @@ void readbyte(int address, int dest, int tmp)
 void readword(int address, int dest, int tmp)
 {
 #ifdef UAE
-	if ((special_mem & S_READ) || distrust_word())
+	if ((special_mem & S_READ) || distrust_word() || jit_use_memory_helpers()) {
+		sync_compiled_exception_state();
 		readmem_special(address, dest, 1 * SIZEOF_VOID_P, 2, tmp);
-	else
+	} else
 #endif
 		readmem_real(address,dest,2,tmp);
 }
@@ -3458,9 +4259,10 @@ void readword(int address, int dest, int tmp)
 void readlong(int address, int dest, int tmp)
 {
 #ifdef UAE
-	if ((special_mem & S_READ) || distrust_long())
+	if ((special_mem & S_READ) || distrust_long() || jit_use_memory_helpers()) {
+		sync_compiled_exception_state();
 		readmem_special(address, dest, 0 * SIZEOF_VOID_P, 4, tmp);
-	else
+	} else
 #endif
 		readmem_real(address,dest,4,tmp);
 }
@@ -3468,11 +4270,27 @@ void readlong(int address, int dest, int tmp)
 void get_n_addr(int address, int dest, int tmp)
 {
 #ifdef UAE
-	if (special_mem || distrust_addr()) {
+	if (special_mem || distrust_addr() || jit_use_memory_helpers()) {
 		/* This one might appear a bit odd... */
-		readmem(address, dest, 6 * SIZEOF_VOID_P, 4, tmp);
+		sync_compiled_exception_state();
+		readmem_special(address, dest, 6 * SIZEOF_VOID_P, 4, tmp);
+		return;
+	}
+#endif
+
+#if X86_TARGET_64BIT
+#ifdef NATMEM_OFFSET
+	if (canbang) {
+		int hw_address = readreg(address, 4);
+		int hw_dest = writereg(dest, 4);
+		compemu_raw_mov_l_rr(hw_dest, hw_address);
+		LEAQmr(0, R_MEMSTART, hw_dest, 1, hw_dest);
+		unlock2(hw_dest);
+		unlock2(hw_address);
+		forget_about(tmp);
 		return;
 	}
+#endif
 #endif
 
 	// a is the register containing the virtual address
@@ -3519,6 +4337,26 @@ void get_n_addr_jmp(int address, int dest, int tmp)
 	 would --- otherwise we end up translating everything twice */
 	get_n_addr(address,dest,tmp);
 #else
+#ifdef UAE
+	if (special_mem || distrust_addr() || jit_use_memory_helpers()) {
+		get_n_addr(address,dest,tmp);
+		return;
+	}
+#endif
+#if X86_TARGET_64BIT
+	if (canbang && dest == PC_P) {
+		clobber_flags();
+		int hw_address = readreg(address, 4);
+		int hw_dest = writereg(dest, 4);
+		compemu_raw_mov_l_rr(hw_dest, hw_address);
+		LEAQmr(0, R_MEMSTART, hw_dest, 1, hw_dest);
+		ANDQir((IMM)~1, hw_dest);
+		unlock2(hw_dest);
+		unlock2(hw_address);
+		forget_about(tmp);
+		return;
+	}
+#endif
 	int f=tmp;
 	if (address!=dest)
 		f=dest;
@@ -3526,6 +4364,13 @@ void get_n_addr_jmp(int address, int dest, int tmp)
 	shrl_l_ri(f,16);   /* The index into the baseaddr bank table */
 	mov_l_rm_indexed(dest,uae_p32(baseaddr),f,SIZEOF_VOID_P); /* FIXME: is SIZEOF_VOID_P correct? */
 	add_l(dest,address);
+#if X86_TARGET_64BIT
+	if (dest == PC_P) {
+		int hw_dest = rmw(dest, 4, 4);
+		ANDQir((IMM)~1, hw_dest);
+		unlock2(hw_dest);
+	} else
+#endif
 	and_l_ri (dest, ~1);
 	forget_about(tmp);
 #endif
@@ -3590,8 +4435,8 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
 	}
 	else { /* 68000 version */
 		if ((dp & 0x800) == 0) { /* Sign extend */
-			sign_extend_16_rr(target,reg);
-			lea_l_brr_indexed(target,base,target,1<<regd_shift,(uae_s32)((uae_s8)dp));
+			sign_extend_16_rr(tmp,reg);
+			lea_l_brr_indexed(target,base,tmp,1<<regd_shift,(uae_s32)((uae_s8)dp));
 		}
 		else {
 			lea_l_brr_indexed(target,base,reg,1<<regd_shift,(uae_s32)((uae_s8)dp));
@@ -3626,15 +4471,28 @@ uae_u32 get_jitted_size(void)
 static uint8 *do_alloc_code(uint32 size, int depth)
 {
 	UNUSED(depth);
-	uint8 *code = (uint8 *)vm_acquire(size, VM_MAP_DEFAULT | VM_MAP_32BIT);
+#if X86_TARGET_64BIT
+#if defined(__FreeBSD__)
+	/* FreeBSD ASLR places mmap at high addresses; force JIT cache below
+	 * 2GB so ADDR32 (0x67-prefix) absolute addressing works correctly. */
+	uint8 *code = (uint8 *)jit_vm_acquire(size, VM_MAP_DEFAULT | VM_MAP_32BIT);
+#else
+	/* Linux/macOS/Windows: RIP-relative anchor placement handles this */
+	uint8 *code = (uint8 *)jit_vm_acquire(size, VM_MAP_DEFAULT);
+#endif
+#else
+	uint8 *code = (uint8 *)jit_vm_acquire(size, VM_MAP_DEFAULT | VM_MAP_32BIT);
+#endif
 	return code == VM_MAP_FAILED ? NULL : code;
 }
 
 static inline uint8 *alloc_code(uint32 size)
 {
 	uint8 *ptr = do_alloc_code(size, 0);
+#if !X86_TARGET_64BIT
 	/* allocated code must fit in 32-bit boundaries */
 	assert((uintptr)ptr <= 0xffffffff);
+#endif
 	return ptr;
 }
 
@@ -3644,6 +4502,9 @@ void alloc_cache(void)
 		flush_icache_hard(3);
 		vm_release(compiled_code, cache_size * 1024);
 		compiled_code = 0;
+#if defined(CPU_x86_64)
+		vm_acquire_anchor = NULL;
+#endif
 	}
 
 #ifdef UAE
@@ -3658,10 +4519,54 @@ void alloc_cache(void)
 			cache_size /= 2;
 		}
 	}
-	vm_protect(compiled_code, cache_size * 1024, VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE);
+	if (!compiled_code)
+		return;
+	if (!vm_protect(compiled_code, cache_size * 1024,
+		VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE)) {
+#if defined(__APPLE__)
+		disable_jit_on_runtime_alloc_failure(
+			"Could not make the x86 JIT cache executable. "
+			"Signed macOS Intel builds need the "
+			"com.apple.security.cs.allow-unsigned-executable-memory entitlement.");
+#else
+		disable_jit_on_runtime_alloc_failure(
+			"Could not make the x86 JIT cache executable.");
+#endif
+		vm_release(compiled_code, cache_size * 1024);
+		compiled_code = 0;
+#if defined(CPU_x86_64)
+		vm_acquire_anchor = NULL;
+#endif
+		cache_size = 0;
+		return;
+	}
 	
 	if (compiled_code) {
 		jit_log("<JIT compiler> : actual translation cache size : %d KB at %p-%p", cache_size, compiled_code, compiled_code + cache_size*1024);
+#if defined(CPU_x86_64)
+		/* Anchor subsequent jit_vm_acquire() calls at the JIT cache so
+		 * blockinfo pools stay within RIP-relative range of code. */
+		vm_acquire_anchor = compiled_code;
+
+		/* Verify JIT cache is within RIP-relative reach of globals */
+		{
+			intptr_t dist = (intptr_t)compiled_code - (intptr_t)&regs;
+			jit_log("code cache at %p, regs at %p, distance=%+lld bytes",
+				compiled_code, (void *)&regs, (long long)dist);
+			if (llabs(dist) > (intptr_t)0x7F000000) {
+				jit_log("WARNING: code cache is %+lld bytes from globals -- "
+					"RIP-relative addressing may fail! Disabling JIT.",
+					(long long)dist);
+				vm_release(compiled_code, cache_size * 1024);
+				compiled_code = 0;
+				vm_acquire_anchor = NULL;
+				changed_prefs.cachesize = 0;
+				currprefs.cachesize = 0;
+				cache_size = 0;
+				return;
+			}
+		}
+#endif
 #ifdef USE_DATA_BUFFER
 		max_compile_start = compiled_code + cache_size*1024 - BYTES_PER_INST - DATA_BUFFER_SIZE;
 #else
@@ -3960,6 +4865,13 @@ static inline void create_popalls(void)
 	pushall_call_handler=get_target();
 	raw_push_regs_to_preserve();
 	raw_dec_sp(stack_space);
+#if X86_TARGET_64BIT
+	/* Load R_MEMSTART (R15) with natmem_offset - used as base register
+	   for all JIT memory accesses: [R_MEMSTART + m68k_addr].
+	   Loaded from the global variable (not immediate) so it stays correct
+	   if natmem_offset changes across resets. */
+	raw_mov_q_rm(R_MEMSTART, (uintptr)&natmem_offset);
+#endif
 	r=REG_PC_TMP;
 	compemu_raw_mov_l_rm(r, uae_p32(&regs.pc_p));
 	compemu_raw_and_l_ri(r,TAGMASK);
@@ -4037,14 +4949,24 @@ static void prepare_block(blockinfo* bi)
 	set_target(current_compile_p);
 	align_target(align_jumps);
 	bi->direct_pen=(cpuop_func*)get_target();
+#if X86_TARGET_64BIT
+	raw_mov_q_rm(0, (uintptr)&(bi->pc_p));
+	raw_mov_q_mr((uintptr)&regs.pc_p, 0);
+#else
 	compemu_raw_mov_l_rm(0, JITPTR &(bi->pc_p));
 	compemu_raw_mov_l_mr(JITPTR &regs.pc_p,0);
+#endif
 	compemu_raw_jmp(JITPTR popall_execute_normal);
 
 	align_target(align_jumps);
 	bi->direct_pcc=(cpuop_func*)get_target();
+#if X86_TARGET_64BIT
+	raw_mov_q_rm(0, (uintptr)&(bi->pc_p));
+	raw_mov_q_mr((uintptr)&regs.pc_p, 0);
+#else
 	compemu_raw_mov_l_rm(0, JITPTR &(bi->pc_p));
 	compemu_raw_mov_l_mr(JITPTR &regs.pc_p,0);
+#endif
 	compemu_raw_jmp(JITPTR popall_check_checksum);
 	flush_cpu_icache((void *)current_compile_p, (void *)target);
 	current_compile_p=get_target();
@@ -4162,7 +5084,7 @@ static bool read_fpu_opcode(const char *p, size_t len)
 	
 	for (i = 0; i < (sizeof(jit_opcodes) / sizeof(jit_opcodes[0])); i++)
 	{
-		if (len == strlen(jit_opcodes[i].name) && strnicmp(jit_opcodes[i].name, p, len) == 0)
+		if (len == strlen(jit_opcodes[i].name) && _strnicmp(jit_opcodes[i].name, p, len) == 0)
 		{
 			*jit_opcodes[i].disabled = true;
 			jit_log("<JIT compiler> : disabled %s", jit_opcodes[i].name);
@@ -4340,6 +5262,7 @@ void build_comp(void)
 			compfunctbl[cft_map(tbl[i].opcode)] = tbl[i].handler;
 	}
 
+	int jit_unavail_count = 0;
 	for (i = 0; nftbl[i].opcode < 65536; i++) {
 		bool uses_fpu = (tbl[i].specific & COMP_OPCODE_USES_FPU) != 0;
 		if (uses_fpu && avoid_fpu)
@@ -4359,15 +5282,12 @@ void build_comp(void)
 			}
 		}
 		if (!nfctbl[j].handler_ff && currprefs.cachesize) {
-			int mnemo = table68k[nftbl[i].opcode].mnemo;
-			struct mnemolookup *lookup;
-			for (lookup = lookuptab; lookup->mnemo != mnemo; lookup++)
-				;
-			char *s = ua(lookup->name);
-			jit_log("%04x (%s) unavailable", nftbl[i].opcode, s);
-			xfree(s);
+			jit_unavail_count++;
 		}
 	}
+	if (jit_unavail_count > 0) {
+		jit_log("%d opcodes unavailable for JIT compilation", jit_unavail_count);
+	}
 
 #ifdef NOFLAGS_SUPPORT_GENCOMP
 #ifdef NOFLAGS_SUPPORT_GENCPU
@@ -4765,9 +5685,16 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 		if (current_compile_p >= MAX_COMPILE_PTR)
 			flush_icache_hard(3);
 
-		alloc_blockinfos();
+		if (!alloc_blockinfos()) {
+			flush_icache_hard(3);
+			return;
+		}
 
 		bi=get_blockinfo_addr_new(pc_hist[0].location,0);
+		if (!bi) {
+			flush_icache_hard(3);
+			return;
+		}
 		bi2=get_blockinfo(cl);
 
 		optlev=bi->optlevel;
@@ -4800,15 +5727,28 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 
 		liveflags[blocklen]=FLAG_ALL; /* All flags needed afterwards */
+		const bool unsafe_memory_helpers = jit_use_memory_helpers();
+		const bool unsafe_compile_fallbacks = jit_use_compile_fallbacks();
+		const bool high_natmem_rom_block =
+			jit_n_addr_unsafe && !jit_n_addr_bank_unsafe &&
+			isinrom((uintptr)pc_hist[0].location) != 0;
+		bool unsafe_special_mem_block = high_natmem_rom_block;
 		i=blocklen;
 		while (i--) {
 			uae_u16* currpcp=pc_hist[i].location;
 			uae_u32 op=DO_GET_OPCODE(currpcp);
+			if ((unsafe_compile_fallbacks || unsafe_memory_helpers) && pc_hist[i].specmem)
+				unsafe_special_mem_block = true;
 
 #if USE_CHECKSUM_INFO
 			trace_in_rom = trace_in_rom && isinrom((uintptr)currpcp);
 			if (follow_const_jumps && is_const_jump(op)) {
 				checksum_info *csi = alloc_checksum_info();
+				if (!csi) {
+					invalidate_block(bi);
+					flush_icache_hard(3);
+					return;
+				}
 				csi->start_p = (uae_u8 *)min_pcp;
 				csi->length = JITPTR max_pcp - JITPTR min_pcp + LONGEST_68K_INST;
 				csi->next = bi->csi;
@@ -4838,6 +5778,11 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 
 #if USE_CHECKSUM_INFO
 		checksum_info *csi = alloc_checksum_info();
+		if (!csi) {
+			invalidate_block(bi);
+			flush_icache_hard(3);
+			return;
+		}
 		csi->start_p = (uae_u8 *)min_pcp;
 		csi->length = JITPTR max_pcp - JITPTR min_pcp + LONGEST_68K_INST;
 		csi->next = bi->csi;
@@ -4857,13 +5802,21 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 		log_startblock();
 
 		if (bi->count>=0) { /* Need to generate countdown code */
+#if X86_TARGET_64BIT
+			raw_mov_q_mi((uintptr)&regs.pc_p, (uintptr)pc_hist[0].location);
+#else
 			compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR pc_hist[0].location);
+#endif
 			compemu_raw_sub_l_mi(JITPTR &(bi->count),1);
 			compemu_raw_jl(JITPTR popall_recompile_block);
 		}
-		if (optlev==0) { /* No need to actually translate */
+		if (optlev==0 || unsafe_special_mem_block) { /* No need to actually translate */
 			/* Execute normally without keeping stats */
+#if X86_TARGET_64BIT
+			raw_mov_q_mi((uintptr)&regs.pc_p, (uintptr)pc_hist[0].location);
+#else
 			compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR pc_hist[0].location);
+#endif
 			compemu_raw_jmp(JITPTR popall_exec_nostats);
 		}
 		else {
@@ -4889,8 +5842,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 
 #ifdef JIT_DEBUG
 			if (JITDebug) {
+#if X86_TARGET_64BIT
+				raw_mov_q_mi((uintptr)&last_regs_pc_p,(uintptr)pc_hist[0].location);
+				raw_mov_q_mi((uintptr)&last_compiled_block_addr,current_block_start_target);
+#else
 				compemu_raw_mov_l_mi((uintptr)&last_regs_pc_p,(uintptr)pc_hist[0].location);
 				compemu_raw_mov_l_mi((uintptr)&last_compiled_block_addr,current_block_start_target);
+#endif
 			}
 #endif
 
@@ -4899,9 +5857,17 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 				compop_func **comptbl;
 				uae_u32 opcode=DO_GET_OPCODE(pc_hist[i].location);
 				needed_flags=(liveflags[i+1] & prop[opcode].set_flags);
+				const bool unsafe_dbcc = unsafe_compile_fallbacks && is_dbcc_opcode(opcode);
+				const bool unsafe_cmp_w_an_postinc_dn =
+					unsafe_compile_fallbacks && is_cmp_w_an_postinc_dn_opcode(opcode);
+				const bool unsafe_control_flow = unsafe_compile_fallbacks && prop[opcode].cflow != fl_normal && !unsafe_dbcc;
+				const bool unsafe_flags = unsafe_compile_fallbacks && prop[opcode].set_flags &&
+					!unsafe_cmp_w_an_postinc_dn;
+				if (unsafe_compile_fallbacks)
+					needed_flags=prop[opcode].set_flags;
 #ifdef UAE
 				special_mem=pc_hist[i].specmem;
-				if (!needed_flags && currprefs.compnf)
+				if (!unsafe_compile_fallbacks && !needed_flags && currprefs.compnf)
 #else
 				if (!needed_flags)
 #endif
@@ -4934,7 +5900,8 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 
 				failure = 1; // gb-- defaults to failure state
-				if (comptbl[opcode] && optlev>1) {
+				prepare_compiled_exception_state((uintptr)pc_hist[i].location, opcode);
+				if (comptbl[opcode] && optlev>1 && !unsafe_control_flow && !unsafe_flags) {
 					failure=0;
 					if (!was_comp) {
 						comp_pc_p=(uae_u8*)pc_hist[i].location;
@@ -4961,7 +5928,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 
 					comptbl[opcode](opcode);
 					freescratch();
-					if (!(liveflags[i+1] & FLAG_CZNV)) {
+					if (!unsafe_compile_fallbacks && !(liveflags[i+1] & FLAG_CZNV)) {
 						/* We can forget about flags */
 						dont_care_flags();
 					}
@@ -5031,7 +5998,19 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #if USE_NORMAL_CALLING_CONVENTION
 					raw_push_l_r(REG_PAR1);
 #endif
-					compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR pc_hist[i].location);
+					{
+						uintptr native_pc = (uintptr)pc_hist[i].location;
+						uae_u32 m68k_pc = get_virtual_compile_pc(native_pc);
+#if X86_TARGET_64BIT
+						raw_mov_q_mi((uintptr)&regs.pc_p, native_pc);
+						raw_mov_q_mi((uintptr)&regs.pc_oldp, native_pc);
+#else
+						compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR native_pc);
+						compemu_raw_mov_l_mi(JITPTR &regs.pc_oldp, JITPTR native_pc);
+#endif
+						compemu_raw_mov_l_mi(JITPTR &regs.pc, m68k_pc);
+						compemu_raw_mov_l_mi(JITPTR &regs.instruction_pc, m68k_pc);
+					}
 					raw_dec_sp(STACK_SHADOW_SPACE);
 					compemu_raw_call(JITPTR cputbl[opcode]);
 					raw_inc_sp(STACK_SHADOW_SPACE);
@@ -5043,6 +6022,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 					raw_inc_sp(4);
 #endif
 
+					if (unsafe_compile_fallbacks && unsafe_control_flow) {
+#ifdef UAE
+						raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles));
+#endif
+						compemu_raw_jmp(JITPTR popall_do_nothing);
+					}
+
 					if (i < blocklen - 1) {
 						uae_u8* branchadd;
 
@@ -5063,8 +6049,10 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 					}
 				}
 			}
-#if 1 /* This isn't completely kosher yet; It really needs to be
-		 be integrated into a general inter-block-dependency scheme */
+#if 0 /* Disabled: inter-block flag optimization uses single-instruction
+		 lookahead which is insufficient. Can discard flags that later
+		 instructions in the next block depend on, causing visual corruption.
+		 Same issue as ARM64 fix (compemu_support_arm.cpp:3528). */
 			if (next_pc_p && taken_pc_p &&
 				was_comp && taken_pc_p==current_block_pc_p)
 			{
@@ -5130,7 +6118,11 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 				tba=(uae_u32*)get_target();
 				emit_jmp_target(JITPTR get_handler(t1));
+	#if X86_TARGET_64BIT
+				raw_mov_q_mi((uintptr)&regs.pc_p, t1);
+#else
 				compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR t1);
+#endif
 				flush_reg_count();
 				compemu_raw_jmp(JITPTR popall_do_nothing);
 				create_jmpdep(bi,0,tba, JITPTR t1);
@@ -5152,7 +6144,11 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 				tba=(uae_u32*)get_target();
 				emit_jmp_target(JITPTR get_handler(t2));
+	#if X86_TARGET_64BIT
+				raw_mov_q_mi((uintptr)&regs.pc_p, t2);
+#else
 				compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR t2);
+#endif
 				flush_reg_count();
 				compemu_raw_jmp(JITPTR popall_do_nothing);
 				create_jmpdep(bi,1,tba, JITPTR t2);
@@ -5167,15 +6163,28 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 				/* Let's find out where next_handler is... */
 				if (was_comp && isinreg(PC_P)) {
 					r=live.state[PC_P].realreg;
-					compemu_raw_and_l_ri(r,TAGMASK);
-					int r2 = (r==0) ? 1 : 0;
+#if X86_TARGET_64BIT
+					int rtag = (r != R10_INDEX) ? R10_INDEX : R11_INDEX;
+					int r2 = (r != R11_INDEX && rtag != R11_INDEX) ? R11_INDEX : EAX_INDEX;
+#else
+					int rtag = (r != EAX_INDEX) ? EAX_INDEX : ECX_INDEX;
+					int r2 = (r != ECX_INDEX && rtag != ECX_INDEX) ? ECX_INDEX : EDX_INDEX;
+#endif
+					free_nreg(rtag);
+					free_nreg(r2);
+					compemu_raw_mov_l_rr(rtag,r);
+					compemu_raw_and_l_ri(rtag,TAGMASK);
+#if X86_TARGET_64BIT
+					raw_mov_q_ri(r2, JITPTR popall_do_nothing);
+#else
 					compemu_raw_mov_l_ri(r2, JITPTR popall_do_nothing);
+#endif
 #ifdef UAE
 					raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles));
-					raw_cmov_l_rm_indexed(r2, JITPTR cache_tags,r,sizeof(void *),NATIVE_CC_PL);
+					raw_cmov_l_rm_indexed(r2, JITPTR cache_tags,rtag,sizeof(void *),NATIVE_CC_PL);
 #else
 					compemu_raw_cmp_l_mi8((uintptr)specflags,0);
-					compemu_raw_cmov_l_rm_indexed(r2,(uintptr)cache_tags,r,sizeof(void *),NATIVE_CC_EQ);
+					compemu_raw_cmov_l_rm_indexed(r2,(uintptr)cache_tags,rtag,sizeof(void *),NATIVE_CC_EQ);
 #endif
 					compemu_raw_jmp_r(r2);
 				}
@@ -5196,7 +6205,11 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 					tba=(uae_u32*)get_target();
 					emit_jmp_target(JITPTR get_handler(v));
+	#if X86_TARGET_64BIT
+					raw_mov_q_mi((uintptr)&regs.pc_p, v);
+#else
 					compemu_raw_mov_l_mi(JITPTR &regs.pc_p, JITPTR v);
+#endif
 					compemu_raw_jmp(JITPTR popall_do_nothing);
 					create_jmpdep(bi,0,tba, JITPTR v);
 				}
@@ -5205,7 +6218,11 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 					compemu_raw_mov_l_rm(r,JITPTR &regs.pc_p);
 					compemu_raw_and_l_ri(r,TAGMASK);
 					int r2 = (r==0) ? 1 : 0;
+#if X86_TARGET_64BIT
+					raw_mov_q_ri(r2, JITPTR popall_do_nothing);
+#else
 					compemu_raw_mov_l_ri(r2, JITPTR popall_do_nothing);
+#endif
 #ifdef UAE
 					raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles));
 					raw_cmov_l_rm_indexed(r2, JITPTR cache_tags,r,sizeof(void *),NATIVE_CC_PL);
@@ -5292,7 +6309,17 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 		/* This is the non-direct handler */
 		bi->handler=
 			bi->handler_to_use=(cpuop_func *)get_target();
+#if X86_TARGET_64BIT
+		/* regs.pc_p is a 64-bit pointer - must compare all 8 bytes.
+		   x86-64 has no CMP [mem], imm64, so load into scratch and CMP. */
+		{
+			int r_tmp = REG_PC_TMP;
+			raw_mov_q_ri(r_tmp, (uintptr)pc_hist[0].location);
+			raw_cmp_q_mr((uintptr)&regs.pc_p, r_tmp);
+		}
+#else
 		compemu_raw_cmp_l_mi(JITPTR &regs.pc_p, JITPTR pc_hist[0].location);
+#endif
 		compemu_raw_jnz(JITPTR popall_cache_miss);
 		comp_pc_p=(uae_u8*)pc_hist[0].location;
 
@@ -5450,3 +6477,5 @@ setjmpagain:
 #endif
 
 #endif /* JIT */
+
+#endif /* CPU_AARCH64 */
diff --git a/jit/compstbl.cpp b/jit/compstbl.cpp
index 05af8957..e272ed8b 100644
--- a/jit/compstbl.cpp
+++ b/jit/compstbl.cpp
@@ -1,3 +1,6 @@
+#if defined(CPU_AARCH64)
+#include "arm/compstbl_arm.cpp"
+#else
 #include "sysconfig.h"
 #if defined(JIT)
 #include "sysdeps.h"
@@ -3756,3 +3759,4 @@ const struct comptbl op_smalltbl_0_comp_nf[] = {
 { NULL, 63488, COMP_OPCODE_ISJUMP }, /* LPSTOP */
 { 0, 65536, 0 }};
 #endif
+#endif /* CPU_AARCH64 */
diff --git a/jit/comptbl.h b/jit/comptbl.h
index c1adbfc8..77fc1bc8 100644
--- a/jit/comptbl.h
+++ b/jit/comptbl.h
@@ -1,3 +1,6 @@
+#if defined(CPU_AARCH64)
+#include "arm/comptbl_arm.h"
+#else
 extern const struct comptbl op_smalltbl_0_comp_nf[];
 extern const struct comptbl op_smalltbl_0_comp_ff[];
 extern compop_func op_0_0_comp_ff;
@@ -2801,3 +2804,4 @@ extern compop_func op_f608_0_comp_nf;
 extern compop_func op_f610_0_comp_nf;
 extern compop_func op_f618_0_comp_nf;
 extern compop_func op_f620_0_comp_nf;
+#endif /* CPU_AARCH64 */
diff --git a/memory.cpp b/memory.cpp
index c26b7b97..ca37c6dd 100644
--- a/memory.cpp
+++ b/memory.cpp
@@ -54,6 +54,7 @@ static bool rom_write_enabled;
 int special_mem, special_mem_default;
 /* do not use get_n_addr */
 int jit_n_addr_unsafe;
+int jit_n_addr_bank_unsafe;
 #endif
 static int mem_hardreset;
 static bool roms_modified;
@@ -3100,7 +3101,17 @@ void memory_reset (void)
 	need_hardreset = false;
 	rom_write_enabled = true;
 #ifdef JIT
+	/* Start in direct n_addr mode; map_banks() will mark real
+	 * S_N_ADDR banks separately. High x86-64 natmem only needs
+	 * pointer-clean codegen, not helper fallback. */
 	jit_n_addr_unsafe = 0;
+	jit_n_addr_bank_unsafe = 0;
+#if defined(CPU_x86_64) && defined(NATMEM_OFFSET)
+	if ((uintptr_t)natmem_offset + natmem_reserved_size > (uintptr_t)0x100000000ULL) {
+		write_log(_T("JIT: jit_n_addr_unsafe enabled for high x86-64 natmem at %p\n"), natmem_offset);
+		jit_n_addr_unsafe = 1;
+	}
+#endif
 #endif
 	/* Use changed_prefs, as m68k_reset is called later.  */
 	if (last_address_space_24 != changed_prefs.address_space_24)
@@ -3733,7 +3744,12 @@ void map_banks (addrbank *bank, int start, int size, int realsize)
 
 #ifdef JIT
 	if ((bank->jit_read_flag | bank->jit_write_flag) & S_N_ADDR) {
+		if (!jit_n_addr_bank_unsafe) {
+			write_log(_T("JIT: jit_n_addr_unsafe enabled by bank '%s' at %08x (r=%d w=%d)\n"),
+				bank->name ? bank->name : _T("<unnamed>"), start << 16, bank->jit_read_flag, bank->jit_write_flag);
+		}
 		jit_n_addr_unsafe = 1;
+		jit_n_addr_bank_unsafe = 1;
 	}
 #endif
 
diff --git a/newcpu.cpp b/newcpu.cpp
index ebd2d800..98d46922 100644
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -5535,6 +5535,14 @@ void execute_normal(void)
 		/* Take note: This is the do-it-normal loop */
 		r->opcode = get_jit_opcode();
 
+#if defined(JIT) && defined(CPU_x86_64)
+		/* High x86-64 natmem uses jit_n_addr_unsafe for pointer-clean
+		 * codegen decisions. Keep pc_hist.specmem reserved for real
+		 * special-bank flags. */
+		if (jit_n_addr_unsafe && !jit_n_addr_bank_unsafe) {
+			special_mem = 0;
+		} else
+#endif
 		special_mem = special_mem_default;
 		pc_hist[blocklen].location = (uae_u16*)r->pc_p;
 
diff --git a/od-win32/sysconfig.h b/od-win32/sysconfig.h
index edb7b6c2..7f2ecacf 100644
--- a/od-win32/sysconfig.h
+++ b/od-win32/sysconfig.h
@@ -29,10 +29,8 @@
 
 #ifndef UAE_MINI
 
-#if !defined(_M_ARM64) && !defined(_M_ARM64EC)
 #define JIT /* JIT compiler support */
 #define USE_JIT_FPU
-#endif
 
 #define DEBUGGER
 //#define GDBSERVER