From: Toni Wilen <twilen@winuae.net>
Date: Mon, 13 Jul 2020 18:00:59 +0000 (+0300)
Subject: CPU tester undefined CCR option.
X-Git-Tag: 4900~348
X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=91bec2f69d7df319cce5295ac0eb2dce3d9c539d;p=francis%2Fwinuae.git

CPU tester undefined CCR option.
---

diff --git a/cputest.cpp b/cputest.cpp
index 072b506b..7a8b32a9 100644
--- a/cputest.cpp
+++ b/cputest.cpp
@@ -55,6 +55,7 @@ static int verbose = 1;
 static int feature_exception3_data = 0;
 static int feature_exception3_instruction = 0;
 static int feature_sr_mask = 0;
+static int feature_undefined_ccr = 0;
 static int feature_min_interrupt_mask = 0;
 static int feature_loop_mode = 0;
 static int feature_loop_mode_register = -1;
@@ -4132,10 +4133,25 @@ static uae_u8 *save_exception(uae_u8 *p, struct instr *dp)
 static uae_u16 get_ccr_ignore(struct instr *dp, uae_u16 extra)
 {
 	uae_u16 ccrignoremask = 0;
-	if ((cpu_lvl == 2 || cpu_lvl == 3) && (test_exception == 5 || exception_extra_frame_type == 5)) {
-		if ((dp->mnemo == i_DIVS) || (dp->mnemo == i_DIVL && (extra & 0x0800) && !(extra & 0x0400))) {
-			// 68020/030 DIVS.W/.L + Divide by Zero: V state is not stable.
-			ccrignoremask |= 2; // mask CCR=V
+	if (!feature_undefined_ccr) {
+		if (test_exception == 5 || exception_extra_frame_type == 5) {
+			if (dp->mnemo == i_DIVS || dp->mnemo == i_DIVU || dp->mnemo == i_DIVL) {
+				// DIV + Divide by Zero: flags are undefined
+				ccrignoremask |= 0x08 | 0x04 | 0x02 | 0x01;
+			}
+		} else {
+			if ((dp->mnemo == i_DIVS || dp->mnemo == i_DIVU || dp->mnemo == i_DIVL) && (regs.sr & 0x02)) {
+				// DIV + V: other flags are undefined
+				ccrignoremask |= 0x08 | 0x04 | 0x01;
+			}
+		}
+		if (dp->mnemo == i_CHK2) {
+			// CHK: N and V are undefined
+			ccrignoremask |= 0x08 | 0x02;
+		}
+		if (dp->mnemo == i_CHK) {
+			// CHK: N and V are undefined
+			ccrignoremask |= 0x04 | 0x02 | 0x01;
 		}
 	}
 	return ccrignoremask;
@@ -6259,6 +6275,9 @@ static int test(struct ini_data *ini, const TCHAR *sections, const TCHAR *testna
 
 	feature_sr_mask = 0;
 	ini_getvalx(ini, sections, _T("feature_sr_mask"), &feature_sr_mask);
+	feature_undefined_ccr = 0;
+	ini_getvalx(ini, sections, _T("feature_undefined_ccr"), &feature_undefined_ccr);
+
 	feature_min_interrupt_mask = 0;
 	ini_getvalx(ini, sections, _T("feature_min_interrupt_mask"), &feature_min_interrupt_mask);
 
diff --git a/cputest/cputestgen.ini b/cputest/cputestgen.ini
index 7429d9c6..dbf9b608 100644
--- a/cputest/cputestgen.ini
+++ b/cputest/cputestgen.ini
@@ -142,6 +142,10 @@ feature_interrupts=0
 ; Note: instructions that generate privilege violation exception will automatically add extra S=1 round.
 feature_sr_mask=0x0000
 
+; Do not check undefined flags
+; Currently supported: CHK, CHK2, DIV
+feature_undefined_ccr=0
+
 ; Forced register, always use this value in all tests
 ; D0-D7, A0-A6, FP0-FP7, SR, CCR, FPSR, FPCR, FPIAR
 ; reg=0x1234 or reg=100
@@ -200,6 +204,7 @@ feature_sr_mask=0x8000
 cpu=68000-68010
 enabled=0
 feature_sr_mask=0x8000
+feature_undefined_ccr=1
 mode=all
 
 ; interrupt exception
@@ -208,6 +213,7 @@ enabled=0
 cpu=68000-68010
 feature_sr_mask=0x8000
 feature_interrupts=1
+feature_undefined_ccr=1
 mode=jsr,jmp,bsr,bcc,dbcc,nop,exg,swap,stop,mvsr2,mv2sr,andsr,eorsr,orsr
 min_opcode_test_rounds=100
 
@@ -217,6 +223,7 @@ enabled=0
 cpu=68000-68010
 feature_target_src_ea=0x37fff1,0x7111
 feature_target_dst_ea=
+feature_undefined_ccr=1
 mode=all
 
 ; destination EA address error (MOVE, MOVEM)
@@ -226,6 +233,7 @@ cpu=68000-68010
 feature_target_src_ea=
 feature_target_dst_ea=0x37fff1,0x7111
 verbose=0
+feature_undefined_ccr=1
 mode=move,movea,mvmel,mvmle
 
 ; user stack address error
@@ -234,6 +242,7 @@ enabled=0
 cpu=68000-68010
 feature_usp=2
 verbose=0
+feature_undefined_ccr=1
 mode=rts,rtd,rtr,jsr,bsr,link,unlk,pea
 
 ; exception vector address error
@@ -242,6 +251,7 @@ enabled=0
 cpu=68000-68010
 feature_exception_vectors=0x000123
 verbose=0
+feature_undefined_ccr=1
 mode=mv2sr.w,mvusp2r,mvr2usp,illegal,chk,trap,trapv,divu,divs,orsr.w
 
 ; interrupt exception with odd interrupt vectors
@@ -250,6 +260,7 @@ enabled=0
 cpu=68000-68010
 mode=nop,ext,swap
 feature_interrupts=1
+feature_undefined_ccr=1
 feature_exception_vectors=0x000123
 
 ; prefetch bus error (requires extra hardware)
@@ -264,6 +275,7 @@ opcode_memory_start=0x87ffee
 test_memory_size=0xa0000
 test_memory_size=0x100000
 opcode_memory_start=0x87ffa0
+feature_undefined_ccr=1
 mode=all
 
 ; source EA read bus error (requires extra hardware)
@@ -278,6 +290,7 @@ feature_target_dst_ea=
 test_memory_start=0x860000
 test_memory_size=0x100000
 opcode_memory_start=0x87ffa0
+feature_undefined_ccr=1
 mode=all
 
 ; destination EA read bus error (requires extra hardware)
@@ -292,6 +305,7 @@ feature_target_dst_ea=0x87fffc,0x87fffd,0x87fffe,0x87ffff,0x880000,0x880001,0x88
 test_memory_start=0x860000
 test_memory_size=0x100000
 opcode_memory_start=0x87ffa0
+feature_undefined_ccr=1
 mode=all
 
 ; source EA (=RMW instructions like NOT have only source EA) write bus error (requires extra hardware)
@@ -307,7 +321,8 @@ opcode_memory_start=0x8fffa0
 test_memory_start=0x880000
 test_memory_size=0x100000
 mode=moves
-;mode=all
+feature_undefined_ccr=1
+mode=all
 
 ; destination EA write bus error (requires extra hardware)
 [test=BEDSTW]
@@ -321,6 +336,7 @@ feature_target_dst_ea=0x8ffffc,0x8ffffd,0x8ffffe,0x8fffff,0x900000,0x900001,0x90
 opcode_memory_start=0x8fffa0
 test_memory_start=0x880000
 test_memory_size=0x100000
+feature_undefined_ccr=1
 mode=all
 
 
@@ -332,6 +348,7 @@ feature_loop_mode_68010=1
 feature_loop_mode=3
 feature_loop_mode_register=7
 min_opcode_test_rounds=100
+feature_undefined_ccr=1
 mode=all
 
 ; **************
diff --git a/cputest/main.c b/cputest/main.c
index c832dc14..9d6b061e 100644
--- a/cputest/main.c
+++ b/cputest/main.c
@@ -1661,7 +1661,7 @@ static uae_u8 *validate_exception(struct registers *regs, uae_u8 *p, short excnu
 				p += 2;
 				v = opcode_memory_addr;
 				p = restore_rel_ordered(p, &v);
-				if (vsr != sr) {
+				if ((vsr & test_ccrignoremask) != (sr & test_ccrignoremask)) {
 					sprintf(outbp, "Trace (non-stacked) SR mismatch: %04x != %04x (PC=%08x)\n", sr, vsr, v);
 					outbp += strlen(outbp);
 					*experr = 1;
diff --git a/cputest/readme.txt b/cputest/readme.txt
index abcc34c8..87094a69 100644
--- a/cputest/readme.txt
+++ b/cputest/readme.txt
@@ -130,6 +130,10 @@ If mismatch is detected, opcode word(s), instruction disassembly, registers befo
 
 Change log:
 
+13.07.2020
+
+- Added undefined_ccr option. Ignores undefined flags, currently supports DIVx, CHK and CHK2 (Instructions that don't have simple undefined behavior)
+
 10.07.2020
 
 - 68020+ stack frame PC field was ignored.