From: Toni Wilen Date: Sun, 26 Jan 2020 18:43:55 +0000 (+0200) Subject: 68000 prefetch mode exception timing adjustments. X-Git-Tag: 4400~164 X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=a07cb881070f0693a90f5695571dc04c89070e6d;p=francis%2Fwinuae.git 68000 prefetch mode exception timing adjustments. --- diff --git a/cputest/main.c b/cputest/main.c index 3dba92a7..7636a17a 100644 --- a/cputest/main.c +++ b/cputest/main.c @@ -1681,7 +1681,7 @@ static int getexceptioncycles(int exc) { case 2: case 3: - return 58; + return 56; case 4: case 5: case 6: @@ -1709,7 +1709,7 @@ static int getexceptioncycles(int exc) { case 2: case 3: - return 126; + return 132; case 4: case 5: case 6: diff --git a/gencpu.cpp b/gencpu.cpp index 877c8fa9..b4465919 100644 --- a/gencpu.cpp +++ b/gencpu.cpp @@ -6494,10 +6494,14 @@ static void gen_opcode (unsigned int opcode) if (curi->smode >= Ad16 && cpu_level == 1 && using_prefetch) { dummy_prefetch("srca", NULL); } - if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16) - addcycles000(2); - if (curi->smode == Ad8r || curi->smode == PC8r) - addcycles000(6); + if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16) { + addcycles000_onlyce(2); + addcycles000_nonce("\t\t", 2); + } + if (curi->smode == Ad8r || curi->smode == PC8r) { + addcycles000_onlyce(6); + addcycles000_nonce("\t\t", 6); + } printf("\t\texception3i(opcode, srca);\n"); write_return_cycles("\t\t", 0); printf("\t}\n"); @@ -6573,7 +6577,8 @@ static void gen_opcode (unsigned int opcode) } branch_inst = 1; next_level_040_to_030(); - } + next_level_000(); + } break; case i_JMP: no_prefetch_ce020 = true; @@ -6584,10 +6589,14 @@ static void gen_opcode (unsigned int opcode) if (curi->smode >= Ad16 && cpu_level == 1 && using_prefetch) { dummy_prefetch("srca", NULL); } - if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16) - addcycles000(2); - if (curi->smode == Ad8r || curi->smode == PC8r) - addcycles000(6); + if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16) { + addcycles000_onlyce(2); + addcycles000_nonce("\t\t", 2); + } + if (curi->smode == Ad8r || curi->smode == PC8r) { + addcycles000_onlyce(6); + addcycles000_nonce("\t\t", 6); + } printf("\t\texception3i(opcode, srca);\n"); write_return_cycles("\t\t", 0); printf("\t}\n"); @@ -6617,6 +6626,7 @@ static void gen_opcode (unsigned int opcode) fill_prefetch_full(0); } branch_inst = 1; + next_level_000(); break; case i_BSR: // .b/.w = idle cycle, store high, store low, 2xprefetch @@ -6647,7 +6657,7 @@ static void gen_opcode (unsigned int opcode) printf("\t}\n"); } } - addcycles000 (2); + addcycles000(2); printf("\tuaecptr oldpc = %s;\n", getpc); printf("\tuaecptr nextpc = oldpc + %d;\n", m68k_pc_offset); if (using_exception_3 && cpu_level == 1) { @@ -6675,7 +6685,7 @@ static void gen_opcode (unsigned int opcode) } else if (using_ce020 == 2) { printf("\tm68k_do_bsr_ce030(nextpc, s);\n"); } else if (using_ce) { - printf("\tm68k_do_bsr_ce (nextpc, s);\n"); + printf("\tm68k_do_bsr_ce(nextpc, s);\n"); } else if (using_prefetch || (using_test && cpu_level <= 1)) { printf("\tm68k_areg(regs, 7) -= 4;\n"); printf("\tuaecptr dsta = m68k_areg(regs, 7);\n"); @@ -6689,6 +6699,7 @@ static void gen_opcode (unsigned int opcode) } else { printf("\tm68k_do_bsr (nextpc, s);\n"); } + count_write += 2; if (using_exception_3 && cpu_level == 0) { printf("\tif (%s & 1) {\n", getpc); printf("\t\texception3b(opcode, %s, false, true, %s);\n", getpc, getpc); @@ -6699,7 +6710,6 @@ static void gen_opcode (unsigned int opcode) printf("\tif (debugmem_trace)\n"); printf("\t\tbranch_stack_push(oldpc, nextpc);\n"); } - count_write += 2; clear_m68k_offset(); if (using_prefetch || using_ce) { fill_prefetch_full_000_special(); @@ -6707,6 +6717,7 @@ static void gen_opcode (unsigned int opcode) fill_prefetch_full(0); } branch_inst = 1; + next_level_000(); break; case i_Bcc: tail_ce020_done = true; diff --git a/newcpu.cpp b/newcpu.cpp index e8f0dbb1..7cf86796 100644 --- a/newcpu.cpp +++ b/newcpu.cpp @@ -2482,13 +2482,11 @@ static void Exception_ce000 (int nr) start = 6; interrupt = nr >= 24 && nr < 24 + 8; if (!interrupt) { - start = 8; + start = 4; if (nr == 7) // TRAPV start = 0; - else if (nr >= 32 && nr < 32 + 16) // TRAP #x - start = 4; - else if (nr == 4 || nr == 5 || nr == 6 || nr == 8 || nr == 9 || nr == 10 || nr == 11 || nr == 14) // ILLG, DIVBYZERO, PRIV, TRACE, LINEA, LINEF, RTE - start = 4; + else if (nr == 2 || nr == 3) + start = 8; } if (start) @@ -2797,15 +2795,15 @@ static void add_approximate_exception_cycles(int nr) if (currprefs.cpu_model == 68000) { if (nr >= 24 && nr <= 31) { /* Interrupts */ - cycles = 44 + 4; + cycles = 44; } else if (nr >= 32 && nr <= 47) { /* Trap (total is 34, but cpuemux.c already adds 4) */ cycles = 34 - 4; } else { switch (nr) { - case 2: cycles = 50; break; /* Bus error */ - case 3: cycles = 50; break; /* Address error */ + case 2: cycles = 56; break; /* Bus error */ + case 3: cycles = 56; break; /* Address error */ case 4: cycles = 34; break; /* Illegal instruction */ case 5: cycles = 34; break; /* Division by zero */ case 6: cycles = 34; break; /* CHK */ @@ -2822,15 +2820,15 @@ static void add_approximate_exception_cycles(int nr) } else if (currprefs.cpu_model == 68010) { if (nr >= 24 && nr <= 31) { /* Interrupts */ - cycles = 48 + 4; + cycles = 48; } else if (nr >= 32 && nr <= 47) { /* Trap */ cycles = 38 - 4; } else { switch (nr) { - case 2: cycles = 126; break; /* Bus error */ - case 3: cycles = 126; break; /* Address error */ + case 2: cycles = 132; break; /* Bus error */ + case 3: cycles = 132; break; /* Address error */ case 4: cycles = 38; break; /* Illegal instruction */ case 5: cycles = 38; break; /* Division by zero */ case 6: cycles = 38; break; /* CHK */