From: Toni Wilen <twilen@winuae.net>
Date: Fri, 30 Mar 2007 14:51:39 +0000 (+0300)
Subject: imported winuaesrc1420b2.zip
X-Git-Tag: 2100~234
X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=a6c1b8c07dd74e3fbfe47fbd7de24d1d6b61e9a7;p=francis%2Fwinuae.git

imported winuaesrc1420b2.zip
---

diff --git a/audio.c b/audio.c
index d9d0f98d..7b6615f2 100755
--- a/audio.c
+++ b/audio.c
@@ -1076,7 +1076,7 @@ static void audio_handler (int nr, int timed)
 		cdp->state = 1;
 		cdp->wlen = cdp->len;
 		/* there are too many stupid sound routines that fail on "too" fast cpus.. */
-		if (currprefs.cpu_level > 1)
+		if (currprefs.cpu_model >= 68020)
 		    cdp->pt = cdp->lc;
 #ifdef DEBUG_AUDIO
 		if (debugchannel (nr))
diff --git a/autoconf.c b/autoconf.c
index d8c809e8..69072c49 100755
--- a/autoconf.c
+++ b/autoconf.c
@@ -36,11 +36,12 @@ static void REGPARAM3 rtarea_lput (uaecptr, uae_u32) REGPARAM;
 static void REGPARAM3 rtarea_wput (uaecptr, uae_u32) REGPARAM;
 static void REGPARAM3 rtarea_bput (uaecptr, uae_u32) REGPARAM;
 static uae_u8 *REGPARAM3 rtarea_xlate (uaecptr) REGPARAM;
+static int REGPARAM3 rtarea_check (uaecptr addr, uae_u32 size) REGPARAM;
 
 addrbank rtarea_bank = {
     rtarea_lget, rtarea_wget, rtarea_bget,
     rtarea_lput, rtarea_wput, rtarea_bput,
-    rtarea_xlate, default_check, NULL, "UAE Boot ROM",
+    rtarea_xlate, rtarea_check, NULL, "UAE Boot ROM",
     rtarea_lget, rtarea_wget, ABFLAG_ROMIN
 };
 
@@ -50,6 +51,12 @@ static uae_u8 *REGPARAM2 rtarea_xlate (uaecptr addr)
     return rtarea + addr;
 }
 
+static int REGPARAM2 rtarea_check (uaecptr addr, uae_u32 size)
+{
+    addr &= 0xFFFF;
+    return (addr + size) <= 0xFFFF;
+}
+
 static uae_u32 REGPARAM2 rtarea_lget (uaecptr addr)
 {
 #ifdef JIT
diff --git a/blitter.c b/blitter.c
index d0468589..9235baf4 100755
--- a/blitter.c
+++ b/blitter.c
@@ -56,7 +56,7 @@ enum blitter_states bltstate;
 static int blit_cyclecounter, blit_maxcyclecounter, blit_slowdown;
 static int blit_linecyclecounter, blit_misscyclecounter;
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 extern uae_u8 cycle_line[];
 #endif
 
@@ -568,7 +568,7 @@ STATIC_INLINE void blitter_nxline(void)
     bltstate = BLT_read;
 }
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 
 static int blit_last_hpos;
 
@@ -673,7 +673,7 @@ void blitter_handler(uae_u32 data)
     blitter_done ();
 }
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 
 static uae_u32 preva, prevb;
 STATIC_INLINE uae_u16 blitter_doblit (void)
diff --git a/cdtv.c b/cdtv.c
index 21ee3dff..e06f5c2f 100755
--- a/cdtv.c
+++ b/cdtv.c
@@ -9,8 +9,8 @@
   *
   */
 
-//#define CDTV_DEBUG
-//#define CDTV_DEBUG_CMD
+#define CDTV_DEBUG
+#define CDTV_DEBUG_CMD
 //#define CDTV_DEBUG_6525
 
 #include "sysconfig.h"
@@ -50,7 +50,8 @@ static volatile int cdtv_command_len;
 static volatile uae_u8 cdtv_command_buf[6];
 static volatile uae_u8 dmac_istr, dmac_cntr;
 static volatile uae_u16 dmac_dawr;
-static volatile uae_u32 dmac_acr, dmac_wtc;
+static volatile uae_u32 dmac_acr;
+static volatile int dmac_wtc;
 static volatile int dmac_dma;
 
 static volatile int activate_stch, cdrom_command_done, play_state, play_statewait;
@@ -508,10 +509,8 @@ static void dma_do_thread(void)
     static int readsector;
     uae_u8 *p = NULL;
 
-#ifdef CDTV_DEBUG
-    write_log("DMAC DMA: sector=%d, cnt=%d, addr=%08.8X, %d\n",
-	cdrom_sector, cdrom_sectors, dmac_acr, dmac_wtc);
-#endif
+    write_log("DMAC DMA: sector=%d, addr=%08.8X, words=%d\n",
+	cdrom_offset / 2048, dmac_acr, dmac_wtc);
     dma_wait += dmac_wtc * 312 * 50 / 75 + 1;
     while (dmac_wtc > 0 && dmac_dma) {
 	if (!p || readsector != (cdrom_offset / 2048)) {
diff --git a/cfgfile.c b/cfgfile.c
index 4aea8486..c24ac77c 100755
--- a/cfgfile.c
+++ b/cfgfile.c
@@ -46,7 +46,8 @@ static const struct cfg_lines opttable[] =
     {"use_gui", "Enable the GUI?  If no, then goes straight to emulator" },
     {"use_debugger", "Enable the debugger?" },
     {"cpu_speed", "can be max, real, or a number between 1 and 20" },
-    {"cpu_type", "Can be 68000, 68010, 68020, 68020/68881" },
+    {"cpu_model", "Can be 68000, 68010, 68020, 68030, 68040, 68060" },
+    {"fpu_model", "Can be 68881, 68882, 68040, 68060" },
     {"cpu_compatible", "yes enables compatibility-mode" },
     {"cpu_24bit_addressing", "must be set to 'no' in order for Z3mem or P96mem to work" },
     {"autoconfig", "yes = add filesystems and extra ram" },
@@ -119,10 +120,6 @@ static const char *csmode[] = { "ocs", "ecs_agnus", "ecs_denise", "ecs", "aga",
 static const char *linemode1[] = { "none", "double", "scanlines", 0 };
 static const char *linemode2[] = { "n", "d", "s", 0 };
 static const char *speedmode[] = { "max", "real", 0 };
-static const char *cpumode[] = {
-    "68000", "68000", "68010", "68010", "68ec020", "68020", "68ec020/68881", "68020/68881",
-    "68040", "68040", "xxxxx", "xxxxx", "68060", "68060", 0
-};
 static const char *colormode1[] = { "8bit", "15bit", "16bit", "8bit_dither", "4bit_dither", "32bit", 0 };
 static const char *colormode2[] = { "8", "15", "16", "8d", "4d", "32", 0 };
 static const char *soundmode1[] = { "none", "interrupts", "normal", "exact", 0 };
@@ -151,7 +148,8 @@ static const char *cscompa[] = {
     "-", "Generic", "CDTV", "CD32", "A500", "A500+", "A600",
     "A1000", "A1200", "A2000", "A3000", "A3000T", "A4000", "A4000T", 0
 };
-static const char *fullmodes[] = { "false", "true", "fullwindow", 0 };
+/* 3-state boolean! */
+static const char *fullmodes[] = { "false", "true", /* "FILE_NOT_FOUND", */ "fullwindow", 0 };
 
 static const char *obsolete[] = {
     "accuracy", "gfx_opengl", "gfx_32bit_blits", "32bit_blits",
@@ -250,6 +248,24 @@ static void write_filesys_config (struct uae_prefs *p, const char *unexpanded,
     }
 }
 
+static void write_compatibility_cpu(struct zfile *f, struct uae_prefs *p)
+{
+    char tmp[100];
+    int model;
+
+    model = p->cpu_model;
+    if (model == 68030)
+	model = 68020;
+    if (model == 68060)
+	model = 68040;
+    if (p->address_space_24 && model == 68020)
+	strcpy (tmp, "68ec020");
+    else
+	sprintf(tmp, "%d", model);
+    if (model == 68020 && (p->fpu_model == 68881 || p->fpu_model == 68882)) 
+	strcat(tmp,"/68881");
+    cfgfile_write (f, "cpu_type=%s\n", tmp);
+}
 
 void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type)
 {
@@ -501,8 +517,14 @@ void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type)
     else
 	cfgfile_write (f, "cpu_speed=%s\n", p->m68k_speed == -1 ? "max" : "real");
 
-    cfgfile_write (f, "cpu_type=%s\n", cpumode[p->cpu_level * 2 + !p->address_space_24]);
+    /* do not reorder start */
+    write_compatibility_cpu(f, p);
+    cfgfile_write (f, "cpu_model=%d\n", p->cpu_model);
+    if (p->fpu_model)
+	cfgfile_write (f, "fpu_model=%d\n", p->fpu_model);
     cfgfile_write (f, "cpu_compatible=%s\n", p->cpu_compatible ? "true" : "false");
+    cfgfile_write (f, "cpu_24bit_addressing=%s\n", p->address_space_24 ? "true" : "false");
+    /* do not reorder end */
     cfgfile_write (f, "cpu_cycle_exact=%s\n", p->cpu_cycle_exact ? "true" : "false");
     cfgfile_write (f, "blitter_cycle_exact=%s\n", p->blitter_cycle_exact ? "true" : "false");
     cfgfile_write (f, "rtg_nocustom=%s\n", p->picasso96_nocustom ? "true" : "false");
@@ -1101,7 +1123,7 @@ static int cfgfile_parse_hardware (struct uae_prefs *p, char *option, char *valu
 
     if (cfgfile_yesno (option, value, "cpu_cycle_exact", &p->cpu_cycle_exact)
 	|| cfgfile_yesno (option, value, "blitter_cycle_exact", &p->blitter_cycle_exact)) {
-	if (p->cpu_level > 1 && p->cachesize > 0)
+	if (p->cpu_model >= 68020 && p->cachesize > 0)
 	    p->cpu_cycle_exact = p->blitter_cycle_exact = 0;
 	/* we don't want cycle-exact in 68020/40+JIT modes */
 	return 1;
@@ -1218,11 +1240,48 @@ static int cfgfile_parse_hardware (struct uae_prefs *p, char *option, char *valu
 	return 1;
     }
 
-    if (cfgfile_strval (option, value, "cpu_type", &p->cpu_level, cpumode, 0)) {
-	p->address_space_24 = p->cpu_level < 8 && !(p->cpu_level & 1);
-	p->cpu_level >>= 1;
+    if (cfgfile_string (option, value, "fpu_model", tmpbuf, sizeof tmpbuf)) {
+	p->fpu_model = atol(tmpbuf);
+	return 1;
+    }
+
+    if (cfgfile_string (option, value, "cpu_model", tmpbuf, sizeof tmpbuf)) {
+	p->cpu_model = atol(tmpbuf);
+	p->fpu_model = 0;
 	return 1;
     }
+
+    /* old-style CPU configuration */
+    if (cfgfile_string (option, value, "cpu_type", tmpbuf, sizeof tmpbuf)) {
+	p->fpu_model = 0;
+	p->address_space_24 = 0;
+	p->cpu_model = 680000;
+	if (!strcmp(tmpbuf, "68000")) {
+	    p->cpu_model = 68000;
+	} else if (!strcmp(tmpbuf, "68010")) {
+	    p->cpu_model = 68010;
+	} else if (!strcmp(tmpbuf, "68ec020")) {
+	    p->cpu_model = 68020;
+	    p->address_space_24 = 1;
+	} else if (!strcmp(tmpbuf, "68020")) {
+	    p->cpu_model = 68020;
+	} else if (!strcmp(tmpbuf, "68ec020/68881")) {
+	    p->cpu_model = 68020;
+	    p->fpu_model = 68881;
+	    p->address_space_24 = 1;
+	} else if (!strcmp(tmpbuf, "68020/68881")) {
+	    p->cpu_model = 68020;
+	    p->fpu_model = 68881;
+	} else if (!strcmp(tmpbuf, "68040")) {
+	    p->cpu_model = 68040;
+	    p->fpu_model = 68040;
+	} else if (!strcmp(tmpbuf, "68060")) {
+	    p->cpu_model = 68060;
+	    p->fpu_model = 68060;
+	}
+	return 1;
+    }
+
     if (p->config_version < (21 << 16)) {
 	if (cfgfile_strval (option, value, "cpu_speed", &p->m68k_speed, speedmode, 1)
 	    /* Broken earlier versions used to write this out as a string.  */
@@ -1899,21 +1958,21 @@ static void parse_cpu_specs (struct uae_prefs *p, char *spec)
 	return;
     }
 
-    p->cpu_level = *spec++ - '0';
-    p->address_space_24 = p->cpu_level < 2;
+    p->cpu_model = (*spec++) * 10 + 68000;
+    p->address_space_24 = p->cpu_model < 68020;
     p->cpu_compatible = 0;
     while (*spec != '\0') {
 	switch (*spec) {
 	 case 'a':
-	    if (p->cpu_level < 2)
+	    if (p->cpu_model < 68020)
 		write_log ("In 68000/68010 emulation, the address space is always 24 bit.\n");
-	    else if (p->cpu_level >= 4)
+	    else if (p->cpu_model >= 68040)
 		write_log ("In 68040/060 emulation, the address space is always 32 bit.\n");
 	    else
 		p->address_space_24 = 1;
 	    break;
 	 case 'c':
-	    if (p->cpu_level != 0)
+	    if (p->cpu_model != 68000)
 		write_log  ("The more compatible CPU emulation is only available for 68000\n"
 			 "emulation, not for 68010 upwards.\n");
 	    else
@@ -2476,7 +2535,7 @@ static void default_prefs_mini (struct uae_prefs *p, int type)
     p->nr_floppies = 1;
     p->dfxtype[0] = DRV_35_DD;
     p->dfxtype[1] = DRV_NONE;
-    p->cpu_level = 0;
+    p->cpu_model = 68000;
     p->address_space_24 = 1;
     p->chipmem_size = 0x00080000;
     p->bogomem_size = 0x00080000;
@@ -2631,7 +2690,8 @@ void default_prefs (struct uae_prefs *p, int type)
     p->prtname[0] = 0;
     p->sername[0] = 0;
 
-    p->cpu_level = 0;
+    p->fpu_model = 0;
+    p->cpu_model = 68000;
     p->m68k_speed = 0;
     p->cpu_compatible = 1;
     p->address_space_24 = 1;
@@ -2671,7 +2731,8 @@ void default_prefs (struct uae_prefs *p, int type)
 
 static void buildin_default_prefs_68020 (struct uae_prefs *p)
 {
-    p->cpu_level = 2;
+    p->cpu_model = 68020;
+    p->address_space_24 = 1;
     p->cpu_compatible = 1;
     p->chipset_mask = CSMASK_ECS_AGNUS | CSMASK_ECS_DENISE | CSMASK_AGA;
     p->chipmem_size = 0x200000;
@@ -2700,7 +2761,8 @@ static void buildin_default_prefs (struct uae_prefs *p)
     p->dfxtype[3] = DRV_NONE;
     p->floppy_speed = 100;
 
-    p->cpu_level = 0;
+    p->fpu_model = 0;
+    p->cpu_model = 68000;
     p->m68k_speed = 0;
     p->cpu_compatible = 1;
     p->address_space_24 = 1;
@@ -2998,7 +3060,8 @@ static int bip_super (struct uae_prefs *p, int config, int compa, int romcheck)
     p->chipmem_size = 0x400000;
     p->z3fastmem_size = 8 * 1024 * 1024;
     p->gfxmem_size = 8 * 1024 * 1024;
-    p->cpu_level = 4;
+    p->cpu_model = 68060;
+    p->fpu_model = 68060;
     p->chipset_mask = CSMASK_AGA | CSMASK_ECS_AGNUS | CSMASK_ECS_DENISE;
     p->cpu_compatible = p->address_space_24 = 0;
     p->m68k_speed = -1;
diff --git a/cia.c b/cia.c
index a49fac15..4c252205 100755
--- a/cia.c
+++ b/cia.c
@@ -1089,7 +1089,7 @@ uae_u32 REGPARAM2 cia_bget (uaecptr addr)
 	v = (addr & 1) ? ReadCIAA (r) : 0xff;
 	break;
 	case 3:
-	if (currprefs.cpu_level == 0 && currprefs.cpu_compatible)
+	if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible)
 	    v = (addr & 1) ? regs.irc : regs.irc >> 8;
 	if (warned > 0) {
 	    write_log ("cia_bget: unknown CIA address %x PC=%x\n", addr, M68K_GETPC);
@@ -1123,7 +1123,7 @@ uae_u32 REGPARAM2 cia_wget (uaecptr addr)
 	v = (0xff << 8) | ReadCIAA (r);
 	break;
 	case 3:
-	if (currprefs.cpu_level == 0 && currprefs.cpu_compatible)
+	if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible)
 	    v = regs.irc;
 	if (warned > 0) {
 	    write_log ("cia_wget: unknown CIA address %x PC=%x\n", addr, M68K_GETPC);
@@ -1149,13 +1149,13 @@ uae_u32 REGPARAM2 cia_lget (uaecptr addr)
 
 static uae_u32 REGPARAM2 cia_wgeti (uaecptr addr)
 {
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return dummy_wgeti(addr);
     return cia_wget(addr);
 }
 static uae_u32 REGPARAM2 cia_lgeti (uaecptr addr)
 {
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return dummy_lgeti(addr);
     return cia_lget(addr);
 }
@@ -1270,7 +1270,7 @@ uae_u32 REGPARAM2 clock_bget (uaecptr addr)
     addr &= 0x3f;
     if ((addr & 3) == 2 || (addr & 3) == 0) {
 	int v = 0;
-	if (currprefs.cpu_level == 0 && currprefs.cpu_compatible)
+	if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible)
 	    v = regs.irc >> 8;
 	return v;
     }
diff --git a/compemu_fpp.c b/compemu_fpp.c
index 2e1a6b97..2983faee 100755
--- a/compemu_fpp.c
+++ b/compemu_fpp.c
@@ -676,140 +676,14 @@ x86 conditions
     */
 void comp_fsave_opp (uae_u32 opcode)
 {
-    uae_u32 ad;
-    int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
-    int i;
-
     FAIL(1);
     return;
-
-    if (!currprefs.compfpu) {
-	FAIL(1);
-	return;
-    }
-
-#if DEBUG_FPP
-    write_log ("JIT: fsave_opp at %08lx\n", M68K_GETPC);
-#endif
-    if (!comp_fp_adr (opcode)) {
-	m68k_setpc (&regs, m68k_getpc (&regs) - 2);
-	op_illg (opcode, &regs);
-	return;
-    }
-
-    if (currprefs.cpu_level >= 4) {
-	/* 4 byte 68040 IDLE frame.  */
-	if (incr < 0) {
-	    ad -= 4;
-	    put_long (ad, 0x41000000);
-	} else {
-	    put_long (ad, 0x41000000);
-	    ad += 4;
-	}
-    } else {
-	if (incr < 0) {
-	    ad -= 4;
-	    put_long (ad, 0x70000000);
-	    for (i = 0; i < 5; i++) {
-		ad -= 4;
-		put_long (ad, 0x00000000);
-	    }
-	    ad -= 4;
-	    put_long (ad, 0x1f180000);
-	} else {
-	    put_long (ad, 0x1f180000);
-	    ad += 4;
-	    for (i = 0; i < 5; i++) {
-		put_long (ad, 0x00000000);
-		ad += 4;
-	    }
-	    put_long (ad, 0x70000000);
-	    ad += 4;
-	}
-    }
-    if ((opcode & 0x38) == 0x18)
-	m68k_areg (&regs, opcode & 7) = ad;
-    if ((opcode & 0x38) == 0x20)
-	m68k_areg (&regs, opcode & 7) = ad;
 }
 
 void comp_frestore_opp (uae_u32 opcode)
 {
-    uae_u32 ad;
-    uae_u32 d;
-    int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
-
     FAIL(1);
     return;
-
-    if (!currprefs.compfpu) {
-	FAIL(1);
-	return;
-    }
-
-#if DEBUG_FPP
-    write_log ("frestore_opp at %08lx\n", M68K_GETPC);
-#endif
-    if (!comp_fp_adr (opcode)) {
-	m68k_setpc (&regs, m68k_getpc (&regs) - 2);
-	op_illg (opcode, &regs);
-	return;
-    }
-    if (currprefs.cpu_level >= 4) {
-	/* 68040 */
-	if (incr < 0) {
-	    /* @@@ This may be wrong.  */
-	    ad -= 4;
-	    d = get_long (ad);
-	    if (d & 0xff000000) { /* Not a NULL frame? */
-		if (!(d & 0x00ff0000)) { /* IDLE */
-		} else if ((d & 0x00ff0000) == 0x00300000) { /* UNIMP */
-		    ad -= 44;
-		} else if ((d & 0x00ff0000) == 0x00600000) { /* BUSY */
-		    ad -= 92;
-		}
-	    }
-	} else {
-	    d = get_long (ad);
-	    ad += 4;
-	    if (d & 0xff000000) { /* Not a NULL frame? */
-		if (!(d & 0x00ff0000)) { /* IDLE */
-		} else if ((d & 0x00ff0000) == 0x00300000) { /* UNIMP */
-		    ad += 44;
-		} else if ((d & 0x00ff0000) == 0x00600000) { /* BUSY */
-		    ad += 92;
-		}
-	    }
-	}
-    } else {
-	if (incr < 0) {
-	    ad -= 4;
-	    d = get_long (ad);
-	    if (d & 0xff000000) {
-		if ((d & 0x00ff0000) == 0x00180000)
-		    ad -= 6 * 4;
-		else if ((d & 0x00ff0000) == 0x00380000)
-		    ad -= 14 * 4;
-		else if ((d & 0x00ff0000) == 0x00b40000)
-		    ad -= 45 * 4;
-	    }
-	} else {
-	    d = get_long (ad);
-	    ad += 4;
-	    if (d & 0xff000000) {
-		if ((d & 0x00ff0000) == 0x00180000)
-		    ad += 6 * 4;
-		else if ((d & 0x00ff0000) == 0x00380000)
-		    ad += 14 * 4;
-		else if ((d & 0x00ff0000) == 0x00b40000)
-		    ad += 45 * 4;
-	    }
-	}
-    }
-    if ((opcode & 0x38) == 0x18)
-	m68k_areg (&regs, opcode & 7) = ad;
-    if ((opcode & 0x38) == 0x20)
-	m68k_areg (&regs, opcode & 7) = ad;
 }
 
 extern uae_u32 xhex_pi[], xhex_exp_1[], xhex_l2_e[], xhex_ln_2[], xhex_ln_10[];
diff --git a/compemu_support.c b/compemu_support.c
index e45ebbc4..b75a5fbc 100755
--- a/compemu_support.c
+++ b/compemu_support.c
@@ -5663,9 +5663,9 @@ void build_comp(void)
     const struct comptbl* nftbl=op_smalltbl_0_comp_nf;
     int count;
 #ifdef NOFLAGS_SUPPORT
-    struct comptbl *nfctbl = (currprefs.cpu_level >= 4 ? op_smalltbl_0_nf
-			     : currprefs.cpu_level == 3 ? op_smalltbl_1_nf
-			     : currprefs.cpu_level == 2 ? op_smalltbl_2_nf
+    struct comptbl *nfctbl = (currprefs.cpu_level >= 5 ? op_smalltbl_0_nf
+			     : currprefs.cpu_level == 4 ? op_smalltbl_1_nf
+			     : (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) ? op_smalltbl_2_nf
 			     : currprefs.cpu_level == 1 ? op_smalltbl_3_nf
 			     : ! currprefs.cpu_compatible ? op_smalltbl_4_nf
 			     : op_smalltbl_5_nf);
diff --git a/custom.c b/custom.c
index 077892e9..1e96d6f4 100755
--- a/custom.c
+++ b/custom.c
@@ -198,7 +198,7 @@ static int sprite_last_drawn_at[MAX_SPRITES];
 static int last_sprite_point, nr_armed;
 static int sprite_width, sprres, sprite_buffer_res;
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 uae_u8 cycle_line[256];
 #endif
 
@@ -305,13 +305,13 @@ static int delta_sprite_entry = 0;
 static int max_color_change = 400;
 static int delta_color_change = 0;
 #else
-struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
-struct color_change color_changes[2][MAX_REG_CHANGE];
+static struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
+static struct color_change color_changes[2][MAX_REG_CHANGE];
 #endif
 
 struct decision line_decisions[2 * (MAXVPOS + 1) + 1];
-struct draw_info line_drawinfo[2][2 * (MAXVPOS + 1) + 1];
-struct color_entry color_tables[2][(MAXVPOS + 1) * 2];
+static struct draw_info line_drawinfo[2][2 * (MAXVPOS + 1) + 1];
+static struct color_entry color_tables[2][(MAXVPOS + 1) * 2];
 
 static int next_sprite_entry = 0;
 static int prev_next_sprite_entry;
@@ -440,9 +440,9 @@ void notice_new_xcolors (void)
 
     docols(&current_colors);
 /*    docols(&colors_for_drawing);*/
-    for (i = 0; i < (MAXVPOS + 1)*2; i++) {
-	docols(color_tables[0]+i);
-	docols(color_tables[1]+i);
+    for (i = 0; i < (MAXVPOS + 1) * 2; i++) {
+	docols(color_tables[0] + i);
+	docols(color_tables[1] + i);
     }
 }
 
@@ -2430,7 +2430,7 @@ STATIC_INLINE uae_u16 VPOSR (void)
 #if 0
     write_log ("vposr %x at %x\n", vp, m68k_getpc(&regs));
 #endif
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	hsyncdelay();
     return vp;
 }
@@ -2452,7 +2452,7 @@ STATIC_INLINE uae_u16 VHPOSR (void)
     uae_u16 hp = GETHPOS();
     vp <<= 8;
     vp |= hp;
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	hsyncdelay();
     return vp;
 }
@@ -3524,7 +3524,7 @@ static void update_copper (int until_hpos)
 	    if (copper_cant_read (old_hpos))
 		continue;
 	    cop_state.i1 = chipmem_agnus_wget (cop_state.ip);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 	    cycle_line[old_hpos] |= CYCLE_COPPER;
 #endif
 	    cop_state.ip += 2;
@@ -3538,7 +3538,7 @@ static void update_copper (int until_hpos)
 	    if (copper_cant_read (old_hpos))
 		continue;
 	    cop_state.i2 = chipmem_agnus_wget (cop_state.ip);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 	    cycle_line[old_hpos] |= CYCLE_COPPER;
 #endif
 	    cop_state.ip += 2;
@@ -3725,7 +3725,7 @@ STATIC_INLINE uae_u16 sprite_fetch (struct sprite *s, int dma, int hpos, int cyc
     uae_u16 data = last_custom_value;
     if (dma) {
 	data = last_custom_value = chipmem_agnus_wget (s->pt);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 	cycle_line[hpos] |= CYCLE_SPRITE;
 #endif
     }
@@ -4285,7 +4285,7 @@ static void hsync_handler (void)
 #ifdef CDTV
 	CDTV_hsync_handler ();
 #endif
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 	if (currprefs.cpu_cycle_exact || currprefs.blitter_cycle_exact) {
 	    decide_blitter (hpos);
 	    memset (cycle_line, 0, sizeof cycle_line);
@@ -4854,13 +4854,13 @@ addrbank custom_bank = {
 
 static uae_u32 REGPARAM2 custom_wgeti (uaecptr addr)
 {
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return dummy_wgeti(addr);
     return custom_wget(addr);
 }
 static uae_u32 REGPARAM2 custom_lgeti (uaecptr addr)
 {
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return dummy_lgeti(addr);
     return custom_lget(addr);
 }
@@ -5652,7 +5652,7 @@ void check_prefs_changed_custom (void)
 #endif
 }
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 
 STATIC_INLINE void sync_copper (int hpos)
 {
diff --git a/debug.c b/debug.c
index e4e0c5b7..4cd8bc3a 100755
--- a/debug.c
+++ b/debug.c
@@ -299,7 +299,7 @@ int safe_addr(uaecptr addr, int size)
 	return 0;
     if (!ab->check (addr, size))
 	return 0;
-    if (ab->flags == ABFLAG_RAM || ab->flags == ABFLAG_ROM)
+    if (ab->flags == ABFLAG_RAM || ab->flags == ABFLAG_ROM || ab->flags == ABFLAG_ROMIN)
 	return 1;
     return 0;
 }
@@ -1067,7 +1067,7 @@ static void smc_detector(uaecptr addr, int rwi, int size, uae_u32 *valp)
     }
     if ((hitpc & 0xFFF80000) == 0xF80000)
 	return;
-    if (currprefs.cpu_level == 0 && currprefs.cpu_compatible) {
+    if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible) {
 	/* ignore single-word unconditional jump instructions
 	 * (instruction prefetch from PC+2 can cause false positives) */
 	if (regs.irc == 0x4e75 || regs.irc == 4e74 || regs.irc == 0x4e72 || regs.irc == 4e77)
@@ -1942,6 +1942,7 @@ static void debug_1 (void)
 
     m68k_dumpstate (stdout, &nextpc);
     nxdis = nextpc; nxmem = 0;
+    debugger_active = 1;
 
     for (;;) {
 	char cmd, *inptr;
@@ -2375,7 +2376,7 @@ void mmu_do_hit(void)
     regs.t0 = regs.t1 = 0;
     if (!regs.s) {
 	regs.usp = m68k_areg(&regs, 7);
-	if (currprefs.cpu_level >= 2)
+	if (currprefs.cpu_model >= 68020)
 	    m68k_areg(&regs, 7) = regs.m ? regs.msp : regs.isp;
 	else
 	    m68k_areg(&regs, 7) = regs.isp;
@@ -2385,7 +2386,7 @@ void mmu_do_hit(void)
     m68k_setpc (&regs, mmu_callback);
     fill_prefetch_slow (&regs);
 
-    if (currprefs.cpu_level > 0) {
+    if (currprefs.cpu_model > 68000) {
 	for (i = 0 ; i < 9; i++) {
 	    m68k_areg(&regs, 7) -= 4;
 	    put_long (m68k_areg(&regs, 7), 0);
diff --git a/disk.c b/disk.c
index c0d155d3..9bf52abf 100755
--- a/disk.c
+++ b/disk.c
@@ -1118,7 +1118,7 @@ static void drive_motor (drive * drv, int off)
 #endif
 	if (disk_debug_logging > 1)
 	    write_log (" ->motor off");
-	if (currprefs.cpu_level <= 1 && currprefs.m68k_speed == 0) {
+	if (currprefs.cpu_model <= 68010 && currprefs.m68k_speed == 0) {
 	    drv->motordelay = 1;
 	    event2_newevent2(30, drv - floppy, motordelay_func);
 	}
diff --git a/drawing.c b/drawing.c
index 5131570d..bd607ac8 100755
--- a/drawing.c
+++ b/drawing.c
@@ -1483,7 +1483,7 @@ static void pfield_draw_line (int lineno, int gfx_ypos, int follow_ypos)
     dh = dh_line;
     xlinebuffer = gfxvidinfo.linemem;
     if (xlinebuffer == 0 && do_double
-	&& (border == 0 || (border != 1 && dip_for_drawing->nr_color_changes > 0)))
+	&& (border == 0 || dip_for_drawing->nr_color_changes > 0))
 	xlinebuffer = gfxvidinfo.emergmem, dh = dh_emerg;
     if (xlinebuffer == 0)
 	xlinebuffer = row_map[gfx_ypos], dh = dh_buf;
diff --git a/filesys.asm b/filesys.asm
index b8a15c79..247320c4 100755
--- a/filesys.asm
+++ b/filesys.asm
@@ -12,6 +12,7 @@
 ; 200?.??.?? Picasso96 vblank hack (TW)
 ; 2006.03.04 Mousehack code integrated (TW)
 ; 2006.18.07 FileSystem.resource find routine access fault fixed (TW)
+; 2007.03.30 mousehack do not start multiple times anymore (TW)
 
 AllocMem = -198
 FreeMem = -210
@@ -160,7 +161,7 @@ general_ret:
 exter_data:
 exter_server:
 	movem.l a2,-(sp)
-	move.w #$FF50,d0
+	move.w #$FF50,d0 ; exter_int_helper
 	bsr.w getrtbase
 	moveq.l #0,d0
 	jsr (a0)
@@ -169,7 +170,7 @@ exter_server:
 	; This is the hard part - we have to send some messages.
 	move.l 4.w,a6
 EXTS_loop:
-	move.w #$FF50,d0 ;exter_int_helper
+	move.w #$FF50,d0 ; exter_int_helper
 	bsr.w getrtbase
 	moveq.l #2,d0
 	jsr (a0)
@@ -621,8 +622,10 @@ filesys_mainloop:
 
 FSML_loop:
 	bsr.w mousehack_init
+
 	move.l a5,a0
 	jsr -384(a6) ; WaitPort
+
 	move.l a5,a0
 	jsr -372(a6) ; GetMsg
 	move.l d0,a4
@@ -665,7 +668,7 @@ nonotif
 	move.l (a2),a0
 FSML_check_old:
 	move.l a0,d0
-	beq.b FSML_loop
+	beq.w FSML_loop
 	move.l (a0),a1
 	move.l d0,a0
 	; This field may be accessed concurrently by several UAE threads.
@@ -697,7 +700,7 @@ FSML_FromDOS:
 
 FSML_DoCommand:
 	bsr.b LockCheck  ; Make sure there are enough locks for the C code to grab.
-	move.w #$FF30,d0
+	move.w #$FF30,d0 ; filesys_handler
 	bsr.w getrtbase
 	jsr (a0)
 	tst.l d0
@@ -903,12 +906,16 @@ mousehack_init:
 	tst.b 157(a3)
 	bne.s .no
 	lea mousehack_e(pc),a0
-	tst.w (a0)
-	beq.s .no
+	cmp.b #1,(a0)
+	bne.s .no
 	lea mhname(pc),a0
 	lea mousehack_task(pc),a1
 	bsr createtask
 	st 157(a3)
+	;tell native side that mousehack is active
+	move.w #$FF38,d0
+	bsr.w getrtbase
+	jsr (a0)
 .no	move.l (sp)+,a0
 	rts
 
diff --git a/filesys.c b/filesys.c
index 50538ed6..c7173a92 100755
--- a/filesys.c
+++ b/filesys.c
@@ -4278,6 +4278,13 @@ static uae_u32 REGPARAM2 filesys_dev_storeinfo (TrapContext *context)
     return type;
 }
 
+static uae_u32 REGPARAM2 mousehack_done (TrapContext *context)
+{
+    /* do not allow other fs threads to start another mousehack */
+    rtarea[get_long (RTAREA_BASE + 40) + 12 - 2] = 0xff;
+    return 1;
+}
+
 void filesys_install (void)
 {
     uaecptr loop;
@@ -4312,6 +4319,10 @@ void filesys_install (void)
     calltrap (deftrap2 (filesys_handler, 0, "filesys_handler"));
     dw (RTS);
 
+    org (RTAREA_BASE + 0xFF38);
+    calltrap (deftrap2 (mousehack_done, 0, "mousehack_done"));
+    dw (RTS);
+
     org (RTAREA_BASE + 0xFF40);
     calltrap (deftrap2 (startup_handler, 0, "startup_handler"));
     dw (RTS);
diff --git a/filesys_bootrom.c b/filesys_bootrom.c
index 30267c1c..09211a0a 100755
--- a/filesys_bootrom.c
+++ b/filesys_bootrom.c
@@ -3,14 +3,14 @@
  db(0x00); db(0x00); db(0x00); db(0x34); db(0x00); db(0x00); db(0x00); db(0xd4);
  db(0x00); db(0x00); db(0x00); db(0x20); db(0x00); db(0x00); db(0x01); db(0x8e);
  db(0x00); db(0x00); db(0x06); db(0xb8); db(0x00); db(0x00); db(0x07); db(0xdc);
- db(0x43); db(0xfa); db(0x09); db(0xa8); db(0x4e); db(0xae); db(0xff); db(0xa0);
+ db(0x43); db(0xfa); db(0x09); db(0xb4); db(0x4e); db(0xae); db(0xff); db(0xa0);
  db(0x20); db(0x40); db(0x20); db(0x28); db(0x00); db(0x16); db(0x20); db(0x40);
  db(0x4e); db(0x90); db(0x4e); db(0x75); db(0x48); db(0xe7); db(0xff); db(0xfe);
  db(0x2c); db(0x78); db(0x00); db(0x04); db(0x30); db(0x3c); db(0xff); db(0xfc);
  db(0x61); db(0x00); db(0x06); db(0x66); db(0x2a); db(0x50); db(0x43); db(0xfa);
- db(0x09); db(0xa0); db(0x70); db(0x24); db(0x7a); db(0x00); db(0x4e); db(0xae);
+ db(0x09); db(0xac); db(0x70); db(0x24); db(0x7a); db(0x00); db(0x4e); db(0xae);
  db(0xfd); db(0xd8); db(0x4a); db(0x80); db(0x66); db(0x0c); db(0x43); db(0xfa);
- db(0x09); db(0x90); db(0x70); db(0x00); db(0x7a); db(0x01); db(0x4e); db(0xae);
+ db(0x09); db(0x9c); db(0x70); db(0x00); db(0x7a); db(0x01); db(0x4e); db(0xae);
  db(0xfd); db(0xd8); db(0x28); db(0x40); db(0x20); db(0x3c); db(0x00); db(0x00);
  db(0x02); db(0x2c); db(0x72); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a);
  db(0x26); db(0x40); db(0x27); db(0x4c); db(0x01); db(0x9c); db(0x7c); db(0x00);
@@ -51,7 +51,7 @@
  db(0x4c); db(0xdf); db(0x04); db(0x00); db(0x4e); db(0x75); db(0x48); db(0xe7);
  db(0xc0); db(0xc0); db(0x70); db(0x1a); db(0x22); db(0x3c); db(0x00); db(0x01);
  db(0x00); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a); db(0x22); db(0x40);
- db(0x41); db(0xfa); db(0x08); db(0x19); db(0x23); db(0x48); db(0x00); db(0x0a);
+ db(0x41); db(0xfa); db(0x08); db(0x25); db(0x23); db(0x48); db(0x00); db(0x0a);
  db(0x41); db(0xfa); db(0xff); db(0x2a); db(0x23); db(0x48); db(0x00); db(0x0e);
  db(0x41); db(0xfa); db(0xff); db(0x22); db(0x23); db(0x48); db(0x00); db(0x12);
  db(0x33); db(0x7c); db(0x02); db(0x14); db(0x00); db(0x08); db(0x70); db(0x03);
@@ -64,7 +64,7 @@
  db(0x00); db(0x00); db(0x00); db(0x0e); db(0x52); db(0x40); db(0x0c); db(0x40);
  db(0x00); db(0x8c); db(0x66); db(0xf2); db(0x20); db(0x0a); db(0xe4); db(0x88);
  db(0x21); db(0x40); db(0x00); db(0x36); db(0x22); db(0x48); db(0x41); db(0xfa);
- db(0x07); db(0xb3); db(0x23); db(0x48); db(0x00); db(0x0a); db(0x20); db(0x6b);
+ db(0x07); db(0xbf); db(0x23); db(0x48); db(0x00); db(0x0a); db(0x20); db(0x6b);
  db(0x01); db(0x98); db(0x41); db(0xe8); db(0x00); db(0x12); db(0x4e); db(0xae);
  db(0xff); db(0x10); db(0x4c); db(0xdf); db(0x4f); db(0x03); db(0x4e); db(0x75);
  db(0x48); db(0xe7); db(0x7f); db(0x7e); db(0x2c); db(0x78); db(0x00); db(0x04);
@@ -106,13 +106,13 @@
  db(0x60); db(0xd4); db(0x48); db(0xe7); db(0x40); db(0xe2); db(0x2c); db(0x78);
  db(0x00); db(0x04); db(0x41); db(0xee); db(0x01); db(0x50); db(0x20); db(0x50);
  db(0x4a); db(0x90); db(0x67); db(0x1a); db(0x22); db(0x68); db(0x00); db(0x0a);
- db(0x45); db(0xfa); db(0x06); db(0xa0); db(0x10); db(0x19); db(0x12); db(0x1a);
+ db(0x45); db(0xfa); db(0x06); db(0xac); db(0x10); db(0x19); db(0x12); db(0x1a);
  db(0xb0); db(0x01); db(0x66); db(0x06); db(0x4a); db(0x00); db(0x67); db(0x42);
  db(0x60); db(0xf2); db(0x20); db(0x50); db(0x60); db(0xe2); db(0x70); db(0x20);
  db(0x22); db(0x3c); db(0x00); db(0x01); db(0x00); db(0x01); db(0x4e); db(0xae);
  db(0xff); db(0x3a); db(0x24); db(0x40); db(0x15); db(0x7c); db(0x00); db(0x08);
- db(0x00); db(0x08); db(0x41); db(0xfa); db(0x06); db(0x76); db(0x25); db(0x48);
- db(0x00); db(0x0a); db(0x41); db(0xfa); db(0x06); db(0x2f); db(0x25); db(0x48);
+ db(0x00); db(0x08); db(0x41); db(0xfa); db(0x06); db(0x82); db(0x25); db(0x48);
+ db(0x00); db(0x0a); db(0x41); db(0xfa); db(0x06); db(0x3b); db(0x25); db(0x48);
  db(0x00); db(0x0e); db(0x41); db(0xea); db(0x00); db(0x12); db(0x20); db(0x88);
  db(0x58); db(0x90); db(0x21); db(0x48); db(0x00); db(0x08); db(0x41); db(0xee);
  db(0x01); db(0x50); db(0x22); db(0x4a); db(0x4e); db(0xae); db(0xff); db(0x0a);
@@ -160,7 +160,7 @@
  db(0x70); db(0xff); db(0x2c); db(0x4c); db(0x4e); db(0xee); db(0xff); db(0x6a);
  db(0x2c); db(0x78); db(0x00); db(0x04); db(0x70); db(0x00); db(0x22); db(0x40);
  db(0x4e); db(0xae); db(0xfe); db(0xda); db(0x20); db(0x40); db(0x4b); db(0xe8);
- db(0x00); db(0x5c); db(0x43); db(0xfa); db(0x04); db(0xbe); db(0x70); db(0x00);
+ db(0x00); db(0x5c); db(0x43); db(0xfa); db(0x04); db(0xca); db(0x70); db(0x00);
  db(0x4e); db(0xae); db(0xfd); db(0xd8); db(0x24); db(0x40); db(0x20); db(0x3c);
  db(0x00); db(0x00); db(0x00); db(0x9e); db(0x22); db(0x3c); db(0x00); db(0x01);
  db(0x00); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a); db(0x26); db(0x40);
@@ -251,75 +251,76 @@
  db(0x00); db(0x36); db(0x22); db(0x4a); db(0x24); db(0x43); db(0x97); db(0xcb);
  db(0x4e); db(0xae); db(0xfe); db(0xe6); db(0x4c); db(0xdf); db(0x4c); db(0x0c);
  db(0x4e); db(0x75); db(0x00); db(0x00); db(0x00); db(0x00); db(0x00); db(0x00);
- db(0x2f); db(0x08); db(0x4a); db(0x2b); db(0x00); db(0x9d); db(0x66); db(0x18);
- db(0x41); db(0xfa); db(0xff); db(0xf0); db(0x4a); db(0x50); db(0x67); db(0x10);
- db(0x41); db(0xfa); db(0x01); db(0xba); db(0x43); db(0xfa); db(0x00); db(0x0e);
- db(0x61); db(0x00); db(0xff); db(0x8c); db(0x50); db(0xeb); db(0x00); db(0x9d);
- db(0x20); db(0x5f); db(0x4e); db(0x75); db(0x2c); db(0x79); db(0x00); db(0x00);
- db(0x00); db(0x04); db(0x70); db(0xff); db(0x4e); db(0xae); db(0xfe); db(0xb6);
- db(0x74); db(0x00); db(0x01); db(0xc2); db(0x93); db(0xc9); db(0x4e); db(0xae);
- db(0xfe); db(0xda); db(0x28); db(0x40); db(0x70); db(0x14); db(0x22); db(0x4c);
- db(0x4e); db(0xae); db(0xfe); db(0xd4); db(0x70); db(0x00); db(0x43); db(0xfa);
- db(0x01); db(0xae); db(0x4e); db(0xae); db(0xfd); db(0xd8); db(0x2e); db(0x00);
- db(0x70); db(0x00); db(0x30); db(0x3c); db(0x00); db(0x44); db(0x22); db(0x3c);
- db(0x00); db(0x01); db(0x00); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a);
- db(0x2a); db(0x40); db(0x61); db(0x00); db(0xfe); db(0xbe); db(0x61); db(0x00);
- db(0xff); db(0x0a); db(0x2b); db(0x40); db(0x00); db(0x3c); db(0x67); db(0x00);
- db(0x00); db(0x7a); db(0x22); db(0x40); db(0x41); db(0xfa); db(0x01); db(0x3c);
- db(0x70); db(0x00); db(0x72); db(0x00); db(0x4e); db(0xae); db(0xfe); db(0x44);
- db(0x4a); db(0x80); db(0x66); db(0x00); db(0x00); db(0x66); db(0x61); db(0x00);
- db(0xfe); db(0x9a); db(0x61); db(0x00); db(0xfe); db(0xe6); db(0x2b); db(0x40);
- db(0x00); db(0x40); db(0x67); db(0x00); db(0x00); db(0x56); db(0x22); db(0x40);
- db(0x41); db(0xfa); db(0x01); db(0x25); db(0x70); db(0x00); db(0x72); db(0x00);
+ db(0x2f); db(0x08); db(0x4a); db(0x2b); db(0x00); db(0x9d); db(0x66); db(0x24);
+ db(0x41); db(0xfa); db(0xff); db(0xf0); db(0x0c); db(0x10); db(0x00); db(0x01);
+ db(0x66); db(0x1a); db(0x41); db(0xfa); db(0x01); db(0xc4); db(0x43); db(0xfa);
+ db(0x00); db(0x18); db(0x61); db(0x00); db(0xff); db(0x8a); db(0x50); db(0xeb);
+ db(0x00); db(0x9d); db(0x30); db(0x3c); db(0xff); db(0x38); db(0x61); db(0x00);
+ db(0xfe); db(0xa0); db(0x4e); db(0x90); db(0x20); db(0x5f); db(0x4e); db(0x75);
+ db(0x2c); db(0x79); db(0x00); db(0x00); db(0x00); db(0x04); db(0x70); db(0xff);
+ db(0x4e); db(0xae); db(0xfe); db(0xb6); db(0x74); db(0x00); db(0x01); db(0xc2);
+ db(0x93); db(0xc9); db(0x4e); db(0xae); db(0xfe); db(0xda); db(0x28); db(0x40);
+ db(0x70); db(0x14); db(0x22); db(0x4c); db(0x4e); db(0xae); db(0xfe); db(0xd4);
+ db(0x70); db(0x00); db(0x43); db(0xfa); db(0x01); db(0xae); db(0x4e); db(0xae);
+ db(0xfd); db(0xd8); db(0x2e); db(0x00); db(0x70); db(0x00); db(0x30); db(0x3c);
+ db(0x00); db(0x44); db(0x22); db(0x3c); db(0x00); db(0x01); db(0x00); db(0x01);
+ db(0x4e); db(0xae); db(0xff); db(0x3a); db(0x2a); db(0x40); db(0x61); db(0x00);
+ db(0xfe); db(0xb2); db(0x61); db(0x00); db(0xfe); db(0xfe); db(0x2b); db(0x40);
+ db(0x00); db(0x3c); db(0x67); db(0x00); db(0x00); db(0x7a); db(0x22); db(0x40);
+ db(0x41); db(0xfa); db(0x01); db(0x3c); db(0x70); db(0x00); db(0x72); db(0x00);
  db(0x4e); db(0xae); db(0xfe); db(0x44); db(0x4a); db(0x80); db(0x66); db(0x00);
- db(0x00); db(0x42); db(0x47); db(0xed); db(0x00); db(0x16); db(0x27); db(0x4c);
- db(0x00); db(0x0c); db(0x27); db(0x42); db(0x00); db(0x08); db(0x70); db(0xff);
- db(0x26); db(0x80); db(0x27); db(0x40); db(0x00); db(0x04); db(0x43); db(0xed);
- db(0x00); db(0x00); db(0x13); db(0x7c); db(0x00); db(0x02); db(0x00); db(0x08);
- db(0x13); db(0x7c); db(0x00); db(0x05); db(0x00); db(0x09); db(0x41); db(0xfa);
- db(0x00); db(0xfc); db(0x23); db(0x48); db(0x00); db(0x0a); db(0x41); db(0xfa);
- db(0x00); db(0xa0); db(0x23); db(0x48); db(0x00); db(0x12); db(0x23); db(0x4b);
- db(0x00); db(0x0e); db(0x70); db(0x05); db(0x4e); db(0xae); db(0xff); db(0x58);
- db(0x60); db(0x02); db(0x4e); db(0x75); db(0x20); db(0x02); db(0x4e); db(0xae);
- db(0xfe); db(0xc2); db(0x22); db(0x6d); db(0x00); db(0x3c); db(0x45); db(0xed);
- db(0x00); db(0x26); db(0x33); db(0x7c); db(0x00); db(0x0b); db(0x00); db(0x1c);
- db(0x23); db(0x7c); db(0x00); db(0x00); db(0x00); db(0x16); db(0x00); db(0x24);
- db(0x23); db(0x4a); db(0x00); db(0x28); db(0x13); db(0x7c); db(0x00); db(0x01);
- db(0x00); db(0x1e); db(0x15); db(0x7c); db(0x00); db(0x04); db(0x00); db(0x04);
- db(0x42); db(0x2a); db(0x00); db(0x05); db(0x42); db(0x6a); db(0x00); db(0x06);
- db(0x42); db(0x6a); db(0x00); db(0x08); db(0x20); db(0x47); db(0x20); db(0x2d);
- db(0x00); db(0x16); db(0x32); db(0x28); db(0x00); db(0x30); db(0xd2); db(0x41);
- db(0x90); db(0x41); db(0x35); db(0x40); db(0x00); db(0x0a); db(0x20); db(0x2d);
- db(0x00); db(0x1a); db(0x32); db(0x28); db(0x00); db(0x2e); db(0xd2); db(0x41);
- db(0x90); db(0x41); db(0x48); db(0xc0); db(0x35); db(0x40); db(0x00); db(0x0c);
- db(0x22); db(0x6d); db(0x00); db(0x40); db(0x33); db(0x7c); db(0x00); db(0x0a);
- db(0x00); db(0x1c); db(0x13); db(0x7c); db(0x00); db(0x01); db(0x00); db(0x1e);
- db(0x4e); db(0xae); db(0xfe); db(0x38); db(0x22); db(0x6d); db(0x00); db(0x40);
- db(0x25); db(0x69); db(0x00); db(0x20); db(0x00); db(0x0e); db(0x25); db(0x69);
- db(0x00); db(0x24); db(0x00); db(0x12); db(0x22); db(0x6d); db(0x00); db(0x3c);
- db(0x4e); db(0xae); db(0xfe); db(0x38); db(0x60); db(0x00); db(0xff); db(0x76);
- db(0x30); db(0x3a); db(0xfe); db(0x82); db(0x48); db(0xc0); db(0x32); db(0x3a);
- db(0xfe); db(0x7e); db(0x48); db(0xc1); db(0xb0); db(0x91); db(0x66); db(0x00);
- db(0x00); db(0x0a); db(0xb2); db(0xa9); db(0x00); db(0x04); db(0x67); db(0x00);
- db(0x00); db(0x18); db(0x23); db(0x41); db(0x00); db(0x04); db(0x22); db(0x80);
- db(0x20); db(0x29); db(0x00); db(0x08); db(0x22); db(0x69); db(0x00); db(0x0c);
- db(0x2c); db(0x78); db(0x00); db(0x04); db(0x4e); db(0xae); db(0xfe); db(0xbc);
- db(0x41); db(0xf9); db(0x00); db(0xdf); db(0xf0); db(0x00); db(0x70); db(0x00);
- db(0x4e); db(0x75); db(0x69); db(0x6e); db(0x70); db(0x75); db(0x74); db(0x2e);
- db(0x64); db(0x65); db(0x76); db(0x69); db(0x63); db(0x65); db(0x00); db(0x74);
- db(0x69); db(0x6d); db(0x65); db(0x72); db(0x2e); db(0x64); db(0x65); db(0x76);
- db(0x69); db(0x63); db(0x65); db(0x00); db(0x55); db(0x41); db(0x45); db(0x20);
- db(0x6d); db(0x6f); db(0x75); db(0x73); db(0x65); db(0x20); db(0x68); db(0x61);
- db(0x63); db(0x6b); db(0x00); db(0x55); db(0x41); db(0x45); db(0x20); db(0x66);
- db(0x69); db(0x6c); db(0x65); db(0x73); db(0x79); db(0x73); db(0x74); db(0x65);
- db(0x6d); db(0x00); db(0x64); db(0x6f); db(0x73); db(0x2e); db(0x6c); db(0x69);
- db(0x62); db(0x72); db(0x61); db(0x72); db(0x79); db(0x00); db(0x69); db(0x6e);
- db(0x74); db(0x75); db(0x69); db(0x74); db(0x69); db(0x6f); db(0x6e); db(0x2e);
- db(0x6c); db(0x69); db(0x62); db(0x72); db(0x61); db(0x72); db(0x79); db(0x00);
- db(0x65); db(0x78); db(0x70); db(0x61); db(0x6e); db(0x73); db(0x69); db(0x6f);
- db(0x6e); db(0x2e); db(0x6c); db(0x69); db(0x62); db(0x72); db(0x61); db(0x72);
- db(0x79); db(0x00); db(0x46); db(0x69); db(0x6c); db(0x65); db(0x53); db(0x79);
- db(0x73); db(0x74); db(0x65); db(0x6d); db(0x2e); db(0x72); db(0x65); db(0x73);
- db(0x6f); db(0x75); db(0x72); db(0x63); db(0x65); db(0x00); db(0x00); db(0x00);
- db(0x00); db(0x00); db(0x03); db(0xf2);
+ db(0x00); db(0x66); db(0x61); db(0x00); db(0xfe); db(0x8e); db(0x61); db(0x00);
+ db(0xfe); db(0xda); db(0x2b); db(0x40); db(0x00); db(0x40); db(0x67); db(0x00);
+ db(0x00); db(0x56); db(0x22); db(0x40); db(0x41); db(0xfa); db(0x01); db(0x25);
+ db(0x70); db(0x00); db(0x72); db(0x00); db(0x4e); db(0xae); db(0xfe); db(0x44);
+ db(0x4a); db(0x80); db(0x66); db(0x00); db(0x00); db(0x42); db(0x47); db(0xed);
+ db(0x00); db(0x16); db(0x27); db(0x4c); db(0x00); db(0x0c); db(0x27); db(0x42);
+ db(0x00); db(0x08); db(0x70); db(0xff); db(0x26); db(0x80); db(0x27); db(0x40);
+ db(0x00); db(0x04); db(0x43); db(0xed); db(0x00); db(0x00); db(0x13); db(0x7c);
+ db(0x00); db(0x02); db(0x00); db(0x08); db(0x13); db(0x7c); db(0x00); db(0x05);
+ db(0x00); db(0x09); db(0x41); db(0xfa); db(0x00); db(0xfc); db(0x23); db(0x48);
+ db(0x00); db(0x0a); db(0x41); db(0xfa); db(0x00); db(0xa0); db(0x23); db(0x48);
+ db(0x00); db(0x12); db(0x23); db(0x4b); db(0x00); db(0x0e); db(0x70); db(0x05);
+ db(0x4e); db(0xae); db(0xff); db(0x58); db(0x60); db(0x02); db(0x4e); db(0x75);
+ db(0x20); db(0x02); db(0x4e); db(0xae); db(0xfe); db(0xc2); db(0x22); db(0x6d);
+ db(0x00); db(0x3c); db(0x45); db(0xed); db(0x00); db(0x26); db(0x33); db(0x7c);
+ db(0x00); db(0x0b); db(0x00); db(0x1c); db(0x23); db(0x7c); db(0x00); db(0x00);
+ db(0x00); db(0x16); db(0x00); db(0x24); db(0x23); db(0x4a); db(0x00); db(0x28);
+ db(0x13); db(0x7c); db(0x00); db(0x01); db(0x00); db(0x1e); db(0x15); db(0x7c);
+ db(0x00); db(0x04); db(0x00); db(0x04); db(0x42); db(0x2a); db(0x00); db(0x05);
+ db(0x42); db(0x6a); db(0x00); db(0x06); db(0x42); db(0x6a); db(0x00); db(0x08);
+ db(0x20); db(0x47); db(0x20); db(0x2d); db(0x00); db(0x16); db(0x32); db(0x28);
+ db(0x00); db(0x30); db(0xd2); db(0x41); db(0x90); db(0x41); db(0x35); db(0x40);
+ db(0x00); db(0x0a); db(0x20); db(0x2d); db(0x00); db(0x1a); db(0x32); db(0x28);
+ db(0x00); db(0x2e); db(0xd2); db(0x41); db(0x90); db(0x41); db(0x48); db(0xc0);
+ db(0x35); db(0x40); db(0x00); db(0x0c); db(0x22); db(0x6d); db(0x00); db(0x40);
+ db(0x33); db(0x7c); db(0x00); db(0x0a); db(0x00); db(0x1c); db(0x13); db(0x7c);
+ db(0x00); db(0x01); db(0x00); db(0x1e); db(0x4e); db(0xae); db(0xfe); db(0x38);
+ db(0x22); db(0x6d); db(0x00); db(0x40); db(0x25); db(0x69); db(0x00); db(0x20);
+ db(0x00); db(0x0e); db(0x25); db(0x69); db(0x00); db(0x24); db(0x00); db(0x12);
+ db(0x22); db(0x6d); db(0x00); db(0x3c); db(0x4e); db(0xae); db(0xfe); db(0x38);
+ db(0x60); db(0x00); db(0xff); db(0x76); db(0x30); db(0x3a); db(0xfe); db(0x76);
+ db(0x48); db(0xc0); db(0x32); db(0x3a); db(0xfe); db(0x72); db(0x48); db(0xc1);
+ db(0xb0); db(0x91); db(0x66); db(0x00); db(0x00); db(0x0a); db(0xb2); db(0xa9);
+ db(0x00); db(0x04); db(0x67); db(0x00); db(0x00); db(0x18); db(0x23); db(0x41);
+ db(0x00); db(0x04); db(0x22); db(0x80); db(0x20); db(0x29); db(0x00); db(0x08);
+ db(0x22); db(0x69); db(0x00); db(0x0c); db(0x2c); db(0x78); db(0x00); db(0x04);
+ db(0x4e); db(0xae); db(0xfe); db(0xbc); db(0x41); db(0xf9); db(0x00); db(0xdf);
+ db(0xf0); db(0x00); db(0x70); db(0x00); db(0x4e); db(0x75); db(0x69); db(0x6e);
+ db(0x70); db(0x75); db(0x74); db(0x2e); db(0x64); db(0x65); db(0x76); db(0x69);
+ db(0x63); db(0x65); db(0x00); db(0x74); db(0x69); db(0x6d); db(0x65); db(0x72);
+ db(0x2e); db(0x64); db(0x65); db(0x76); db(0x69); db(0x63); db(0x65); db(0x00);
+ db(0x55); db(0x41); db(0x45); db(0x20); db(0x6d); db(0x6f); db(0x75); db(0x73);
+ db(0x65); db(0x20); db(0x68); db(0x61); db(0x63); db(0x6b); db(0x00); db(0x55);
+ db(0x41); db(0x45); db(0x20); db(0x66); db(0x69); db(0x6c); db(0x65); db(0x73);
+ db(0x79); db(0x73); db(0x74); db(0x65); db(0x6d); db(0x00); db(0x64); db(0x6f);
+ db(0x73); db(0x2e); db(0x6c); db(0x69); db(0x62); db(0x72); db(0x61); db(0x72);
+ db(0x79); db(0x00); db(0x69); db(0x6e); db(0x74); db(0x75); db(0x69); db(0x74);
+ db(0x69); db(0x6f); db(0x6e); db(0x2e); db(0x6c); db(0x69); db(0x62); db(0x72);
+ db(0x61); db(0x72); db(0x79); db(0x00); db(0x65); db(0x78); db(0x70); db(0x61);
+ db(0x6e); db(0x73); db(0x69); db(0x6f); db(0x6e); db(0x2e); db(0x6c); db(0x69);
+ db(0x62); db(0x72); db(0x61); db(0x72); db(0x79); db(0x00); db(0x46); db(0x69);
+ db(0x6c); db(0x65); db(0x53); db(0x79); db(0x73); db(0x74); db(0x65); db(0x6d);
+ db(0x2e); db(0x72); db(0x65); db(0x73); db(0x6f); db(0x75); db(0x72); db(0x63);
+ db(0x65); db(0x00); db(0x00); db(0x00); db(0x00); db(0x00); db(0x03); db(0xf2);
 
diff --git a/fpp.c b/fpp.c
index 3aeb8475..ee9ef2d3 100755
--- a/fpp.c
+++ b/fpp.c
@@ -25,6 +25,15 @@
 
 #define DEBUG_FPP 0
 
+STATIC_INLINE int isfpu(struct regstruct *regs)
+{
+    if (regs->pcr & 2)
+	return FALSE;
+    if (currprefs.fpu_model <= 0)
+	return FALSE;
+    return TRUE;
+}
+
 STATIC_INLINE int isinrom (void)
 {
     return (munge24 (m68k_getpc (&regs)) & 0xFFF80000) == 0xF80000;
@@ -137,6 +146,24 @@ typedef uae_s64 tointtype;
 typedef uae_s32 tointtype;
 #endif
 
+static int get_fpu_version(void)
+{
+    int v = 0;
+    switch (currprefs.fpu_model)
+    {
+	case 68881:
+	v = 0x1f;
+	break;
+	case 68882:
+	v = 0x20; /* ??? */
+	break;
+	case 68040:
+	v = 0x41;
+	break;
+    }
+    return v;
+}
+
 STATIC_INLINE tointtype toint(fptype src, fptype minval, fptype maxval)
 {
     if (src < minval)
@@ -708,7 +735,7 @@ void fdbcc_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
 	write_log ("fdbcc_opp at %08lx\n", m68k_getpc (regs));
 #endif
     cc = fpp_cond (opcode, extra & 0x3f);
-    if (cc == -1) {
+    if (cc == -1 || !isfpu(regs)) {
 	m68k_setpc (regs, pc - 4);
 	op_illg (opcode, regs);
     } else if (!cc) {
@@ -731,7 +758,7 @@ void fscc_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
 	write_log ("fscc_opp at %08lx\n", m68k_getpc (regs));
 #endif
     cc = fpp_cond (opcode, extra & 0x3f);
-    if (cc == -1) {
+    if (cc == -1 || !isfpu(regs)) {
 	m68k_setpc (regs, m68k_getpc (regs) - 4);
 	op_illg (opcode, regs);
     } else if ((opcode & 0x38) == 0) {
@@ -754,7 +781,7 @@ void ftrapcc_opp (uae_u32 opcode, struct regstruct *regs, uaecptr oldpc)
 	write_log ("ftrapcc_opp at %08lx\n", m68k_getpc (regs));
 #endif
     cc = fpp_cond (opcode, opcode & 0x3f);
-    if (cc == -1) {
+    if (cc == -1 || !isfpu(regs)) {
 	m68k_setpc (regs, oldpc);
 	op_illg (opcode, regs);
     }
@@ -771,7 +798,7 @@ void fbcc_opp (uae_u32 opcode, struct regstruct *regs, uaecptr pc, uae_u32 extra
 	write_log ("fbcc_opp at %08lx\n", m68k_getpc (regs));
 #endif
     cc = fpp_cond (opcode, opcode & 0x3f);
-    if (cc == -1) {
+    if (cc == -1 || !isfpu(regs)) {
 	m68k_setpc (regs, pc);
 	op_illg (opcode, regs);
     } else if (cc) {
@@ -785,56 +812,60 @@ void fsave_opp (uae_u32 opcode, struct regstruct *regs)
 {
     uae_u32 ad;
     int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
-    int fpu_version = 0x18; /* 68881 */
-//    int fpu_version = 0x38; /* 68882 */
+    int fpu_version = get_fpu_version();
     int i;
 
-
 #if DEBUG_FPP
     if (!isinrom ())
 	write_log ("fsave_opp at %08lx\n", m68k_getpc (regs));
 #endif
-    if (get_fp_ad (opcode, &ad) == 0) {
+    if (get_fp_ad (opcode, &ad) == 0 || !isfpu(regs)) {
 	m68k_setpc (regs, m68k_getpc (regs) - 2);
 	op_illg (opcode, regs);
 	return;
     }
 
-#if 0
-    if (currprefs.cpu_level >= 6) {
-	/* 6 byte 68060 IDLE frame.  */
+    if (currprefs.fpu_model == 68060) {
+	/* 12 byte 68060 IDLE frame.  */
 	if (incr < 0) {
-	    ad -= 6;
+	    ad -= 4;
+	    put_long (ad, 0x00000000);
+	    ad -= 4;
+	    put_long (ad, 0x00000000);
+	    ad -= 4;
 	    put_long (ad, 0x00006000);
 	} else {
 	    put_long (ad, 0x00006000);
-	    ad += 6;
+	    ad += 4;
+	    put_long (ad, 0x00000000);
+	    ad += 4;
+	    put_long (ad, 0x00000000);
+	    ad += 4;
 	}
-    } else
-#endif
-    if (currprefs.cpu_level >= 4) {
+    } else if (currprefs.fpu_model == 68040) {
 	/* 4 byte 68040 IDLE frame.  */
 	if (incr < 0) {
 	    ad -= 4;
-	    put_long (ad, 0x41000000);
+	    put_long (ad, fpu_version << 24);
 	} else {
-	    put_long (ad, 0x41000000);
+	    put_long (ad, fpu_version << 24);
 	    ad += 4;
 	}
-    } else {
+    } else { /* 68881/68882 */
+	int idle_size = currprefs.fpu_model == 68882 ? 0x38 : 0x18;
 	if (incr < 0) {
 	    ad -= 4;
 	    put_long (ad, 0x70000000);
-	    for (i = 0; i < 5; i++) {
+	    for (i = 0; i < (idle_size - 1) / 4; i++) {
 		ad -= 4;
 		put_long (ad, 0x00000000);
 	    }
 	    ad -= 4;
-	    put_long (ad, 0x1f000000 | (fpu_version << 16));
+	    put_long (ad, (fpu_version << 24) | (idle_size << 16));
 	} else {
-	    put_long (ad, 0x1f000000 | (fpu_version << 16));
+	    put_long (ad, (fpu_version << 24) | (idle_size << 16));
 	    ad += 4;
-	    for (i = 0; i < 5; i++) {
+	    for (i = 0; i < (idle_size - 1) / 4; i++) {
 		put_long (ad, 0x00000000);
 		ad += 4;
 	    }
@@ -858,23 +889,25 @@ void frestore_opp (uae_u32 opcode, struct regstruct *regs)
     if (!isinrom ())
 	write_log ("frestore_opp at %08lx\n", m68k_getpc (regs));
 #endif
-    if (get_fp_ad (opcode, &ad) == 0) {
+    if (get_fp_ad (opcode, &ad) == 0 || !isfpu(regs)) {
 	m68k_setpc (regs, m68k_getpc (regs) - 2);
 	op_illg (opcode, regs);
 	return;
     }
-#if 0
-    if (currprefs.cpu_level >= 6) {
-	/* 68060 */
-        d = get_long (ad);
+
+    if (currprefs.fpu_model == 68060) {
+	/* all 68060 FPU frames are 12 bytes */
 	if (incr < 0) {
-	    ad -= 6;
+	    ad -= 4;
 	    d = get_long (ad);
-	} else
-	    ad += 6;
-    } else
-#endif
-    if (currprefs.cpu_level >= 4) {
+	    ad -= 8;
+	} else {
+	    d = get_long (ad);
+	    ad += 4;
+	    ad += 8;
+	}
+
+    } else if (currprefs.fpu_model == 68040) {
 	/* 68040 */
 	if (incr < 0) {
 	    /* @@@ This may be wrong.  */
@@ -900,7 +933,7 @@ void frestore_opp (uae_u32 opcode, struct regstruct *regs)
 		}
 	    }
 	}
-    } else {
+    } else { /* 68881/68882 */
 	if (incr < 0) {
 	    ad -= 4;
 	    d = get_long (ad);
@@ -945,6 +978,12 @@ void fpp_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
     if (!isinrom ())
 	write_log ("FPP %04lx %04x at %08lx\n", opcode & 0xffff, extra, m68k_getpc (regs) - 4);
 #endif
+    if (!isfpu(regs)) {
+        m68k_setpc (regs, m68k_getpc (regs) - 4);
+        op_illg (opcode, regs);
+	return;
+    }
+
     switch ((extra >> 13) & 0x7) {
 
     case 3:
@@ -1496,12 +1535,12 @@ void fpp_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
 
 uae_u8 *restore_fpu (uae_u8 *src)
 {
-    int model, i;
+    int i;
 
-    model = restore_u32();
+    changed_prefs.fpu_model = currprefs.fpu_model = restore_u32();
     restore_u32 ();
-    if (currprefs.cpu_level == 2) {
-	currprefs.cpu_level++;
+    if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) {
+	currprefs.cpu_level = 4;
 	init_m68k ();
     }
     changed_prefs.cpu_level = currprefs.cpu_level;
@@ -1520,28 +1559,16 @@ uae_u8 *restore_fpu (uae_u8 *src)
 uae_u8 *save_fpu (int *len, uae_u8 *dstptr)
 {
     uae_u8 *dstbak,*dst;
-    int model,i;
+    int i;
 
     *len = 0;
-    switch (currprefs.cpu_level)
-    {
-	case 3:
-	model = 68881;
-	break;
-	case 4:
-	model = 68040;
-	break;
-	case 6:
-	model = 68060;
-	break;
-	default:
+    if (currprefs.fpu_model == 0)
 	return 0;
-    }
     if (dstptr)
 	dstbak = dst = dstptr;
     else
 	dstbak = dst = malloc(4+4+8*10+4+4+4);
-    save_u32 (model);
+    save_u32 (currprefs.fpu_model);
     save_u32 (0);
     for (i = 0; i < 8; i++) {
 	uae_u32 w1, w2, w3;
diff --git a/gencomp.c b/gencomp.c
index ce5a04a3..6939b2f6 100755
--- a/gencomp.c
+++ b/gencomp.c
@@ -3032,7 +3032,7 @@ generate_func (int noflags)
     using_exception_3 = 0;
     for (i = 0; i < 1; i++) /* We only do one level! */
     {
-	cpu_level = 4 - i;
+	cpu_level = 6 - i;
 	postfix = i;
 
 	if (noflags)
diff --git a/gencpu.c b/gencpu.c
index 4c316b8c..b34560d3 100755
--- a/gencpu.c
+++ b/gencpu.c
@@ -67,7 +67,7 @@ static void read_counts (void)
     if (file) {
 	fscanf (file, "Total: %lu\n", &total);
 	while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
-	    opcode_next_clev[nr] = 4;
+	    opcode_next_clev[nr] = 6;
 	    opcode_last_postfix[nr] = -1;
 	    opcode_map[nr++] = opcode;
 	    counts[opcode] = count;
@@ -80,7 +80,7 @@ static void read_counts (void)
 	if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
 	    && counts[opcode] == 0)
 	{
-	    opcode_next_clev[nr] = 4;
+	    opcode_next_clev[nr] = 6;
 	    opcode_last_postfix[nr] = -1;
 	    opcode_map[nr++] = opcode;
 	    counts[opcode] = count;
@@ -2860,6 +2860,11 @@ static void gen_opcode (unsigned long int opcode)
 	sync_m68k_pc ();
 	printf ("\tmmu_op(opcode, regs, extra);\n");
 	break;
+    case i_MMUOP30:
+	genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+	sync_m68k_pc ();
+	printf ("\tmmu_op30(opcode, regs, extra);\n");
+	break;
     default:
 	abort ();
 	break;
@@ -3176,29 +3181,32 @@ int main (int argc, char **argv)
     using_ce = 0;
 
     postfix2 = -1;
-    for (i = 0; i < 7; i++) {
+    for (i = 0; i < 13; i++) {
 	postfix = i;
-	if (i == 0 || i == 5 || i == 6) {
+	if (i >= 7 && i < 11)
+	    continue;
+	if (i == 0 || i == 11 || i == 12) {
 	    fprintf (stblfile, "#ifdef CPUEMU_%d\n", postfix);
 	    postfix2 = postfix;
 	    sprintf (fname, "cpuemu_%d.c", postfix);
 	    freopen (fname, "wb", stdout);
 	    generate_includes (stdout);
 	}
-	cpu_level = 4 - i;
-	if (i == 5 || i == 6) {
+	cpu_level = 6 - i;
+	if (i == 11 || i == 12) {
 	    cpu_level = 0;
 	    using_prefetch = 1;
 	    using_exception_3 = 1;
-	    if (i == 6) using_ce = 1;
+	    if (i == 12)
+		using_ce = 1;
 	    for (rp = 0; rp < nr_cpuop_funcs; rp++)
 		opcode_next_clev[rp] = 0;
 	}
-	if (i > 0 && i < 4)
+	if (i > 0 && i < 7)
 	    fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
 	fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
 	generate_func ();
-	if (i > 0 && i < 4)
+	if (i > 0 && i < 7)
 	    fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
 	if (postfix2 >= 0)
 	    fprintf (stblfile, "#endif /* CPUEMU_%d */\n", postfix2);
diff --git a/include/cpu_prefetch.h b/include/cpu_prefetch.h
index 38252501..43146c4a 100755
--- a/include/cpu_prefetch.h
+++ b/include/cpu_prefetch.h
@@ -12,7 +12,7 @@ STATIC_INLINE uae_u32 get_long_prefetch (struct regstruct *regs, int o)
     return v;
 }
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 STATIC_INLINE uae_u32 mem_access_delay_word_read (uaecptr addr)
 {
     if (addr < 0x200000 || (addr >= 0xc00000 && addr < 0xe00000)) {
diff --git a/include/newcpu.h b/include/newcpu.h
index 08ca5156..0044a115 100755
--- a/include/newcpu.h
+++ b/include/newcpu.h
@@ -105,7 +105,7 @@ extern struct regstruct
     flagtype stopped;
     int intmask;
 
-    uae_u32 vbr,sfc,dfc;
+    uae_u32 vbr, sfc, dfc;
 
 #ifdef FPUEMU
     fptype fp[8];
@@ -115,6 +115,7 @@ extern struct regstruct
     uae_u32 fpsr_highbyte;
 #endif
 
+    uae_u32 pcr;
     uae_u32 spcflags;
     uae_u32 kick_mask;
     uae_u32 address_space_mask;
@@ -328,20 +329,24 @@ extern void fill_prefetch_slow (struct regstruct *regs);
 
 #define CPU_OP_NAME(a) op ## a
 
-/* 68040 */
+/* 68060 */
 extern const struct cputbl op_smalltbl_0_ff[];
-/* 68020 + 68881 */
+/* 68040 */
 extern const struct cputbl op_smalltbl_1_ff[];
-/* 68020 */
+/* 68020/68030+FPU */
 extern const struct cputbl op_smalltbl_2_ff[];
-/* 68010 */
+/* 68030 */
 extern const struct cputbl op_smalltbl_3_ff[];
-/* 68000 */
+/* 68020 */
 extern const struct cputbl op_smalltbl_4_ff[];
-/* 68000 slow but compatible.  */
+/* 68010 */
 extern const struct cputbl op_smalltbl_5_ff[];
-/* 68000 slow but compatible and cycle-exact.  */
+/* 68000 */
 extern const struct cputbl op_smalltbl_6_ff[];
+/* 68000 slow but compatible.  */
+extern const struct cputbl op_smalltbl_11_ff[];
+/* 68000 slow but compatible and cycle-exact.  */
+extern const struct cputbl op_smalltbl_12_ff[];
 
 extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
 
diff --git a/include/options.h b/include/options.h
index 3229e3a2..64e63fa7 100755
--- a/include/options.h
+++ b/include/options.h
@@ -226,6 +226,8 @@ struct uae_prefs {
 
     int m68k_speed;
     int cpu_level;
+    int cpu_model;
+    int fpu_model;
     int cpu_compatible;
     int address_space_24;
     int picasso96_nocustom;
diff --git a/include/readcpu.h b/include/readcpu.h
index 92c48693..1a1d7d05 100755
--- a/include/readcpu.h
+++ b/include/readcpu.h
@@ -28,7 +28,7 @@ ENUMDECL {
     i_PACK, i_UNPK, i_TAS, i_BKPT, i_CALLM, i_RTM, i_TRAPcc, i_MOVES,
     i_FPP, i_FDBcc, i_FScc, i_FTRAPcc, i_FBcc, i_FSAVE, i_FRESTORE,
     i_CINVL, i_CINVP, i_CINVA, i_CPUSHL, i_CPUSHP, i_CPUSHA, i_MOVE16,
-    i_MMUOP
+    i_MMUOP30, i_MMUOP
 } ENUMNAME (instrmnem);
 
 extern struct mnemolookup {
diff --git a/inputdevice.c b/inputdevice.c
index bb0e4721..24d60dad 100755
--- a/inputdevice.c
+++ b/inputdevice.c
@@ -790,9 +790,9 @@ static void mousehack_enable (void)
 {
     if (!uae_boot_rom)
 	return;
-    if (rtarea[get_long (RTAREA_BASE + 40) + 12 - 1])
+    if (rtarea[get_long (RTAREA_BASE + 40) + 12 - 2] == 0xff)
 	return;
-    rtarea[get_long (RTAREA_BASE + 40) + 12 - 1] = 1;
+    rtarea[get_long (RTAREA_BASE + 40) + 12 - 2] = 1;
 }
 
 static void mousehack_setpos(int mousexpos, int mouseypos)
diff --git a/main.c b/main.c
index 99e08622..ef4c3df5 100755
--- a/main.c
+++ b/main.c
@@ -120,11 +120,53 @@ void fixup_prefs_dimensions (struct uae_prefs *prefs)
     fixup_prefs_dim2(&prefs->gfx_size_win);
 }
 
+static void fixup_cpu(struct uae_prefs *p)
+{
+    p->cpu_level = 0;
+    switch(p->cpu_model)
+    {
+        case 68000:
+        p->cpu_level = 0;
+	p->address_space_24 = 1;
+	p->fpu_model = 0;
+        break;
+	case 68010:
+	p->cpu_level = 1;
+	p->address_space_24 = 1;
+	p->fpu_model = 0;
+	break;
+	case 68020:
+	p->cpu_level = 2;
+	break;
+	case 68030:
+	p->cpu_level = 3;
+	p->address_space_24 = 0;
+	break;
+	case 68040:
+	p->cpu_level = 5;
+	p->address_space_24 = 0;
+	if (p->fpu_model)
+	    p->fpu_model = 68040;
+	break;
+	case 68060:
+	p->cpu_level = 6;
+	p->address_space_24 = 0;
+	if (p->fpu_model)
+	    p->fpu_model = 68060;
+	break;
+    }
+    if ((p->cpu_level == 2 || p->cpu_level == 3) && p->fpu_model)
+	p->cpu_level = 4;
+}
+
+
 void fixup_prefs (struct uae_prefs *p)
 {
     int err = 0;
 
     build_in_chipset_prefs (p);
+    fixup_cpu(p);
+
     if ((p->chipmem_size & (p->chipmem_size - 1)) != 0
 	|| p->chipmem_size < 0x40000
 	|| p->chipmem_size > 0x800000)
@@ -246,13 +288,13 @@ void fixup_prefs (struct uae_prefs *p)
 	p->cachesize = 0;
 	err = 1;
     }
-    if (p->cpu_level < 2 && p->z3fastmem_size > 0) {
+    if (p->z3fastmem_size > 0 && (p->address_space_24 || p->cpu_model < 68020)) {
 	write_log ("Z3 fast memory can't be used with a 68000/68010 emulation. It\n"
 		 "requires a 68020 emulation. Turning off Z3 fast memory.\n");
 	p->z3fastmem_size = 0;
 	err = 1;
     }
-    if (p->gfxmem_size > 0 && (p->cpu_level < 2 || p->address_space_24)) {
+    if (p->gfxmem_size > 0 && (p->cpu_model < 68020 || p->address_space_24)) {
 	write_log ("Picasso96 can't be used with a 68000/68010 or 68EC020 emulation. It\n"
 		 "requires a 68020 emulation. Turning off Picasso96.\n");
 	p->gfxmem_size = 0;
@@ -291,7 +333,7 @@ void fixup_prefs (struct uae_prefs *p)
     if (p->cs_compatible) {
 	p->cs_fatgaryrev = p->cs_ramseyrev = p->cs_mbdmac = -1;
 	p->cs_ide = 0;
-	if (p->cpu_level >= 2) {
+	if (p->cpu_model >= 68020) {
 	    p->cs_fatgaryrev = 0;
 	    p->cs_ide = -1;
 	    p->cs_ramseyrev = 0x0f;
@@ -301,17 +343,19 @@ void fixup_prefs (struct uae_prefs *p)
     fixup_prefs_dimensions (p);
 
 #ifdef CPU_68000_ONLY
+    p->cpu_model = 68000;
     p->cpu_level = 0;
+    p->fpu_model = 0;
 #endif
 #ifndef CPUEMU_0
     p->cpu_compatible = 1;
     p->address_space_24 = 1;
 #endif
-#if !defined(CPUEMU_5) && !defined (CPUEMU_6)
+#if !defined(CPUEMU_11) && !defined (CPUEMU_12)
     p->cpu_compatible = 0;
     p->address_space_24 = 0;
 #endif
-#if !defined (CPUEMU_6)
+#if !defined (CPUEMU_12)
     p->cpu_cycle_exact = p->blitter_cycle_exact = 0;
 #endif
 #ifndef AGA
@@ -332,7 +376,7 @@ void fixup_prefs (struct uae_prefs *p)
 #if !defined (UAESERIAL)
     p->uaeserial = 0;
 #endif
-#if defined(CPUEMU_6)
+#if defined(CPUEMU_12)
     if (p->cpu_cycle_exact)
 	p->gfx_framerate = 1;
 #endif
@@ -640,7 +684,7 @@ static void real_main2 (int argc, char **argv)
     }
 
 #ifdef JIT
-    if (!(( currprefs.cpu_level >= 2 ) && ( currprefs.address_space_24 == 0 ) && ( currprefs.cachesize )))
+    if (!((currprefs.cpu_model >= 68020) && (currprefs.address_space_24 == 0) && (currprefs.cachesize)))
 	canbang = 0;
 #endif
 
diff --git a/memory.c b/memory.c
index 985a533b..b64e7d2b 100755
--- a/memory.c
+++ b/memory.c
@@ -685,7 +685,7 @@ static uae_u32 REGPARAM2 dummy_lget (uaecptr addr)
 #endif
     if (currprefs.illegal_mem)
 	dummylog(0, addr, 4, 0, 0);
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return NONEXISTINGDATA;
     return (regs.irc << 16) | regs.irc;
 }
@@ -696,7 +696,7 @@ uae_u32 REGPARAM2 dummy_lgeti (uaecptr addr)
 #endif
     if (currprefs.illegal_mem)
 	dummylog(0, addr, 4, 0, 1);
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return NONEXISTINGDATA;
     return (regs.irc << 16) | regs.irc;
 }
@@ -708,7 +708,7 @@ static uae_u32 REGPARAM2 dummy_wget (uaecptr addr)
 #endif
     if (currprefs.illegal_mem)
 	dummylog(0, addr, 2, 0, 0);
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return NONEXISTINGDATA;
     return regs.irc;
 }
@@ -719,7 +719,7 @@ uae_u32 REGPARAM2 dummy_wgeti (uaecptr addr)
 #endif
     if (currprefs.illegal_mem)
 	dummylog(0, addr, 2, 0, 1);
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return NONEXISTINGDATA;
     return regs.irc;
 }
@@ -731,7 +731,7 @@ static uae_u32 REGPARAM2 dummy_bget (uaecptr addr)
 #endif
     if (currprefs.illegal_mem)
 	dummylog(0, addr, 1, 0, 0);
-    if (currprefs.cpu_level >= 2)
+    if (currprefs.cpu_model >= 68020)
 	return NONEXISTINGDATA;
     return (addr & 1) ? regs.irc : regs.irc >> 8;
 }
@@ -1514,7 +1514,7 @@ uae_u8 *REGPARAM2 default_xlate (uaecptr a)
 {
     if (quit_program == 0) {
 	/* do this only in 68010+ mode, there are some tricky A500 programs.. */
-	if (currprefs.cpu_level > 0 || !currprefs.cpu_compatible) {
+	if (currprefs.cpu_model > 68000 || !currprefs.cpu_compatible) {
 #if defined(ENFORCER)
 	    enforcer_disable ();
 #endif
@@ -2213,7 +2213,7 @@ void map_overlay (int chip)
 
     cb = &chipmem_bank;
 #ifdef AGA
-    if (currprefs.cpu_cycle_exact && currprefs.cpu_level >= 2)
+    if (currprefs.cpu_cycle_exact && currprefs.cpu_model >= 68020)
 	cb = &chipmem_bank_ce2;
 #endif
     if (chip)
@@ -2273,10 +2273,10 @@ void memory_reset (void)
 	} else {
 	    struct romdata *rd = getromdatabydata (kickmemory, kickmem_size);
 	    if (rd) {
-		if ((rd->cpu & 3) == 1 && changed_prefs.cpu_level < 2) {
+		if ((rd->cpu & 3) == 1 && changed_prefs.cpu_model < 68020) {
 		    notify_user (NUMSG_KS68EC020);
 		    uae_restart (-1, NULL);
-		} else if ((rd->cpu & 3) == 2 && (changed_prefs.cpu_level < 2 || changed_prefs.address_space_24)) {
+		} else if ((rd->cpu & 3) == 2 && (changed_prefs.cpu_model < 68020 || changed_prefs.address_space_24)) {
 		    notify_user (NUMSG_KS68020);
 		    uae_restart (-1, NULL);
 		}
@@ -2313,7 +2313,7 @@ void memory_reset (void)
 	int t = allocated_bogomem >> 16;
 	if (t > 0x1C)
 	    t = 0x1C;
-	if (t > 0x10 && ((currprefs.chipset_mask & CSMASK_AGA) || currprefs.cpu_level >= 2))
+	if (t > 0x10 && ((currprefs.chipset_mask & CSMASK_AGA) || currprefs.cpu_model >= 68020))
 	    t = 0x10;
 	map_banks (&bogomem_bank, 0xC0, t, 0);
     }
diff --git a/newcpu.c b/newcpu.c
index 123d63c2..62b0cc4a 100755
--- a/newcpu.c
+++ b/newcpu.c
@@ -74,6 +74,7 @@ cpuop_func *cpufunctbl[65536];
 extern uae_u32 get_fpsr(void);
 
 #define COUNT_INSTRS 0
+#define MC68060_PCR 0x04300100
 
 #if COUNT_INSTRS
 static unsigned long int instrcount[65536];
@@ -142,35 +143,41 @@ static void build_cpufunctbl (void)
     int i, opcnt;
     unsigned long opcode;
     const struct cputbl *tbl = 0;
+    int fpu_model = 0;
 
-   switch (currprefs.cpu_level)
+    switch (currprefs.cpu_level)
     {
 #ifdef CPUEMU_0
 #ifndef CPUEMU_68000_ONLY
-	case 4:
-	case 6:
+	case 6: /* 68060 */
 	tbl = op_smalltbl_0_ff;
 	break;
-	case 3:
-	tbl = op_smalltbl_1_ff;
+	case 5: /* 68040 */
+	tbl = op_smalltbl_0_ff;
 	break;
-	case 2:
+	case 4: /* 68020/68030 + 68881+68882 */
 	tbl = op_smalltbl_2_ff;
 	break;
-	case 1:
+	case 3: /* 68030 */
 	tbl = op_smalltbl_3_ff;
 	break;
+	case 2: /* 68020 */
+	tbl = op_smalltbl_4_ff;
+	break;
+	case 1: /* 68010 */
+	tbl = op_smalltbl_5_ff;
+	break;
 #endif
 #endif
-	case 0:
-	tbl = op_smalltbl_4_ff;
-#ifdef CPUEMU_5
+	case 0: /* 68000 */
+	tbl = op_smalltbl_6_ff;
+#ifdef CPUEMU_11
 	if (currprefs.cpu_compatible)
-	    tbl = op_smalltbl_5_ff; /* prefetch */
+	    tbl = op_smalltbl_11_ff; /* prefetch */
 #endif
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 	if (currprefs.cpu_cycle_exact)
-	    tbl = op_smalltbl_6_ff; /* prefetch and cycle-exact */
+	    tbl = op_smalltbl_12_ff; /* prefetch and cycle-exact */
 #endif
 	break;
     }
@@ -200,10 +207,10 @@ static void build_cpufunctbl (void)
 	    opcnt++;
 	}
     }
-    write_log ("Building CPU function table, %d opcodes (%d %d %d).\n",
+    write_log ("Building CPU function table, %d opcodes (%d %d %d). CPU=%d, FPU=%d.\n",
 	opcnt, currprefs.cpu_level,
 	currprefs.cpu_cycle_exact ? -1 : currprefs.cpu_compatible ? 1 : 0,
-	currprefs.address_space_24);
+	currprefs.address_space_24, currprefs.cpu_model, currprefs.fpu_model);
 #ifdef JIT
     build_comp ();
 #endif
@@ -211,7 +218,7 @@ static void build_cpufunctbl (void)
 
 void fill_prefetch_slow (struct regstruct *regs)
 {
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
     if (currprefs.cpu_cycle_exact) {
 	regs->ir = get_word_ce (m68k_getpc (regs));
 	regs->irc = get_word_ce (m68k_getpc (regs) + 2);
@@ -219,7 +226,7 @@ void fill_prefetch_slow (struct regstruct *regs)
 #endif
 	regs->ir = get_word (m68k_getpc (regs));
 	regs->irc = get_word (m68k_getpc (regs) + 2);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
     }
 #endif
 }
@@ -239,6 +246,8 @@ static void update_68k_cycles (void)
 void check_prefs_changed_cpu (void)
 {
     if (currprefs.cpu_level != changed_prefs.cpu_level
+	|| currprefs.cpu_model != changed_prefs.cpu_model
+	|| currprefs.fpu_model != changed_prefs.fpu_model
 	|| currprefs.cpu_compatible != changed_prefs.cpu_compatible
 	|| currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) {
 
@@ -246,6 +255,8 @@ void check_prefs_changed_cpu (void)
 	    fill_prefetch_slow (&regs);
 
 	currprefs.cpu_level = changed_prefs.cpu_level;
+	currprefs.cpu_model = changed_prefs.cpu_model;
+	currprefs.fpu_model = changed_prefs.fpu_model;
 	currprefs.cpu_compatible = changed_prefs.cpu_compatible;
 	currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
 	currprefs.blitter_cycle_exact = changed_prefs.cpu_cycle_exact;
@@ -303,38 +314,16 @@ void init_m68k (void)
 	}
     }
 #endif
-    write_log ("Building CPU table for configuration: 68");
+    write_log ("Building CPU table for configuration: %d", currprefs.cpu_model);
     regs.address_space_mask = 0xffffffff;
     if (currprefs.cpu_compatible > 0) {
-	if (currprefs.address_space_24 && currprefs.cpu_level > 3)
+	if (currprefs.address_space_24 && currprefs.cpu_model >= 68030)
 	    currprefs.address_space_24 = 0;
-	if (currprefs.address_space_24 && currprefs.cpu_level > 1)
-	    write_log ("EC");
-    }
-    switch (currprefs.cpu_level) {
-    case 1:
-	write_log ("010");
-	break;
-    case 2:
-	write_log ("020");
-	break;
-    case 3:
-	write_log ("020/881");
-	break;
-    case 4:
-	/* Who is going to miss the MMU anyway...? :-)  */
-	write_log ("040");
-	break;
-    case 6:
-	/* Who is going to miss the MMU anyway...? :-)  */
-	write_log ("060");
-	break;
-    default:
-	write_log ("000");
-	break;
     }
+    if (currprefs.fpu_model > 0)
+	write_log("/%d", currprefs.fpu_model);
     if (currprefs.cpu_cycle_exact) {
-	if (currprefs.cpu_level == 0)
+	if (currprefs.cpu_model == 68000)
 	    write_log (" prefetch and cycle-exact");
 	else
 	    write_log (" ~cycle-exact");
@@ -342,7 +331,7 @@ void init_m68k (void)
 	write_log (" prefetch");
     if (currprefs.address_space_24) {
 	regs.address_space_mask = 0x00ffffff;
-	write_log (" 24-bit addressing");
+	write_log (" 24-bit");
     }
     write_log ("\n");
 
@@ -778,7 +767,10 @@ void REGPARAM2 MakeFromSR (struct regstruct *regs)
     regs->s  = (regs->sr >> 13) & 1;
     regs->m  = (regs->sr >> 12) & 1;
     regs->intmask = (regs->sr >> 8) & 7;
-    if (currprefs.cpu_level >= 2) {
+    if (currprefs.cpu_model >= 68020) {
+	 /* 68060 does not have MSP but does have M-bit.. */
+	if (currprefs.cpu_model >= 68060)
+	    regs->msp = regs->isp;
 	if (olds != regs->s) {
 	    if (olds) {
 		if (oldm)
@@ -799,6 +791,8 @@ void REGPARAM2 MakeFromSR (struct regstruct *regs)
 		m68k_areg (regs, 7) = regs->msp;
 	    }
 	}
+	if (currprefs.cpu_model >= 68060)
+	    regs->t0 = 0;
     } else {
 	regs->t0 = regs->m = 0;
 	if (olds != regs->s) {
@@ -843,7 +837,7 @@ static void exception_debug (int nr)
 #endif
 }
 
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
 
 /* cycle-exact exception handler, 68000 only */
 
@@ -964,16 +958,16 @@ static void Exception_normal (int nr, struct regstruct *regs, uaecptr oldpc)
 
     if (!regs->s) {
 	regs->usp = m68k_areg(regs, 7);
-	if (currprefs.cpu_level >= 2)
+	if (currprefs.cpu_model >= 68020)
 	    m68k_areg(regs, 7) = regs->m ? regs->msp : regs->isp;
 	else
 	    m68k_areg(regs, 7) = regs->isp;
 	regs->s = 1;
     }
-    if (currprefs.cpu_level > 0) {
+    if (currprefs.cpu_model > 68000) {
 	if (nr == 2 || nr == 3) {
 	    int i;
-	    if (currprefs.cpu_level >= 4) { /* 68040 */
+	    if (currprefs.cpu_model >= 68040) {
 		if (nr == 2) {
 		    for (i = 0 ; i < 18 ; i++) {
 			m68k_areg(regs, 7) -= 2;
@@ -1081,8 +1075,8 @@ void REGPARAM2 Exception (int nr, struct regstruct *regs, uaecptr oldpc)
 	write_log ("exception %d %08.8X %08.8X (%04.4X %04.4X)\n",
 	    nr, oldpc, m68k_getpc(), intena, intreq);
 #endif
-#ifdef CPUEMU_6
-    if (currprefs.cpu_cycle_exact && currprefs.cpu_level == 0)
+#ifdef CPUEMU_12
+    if (currprefs.cpu_cycle_exact && currprefs.cpu_model == 68000)
 	Exception_ce (nr, regs, oldpc);
     else
 #endif
@@ -1109,30 +1103,39 @@ void Interrupt (int nr)
     do_interrupt (nr, &regs);
 }
 
-static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp, buscr, pcr;
+static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp, buscr;
 
 #ifndef CPUEMU_68000_ONLY
 
 static int movec_illg (int regno)
 {
     int regno2 = regno & 0x7ff;
-    if (currprefs.cpu_level == 1) { /* 68010 */
+
+    if (currprefs.cpu_model == 68060) {
+	if (regno <= 8)
+	    return 0;
+	if (regno == 0x800 || regno == 0x801 ||
+	    regno == 0x806 || regno == 0x807 || regno == 0x808)
+	    return 0;
+	return 1;
+    } else if (currprefs.cpu_model == 68010) {
 	if (regno2 < 2)
 	    return 0;
 	return 1;
-    }
-    if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
+    } else if (currprefs.cpu_model == 68020) {
 	if (regno == 3) return 1; /* 68040 only */
 	 /* 4 is >=68040, but 0x804 is in 68020 */
 	 if (regno2 < 4 || regno == 0x804)
 	    return 0;
 	return 1;
-    }
-    if (currprefs.cpu_level >= 4) { /* 68040 */
+    } else if (currprefs.cpu_model == 68030) {
+	if (regno2 <= 2) return 0;
+	if (regno == 0x803 || regno == 0x804)
+	    return 0;
+	return 1;
+    } else if (currprefs.cpu_model == 68040) {
 	if (regno == 0x802) return 1; /* 68020 only */
 	if (regno2 < 8) return 0;
-	if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
-	    return 0;
 	return 1;
     }
     return 1;
@@ -1140,7 +1143,9 @@ static int movec_illg (int regno)
 
 int m68k_move2c (int regno, uae_u32 *regp)
 {
-    //write_log("move2c %04.4X <- %08.8X\n", regno, *regp);
+#ifdef MOVEC_DEBUG
+    write_log("move2c %04.4X <- %08.8X PC=%x\n", regno, *regp, M68K_GETPC);
+#endif
     if (movec_illg (regno)) {
 	op_illg (0x4E7B, &regs);
 	return 0;
@@ -1148,10 +1153,20 @@ int m68k_move2c (int regno, uae_u32 *regp)
 	switch (regno) {
 	case 0: regs.sfc = *regp & 7; break;
 	case 1: regs.dfc = *regp & 7; break;
-	 case 2:
-	    cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : (currprefs.cpu_level == 4 ? 0x80008000 : 0xf8800e00));
+	case 2:
+	{
+	    uae_u32 cacr_mask = 0;
+	    if (currprefs.cpu_model == 68020)
+		cacr_mask = 0x00000003;
+	    else if (currprefs.cpu_model == 68030)
+		cacr_mask = 0x00003313;
+	    else if (currprefs.cpu_model == 68040)
+		cacr_mask = 0x80008000;
+	    else if (currprefs.cpu_model == 68060)
+		cacr_mask = 0xf880e000;
+	    cacr = *regp & cacr_mask;
 #ifdef JIT
-	    if (currprefs.cpu_level < 4) {
+	    if (currprefs.cpu_model < 68040) {
 		set_cache_state(cacr & 1);
 		if (*regp & 0x08) {
 		    flush_icache(1);
@@ -1163,7 +1178,8 @@ int m68k_move2c (int regno, uae_u32 *regp)
 		}
 	    }
 #endif
-	    break;
+	}
+	break;
 	case 3: tc = *regp & 0xc000; break;
 	    /* Mask out fields that should be zero.  */
 	case 4: itt0 = *regp & 0xffffe364; break;
@@ -1180,7 +1196,16 @@ int m68k_move2c (int regno, uae_u32 *regp)
 	case 0x805: mmusr = *regp; break;
 	case 0x806: urp = *regp; break;
 	case 0x807: srp = *regp; break;
-	case 0x808: pcr = *regp & (0x40 | 2 | 1); break;
+	case 0x808:
+	{
+	    uae_u32 opcr = regs.pcr;
+	    regs.pcr = (*regp & (0x40 | 2 | 1)) | MC68060_PCR;
+	    if (((opcr ^ regs.pcr) & 2) == 2) {
+		write_log("68060 FPU state: %s\n", regs.pcr & 2 ? "disabled" : "enabled");
+		flush_icache(2);
+	    }
+	}
+	break;
 	default:
 	    op_illg (0x4E7B, &regs);
 	    return 0;
@@ -1191,7 +1216,9 @@ int m68k_move2c (int regno, uae_u32 *regp)
 
 int m68k_movec2 (int regno, uae_u32 *regp)
 {
-    //write_log("movec2 %04.4X\n", regno);
+#ifdef MOVEC_DEBUG
+    write_log("movec2 %04.4X PC=%x\n", regno, M68K_GETPC);
+#endif
     if (movec_illg (regno)) {
 	op_illg (0x4E7A, &regs);
 	return 0;
@@ -1215,14 +1242,16 @@ int m68k_movec2 (int regno, uae_u32 *regp)
 	case 0x805: *regp = mmusr; break;
 	case 0x806: *regp = urp; break;
 	case 0x807: *regp = srp; break;
-	case 0x808: *regp = 0x04300100 | pcr; break;
+	case 0x808: *regp = MC68060_PCR | regs.pcr; break;
 
 	default:
 	    op_illg (0x4E7A, &regs);
 	    return 0;
 	}
     }
-    //write_log("-> %08.8X\n", *regp);
+#ifdef MOVEC_DEBUG
+    write_log("-> %08.8X\n", *regp);
+#endif
     return 1;
 }
 
@@ -1517,6 +1546,15 @@ void m68k_reset (void)
     regs.fp_result=1;
     regs.irc = 0xffff;
 #endif
+    caar = cacr = 0;
+    itt0 = itt1 = dtt0 = dtt1 = 0;
+    tc = mmusr = urp = srp = buscr = 0;
+    /* 68060 FPU is not compatible with 68040,
+     * 68060 accelerators' boot ROM disables the FPU
+     */
+    if (currprefs.cpu_model == 68060)
+	regs.pcr |= 2;
+
     fill_prefetch_slow (&regs);
 }
 
@@ -1600,18 +1638,48 @@ unsigned long REGPARAM2 op_illg (uae_u32 opcode, struct regstruct *regs)
 }
 
 #ifdef CPUEMU_0
+void mmu_op30(uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
+{
+    if (currprefs.cpu_model != 68030) {
+	m68k_setpc (regs, m68k_getpc (regs) - 2);
+	op_illg (opcode, regs);
+	return;
+    }
+    write_log("MMU030: %04.4x\n", opcode);
+    return;
+}
 
 void mmu_op(uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
 {
+#ifdef MOVEC_DEBUG
+    write_log("mmu_op %04.4x\n", opcode);
+#endif
     if ((opcode & 0xFE0) == 0x0500) {
 	/* PFLUSH */
 	mmusr = 0;
 	//write_log ("PFLUSH @$%lx\n", m68k_getpc());
+	return;
     } else if ((opcode & 0x0FD8) == 0x548) {
-	/* PTEST */
-	//write_log ("PTEST @$%lx\n", m68k_getpc());
-    } else
-	op_illg (opcode, regs);
+	if (currprefs.cpu_model < 68060) { /* PTEST not in 68060 */
+	    /* PTEST */
+	    //write_log ("PTEST @$%lx\n", m68k_getpc());
+	    return;
+	}
+    } else if ((opcode & 0x0FB8) == 0x588) {
+	/* PLPA */
+	if (currprefs.cpu_model == 68060) {
+	    write_log("PLPA\n");
+	    return;
+	}
+    } else if (opcode == 0xff00 && extra == 0x01c0) {
+	/* LPSTOP */
+	if (currprefs.cpu_model == 68060) {
+	    write_log("LPSTOP\n");
+	    return;
+	}
+    }
+    m68k_setpc (regs, m68k_getpc (regs) - 2);
+    op_illg (opcode, regs);
 }
 
 #endif
@@ -1620,7 +1688,7 @@ static uaecptr last_trace_ad = 0;
 
 static void do_trace (void)
 {
-    if (regs.t0 && currprefs.cpu_level >= 2) {
+    if (regs.t0 && currprefs.cpu_model >= 68020) {
 	uae_u16 opcode;
 	/* should also include TRAP, CHK, SR modification FPcc */
 	/* probably never used so why bother */
@@ -1864,7 +1932,7 @@ static void out_cd32io (uae_u32 pc)
 
 #endif
 
-#ifndef CPUEMU_5
+#ifndef CPUEMU_11
 
 static void m68k_run_1 (void)
 {
@@ -1907,14 +1975,14 @@ static void m68k_run_1 (void)
 	    if (do_specialties (cpu_cycles, r))
 		return;
 	}
-	if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_level == 0))
+	if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_model == 68000))
 	    return;
     }
 }
 
-#endif /* CPUEMU_5 */
+#endif /* CPUEMU_11 */
 
-#ifndef CPUEMU_6
+#ifndef CPUEMU_12
 
 static void m68k_run_1_ce (void)
 {
@@ -1936,7 +2004,7 @@ static void m68k_run_1_ce (void)
 	    if (do_specialties (0, r))
 		return;
 	}
-	if (!currprefs.cpu_cycle_exact || currprefs.cpu_level > 0)
+	if (!currprefs.cpu_cycle_exact || currprefs.cpu_model > 68000)
 	    return;
     }
 }
@@ -2219,16 +2287,16 @@ void m68k_go (int may_quit)
 	}
 #endif
 #ifndef JIT
-	run_func = currprefs.cpu_level == 0 && currprefs.cpu_cycle_exact ? m68k_run_1_ce :
-		    currprefs.cpu_level == 0 && currprefs.cpu_compatible ? m68k_run_1 :
+	run_func = currprefs.cpu_model == 68000 && currprefs.cpu_cycle_exact ? m68k_run_1_ce :
+		    currprefs.cpu_model == 68000 && currprefs.cpu_compatible ? m68k_run_1 :
 		    currprefs.cpu_compatible ? m68k_run_2p : m68k_run_2;
 #else
 	if (mmu_enabled && !currprefs.cachesize) {
 	    run_func = m68k_run_mmu;
 	} else {
-	    run_func = currprefs.cpu_cycle_exact && currprefs.cpu_level == 0 ? m68k_run_1_ce :
-		   currprefs.cpu_compatible > 0 && currprefs.cpu_level == 0 ? m68k_run_1 :
-		   currprefs.cpu_level >= 2 && currprefs.cachesize ? m68k_run_2a :
+	    run_func = currprefs.cpu_cycle_exact && currprefs.cpu_model == 68000 ? m68k_run_1_ce :
+		   currprefs.cpu_compatible > 0 && currprefs.cpu_model == 68000 ? m68k_run_1 :
+		   currprefs.cpu_model >= 68020 && currprefs.cachesize ? m68k_run_2a :
 		   currprefs.cpu_compatible ? m68k_run_2p : m68k_run_2;
 	}
 #endif
@@ -2437,30 +2505,68 @@ void sm68k_disasm(char *instrname, char *instrcode, uaecptr addr, uaecptr *nextp
 	*nextpc = m68k_getpc (&regs) + m68kpc_offset;
 }
 
+static int m2cregn[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 0x800, 0x801, 0x802, 0x803, 0x804, 0x805, 0x806, 0x807, 0x808, -1 };
+static char *m2cregs[] = { "SFC ", "DFC ", "CACR", "TC  ", "ITT0", "ITT1", "DTT0", "DTT1", "BUSC",
+    "USP ", "VBR ", "CAAR", "MSP ", "ISP ", "MMUS", "URP ", "SRP ", "PCR ", 0 };
+
+static uae_u32 val_move2c (int regno)
+{
+    switch (regno) {
+    case 0: return regs.sfc;
+    case 1: return regs.dfc;
+    case 2: return cacr;
+    case 3: return tc;
+    case 4: return itt0;
+    case 5: return itt1;
+    case 6: return dtt0;
+    case 7: return dtt1;
+    case 8: return buscr;
+    case 0x800: return regs.usp;
+    case 0x801: return regs.vbr;
+    case 0x802: return caar;
+    case 0x803: return regs.msp;
+    case 0x804: return regs.isp;
+    case 0x805: return mmusr;
+    case 0x806: return urp;
+    case 0x807: return srp;
+    case 0x808: return regs.pcr | MC68060_PCR;
+    default: return 0;
+    }
+}    
+
 void m68k_dumpstate (void *f, uaecptr *nextpc)
 {
-    int i;
+    int i, j;
 
     for (i = 0; i < 8; i++){
-	f_out (f, "D%d: %08lx ", i, m68k_dreg(&regs, i));
+	f_out (f, "  D%d %08lX ", i, m68k_dreg(&regs, i));
 	if ((i & 3) == 3) f_out (f, "\n");
     }
     for (i = 0; i < 8; i++){
-	f_out (f, "A%d: %08lx ", i, m68k_areg(&regs, i));
+	f_out (f, "  A%d %08lX ", i, m68k_areg(&regs, i));
 	if ((i & 3) == 3) f_out (f, "\n");
     }
     if (regs.s == 0) regs.usp = m68k_areg(&regs, 7);
     if (regs.s && regs.m) regs.msp = m68k_areg(&regs, 7);
     if (regs.s && regs.m == 0) regs.isp = m68k_areg(&regs, 7);
-    f_out (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
-	regs.usp,regs.isp,regs.msp,regs.vbr);
+    j = 0;
+    for (i = 0; m2cregn[i] >= 0; i++) {
+	if (!movec_illg(m2cregn[i])) {
+	    if (j > 0 && (j % 4) == 0)
+		f_out(f, "\n");
+	    f_out (f, "%s %08.8X ", m2cregs[i], val_move2c(m2cregn[i]));
+	    j++;
+	}
+    }
+    if (j > 0)
+	f_out (f, "\n");
     f_out (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d STP=%d\n",
 	regs.t1, regs.t0, regs.s, regs.m,
 	GET_XFLG(&regs.ccrflags), GET_NFLG(&regs.ccrflags), GET_ZFLG(&regs.ccrflags),
 	GET_VFLG(&regs.ccrflags), GET_CFLG(&regs.ccrflags),
 	regs.intmask, regs.stopped);
 #ifdef FPUEMU
-    if (currprefs.cpu_level >= 2) {
+    if (currprefs.fpu_model) {
 	uae_u32 fpsr;
 	for (i = 0; i < 8; i++){
 	    f_out (f, "FP%d: %g ", i, regs.fp[i]);
@@ -2474,7 +2580,7 @@ void m68k_dumpstate (void *f, uaecptr *nextpc)
 		(fpsr & 0x1000000) != 0);
     }
 #endif
-    if (currprefs.cpu_compatible) {
+    if (currprefs.cpu_compatible && currprefs.cpu_model == 68000) {
 	struct instr *dp;
 	struct mnemolookup *lookup1, *lookup2;
 	dp = table68k + regs.irc;
@@ -2498,38 +2604,16 @@ void m68k_dumpstate (void *f, uaecptr *nextpc)
 
 uae_u8 *restore_cpu (uae_u8 *src)
 {
-    int i,model,flags;
+    int i, flags, model;
     uae_u32 l;
 
-    model = restore_u32();
-    switch (model) {
-    case 68000:
-	changed_prefs.cpu_level = 0;
-	break;
-    case 68010:
-	changed_prefs.cpu_level = 1;
-	break;
-    case 68020:
-	changed_prefs.cpu_level = 2;
-	break;
-    case 68040:
-	changed_prefs.cpu_level = 4;
-	break;
-    case 68060:
-	changed_prefs.cpu_level = 6;
-	break;
-    default:
-	write_log ("Unknown cpu type %d\n", model);
-	break;
-    }
-
+    changed_prefs.cpu_model = model = restore_u32();
     flags = restore_u32();
     changed_prefs.address_space_24 = 0;
     if (flags & CPUTYPE_EC)
 	changed_prefs.address_space_24 = 1;
     if (model > 68000)
 	changed_prefs.cpu_compatible = 0;
-    currprefs.cpu_level = changed_prefs.cpu_level;
     currprefs.address_space_24 = changed_prefs.address_space_24;
     currprefs.cpu_compatible = changed_prefs.cpu_compatible;
     currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
@@ -2584,7 +2668,7 @@ uae_u8 *save_cpu (int *len, uae_u8 *dstptr)
 	dstbak = dst = dstptr;
     else
 	dstbak = dst = malloc(4+4+15*4+4+4+4+4+2+4+4+4+4+4+4+4);
-    model = cpumodel[currprefs.cpu_level];
+    model = currprefs.cpu_model;
     save_u32 (model);					/* MODEL */
     save_u32 (currprefs.address_space_24 ? 1 : 0);	/* FLAGS */
     for(i = 0;i < 15; i++) save_u32 (regs.regs[i]);	/* D0-D7 A0-A6 */
diff --git a/od-win32/debug_win32.c b/od-win32/debug_win32.c
index ff42c399..d7567127 100755
--- a/od-win32/debug_win32.c
+++ b/od-win32/debug_win32.c
@@ -651,7 +651,7 @@ static LRESULT CALLBACK DebuggerProc (HWND hDlg, UINT message, WPARAM wParam, LP
                 hwnd = GetDlgItem(hDlg, IDC_DBG_PREFETCH);
                 EnableWindow(hwnd, FALSE);
             }
-            if (currprefs.cpu_level < 2) {
+            if (currprefs.cpu_model < 68020) {
                 hwnd = GetDlgItem(hDlg, IDC_DBG_FPREG);
                 EnableWindow(hwnd, FALSE);
                 hwnd = GetDlgItem(hDlg, IDC_DBG_FPSR);
diff --git a/od-win32/dxwrap.c b/od-win32/dxwrap.c
index 99691921..fc0c0ee0 100755
--- a/od-win32/dxwrap.c
+++ b/od-win32/dxwrap.c
@@ -251,7 +251,7 @@ static int LockStub( surface_type_e type )
 	break;
     }
 
-    if( lockcnt )
+    if(lockcnt)
     {
 #ifdef _DEBUG
 	DebugBreak();
@@ -259,9 +259,9 @@ static int LockStub( surface_type_e type )
 	return 1;
     }
 
-    if( type == secondary_surface && DirectDrawState.flipping != single_buffer )
+    if(type == secondary_surface && DirectDrawState.flipping != single_buffer)
     {
-	IDirectDrawSurface7_Restore( DirectDrawState.primary.surface );
+	IDirectDrawSurface7_Restore(DirectDrawState.primary.surface);
     }
 
     while (FAILED(ddrval = IDirectDrawSurface7_Lock(surface, NULL, surfacedesc, DDLOCK_SURFACEMEMORYPTR | DDLOCK_WAIT, NULL)))
diff --git a/od-win32/resources/resource b/od-win32/resources/resource
index 071d0279..d9beb8cd 100755
--- a/od-win32/resources/resource
+++ b/od-win32/resources/resource
@@ -344,7 +344,6 @@
 #define IDC_BLITIMM                     1174
 #define IDC_LORES                       1176
 #define IDC_VSYNC                       1177
-#define IDC_AFULLSCREEN                 1178
 #define IDC_LORES_SMOOTHED              1179
 #define IDC_FRAMERATE                   1185
 #define IDC_RATETEXT                    1186
@@ -359,7 +358,6 @@
 #define IDC_LM_SCANLINES                1191
 #define IDC_INPUTSPEEDM                 1191
 #define IDC_P96RAM                      1192
-#define IDC_PFULLSCREEN                 1192
 #define IDC_P96MEM                      1193
 #define IDC_DA_SLIDER                   1193
 #define IDC_FRAMERATE2                  1194
@@ -370,8 +368,9 @@
 #define IDC_CPU3                        1203
 #define IDC_CPU4                        1204
 #define IDC_CPU5                        1205
-#define IDC_CPU6                        1206
-#define IDC_SPEED                       1207
+#define IDC_FPU1                        1206
+#define IDC_FPU2                        1207
+#define IDC_FPU3                        1208
 #define IDC_CS_HOST                     1209
 #define IDC_CS_68000                    1210
 #define IDC_CS_ADJUSTABLE               1211
@@ -388,6 +387,8 @@
 #define IDC_GENLOCK                     1220
 #define IDC_COMPATIBLE_FPU              1221
 #define IDC_FASTERRTG                   1221
+#define IDC_COMPATIBLE24                1222
+#define IDC_SPEED                       1223
 #define IDC_SOUNDSETTINGS               1229
 #define IDC_8BIT                        1230
 #define IDC_16BIT                       1231
@@ -924,7 +925,7 @@
 #ifndef APSTUDIO_READONLY_SYMBOLS
 #define _APS_NO_MFC                     1
 #define _APS_3D_CONTROLS                     1
-#define _APS_NEXT_RESOURCE_VALUE        258
+#define _APS_NEXT_RESOURCE_VALUE        253
 #define _APS_NEXT_COMMAND_VALUE         40026
 #define _APS_NEXT_CONTROL_VALUE         1761
 #define _APS_NEXT_SYMED_VALUE           101
diff --git a/od-win32/resources/resource.h b/od-win32/resources/resource.h
index e5904f8a..5928a30c 100755
--- a/od-win32/resources/resource.h
+++ b/od-win32/resources/resource.h
@@ -368,8 +368,6 @@
 #define IDC_CPU3                        1203
 #define IDC_CPU4                        1204
 #define IDC_CPU5                        1205
-#define IDC_CPU6                        1206
-#define IDC_SPEED                       1207
 #define IDC_CS_HOST                     1209
 #define IDC_CS_68000                    1210
 #define IDC_CS_ADJUSTABLE               1211
@@ -386,6 +384,12 @@
 #define IDC_GENLOCK                     1220
 #define IDC_COMPATIBLE_FPU              1221
 #define IDC_FASTERRTG                   1221
+#define IDC_COMPATIBLE24                1222
+#define IDC_SPEED                       1223
+#define IDC_FPU0                        1224
+#define IDC_FPU1                        1225
+#define IDC_FPU2                        1226
+#define IDC_FPU3                        1227
 #define IDC_SOUNDSETTINGS               1229
 #define IDC_8BIT                        1230
 #define IDC_16BIT                       1231
diff --git a/od-win32/resources/winuae.rc b/od-win32/resources/winuae.rc
index 7907697e..04fe1211 100755
--- a/od-win32/resources/winuae.rc
+++ b/od-win32/resources/winuae.rc
@@ -8,7 +8,6 @@
 // Generated from the TEXTINCLUDE 2 resource.
 //
 #include "afxres.h"
-
 /////////////////////////////////////////////////////////////////////////////
 #undef APSTUDIO_READONLY_SYMBOLS
 
@@ -143,22 +142,21 @@ BEGIN
     EDITTEXT        IDC_MBRAM2,243,142,30,12,ES_CENTER | ES_READONLY
 END
 
-IDD_CPU DIALOGEX 0, 0, 300, 192
+IDD_CPU DIALOGEX 0, 0, 300, 226
 STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD
 FONT 8, "MS Sans Serif", 0, 0, 0x0
 BEGIN
-    GROUPBOX        "CPU",IDC_STATIC,5,3,81,148,BS_LEFT
-    CONTROL         "68000",IDC_CPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,10,16,63,10
-    CONTROL         "68010",IDC_CPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,31,65,10
-    CONTROL         "68EC020",IDC_CPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,46,65,10
-    CONTROL         "68EC020 + FPU",IDC_CPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,61,68,10
-    CONTROL         "68020",IDC_CPU4,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,76,63,10
-    CONTROL         "68020 + FPU",IDC_CPU5,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,91,64,10
-    CONTROL         "68040",IDC_CPU6,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,106,66,10
+    GROUPBOX        "CPU",IDC_STATIC,5,3,81,139,BS_LEFT
+    CONTROL         "68000",IDC_CPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,13,16,63,10
+    CONTROL         "68010",IDC_CPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,30,65,10
+    CONTROL         "68020",IDC_CPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,44,63,10
+    CONTROL         "68030",IDC_CPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,58,64,10
+    CONTROL         "68040",IDC_CPU4,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,72,66,10
+    CONTROL         "68060",IDC_CPU5,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,85,66,10
     CONTROL         "More compatible [] Emulate 68000's prefetch registers. More compatible but slower.",IDC_COMPATIBLE,
-                    "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,10,124,73,8
+                    "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,10,114,73,8
     CONTROL         "JIT [] Enable just-in-time CPU emulator. Significantly increases the speed of the CPU emulation. Requires 68020 or 68040 CPU.",IDC_JITENABLE,
-                    "Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,137,73,10
+                    "Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,127,73,10
     GROUPBOX        "CPU Emulation Speed",IDC_STATIC,90,3,205,90
     CONTROL         "Fastest possible, but maintain chipset timing",IDC_CS_HOST,
                     "Button",BS_AUTORADIOBUTTON | BS_LEFT | WS_GROUP | WS_TABSTOP,95,18,195,10
@@ -183,8 +181,13 @@ BEGIN
     CONTROL         "Indirect",IDC_TRUST1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,230,155,45,10
     CONTROL         "After RTG",IDC_TRUST2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,230,168,59,10
     CONTROL         "More compatible [] More compatible but slower FPU emulation.",IDC_COMPATIBLE_FPU,
-                    "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,9,169,73,10
-    GROUPBOX        "FPU",IDC_STATIC,6,155,81,32,BS_LEFT
+                    "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,9,206,73,10
+    GROUPBOX        "FPU",IDC_STATIC,6,144,81,76,BS_LEFT
+    CONTROL         "24-bit addressing",IDC_COMPATIBLE24,"Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,10,100,73,8
+    CONTROL         "None",IDC_FPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,14,154,63,10
+    CONTROL         "68881",IDC_FPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,14,166,63,10
+    CONTROL         "68882",IDC_FPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,14,179,63,10
+    CONTROL         "CPU internal",IDC_FPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,14,192,63,10
 END
 
 IDD_FLOPPY DIALOGEX 0, 0, 300, 240
@@ -817,8 +820,8 @@ FONT 8, "Courier New", 0, 0, 0x0
 BEGIN
     EDITTEXT        IDC_DBG_OUTPUT1,1,79,370,205,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
     EDITTEXT        IDC_DBG_OUTPUT2,1,79,370,205,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
-    LISTBOX         IDC_DBG_MEM,1,92,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
-    LISTBOX         IDC_DBG_DASM,1,92,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+    LISTBOX         IDC_DBG_MEM,1,92,370,192,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+    LISTBOX         IDC_DBG_DASM,1,92,370,192,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
     EDITTEXT        IDC_DBG_MEMINPUT,1,79,36,12,ES_AUTOHSCROLL | ES_WANTRETURN
     EDITTEXT        IDC_DBG_INPUT,1,285,354,12,ES_AUTOHSCROLL | ES_WANTRETURN
     PUSHBUTTON      "?",IDC_DBG_HELP,356,285,15,12,NOT WS_TABSTOP
@@ -1268,12 +1271,16 @@ BEGIN
     "resource.\0"
 END
 
-
 3 TEXTINCLUDE 
 BEGIN
     "\r\0"
 END
 
+2 TEXTINCLUDE 
+BEGIN
+    "#include ""afxres.h""\r\0"
+END
+
 #endif    // APSTUDIO_INVOKED
 
 #endif    // Finnish resources
@@ -1287,7 +1294,6 @@ END
 // Generated from the TEXTINCLUDE 3 resource.
 //
 
-
 /////////////////////////////////////////////////////////////////////////////
 #endif    // not APSTUDIO_INVOKED
 
diff --git a/od-win32/sysconfig.h b/od-win32/sysconfig.h
index f992b3ef..3b273f33 100755
--- a/od-win32/sysconfig.h
+++ b/od-win32/sysconfig.h
@@ -37,8 +37,8 @@
 #define UAESERIAL /* uaeserial.device emulation */
 #define FPUEMU /* FPU emulation */
 #define CPUEMU_0 /* generic 680x0 emulation */
-#define CPUEMU_5 /* 68000+prefetch emulation */
-#define CPUEMU_6 /* cycle-exact cpu&blitter */
+#define CPUEMU_11 /* 68000+prefetch emulation */
+#define CPUEMU_12 /* cycle-exact cpu&blitter */
 #define ACTION_REPLAY /* Action Replay 1/2/3 support */
 #define PICASSO96 /* Picasso96 display card emulation */
 #define BSDSOCKET /* bsdsocket.library emulation */
@@ -64,8 +64,8 @@
 #define OPENGL
 #endif
 #define CAPS
-#define CPUEMU_6
-#define CPUEMU_5
+#define CPUEMU_12
+#define CPUEMU_11
 
 
 #endif
diff --git a/od-win32/win32.h b/od-win32/win32.h
index df1ce7f6..c5a8b316 100755
--- a/od-win32/win32.h
+++ b/od-win32/win32.h
@@ -15,9 +15,9 @@
 #define GETBDM(x) (((x) - ((x / 10000) * 10000)) / 100)
 #define GETBDD(x) ((x) % 100)
 
-#define WINUAEBETA 1
+#define WINUAEBETA 2
 #define WINUAEPUBLICBETA 1
-#define WINUAEDATE MAKEBD(2007, 3, 28)
+#define WINUAEDATE MAKEBD(2007, 3, 30)
 
 #define IHF_WINDOWHIDDEN 6
 #define NORMAL_WINDOW_STYLE (WS_VISIBLE | WS_BORDER | WS_CAPTION | WS_MINIMIZEBOX | WS_SYSMENU)
diff --git a/od-win32/win32_scale2x.c b/od-win32/win32_scale2x.c
index cc3238ea..f752c63f 100755
--- a/od-win32/win32_scale2x.c
+++ b/od-win32/win32_scale2x.c
@@ -57,11 +57,13 @@ void S2X_free (void)
 
 void S2X_init (int dw, int dh, int aw, int ah, int mult, int ad, int dd)
 {
-    int flags;
+    int flags = 0;
     HRESULT ddrval;
 
-    flags = usedfilter->x[mult];
-    if (mult) {
+    if (!currprefs.gfx_filter || !usedfilter) {
+	usedfilter = &uaefilters[0];
+	mult = 1;
+    } else if (mult) {
 	if ((ad == 16 && !(flags & UAE_FILTER_MODE_16)) || (ad == 32 && !(flags & UAE_FILTER_MODE_32))) {
 	    usedfilter = &uaefilters[0];
 	    mult = 1;
@@ -108,12 +110,12 @@ void S2X_render (void)
     sptr = gfxvidinfo.bufmem;
     endsptr = gfxvidinfo.realbufmem + (amiga_height - 1) * 3 * gfxvidinfo.rowbytes;
 
-    v = currprefs.gfx_filter_horiz_offset;
+    v = currprefs.gfx_filter ? currprefs.gfx_filter_horiz_offset : 0;
     v += (dst_width / scale - amiga_width) / 8;
     sptr += (int)(-v * 4.0 / 10.0) * (amiga_depth / 8);
     aw -= (int)(-v * 4.0 / 10);
 
-    v = currprefs.gfx_filter_vert_offset;
+    v = currprefs.gfx_filter ? currprefs.gfx_filter_vert_offset : 0;
     v += (dst_height / scale - amiga_height) / 8;
     sptr += (int)(-v * 4.0 / 10.0) * gfxvidinfo.rowbytes;
     ah -= (int)(-v * 4.0 / 10);
@@ -128,9 +130,9 @@ void S2X_render (void)
     if (aw < 16)
 	return;
 
-    if (currprefs.gfx_filter_horiz_zoom || currprefs.gfx_filter_vert_zoom ||
+    if (currprefs.gfx_filter && (currprefs.gfx_filter_horiz_zoom || currprefs.gfx_filter_vert_zoom ||
 	    currprefs.gfx_filter_horiz_zoom_mult != 1000 ||
-	    currprefs.gfx_filter_vert_zoom_mult != 1000) {
+	    currprefs.gfx_filter_vert_zoom_mult != 1000)) {
 	int wz = dst_width * currprefs.gfx_filter_horiz_zoom_mult / 1000;
 	int hz = dst_height * currprefs.gfx_filter_vert_zoom_mult / 1000;
 	wz += currprefs.gfx_filter_horiz_zoom / 4;
@@ -272,7 +274,7 @@ void S2X_render (void)
 
     }
 
-    if (ok == 0) {
+    if (ok == 0 && currprefs.gfx_filter) {
         usedfilter = &uaefilters[0];
         changed_prefs.gfx_filter = usedfilter->type;
     }
diff --git a/od-win32/win32gfx.c b/od-win32/win32gfx.c
index 3652e71a..5ce5bcd8 100755
--- a/od-win32/win32gfx.c
+++ b/od-win32/win32gfx.c
@@ -2032,6 +2032,8 @@ static void updatemodes (void)
 	currentmode->flags |= DM_SWSCALE;
 	if (currentmode->current_depth < 15)
 	    currentmode->current_depth = 16;
+    } else if (!usedfilter && currentmode->current_depth >= 15) {
+	;//currentmode->flags |= DM_SWSCALE;
     }
 #endif
 }
diff --git a/od-win32/win32gui.c b/od-win32/win32gui.c
index f46fdc6a..9375447a 100755
--- a/od-win32/win32gui.c
+++ b/od-win32/win32gui.c
@@ -3319,7 +3319,8 @@ static INT_PTR CALLBACK QuickstartDlgProc (HWND hDlg, UINT msg, WPARAM wParam, L
 	    case IDC_DF1WPQ:
 	    case IDC_EJECT1Q:
 	    case IDC_DF1QQ:
-	    ret = FloppyDlgProc (hDlg, msg, wParam, lParam);
+	    if (currentpage == QUICKSTART_ID)
+		ret = FloppyDlgProc (hDlg, msg, wParam, lParam);
 	    break;
 	    case IDC_QUICKSTART_SETCONFIG:
 	    load_quickstart (hDlg, 1);
@@ -3443,7 +3444,7 @@ static void enable_for_chipsetdlg (HWND hDlg)
 {
     int enable = workprefs.cpu_cycle_exact ? FALSE : TRUE;
 
-#if !defined (CPUEMU_6)
+#if !defined (CPUEMU_12)
     ew (hDlg, IDC_CYCLEEXACT, FALSE);
 #endif
     ew (hDlg, IDC_FASTCOPPER, enable);
@@ -4048,7 +4049,7 @@ static void values_from_chipsetdlg (HWND hDlg, UINT msg, WPARAM wParam, LPARAM l
     if (workprefs.cpu_cycle_exact != n) {
 	workprefs.cpu_cycle_exact = workprefs.blitter_cycle_exact = n;
 	if (n) {
-	    if (workprefs.cpu_level == 0) {
+	    if (workprefs.cpu_model == 68000) {
 		workprefs.cpu_compatible = 1;
 		workprefs.m68k_speed = 0;
 	    }
@@ -5104,21 +5105,24 @@ static INT_PTR CALLBACK MiscDlgProc2 (HWND hDlg, UINT msg, WPARAM wParam, LPARAM
     return MiscDlgProc (hDlg, msg, wParam, lParam);
 }
 
-static int cpu_ids[]   = { IDC_CPU0, IDC_CPU0, IDC_CPU1, IDC_CPU1, IDC_CPU2, IDC_CPU4, IDC_CPU3, IDC_CPU5, IDC_CPU6, IDC_CPU6 };
+static int cpu_ids[]   = { IDC_CPU0, IDC_CPU1, IDC_CPU2, IDC_CPU3, IDC_CPU4, IDC_CPU5 };
+static int fpu_ids[]   = { IDC_FPU0, IDC_FPU1, IDC_FPU2, IDC_FPU3 };
 static int trust_ids[] = { IDC_TRUST0, IDC_TRUST1, IDC_TRUST1, IDC_TRUST2 };
 
 static void enable_for_cpudlg (HWND hDlg)
 {
     BOOL enable = FALSE, enable2 = FALSE;
     BOOL cpu_based_enable = FALSE;
+    BOOL fpu;
 
     /* These four items only get enabled when adjustable CPU style is enabled */
     ew (hDlg, IDC_SPEED, workprefs.m68k_speed > 0);
-    ew (hDlg, IDC_CS_CPU_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_level > 0) && workprefs.m68k_speed > 0);
-    ew (hDlg, IDC_CS_CHIPSET_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_level > 0) && workprefs.m68k_speed > 0);
-    ew (hDlg, IDC_CS_HOST, !workprefs.cpu_cycle_exact || workprefs.cpu_level > 0);
-    ew (hDlg, IDC_CS_68000, !workprefs.cpu_cycle_exact || workprefs.cpu_level > 0);
-    ew (hDlg, IDC_CS_ADJUSTABLE, !workprefs.cpu_cycle_exact || workprefs.cpu_level > 0);
+    ew (hDlg, IDC_COMPATIBLE24, workprefs.cpu_model == 68020);
+    ew (hDlg, IDC_CS_CPU_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000) && workprefs.m68k_speed > 0);
+    ew (hDlg, IDC_CS_CHIPSET_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000) && workprefs.m68k_speed > 0);
+    ew (hDlg, IDC_CS_HOST, !workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000);
+    ew (hDlg, IDC_CS_68000, !workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000);
+    ew (hDlg, IDC_CS_ADJUSTABLE, !workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000);
     ew (hDlg, IDC_CPUTEXT, workprefs.m68k_speed > 0 );
     ew (hDlg, IDC_CPUIDLE, workprefs.m68k_speed != 0 ? TRUE : FALSE);
 #if !defined(CPUEMU_0) || defined(CPUEMU_68000_ONLY)
@@ -5127,10 +5131,9 @@ static void enable_for_cpudlg (HWND hDlg)
     ew (hDlg, IDC_CPU3, FALSE);
     ew (hDlg, IDC_CPU4, FALSE);
     ew (hDlg, IDC_CPU5, FALSE);
-    ew (hDlg, IDC_CPU6, FALSE);
 #endif
 
-    cpu_based_enable = workprefs.cpu_level >= 2 &&
+    cpu_based_enable = workprefs.cpu_model >= 68020 &&
 		       workprefs.address_space_24 == 0;
 
     enable = cpu_based_enable && workprefs.cachesize;
@@ -5152,22 +5155,25 @@ static void enable_for_cpudlg (HWND hDlg)
     ew (hDlg, IDC_FORCE, enable);
     ew (hDlg, IDC_JITENABLE, cpu_based_enable);
     ew (hDlg, IDC_COMPATIBLE, !workprefs.cpu_cycle_exact && !workprefs.cachesize);
-    ew (hDlg, IDC_COMPATIBLE_FPU, workprefs.cpu_level >= 3);
+    ew (hDlg, IDC_COMPATIBLE_FPU, workprefs.fpu_model > 0);
+
+    fpu = TRUE;
+    if (workprefs.cpu_model < 68020 || workprefs.cpu_model > 68030)
+	fpu = FALSE;
+    ew (hDlg, IDC_FPU1, fpu);
+    ew (hDlg, IDC_FPU2, fpu);
+    ew (hDlg, IDC_FPU3, workprefs.cpu_model >= 68040);
 
 #ifdef JIT
-    if( enable )
-    {
-	if(!canbang)
-	{
+    if(enable) {
+	if (!canbang) {
 	    workprefs.compforcesettings = TRUE;
 	    workprefs.comptrustbyte = 1;
 	    workprefs.comptrustword = 1;
 	    workprefs.comptrustlong = 1;
 	    workprefs.comptrustnaddr= 1;
 	}
-    }
-    else
-    {
+    } else {
 	workprefs.cachesize = 0; // Disable JIT
     }
 #endif
@@ -5178,13 +5184,19 @@ static void values_to_cpudlg (HWND hDlg)
     char cache[8] = "";
     BOOL enable = FALSE;
     BOOL cpu_based_enable = FALSE;
+    int cpu;
 
     SendDlgItemMessage (hDlg, IDC_SPEED, TBM_SETPOS, TRUE, workprefs.m68k_speed <= 0 ? 1 : workprefs.m68k_speed / CYCLE_UNIT );
     SetDlgItemInt( hDlg, IDC_CPUTEXT, workprefs.m68k_speed <= 0 ? 1 : workprefs.m68k_speed / CYCLE_UNIT, FALSE );
     CheckDlgButton (hDlg, IDC_COMPATIBLE, workprefs.cpu_compatible);
+    CheckDlgButton (hDlg, IDC_COMPATIBLE24, workprefs.address_space_24);
     CheckDlgButton (hDlg, IDC_COMPATIBLE_FPU, workprefs.fpu_strict);
     SendDlgItemMessage (hDlg, IDC_CPUIDLE, TBM_SETPOS, TRUE, workprefs.cpu_idle == 0 ? 0 : 12 - workprefs.cpu_idle / 15);
-    CheckRadioButton (hDlg, IDC_CPU0, IDC_CPU6, cpu_ids[workprefs.cpu_level * 2 + !workprefs.address_space_24]);
+    cpu = (workprefs.cpu_model - 68000) / 10;
+    if (cpu >= 5)
+	cpu--;
+    CheckRadioButton (hDlg, IDC_CPU0, IDC_CPU5, cpu_ids[cpu]);
+    CheckRadioButton (hDlg, IDC_FPU0, IDC_FPU3, fpu_ids[workprefs.fpu_model == 0 ? 0 : (workprefs.fpu_model == 68881 ? 1 : (workprefs.fpu_model == 68882 ? 2 : 3))]);
 
     if (workprefs.m68k_speed == -1)
 	CheckRadioButton(hDlg, IDC_CS_HOST, IDC_CS_ADJUSTABLE, IDC_CS_HOST);
@@ -5193,13 +5205,13 @@ static void values_to_cpudlg (HWND hDlg)
     else
 	CheckRadioButton(hDlg, IDC_CS_HOST, IDC_CS_ADJUSTABLE, IDC_CS_ADJUSTABLE);
 
-    cpu_based_enable = (workprefs.cpu_level >= 2) && (workprefs.address_space_24 == 0);
+    cpu_based_enable = (workprefs.cpu_model >= 68020) && (workprefs.address_space_24 == 0);
 
     enable = cpu_based_enable && workprefs.cachesize;
 
 #ifdef JIT
     if(enable) {
-	if(!canbang) {
+	if (!canbang) {
 	    workprefs.compforcesettings = TRUE;
 	    workprefs.comptrustbyte = 1;
 	    workprefs.comptrustword = 1;
@@ -5236,53 +5248,68 @@ static void values_to_cpudlg (HWND hDlg)
 
 static void values_from_cpudlg (HWND hDlg)
 {
-    int newcpu, newtrust, oldcache, jitena;
+    int newcpu, newfpu, newtrust, oldcache, jitena;
     static int cachesize_prev;
     
     workprefs.cpu_compatible = workprefs.cpu_cycle_exact | (IsDlgButtonChecked (hDlg, IDC_COMPATIBLE) ? 1 : 0);
     workprefs.fpu_strict = IsDlgButtonChecked (hDlg, IDC_COMPATIBLE_FPU) ? 1 : 0;
+    workprefs.address_space_24 = IsDlgButtonChecked (hDlg, IDC_COMPATIBLE24) ? 1 : 0;
     workprefs.m68k_speed = IsDlgButtonChecked (hDlg, IDC_CS_HOST) ? -1
 	: IsDlgButtonChecked (hDlg, IDC_CS_68000) ? 0
 	: SendMessage (GetDlgItem (hDlg, IDC_SPEED), TBM_GETPOS, 0, 0) * CYCLE_UNIT;
     
-    newcpu = (IsDlgButtonChecked (hDlg, IDC_CPU0) ? 0
-	: IsDlgButtonChecked (hDlg, IDC_CPU1) ? 1
-	: IsDlgButtonChecked (hDlg, IDC_CPU2) ? 2
-	: IsDlgButtonChecked (hDlg, IDC_CPU3) ? 3
-	: IsDlgButtonChecked (hDlg, IDC_CPU4) ? 4
-	: IsDlgButtonChecked (hDlg, IDC_CPU5) ? 5 : 6);
+    newcpu = IsDlgButtonChecked (hDlg, IDC_CPU0) ? 68000
+	: IsDlgButtonChecked (hDlg, IDC_CPU1) ? 68010
+	: IsDlgButtonChecked (hDlg, IDC_CPU2) ? 68020
+	: IsDlgButtonChecked (hDlg, IDC_CPU3) ? 68030
+	: IsDlgButtonChecked (hDlg, IDC_CPU4) ? 68040
+	: IsDlgButtonChecked (hDlg, IDC_CPU5) ? 68060 : 0;
+    newfpu = IsDlgButtonChecked (hDlg, IDC_FPU0) ? 0
+	: IsDlgButtonChecked (hDlg, IDC_FPU1) ? 1
+	: IsDlgButtonChecked (hDlg, IDC_FPU2) ? 2
+	: IsDlgButtonChecked (hDlg, IDC_FPU3) ? 3 : 0;
+
     /* When switching away from 68000, disable 24 bit addressing.  */
-    switch( newcpu )
+    workprefs.cpu_model = newcpu;
+    switch(newcpu)
     {
-	case 0: // 68000
-	case 1: // 68010
-	case 2: // 68EC020
-	case 3: // 68EC020+FPU
+	case 68000:
+	case 68010:
+	    workprefs.fpu_model = 0;
 	    workprefs.address_space_24 = 1;
-	    workprefs.cpu_level = newcpu;
 	    if (newcpu == 0 && workprefs.cpu_cycle_exact)
 		workprefs.m68k_speed = 0;
 	break;
-
-	case 4: // 68020
-	case 5: // 68020+FPU
-	case 6: // 68040
+	case 68020:
+	    workprefs.fpu_model = newfpu == 0 ? 0 : (newfpu == 2 ? 68882 : 68881);
+	break;
+	case 68030:
+	    workprefs.address_space_24 = 0;
+	    workprefs.fpu_model = newfpu == 0 ? 0 : (newfpu == 2 ? 68882 : 68881);
+	break;
+	case 68040:
+	    workprefs.fpu_model = newfpu ? 68040 : 0;
+	    workprefs.address_space_24 = 0;
+	    if (workprefs.fpu_model)
+		workprefs.fpu_model = 68040;
+	break;
+	case 68060:
+	    workprefs.fpu_model = newfpu ? 68060 : 0;
 	    workprefs.address_space_24 = 0;
-	    workprefs.cpu_level = newcpu - 2;
 	break;
     }
-    newtrust = (IsDlgButtonChecked( hDlg, IDC_TRUST0 ) ? 0
-	: IsDlgButtonChecked( hDlg, IDC_TRUST1 ) ? 1 : 3 );
+    newtrust = (IsDlgButtonChecked(hDlg, IDC_TRUST0) ? 0
+	: IsDlgButtonChecked(hDlg, IDC_TRUST1) ? 1 : 3);
     workprefs.comptrustbyte = newtrust;
     workprefs.comptrustword = newtrust;
     workprefs.comptrustlong = newtrust;
     workprefs.comptrustnaddr= newtrust;
 
-    workprefs.compforcesettings = IsDlgButtonChecked( hDlg, IDC_FORCE );
-    workprefs.compnf            = IsDlgButtonChecked( hDlg, IDC_NOFLAGS );
-    workprefs.compfpu           = IsDlgButtonChecked( hDlg, IDC_JITFPU );
-    workprefs.comp_hardflush    = IsDlgButtonChecked( hDlg, IDC_HARDFLUSH );
-    workprefs.comp_constjump    = IsDlgButtonChecked( hDlg, IDC_CONSTJUMP );
+    workprefs.compforcesettings = IsDlgButtonChecked(hDlg, IDC_FORCE);
+    workprefs.compnf            = IsDlgButtonChecked(hDlg, IDC_NOFLAGS);
+    workprefs.compfpu           = IsDlgButtonChecked(hDlg, IDC_JITFPU);
+    workprefs.comp_hardflush    = IsDlgButtonChecked(hDlg, IDC_HARDFLUSH);
+    workprefs.comp_constjump    = IsDlgButtonChecked(hDlg, IDC_CONSTJUMP);
 
 #ifdef JIT
     oldcache = workprefs.cachesize;
@@ -5305,7 +5332,6 @@ static void values_from_cpudlg (HWND hDlg)
 
     if (workprefs.cachesize > 0)
 	workprefs.cpu_compatible = 0;
-
     if (pages[KICKSTART_ID])
 	SendMessage(pages[KICKSTART_ID], WM_USER, 0, 0 );
     if (pages[DISPLAY_ID])
@@ -6606,39 +6632,35 @@ static void getfloppytype (HWND hDlg, int n)
 static int getfloppybox (HWND hDlg, int f_text, char *out, int maxlen)
 {
     LRESULT val;
+    char *p1, *p2, *p;
+    char *tmp;
+    int i;
 
     out[0] = 0;
     val = SendDlgItemMessage (hDlg, f_text, CB_GETCURSEL, 0, 0L);
-    if (val == CB_ERR) {
-	char *p1, *p2;
-        char *tmp;
-	SendDlgItemMessage (hDlg, f_text, WM_GETTEXT, (WPARAM)maxlen, (LPARAM)out);
-	tmp = xmalloc (maxlen + 1);
-        strcpy (tmp, out);
-	p1 = strstr(tmp, " { ");
-	p2 = strstr(tmp, " }");
-	if (p1 && p2 && p2 > p1) {
-	    *p1 = 0;
-	    memset (out, 0, maxlen);
-	    memcpy (out, p1 + 3, p2 - p1 - 3);
-	    strcat (out, tmp);
-	}
-	xfree (tmp);
-    } else {
-	char *p = DISK_history_get (val);
-#if 0
+    if (val != CB_ERR)
 	val = SendDlgItemMessage (hDlg, f_text, CB_GETLBTEXT, (WPARAM)val, (LPARAM)out);
-	if (val != CB_ERR && val > 0) {
-#endif
-	if (p) {
-	    strcpy (out, p);
-	    if (out[0]) {
-		/* add to top of list */
-		DISK_history_add (out, -1);
-	    }
-	} else {
-	    out[0] = 0;
+    else
+	SendDlgItemMessage (hDlg, f_text, WM_GETTEXT, (WPARAM)maxlen, (LPARAM)out);
+
+    tmp = xmalloc (maxlen + 1);
+    strcpy (tmp, out);
+    p1 = strstr(tmp, " { ");
+    p2 = strstr(tmp, " }");
+    if (p1 && p2 && p2 > p1) {
+        *p1 = 0;
+        memset (out, 0, maxlen);
+        memcpy (out, p1 + 3, p2 - p1 - 3);
+        strcat (out, tmp);
+    }
+    xfree (tmp);
+    i = 0;
+    while ((p = DISK_history_get(i))) {
+	if (!strcmp(p, out)) {
+	    DISK_history_add (out, -1);
+	    break;
 	}
+	i++;
     }
     return out[0] ? 1 : 0;
 }
@@ -6760,7 +6782,7 @@ static INT_PTR CALLBACK FloppyDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LPARA
 		case IDC_DF1TEXTQ:
 		getfloppyname (hDlg, 1);
 		addfloppytype (hDlg, 1);
-	        addfloppyhistory (hDlg);
+	        //addfloppyhistory (hDlg);
 		break;
 		case IDC_DF2TEXT:
 		getfloppyname (hDlg, 2);
diff --git a/od-win32/winuae_msvc/winuae_msvc.vcproj b/od-win32/winuae_msvc/winuae_msvc.vcproj
index 63925ee3..3da64215 100755
--- a/od-win32/winuae_msvc/winuae_msvc.vcproj
+++ b/od-win32/winuae_msvc/winuae_msvc.vcproj
@@ -1636,11 +1636,11 @@
 				>
 			</File>
 			<File
-				RelativePath="..\..\cpuemu_5.c"
+				RelativePath="..\..\cpuemu_11.c"
 				>
 			</File>
 			<File
-				RelativePath="..\..\cpuemu_6.c"
+				RelativePath="..\..\cpuemu_12.c"
 				>
 			</File>
 			<File
diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt
index a11697e9..73a53f81 100755
--- a/od-win32/winuaechangelog.txt
+++ b/od-win32/winuaechangelog.txt
@@ -1,5 +1,41 @@
 
+Beta 2:
+
+- 10x+ performance increase during "decrunching" color effects when
+  no filters enabled and bitplanes disabled (background color only)
+- console debugger breakpoints sometimes continued immediately
+- quickstart "random" selection inside archives should be fixed
+- mousehack interrupt do not start multiple times anymore
+- all CPU-specific special registers added to debugger
+- CPU/FPU configuration rewrite.
+  - new FPU options: none/68881/68882/CPU internal
+  - 68030 (EC-version, 030-only MMU instructions are simply ignored)
+  - proper 68060 with FPU support. See NOTEs below!
+  - 68040/68060 without FPU allowed but note that 68060.library does
+  not appear to like non-FPU 68060s..
+  - no FPU+68000/68010 (technically possible but not worth the trouble)
+
+  68060 NOTES: No working Setpatch and 68060.library = NO FPU.
+  68060 has FPU disable bit that all real 68060 accelerators' boot ROM
+  set because KS task switching routine do not understand 68060's
+  FRESTORE/FSAVE frames. Setpatch+68060.library is the fix.
+
+  Real 68060 is also extremely slow without 68060.library because all
+  caches and other speed-up features are not enabled but this is
+  completely irrelevant in emulation.
+
+  You can use "C:CPU" command to check CPU/FPU status:
+  - Incorrect: "System: 68060 (INST: blahblah"
+  - Correct: "System 68060 68882 (INST: blahblah"
+  New setpatch (44.38 confirmed) support 68060.library directly, older
+  versions need dummy 68040.library (less than 1K in size)
+ 
+  NOTE2: FPU emulation emulates all 6888x instructions, even those that
+  were removed from real 68040/060. 
 
+  !!! NOTE3: _EMULATED_ 68040 and 68060 HAVE EQUAL SPEED !!!
+
+  
 Beta 1:
 
 - Chip set extra config load/save missed some models (crash when
diff --git a/od-win32/writelog.c b/od-win32/writelog.c
index fd2d3460..7544057d 100755
--- a/od-win32/writelog.c
+++ b/od-win32/writelog.c
@@ -118,8 +118,11 @@ void reopen_console(void)
 	    rc.top = y;
 	    rc.right = x + w;
 	    rc.bottom = y + h;
-	    if (MonitorFromRect (&rc, MONITOR_DEFAULTTONULL) != NULL)
-	        SetWindowPos(hwnd, HWND_TOP, x, y, w, h, SWP_NOACTIVATE | SWP_DEFERERASE);
+	    if (MonitorFromRect (&rc, MONITOR_DEFAULTTONULL) != NULL) {
+		SetForegroundWindow(hwnd);
+	        SetWindowPos(hwnd, HWND_TOP, x, y, w, h, SWP_NOACTIVATE);
+
+	    }
 	}
     }
 }
@@ -174,20 +177,20 @@ int console_get (char *out, int maxlen)
     *out = 0;
     if (consoleopen > 0) {
 	return console_get_gui (out, maxlen);
-    } else {
-	DWORD len,totallen;
+    } else if (consoleopen < 0) {
+	DWORD len, totallen;
 
 	*out = 0;
-	totallen=0;
-	while(maxlen>0) {
-	    ReadConsole(stdinput,out,1,&len,0);
+	totallen = 0;
+	while(maxlen > 0) {
+	    ReadConsole(stdinput, out, 1, &len, 0);
 	    if(*out == 13)
 		break;
 	    out++;
 	    maxlen--;
 	    totallen++;
 	}
-	*out=0;
+	*out = 0;
 	return totallen;
     }
     return 0;
diff --git a/readcpu.c b/readcpu.c
index 71b20236..9bea8c0e 100755
--- a/readcpu.c
+++ b/readcpu.c
@@ -137,6 +137,7 @@ struct mnemolookup lookuptab[] = {
     { i_CPUSHA, "CPUSHA" },
     { i_MOVE16, "MOVE16" },
 
+    { i_MMUOP30, "MMUOP30" },
     { i_MMUOP, "MMUOP" },
     { i_ILLG, "" },
 };
diff --git a/table68k b/table68k
index aeed7550..ae11d986 100755
--- a/table68k
+++ b/table68k
@@ -29,10 +29,14 @@
 %
 % Fields on a line: 
 % 16 chars bitpattern : 
-% CPU level / privildge level :
+% CPU level / privilege level :
 %   CPU level 0: 68000
 %             1: 68010
 %             2: 68020
+%             3: 68030
+%             4: 68020/68030+FPU
+%             5: 68040
+%             6: 68060 (not used)
 %   privilege level 0: not privileged
 %                   1: unprivileged only on 68000 (check regs.s)
 %                   2: privileged                 (check regs.s)
@@ -232,29 +236,32 @@
 1110 1111 11ss sSSS:20:?????:?????:13: BFINS   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
 
 % floating point co processor
-1111 0010 00ss sSSS:30:?????:?????:11: FPP      #1,s
-1111 0010 01ss sSSS:30:?????:?????:11: FDBcc    #1,s[Areg-Dreg]
-1111 0010 01ss sSSS:30:?????:?????:11: FScc     #1,s[!Areg,Immd,PC8r,PC16]
-1111 0010 0111 1010:30:?????:?????:10: FTRAPcc  #1
-1111 0010 0111 1011:30:?????:?????:10: FTRAPcc  #2
-1111 0010 0111 1100:30:?????:?????:00: FTRAPcc
-1111 0010 10KK KKKK:30:?????:?????:11: FBcc     #K,#1
-1111 0010 11KK KKKK:30:?????:?????:11: FBcc     #K,#2
-1111 0011 00ss sSSS:32:?????:?????:20: FSAVE    s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
-1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
+1111 0010 00ss sSSS:40:?????:?????:11: FPP      #1,s
+1111 0010 01ss sSSS:40:?????:?????:11: FDBcc    #1,s[Areg-Dreg]
+1111 0010 01ss sSSS:40:?????:?????:11: FScc     #1,s[!Areg,Immd,PC8r,PC16]
+1111 0010 0111 1010:40:?????:?????:10: FTRAPcc  #1
+1111 0010 0111 1011:40:?????:?????:10: FTRAPcc  #2
+1111 0010 0111 1100:40:?????:?????:00: FTRAPcc
+1111 0010 10KK KKKK:40:?????:?????:11: FBcc     #K,#1
+1111 0010 11KK KKKK:40:?????:?????:11: FBcc     #K,#2
+1111 0011 00ss sSSS:42:?????:?????:20: FSAVE    s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
+1111 0011 01ss sSSS:42:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
 
-1111 0101 iiii iSSS:40:?????:?????:11: MMUOP    #i,s
+% 68030 MMU
+1111 0000 00ss sSSS:30:?????:?????:11: MMUOP30  #i,s
+% Misc MMU
+1111 0101 iiii iSSS:50:?????:?????:11: MMUOP    #i,s
 
 % 68040 instructions
-1111 0100 pp00 1rrr:42:-----:-----:02: CINVL    #p,Ar
-1111 0100 pp01 0rrr:42:-----:-----:02: CINVP    #p,Ar
-1111 0100 pp01 1rrr:42:-----:-----:00: CINVA    #p
-1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL   #p,Ar
-1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP   #p,Ar
-1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA   #p
+1111 0100 pp00 1rrr:52:-----:-----:02: CINVL    #p,Ar
+1111 0100 pp01 0rrr:52:-----:-----:02: CINVP    #p,Ar
+1111 0100 pp01 1rrr:52:-----:-----:00: CINVA    #p
+1111 0100 pp10 1rrr:52:-----:-----:02: CPUSHL   #p,Ar
+1111 0100 pp11 0rrr:52:-----:-----:02: CPUSHP   #p,Ar
+1111 0100 pp11 1rrr:52:-----:-----:00: CPUSHA   #p
 % destination register number is encoded in the following word
-1111 0110 0010 0rrr:40:-----:-----:12: MOVE16   ArP,AxP
-1111 0110 00ss sSSS:40:-----:-----:12: MOVE16   s[Dreg-Aipi],L
-1111 0110 00dd dDDD:40:-----:-----:12: MOVE16   L,d[Areg-Aipi]
-1111 0110 00ss sSSS:40:-----:-----:12: MOVE16   s[Aind],L
-1111 0110 00dd dDDD:40:-----:-----:12: MOVE16   L,d[Aipi-Aind]
+1111 0110 0010 0rrr:50:-----:-----:12: MOVE16   ArP,AxP
+1111 0110 00ss sSSS:50:-----:-----:12: MOVE16   s[Dreg-Aipi],L
+1111 0110 00dd dDDD:50:-----:-----:12: MOVE16   L,d[Areg-Aipi]
+1111 0110 00ss sSSS:50:-----:-----:12: MOVE16   s[Aind],L
+1111 0110 00dd dDDD:50:-----:-----:12: MOVE16   L,d[Aipi-Aind]