From: Toni Wilen <twilen@winuae.net>
Date: Sat, 23 Apr 2022 13:08:49 +0000 (+0300)
Subject: Small IPL test update
X-Git-Tag: 41000~253
X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=badae6a8191a0e84cafd6de9bf137bfe73cfb1ba;p=francis%2Fwinuae.git

Small IPL test update
---

diff --git a/cputest.cpp b/cputest.cpp
index e19903dd..eca0e790 100644
--- a/cputest.cpp
+++ b/cputest.cpp
@@ -373,8 +373,8 @@ static void count_interrupt_cycles(int cycles)
 		return;
 	interrupt_cycle_cnt -= cycles;
 	if (interrupt_cycle_cnt <= 0) {
-		regs.ipl_pin = 1;
-		interrupt_level = 1;
+		regs.ipl_pin = IPL_TEST_IPL_LEVEL;
+		interrupt_level = regs.ipl_pin;
 		interrupt_cycle_cnt = 0;
 	}
 }
@@ -3045,7 +3045,10 @@ static int create_ea_random(uae_u16 *opcodep, uaecptr pc, int mode, int reg, str
 						*isconstant = -1;
 				} else {
 					put_word_test(pc, imm16_cnt);
-					imm16_cnt += 0x100; // STOP hack
+					if (dp->mnemo == i_STOP && feature_interrupts > 0) {
+						// STOP hack to keep STOP test size smaller.
+						imm16_cnt += 0x0100;
+					}
 					if (imm16_cnt == 0)
 						*isconstant = 0; 
 					else
@@ -3948,6 +3951,7 @@ static void execute_ins(uaecptr endpc, uaecptr targetpc, struct instr *dp, bool
 	int cnt = 2;
 	uaecptr first_pc = regs.pc;
 	uae_u32 loop_mode_reg = 0;
+
 	if (feature_loop_mode_68010) {
 		// 68010 loop mode
 		cnt = (feature_loop_mode_cnt + 1) * 2;
diff --git a/cputest/cputest_defines.h b/cputest/cputest_defines.h
index f98548b6..5aaeb9b1 100644
--- a/cputest/cputest_defines.h
+++ b/cputest/cputest_defines.h
@@ -61,3 +61,4 @@
 #define INTERRUPT_CYCLES 64
 #define MAX_INTERRUPT_DELAY 64
 #define IPL_TRIGGER_ADDR 0xdc0000
+#define IPL_TEST_IPL_LEVEL 4
diff --git a/cputest/cputestgen.ini b/cputest/cputestgen.ini
index 9e3755d8..802919bc 100644
--- a/cputest/cputestgen.ini
+++ b/cputest/cputestgen.ini
@@ -145,6 +145,7 @@ feature_min_interrupt_mask=0
 ; 1 = interrupt request is set before test.
 ; Tests all INTREQ bits one by one. Compatible with cycle count mode.
 ; 2 = test CPU IPL sampling timing.
+; 3 = 2 + Set T1 immediately before test instruction
 ; Uses serial port to generate timing interrupt. Requires serial port TX connected to RX.
 ; Generates multiple extra tests.
 ; Used delay instruction: ROL.L D0,D0 (D0 = number of CPU clocks * 2)
@@ -240,6 +241,7 @@ enabled=1
 verbose=0
 feature_undefined_ccr=1
 feature_interrupts=2
+;feature_sr_mask=0x2100
 mode=all
 
 ; interrupt exception