From: Toni Wilen Date: Sun, 10 Aug 2014 15:50:27 +0000 (+0300) Subject: 2900b10 X-Git-Tag: 3000~88 X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=bd846da4de76ee6010ed8268f456f77b8aa5afc0;p=francis%2Fwinuae.git 2900b10 --- diff --git a/cfgfile.cpp b/cfgfile.cpp index 26b3dbba..b58346ac 100644 --- a/cfgfile.cpp +++ b/cfgfile.cpp @@ -978,6 +978,12 @@ void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type) cfgfile_dwrite_str (f, _T("a4091_rom"), p->a4091romident); if (p->a4091romident2[0]) cfgfile_dwrite_str (f, _T("a4091_2_rom"), p->a4091romident2); + cfgfile_write_rom(f, &p->path_rom, p->acceleratorromfile, _T("cpuboard_rom_file")); + if (p->acceleratorromident[0]) + cfgfile_dwrite_str(f, _T("cpuboard_rom"), p->acceleratorromident); + cfgfile_write_rom(f, &p->path_rom, p->acceleratorextromfile, _T("cpuboard_ext_rom_file")); + if (p->acceleratorextromident[0]) + cfgfile_dwrite_str(f, _T("cpuboard_ext_rom"), p->acceleratorextromident); cfgfile_write_path (f, &p->path_rom, _T("flash_file"), p->flashfile); cfgfile_write_path (f, &p->path_rom, _T("cart_file"), p->cartfile); @@ -1477,6 +1483,8 @@ void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type) cfgfile_write (f, _T("fpu_model"), _T("%d"), p->fpu_model); if (p->mmu_model) cfgfile_write (f, _T("mmu_model"), _T("%d"), p->mmu_model); + if (p->ppc_mode) + cfgfile_write_str(f, _T("ppc_model"), p->ppc_mode == 1 ? _T("automatic") : _T("manual")); cfgfile_write_bool (f, _T("cpu_compatible"), p->cpu_compatible); cfgfile_write_bool (f, _T("cpu_24bit_addressing"), p->address_space_24); /* do not reorder end */ @@ -3661,13 +3669,17 @@ static int cfgfile_parse_hardware (struct uae_prefs *p, const TCHAR *option, TCH || cfgfile_path (option, value, _T("a2091_2_rom_file"), p->a2091romfile2, sizeof p->a2091romfile2 / sizeof (TCHAR), &p->path_rom) || cfgfile_path (option, value, _T("a4091_rom_file"), p->a4091romfile, sizeof p->a4091romfile / sizeof (TCHAR), &p->path_rom) || cfgfile_path (option, value, _T("a4091_2_rom_file"), p->a4091romfile2, sizeof p->a4091romfile2 / sizeof (TCHAR), &p->path_rom) - || cfgfile_rom (option, value, _T("kickstart_rom_file_id"), p->romfile, sizeof p->romfile / sizeof (TCHAR)) + || cfgfile_path(option, value, _T("cpuboard_rom_file"), p->acceleratorromfile, sizeof p->acceleratorromfile / sizeof(TCHAR), &p->path_rom) + || cfgfile_path(option, value, _T("cpuboard_ext_rom_file"), p->acceleratorextromfile, sizeof p->acceleratorextromfile / sizeof(TCHAR), &p->path_rom) + || cfgfile_rom(option, value, _T("kickstart_rom_file_id"), p->romfile, sizeof p->romfile / sizeof(TCHAR)) || cfgfile_rom (option, value, _T("kickstart_ext_rom_file_id"), p->romextfile, sizeof p->romextfile / sizeof (TCHAR)) || cfgfile_rom (option, value, _T("a2091_rom_file_id"), p->a2091romfile, sizeof p->a2091romfile / sizeof (TCHAR)) || cfgfile_rom (option, value, _T("a2091_2_rom_file_id"), p->a2091romfile2, sizeof p->a2091romfile2 / sizeof (TCHAR)) || cfgfile_rom (option, value, _T("a4091_rom_file_id"), p->a4091romfile, sizeof p->a4091romfile / sizeof (TCHAR)) || cfgfile_rom (option, value, _T("a4091_2_rom_file_id"), p->a4091romfile2, sizeof p->a4091romfile2 / sizeof (TCHAR)) - || cfgfile_path (option, value, _T("amax_rom_file"), p->amaxromfile, sizeof p->amaxromfile / sizeof (TCHAR)) + || cfgfile_rom(option, value, _T("cpuboard_rom_file_id"), p->acceleratorromfile, sizeof p->acceleratorromfile / sizeof(TCHAR)) + || cfgfile_rom(option, value, _T("cpuboard_ext_rom_file_id"), p->acceleratorextromfile, sizeof p->acceleratorextromfile / sizeof(TCHAR)) + || cfgfile_path(option, value, _T("amax_rom_file"), p->amaxromfile, sizeof p->amaxromfile / sizeof(TCHAR)) || cfgfile_path (option, value, _T("flash_file"), p->flashfile, sizeof p->flashfile / sizeof (TCHAR), &p->path_rom) || cfgfile_path (option, value, _T("cart_file"), p->cartfile, sizeof p->cartfile / sizeof (TCHAR), &p->path_rom) || cfgfile_path (option, value, _T("rtc_file"), p->rtcfile, sizeof p->rtcfile / sizeof (TCHAR), &p->path_rom) @@ -3764,6 +3776,15 @@ static int cfgfile_parse_hardware (struct uae_prefs *p, const TCHAR *option, TCH return 1; } + if (cfgfile_string(option, value, _T("ppc_model"), tmpbuf, sizeof tmpbuf / sizeof(TCHAR))) { + p->ppc_mode = 0; + if (!_tcsicmp(tmpbuf, _T("automatic"))) + p->ppc_mode = 1; + else if (!_tcsicmp(tmpbuf, _T("manual"))) + p->ppc_mode = 2; + return 1; + } + /* old-style CPU configuration */ if (cfgfile_string (option, value, _T("cpu_type"), tmpbuf, sizeof tmpbuf / sizeof (TCHAR))) { p->fpu_model = 0; @@ -4276,7 +4297,9 @@ static int cfgfile_load_2 (struct uae_prefs *p, const TCHAR *filename, bool real subst (p->path_rom.path[0], p->a2091romfile, sizeof p->a2091romfile / sizeof (TCHAR)); subst (p->path_rom.path[0], p->a2091romfile2, sizeof p->a2091romfile2 / sizeof (TCHAR)); subst (p->path_rom.path[0], p->a4091romfile, sizeof p->a4091romfile / sizeof (TCHAR)); - subst (p->path_rom.path[0], p->a4091romfile2, sizeof p->a4091romfile2 / sizeof (TCHAR)); + subst (p->path_rom.path[0], p->a4091romfile2, sizeof p->a4091romfile2 / sizeof(TCHAR)); + subst(p->path_rom.path[0], p->acceleratorromfile, sizeof p->acceleratorromfile / sizeof(TCHAR)); + subst(p->path_rom.path[0], p->acceleratorextromfile, sizeof p->acceleratorextromfile / sizeof(TCHAR)); return 1; } @@ -5613,6 +5636,8 @@ static void buildin_default_prefs (struct uae_prefs *p) _tcscpy (p->a2091romfile2, _T("")); _tcscpy (p->a4091romfile, _T("")); _tcscpy (p->a4091romfile2, _T("")); + _tcscpy (p->acceleratorromfile, _T("")); + _tcscpy (p->acceleratorextromfile, _T("")); _tcscpy (p->flashfile, _T("")); _tcscpy (p->cartfile, _T("")); _tcscpy (p->rtcfile, _T("")); diff --git a/cpuboard.cpp b/cpuboard.cpp index f3783ea6..22ccbef4 100644 --- a/cpuboard.cpp +++ b/cpuboard.cpp @@ -33,7 +33,7 @@ #define F0_WAITSTATES (2 * CYCLE_UNIT) -// CS MK3 +// CS MK3/PPC #define CYBERSTORM_MAPROM_BASE 0xfff00000 #define CSIII_NCR 0xf40000 #define CSIII_BASE 0xf60000 @@ -92,7 +92,8 @@ #define P5_MAGIC2 0x50 #define P5_MAGIC3 0x30 #define P5_MAGIC4 0x70 -#define P5_GEN_INT2 0x01 +// when cleared, another CPU gets either stopped or can't access memory until set again. +#define P5_LOCK_CPU 0x01 /* REG_INT 0x28 */ // 0x40 always set @@ -148,16 +149,16 @@ static int csmk2_flashaddressing; static bool blizzardmaprom_bank_mapped, blizzardmaprom2_bank_mapped; static int ppc_irq_pending; -static bool ppc_int_interrupt; static void set_ppc_interrupt(int level) { if (ppc_irq_pending > level) return; #if CPUBOARD_IRQ_LOG > 0 - write_log(_T("PPC interrupt set (%d)\n"), level); + if (ppc_irq_pending != level) + write_log(_T("PPC interrupt set (%d)\n"), level); #endif - ppc_interrupt(true); + uae_ppc_interrupt(true); ppc_irq_pending = level; } static void clear_ppc_interrupt(void) @@ -167,7 +168,7 @@ static void clear_ppc_interrupt(void) #if CPUBOARD_IRQ_LOG > 0 write_log(_T("PPC interrupt clear\n")); #endif - ppc_interrupt(false); + uae_ppc_interrupt(false); ppc_irq_pending = 0; } @@ -209,7 +210,7 @@ bool ppc_interrupt(int new_m68k_ipl) if (!m68kint && iplemu && active) { if (new_m68k_ipl > ppcipl) { set_ppc_interrupt(new_m68k_ipl); - } else { + } else if (!new_m68k_ipl) { clear_ppc_interrupt(); } io_reg[CSIII_REG_IPL_EMU] &= ~P5_M68k_IPL_MASK; @@ -779,13 +780,21 @@ void cpuboard_rethink(void) static void blizzardppc_maprom(void) { - if (maprom_state) + if (cpuboard_size <= 2 * 524288) + return; + if (maprom_state) { + write_log(_T("BPPC MAP ROM On\n")); map_banks(&blizzardmaprom2_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0); - else + } else { + write_log(_T("BPPC MAP ROM Off\n")); map_banks(&blizzardmaprom_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0); + } } static void cyberstorm_maprom(void) { + if (a3000hmem_bank.allocated <= 2 * 524288) + return; + write_log(_T("CSMK3 MAP ROM On\n")); if (!(io_reg[CSIII_REG_SHADOW] & P5_SHADOW) && is_ppc()) map_banks(&blizzardmaprom2_bank, CYBERSTORM_MAPROM_BASE >> 16, 524288 >> 16, 0); else @@ -830,11 +839,10 @@ static uae_u32 REGPARAM2 blizzardio_bget(uaecptr addr) int reg = (addr & 0xff) / 8; v = io_reg[reg]; if (reg == CSIII_REG_LOCK) { - v = 0x10; + v &= 0x01; + v |= 0x10; if (is_blizzardppc()) v |= 0x08; // BPPC identification - if (!ppc_irq_pending) - v |= 0x01; } else if (reg == CSIII_REG_IRQ) { v &= 0x3f; } else if (reg == CSIII_REG_INT) { @@ -843,12 +851,12 @@ static uae_u32 REGPARAM2 blizzardio_bget(uaecptr addr) } else if (reg == CSIII_REG_SHADOW) { v |= 0x08; } -#if CPUBOARD_IO_LOG > 1 - if (reg != CSIII_REG_IRQ) +#if CPUBOARD_IO_LOG > 0 + if (reg != CSIII_REG_IRQ || CPUBOARD_IO_LOG > 2) write_log(_T("CS IO BGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC); #endif } else { -#if CPUBOARD_IO_LOG > 1 +#if CPUBOARD_IO_LOG > 0 write_log(_T("CS IO BGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC); #endif } @@ -886,7 +894,7 @@ static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v) #ifdef JIT special_mem |= S_WRITE; #endif -#if CPUBOARD_IO_LOG > 2 +#if CPUBOARD_IO_LOG > 1 write_log(_T("CS IO XBPUT %08x %02x PC=%08x\n"), addr, v & 0xff, M68K_GETPC); #endif if (is_csmk2()) { @@ -905,7 +913,7 @@ static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v) blizzard_copymaprom(); } } else if (is_csmk3() || is_blizzardppc()) { -#if CPUBOARD_IO_LOG > 1 +#if CPUBOARD_IO_LOG > 0 write_log(_T("CS IO BPUT %08x %02x PC=%08x\n"), addr, v & 0xff, M68K_GETPC); #endif uae_u32 bank = addr & 0x10000; @@ -945,18 +953,18 @@ static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v) flash_unlocked = 1; else flash_unlocked &= ~2; - if (v & P5_GEN_INT2) { - if (v & 0x80) - regval |= P5_GEN_INT2; - else - regval &= ~P5_GEN_INT2; - write_log(_T("CSIII_REG_LOCK bit 0 = %d!\n"), (v & 0x80) ? 1 : 0); - ppc_int_interrupt = (v & 0x80) ? false : true; - if (ppc_int_interrupt) { - set_ppc_interrupt(2); + if (v & P5_LOCK_CPU) { + if (v & 0x80) { + if (uae_ppc_cpu_unlock()) + regval |= P5_LOCK_CPU; } else { - clear_ppc_interrupt(); + if (!(regval & P5_LOCK_CPU)) + uae_ppc_cpu_lock(); + regval &= ~P5_LOCK_CPU; } +#if CPUBOARD_IO_LOG > 0 + write_log(_T("CSIII_REG_LOCK bit 0 = %d!\n"), (v & 0x80) ? 1 : 0); +#endif } io_reg[CSIII_REG_LOCK] = regval; } else { @@ -983,25 +991,29 @@ static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v) map_banks(&dummy_bank, 0xf00000 >> 16, 0x80000 >> 16, 0); map_banks(&blizzardio_bank, 0xf60000 >> 16, 0x10000 >> 16, 0); if (regval & P5_SCSI_RESET) { + if ((regval & P5_SCSI_RESET) != (oldval & P5_SCSI_RESET)) + write_log(_T("CS: SCSI reset cleared\n")); map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x40000 >> 16, 0); - if (is_blizzardppc()) { + if (is_blizzardppc() || flash_size(flashrom) >= 262144) { map_banks(&ncr_bank_blizzardppc, 0xf40000 >> 16, 0x10000 >> 16, 0); } else { map_banks(&ncr_bank_cyberstorm, 0xf40000 >> 16, 0x10000 >> 16, 0); map_banks(&blizzardio_bank, 0xf50000 >> 16, 0x10000 >> 16, 0); } } else { + if ((regval & P5_SCSI_RESET) != (oldval & P5_SCSI_RESET)) + write_log(_T("CS: SCSI reset\n")); map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x60000 >> 16, 0); } if (!(regval & P5_AMIGA_RESET)) { uae_reset(0, 0); - io_reg[addr] |= P5_AMIGA_RESET; write_log(_T("CS: Amiga Reset\n")); + io_reg[addr] |= P5_AMIGA_RESET; } if ((oldval & P5_PPC_RESET) && !(regval & P5_PPC_RESET)) { - ppc_stop(); + uae_ppc_cpu_stop(); } else if (!(oldval & P5_PPC_RESET) && (regval & P5_PPC_RESET)) { - ppc_reboot(); + uae_ppc_cpu_reboot(); } if ((regval & P5_M68K_RESET) && !(oldval & P5_M68K_RESET)) { m68k_reset(); @@ -1188,7 +1200,7 @@ void cpuboard_reset(bool hardreset) io_reg[CSIII_REG_RESET] = 0x7f; io_reg[CSIII_REG_IRQ] = 0x7f; io_reg[CSIII_REG_IPL_EMU] = 0x40; - io_reg[CSIII_REG_LOCK] = 0x0; + io_reg[CSIII_REG_LOCK] = 0x01; } flash_unlocked = 0; @@ -1386,9 +1398,9 @@ void cpuboard_clear(void) { } -bool is_ppc_cpu(void) +bool is_ppc_cpu(struct uae_prefs *p) { - return currprefs.cpuboard_type == BOARD_CSPPC || currprefs.cpuboard_type == BOARD_BLIZZARDPPC; + return p->cpuboard_type == BOARD_CSPPC || p->cpuboard_type == BOARD_BLIZZARDPPC; } bool cpuboard_maprom(void) @@ -1422,27 +1434,52 @@ bool cpuboard_08000000(struct uae_prefs *p) static void fixserial(uae_u8 *rom, int size) { - uae_u32 cksum; - int i; - uae_u8 type = rom[16]; - uae_u8 bclock = rom[17]; // A=60MHz,BCD=66MHz - uae_u8 newtype = 0; + uae_u8 value1 = rom[16]; + uae_u8 value2 = rom[17]; + uae_u8 value3 = rom[18]; + int seroffset = 17, longseroffset = 24; + uae_u32 serialnum = 0x1234; + char serial[10]; if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) { - if (type == 'H' || type == 'I') - return; - newtype = 'H'; + value1 = 'I'; + value2 = 'D'; + if (currprefs.cpu_model == 68060) + value3 = 'H'; + else if (currprefs.fpu_model) + value3 = 'B'; + else + value3 = 'A'; + seroffset = 19; + sprintf(serial, "%04X", serialnum); } else if (currprefs.cpuboard_type == BOARD_CSPPC) { - if (type == 'E') - return; - newtype = 'E'; + value1 = 'D'; + value2 = 'B'; + sprintf(serial, "%05X", serialnum); + value3 = 0; + seroffset = 18; } else if (currprefs.cpuboard_type == BOARD_CSMK3) { - if (type == 'F') - return; - newtype = 'F'; - } - if (!newtype) + value1 = 'F'; + sprintf(serial, "%05X", serialnum); + value2 = value3 = 0; + } else { return; + } + + rom[16] = value1; + if (value2) + rom[17] = value2; + if (value3) + rom[18] = value3; + if (rom[seroffset] == 0) { + strcpy((char*)rom + seroffset, serial); + if (longseroffset) { + rom[longseroffset + 0] = serialnum >> 24; + rom[longseroffset + 1] = serialnum >> 16; + rom[longseroffset + 2] = serialnum >> 8; + rom[longseroffset + 3] = serialnum >> 0; + } + } } static struct zfile *flashfile_open(const TCHAR *name) @@ -1450,11 +1487,19 @@ static struct zfile *flashfile_open(const TCHAR *name) struct zfile *f; TCHAR path[MAX_DPATH]; - fetch_rompath(path, sizeof path / sizeof(TCHAR)); - _tcscat(path, name); - f = zfile_fopen(path, _T("rb+"), ZFD_NONE); - if (!f) - f = zfile_fopen(path, _T("rb"), ZFD_NORMAL); + if (!name[0]) + return NULL; + f = zfile_fopen(name, _T("rb+"), ZFD_NONE); + if (!f) { + f = zfile_fopen(name, _T("rb"), ZFD_NORMAL); + if (!f) { + fetch_rompath(path, sizeof path / sizeof(TCHAR)); + _tcscat(path, name); + f = zfile_fopen(path, _T("rb+"), ZFD_NONE); + if (!f) + f = zfile_fopen(path, _T("rb"), ZFD_NORMAL); + } + } return f; } @@ -1478,7 +1523,9 @@ addrbank *cpuboard_autoconfig_init(void) struct zfile *autoconfig_rom = NULL; int roms[2], roms2[2]; bool autoconf = true; - const TCHAR *romname = NULL; + const TCHAR *defaultromname = NULL; + const TCHAR *romname = currprefs.acceleratorromfile; + bool isflashrom = false; roms[0] = -1; roms[1] = -1; @@ -1502,40 +1549,47 @@ addrbank *cpuboard_autoconfig_init(void) case BOARD_WARPENGINE_A4000: return &expamem_null; case BOARD_CSMK1: + roms[0] = 95; + isflashrom = true; + break; case BOARD_CSMK2: + roms[0] = 96; + isflashrom = true; + break; case BOARD_CSMK3: + roms[0] = 97; + isflashrom = true; + break; case BOARD_CSPPC: + roms[0] = 98; + isflashrom = true; + break; case BOARD_BLIZZARDPPC: + roms[0] = 99; + isflashrom = true; break; default: return &expamem_null; } struct romlist *rl = getromlistbyids(roms); - if (rl) { + if (!rl) + return &expamem_null; + defaultromname = rl->rd->defaultfilename; + if (rl && !isflashrom) { autoconfig_rom = read_rom(rl->rd); } - if (currprefs.cpuboard_type == BOARD_CSMK1) { - romname = _T("cyberstormmk1.rom"); - } - if (currprefs.cpuboard_type == BOARD_CSMK2) { - romname = _T("cyberstormmk2.rom"); - } - if (currprefs.cpuboard_type == BOARD_CSMK3) { - romname = _T("cyberstormmk3.rom"); - } - if (currprefs.cpuboard_type == BOARD_CSPPC) { - romname = _T("cyberstormppc.rom"); - } - if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) { - romname = _T("blizzardppc.rom"); - } - - if (romname != NULL) { + if (isflashrom) { autoconfig_rom = flashfile_open(romname); if (!autoconfig_rom) { - write_log(_T("Couldn't open CPU board rom '%s'\n"), romname); + autoconfig_rom = flashfile_open(rl->path); + if (!autoconfig_rom) + autoconfig_rom = flashfile_open(defaultromname); + } + if (!autoconfig_rom) { + romwarning(roms); + write_log(_T("Couldn't open CPU board rom '%s'\n"), defaultromname); return &expamem_null; } } @@ -1588,11 +1642,22 @@ addrbank *cpuboard_autoconfig_init(void) flashrom = flash_new(blizzardea_bank.baseaddr, earom_size, earom_size, 0x20, flashrom_file); memcpy(blizzardf0_bank.baseaddr, blizzardea_bank.baseaddr + 65536, 65536); } else if (is_csmk3() || is_blizzardppc()) { - f0rom_size = is_blizzardppc() ? 524288 : 131072; + uae_u8 flashtype; earom_size = 0; - // empty rom space must be cleared + if (is_blizzardppc()) { + flashtype = 0xa4; + f0rom_size = 524288; + } else { + flashtype = 0x20; + f0rom_size = 131072; + if (zfile_size(autoconfig_rom) >= 262144) { + flashtype = 0xa4; + f0rom_size = 524288; + } + } + // empty rom space must be cleared, not set to ones. memset(blizzardf0_bank.baseaddr, 0x00, f0rom_size); - if (is_blizzardppc()) // but empty config data must be 0xFF + if (f0rom_size == 524288) // but empty config data must be 0xFF memset(blizzardf0_bank.baseaddr + 0x50000, 0xff, 0x10000); zfile_fread(blizzardf0_bank.baseaddr, f0rom_size, 1, autoconfig_rom); autoconf = false; @@ -1601,7 +1666,7 @@ addrbank *cpuboard_autoconfig_init(void) autoconfig_rom = NULL; } fixserial(blizzardf0_bank.baseaddr, f0rom_size); - flashrom = flash_new(blizzardf0_bank.baseaddr, f0rom_size, f0rom_size, is_blizzardppc() ? 0xa4 : 0x20, flashrom_file); + flashrom = flash_new(blizzardf0_bank.baseaddr, f0rom_size, f0rom_size, flashtype, flashrom_file); } else { // 1230 MK IV / 1240/60 f0rom_size = 65536; @@ -1617,11 +1682,15 @@ addrbank *cpuboard_autoconfig_init(void) zfile_fclose(autoconfig_rom); autoconfig_rom = NULL; if (roms2[0] != -1) { - autoconfig_rom = board_rom_open(roms2, _T("blizzard_scsi_kit_iv.rom")); + defaultromname = _T("blizzard_scsi_kit_iv.rom"); + autoconfig_rom = board_rom_open(roms2, currprefs.acceleratorextromfile); + if (!autoconfig_rom) + autoconfig_rom = board_rom_open(roms2, defaultromname); if (autoconfig_rom) { memset(blizzardea_bank.baseaddr + 0x10000, 0xff, 65536); zfile_fread(blizzardea_bank.baseaddr + 0x10000, 32768, 1, autoconfig_rom); } else { + romwarning(roms2); write_log(_T("Blizzard SCSI Kit IV ROM not found\n")); } } diff --git a/cpummu30.cpp b/cpummu30.cpp index cb4ede41..6f07c85e 100644 --- a/cpummu30.cpp +++ b/cpummu30.cpp @@ -1601,7 +1601,7 @@ void mmu030_put_long_atc(uaecptr addr, uae_u32 val, int l, uae_u32 fc) { return; } - x_phys_put_long(physical_addr, val); + phys_put_long(physical_addr, val); } void mmu030_put_word_atc(uaecptr addr, uae_u16 val, int l, uae_u32 fc) { @@ -1620,7 +1620,7 @@ void mmu030_put_word_atc(uaecptr addr, uae_u16 val, int l, uae_u32 fc) { return; } - x_phys_put_word(physical_addr, val); + phys_put_word(physical_addr, val); } void mmu030_put_byte_atc(uaecptr addr, uae_u8 val, int l, uae_u32 fc) { @@ -1639,7 +1639,7 @@ void mmu030_put_byte_atc(uaecptr addr, uae_u8 val, int l, uae_u32 fc) { return; } - x_phys_put_byte(physical_addr, val); + phys_put_byte(physical_addr, val); } uae_u32 mmu030_get_long_atc(uaecptr addr, int l, uae_u32 fc) { @@ -1658,7 +1658,7 @@ uae_u32 mmu030_get_long_atc(uaecptr addr, int l, uae_u32 fc) { return 0; } - return x_phys_get_long(physical_addr); + return phys_get_long(physical_addr); } uae_u32 mmu030_get_ilong_atc(uaecptr addr, int l, uae_u32 fc) { uae_u32 page_index = addr & mmu030.translation.page.mask; @@ -1695,7 +1695,7 @@ uae_u16 mmu030_get_word_atc(uaecptr addr, int l, uae_u32 fc) { return 0; } - return x_phys_get_word(physical_addr); + return phys_get_word(physical_addr); } uae_u16 mmu030_get_iword_atc(uaecptr addr, int l, uae_u32 fc) { @@ -1733,7 +1733,7 @@ uae_u8 mmu030_get_byte_atc(uaecptr addr, int l, uae_u32 fc) { return 0; } - return x_phys_get_byte(physical_addr); + return phys_get_byte(physical_addr); } /* Generic versions of above */ @@ -1753,11 +1753,11 @@ void mmu030_put_atc_generic(uaecptr addr, uae_u32 val, int l, uae_u32 fc, int si return; } if (size == sz_byte) - x_phys_put_byte(physical_addr, val); + phys_put_byte(physical_addr, val); else if (size == sz_word) - x_phys_put_word(physical_addr, val); + phys_put_word(physical_addr, val); else - x_phys_put_long(physical_addr, val); + phys_put_long(physical_addr, val); } uae_u32 mmu030_get_atc_generic(uaecptr addr, int l, uae_u32 fc, int size, int flags, bool checkwrite) { @@ -1776,10 +1776,10 @@ uae_u32 mmu030_get_atc_generic(uaecptr addr, int l, uae_u32 fc, int size, int fl return 0; } if (size == sz_byte) - return x_phys_get_byte(physical_addr); + return phys_get_byte(physical_addr); else if (size == sz_word) - return x_phys_get_word(physical_addr); - return x_phys_get_long(physical_addr); + return phys_get_word(physical_addr); + return phys_get_long(physical_addr); } @@ -1852,7 +1852,7 @@ void mmu030_put_long(uaecptr addr, uae_u32 val, uae_u32 fc) { // addr,super,write if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,true)) || (fc==7)) { - x_phys_put_long(addr,val); + phys_put_long(addr,val); return; } @@ -1870,7 +1870,7 @@ void mmu030_put_word(uaecptr addr, uae_u16 val, uae_u32 fc) { // addr,super,write if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,true)) || (fc==7)) { - x_phys_put_word(addr,val); + phys_put_word(addr,val); return; } @@ -1888,7 +1888,7 @@ void mmu030_put_byte(uaecptr addr, uae_u8 val, uae_u32 fc) { // addr,super,write if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr, fc, true)) || (fc==7)) { - x_phys_put_byte(addr,val); + phys_put_byte(addr,val); return; } @@ -1974,7 +1974,7 @@ uae_u8 mmu030_get_byte(uaecptr addr, uae_u32 fc) { // addr,super,write if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,false)) || (fc==7)) { - return x_phys_get_byte(addr); + return phys_get_byte(addr); } int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false); @@ -1994,11 +1994,11 @@ void mmu030_put_generic(uaecptr addr, uae_u32 val, uae_u32 fc, int size, int acc // addr,super,write if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr, fc, true)) || (fc==7)) { if (size == sz_byte) - x_phys_put_byte(addr, val); + phys_put_byte(addr, val); else if (size == sz_word) - x_phys_put_word(addr, val); + phys_put_word(addr, val); else - x_phys_put_long(addr, val); + phys_put_long(addr, val); return; } @@ -2281,21 +2281,9 @@ void mmu030_reset(int hardreset) if (currprefs.cpu_cycle_exact || currprefs.cpu_compatible) { x_phys_get_iword = get_word_icache030; x_phys_get_ilong = get_long_icache030; - x_phys_get_byte = get_dcache_byte; - x_phys_get_word = get_dcache_word; - x_phys_get_long = get_dcache_long; - x_phys_put_byte = put_dcache_byte; - x_phys_put_word = put_dcache_word; - x_phys_put_long = put_dcache_long; } else { x_phys_get_iword = phys_get_word; x_phys_get_ilong = phys_get_long; - x_phys_get_byte = phys_get_byte; - x_phys_get_word = phys_get_word; - x_phys_get_long = phys_get_long; - x_phys_put_byte = phys_put_byte; - x_phys_put_word = phys_put_word; - x_phys_put_long = phys_put_long; } } diff --git a/custom.cpp b/custom.cpp index 9ba79cd8..6c83d628 100644 --- a/custom.cpp +++ b/custom.cpp @@ -66,6 +66,7 @@ #endif #include "luascript.h" #include "statusline.h" +#include "ppc.h" #define CUSTOM_DEBUG 0 #define SPRITE_DEBUG 0 @@ -7519,6 +7520,9 @@ static void hsync_handler_pre (bool onvsync) void ahi_hsync (void); ahi_hsync (); } +#endif +#ifdef WITH_PPC + uae_ppc_hsync_handler(); #endif DISK_hsync (); if (currprefs.produce_sound) diff --git a/flashrom.cpp b/flashrom.cpp index 8b5c21c9..1ad43411 100644 --- a/flashrom.cpp +++ b/flashrom.cpp @@ -56,6 +56,14 @@ void flash_free(void *fdv) xfree(fdv); } +int flash_size(void *fdv) +{ + struct flashrom_data *fd = (struct flashrom_data*)fdv; + if (!fd) + return 0; + return fd->flashsize; +} + bool flash_active(void *fdv, uaecptr addr) { struct flashrom_data *fd = (struct flashrom_data*)fdv; @@ -67,12 +75,13 @@ bool flash_active(void *fdv, uaecptr addr) bool flash_write(void *fdv, uaecptr addr, uae_u8 v) { struct flashrom_data *fd = (struct flashrom_data*)fdv; - int oldstate = fd->state; + int oldstate; uae_u32 addr2; if (!fd) return false; -#if FLASH_LOG + oldstate = fd->state; +#if FLASH_LOG > 1 write_log(_T("flash write %08x %02x (%d) PC=%08x\n"), addr, v, fd->state, m68k_getpc()); #endif @@ -179,7 +188,7 @@ uae_u32 flash_read(void *fdv, uaecptr addr) else v = fd->rom[addr]; } -#if FLASH_LOG +#if FLASH_LOG > 1 write_log(_T("flash read %08x = %02X (%d) PC=%08x\n"), addr, v, fd->state, m68k_getpc()); #endif diff --git a/gfxboard.cpp b/gfxboard.cpp index 9286ab74..c34fef89 100644 --- a/gfxboard.cpp +++ b/gfxboard.cpp @@ -205,6 +205,7 @@ static void init_board (void) { int vramsize = board->vrammax; + mapped_free(&gfxmem_bank); vram_start_offset = 0; if (ISP4() && !p4z2) // JIT direct compatibility hack vram_start_offset = 0x01000000; @@ -221,6 +222,7 @@ static void init_board (void) vramrealstart = vram; vram += vram_start_offset; gfxmem_bank.baseaddr = vram; + gfxmem_bank.allocated = currprefs.rtgmem_size; vga.vga.vram_size_mb = currprefs.rtgmem_size >> 20; vgaioregion.opaque = &vgaioregionptr; vgavramregion.opaque = &vgavramregionptr; diff --git a/include/cpuboard.h b/include/cpuboard.h index 77ec3541..fc4a954e 100644 --- a/include/cpuboard.h +++ b/include/cpuboard.h @@ -9,7 +9,7 @@ extern void cpuboard_clear(void); extern void cpuboard_vsync(void); extern void cpuboard_rethink(void); extern bool cpuboard_08000000(struct uae_prefs *p); -extern bool is_ppc_cpu(void); +extern bool is_ppc_cpu(struct uae_prefs *); extern bool ppc_interrupt(int new_m68k_ipl); diff --git a/include/flashrom.h b/include/flashrom.h index bf745c8b..127f18f9 100644 --- a/include/flashrom.h +++ b/include/flashrom.h @@ -5,3 +5,4 @@ void flash_free(void *fdv); bool flash_write(void *fdv, uaecptr addr, uae_u8 v); uae_u32 flash_read(void *fdv, uaecptr addr); bool flash_active(void *fdv, uaecptr addr); +int flash_size(void *fdv); \ No newline at end of file diff --git a/include/options.h b/include/options.h index a7c75586..58e85713 100644 --- a/include/options.h +++ b/include/options.h @@ -461,6 +461,10 @@ struct uae_prefs { TCHAR a4091romfile2[MAX_DPATH]; TCHAR a4091romident2[256]; bool a4091; + TCHAR acceleratorromfile[MAX_DPATH]; + TCHAR acceleratorromident[256]; + TCHAR acceleratorextromfile[MAX_DPATH]; + TCHAR acceleratorextromident[256]; TCHAR flashfile[MAX_DPATH]; TCHAR rtcfile[MAX_DPATH]; TCHAR cartfile[MAX_DPATH]; @@ -489,6 +493,7 @@ struct uae_prefs { int cpu060_revision; int fpu_model; int fpu_revision; + int ppc_mode; bool cpu_compatible; bool int_no_unimplemented; bool fpu_no_unimplemented; diff --git a/include/ppc.h b/include/ppc.h index d9ed137b..2f9a7ee5 100644 --- a/include/ppc.h +++ b/include/ppc.h @@ -1,11 +1,15 @@ -void ppc_reboot(void); -void ppc_stop(void); -void uae_ppc_poll_queue(void); -void ppc_interrupt(bool active); - -void ppc_hsync_handler(void); -void ppc_wakeup(void); +void uae_ppc_cpu_reboot(void); +void uae_ppc_cpu_stop(void); +bool uae_ppc_poll_queue(void); +void uae_ppc_interrupt(bool active); +void uae_ppc_cpu_lock(void); +bool uae_ppc_cpu_unlock(void); +void uae_ppc_to_main_thread(void); +void uae_ppc_emulate(void); +void uae_ppc_reset(bool hardreset); +void uae_ppc_hsync_handler(void); +void uae_ppc_wakeup(void); #define PPC_STATE_STOP 0 #define PPC_STATE_ACTIVE 1 diff --git a/include/rommgr.h b/include/rommgr.h index b7bddd2e..ca7082f8 100644 --- a/include/rommgr.h +++ b/include/rommgr.h @@ -18,6 +18,7 @@ extern int decode_cloanto_rom_do (uae_u8 *mem, int size, int real_size); #define ROMTYPE_SPECIALKICK 0x00008000 #define ROMTYPE_PIV 0x00010000 #define ROMTYPE_CPUBOARD 0x00020000 +#define ROMTYPE_CPUBOARDEXT 0x00040000 #define ROMTYPE_MASK 0x001fffff #define ROMTYPE_EVEN 0x02000000 #define ROMTYPE_ODD 0x04000000 @@ -52,6 +53,7 @@ struct romdata { uae_u32 crc32; uae_u32 sha1[5]; TCHAR *configname; + TCHAR *defaultfilename; }; struct romlist { @@ -66,6 +68,7 @@ extern struct romdata *getromdatabydata (uae_u8 *rom, int size); extern struct romdata *getromdatabyid (int id); extern struct romdata *getromdatabyidgroup (int id, int group, int subitem); extern struct romdata *getromdatabyzfile (struct zfile *f); +extern struct romdata *getfrombydefaultname(const TCHAR *name, int size); extern struct romlist **getarcadiaroms (void); extern struct romdata *getarcadiarombyname (const TCHAR *name); extern struct romlist **getromlistbyident (int ver, int rev, int subver, int subrev, const TCHAR *model, int romflags, bool all); diff --git a/include/statusline.h b/include/statusline.h index 1d7c37af..5fafc7ef 100644 --- a/include/statusline.h +++ b/include/statusline.h @@ -17,7 +17,7 @@ static int td_pos = (TD_RIGHT | TD_BOTTOM); #define TD_TOTAL_HEIGHT (TD_PADY * 2 + TD_NUM_HEIGHT) -#define NUMBERS_NUM 16 +#define NUMBERS_NUM 17 #define TD_BORDER 0x333333 diff --git a/main.cpp b/main.cpp index fc192691..e1f9e005 100644 --- a/main.cpp +++ b/main.cpp @@ -258,6 +258,19 @@ void fixup_cpu (struct uae_prefs *p) break; } + // 1 = "automatic" PPC config + if (p->ppc_mode == 1) { + p->cpuboard_type = BOARD_CSPPC; + if (p->cs_compatible == CP_A1200) { + p->cpuboard_type = BOARD_BLIZZARDPPC; + } else if (p->cs_compatible != CP_A4000 && p->cs_compatible != CP_A4000T && p->cs_compatible != CP_A3000 && p->cs_compatible != CP_A3000T) { + if ((p->cs_ide == IDE_A600A1200 || p->cs_pcmcia) && p->cs_mbdmac <= 0) + p->cpuboard_type = BOARD_BLIZZARDPPC; + } + if (p->cpuboardmem1_size < 8 * 1024 * 1024) + p->cpuboardmem1_size = 8 * 1024 * 1024; + } + if (p->cpu_model < 68020 && p->cachesize) { p->cachesize = 0; error_log (_T("JIT requires 68020 or better CPU.")); @@ -423,17 +436,22 @@ void fixup_prefs (struct uae_prefs *p) error_log (_T("Possible Gayle bogomem conflict fixed.")); } if (p->chipmem_size > 0x200000 && p->fastmem_size > 262144) { - error_log (_T("You can't use fastmem and more than 2MB chip at the same time.")); - p->fastmem_size = 0; + error_log(_T("You can't use fastmem and more than 2MB chip at the same time.")); + p->chipmem_size = 0x200000; + err = 1; + } + if (p->chipmem_size > 0x200000 && p->rtgmem_size && !gfxboard_is_z3(p->rtgmem_type)) { + error_log(_T("You can't use Zorro II RTG and more than 2MB chip at the same time.")); + p->chipmem_size = 0x200000; err = 1; } if (p->mbresmem_low_size > 0x04000000 || (p->mbresmem_low_size & 0xfffff)) { p->mbresmem_low_size = 0; - error_log (_T("Unsupported A3000 MB RAM size")); + error_log (_T("Unsupported Mainboard RAM size")); } if (p->mbresmem_high_size > 0x08000000 || (p->mbresmem_high_size & 0xfffff)) { p->mbresmem_high_size = 0; - error_log (_T("Unsupported Motherboard RAM size.")); + error_log (_T("Unsupported CPU Board RAM size.")); } if (p->rtgmem_type >= GFXBOARD_HARDWARE) { @@ -628,7 +646,7 @@ void fixup_prefs (struct uae_prefs *p) #endif if (p->maprom && !p->address_space_24) p->maprom = 0x0f000000; - if (((p->maprom & 0xff000000) && p->address_space_24) || p->mbresmem_high_size == 0x08000000) { + if (((p->maprom & 0xff000000) && p->address_space_24) || (p->maprom && p->mbresmem_high_size == 0x08000000)) { p->maprom = 0x00e00000; } if (p->tod_hack && p->cs_ciaatod == 0) @@ -906,7 +924,7 @@ void reset_all_systems (void) dongle_reset (); sampler_init (); #ifdef WITH_PPC - ppc_stop(); + uae_ppc_reset(false); #endif } @@ -1177,12 +1195,14 @@ static int real_main2 (int argc, TCHAR **argv) #ifdef AUTOCONFIG native2amiga_install (); #endif - custom_init (); /* Must come after memory_init */ #ifdef SERIAL_PORT serial_init (); #endif DISK_init (); +#ifdef WITH_PPC + uae_ppc_reset(true); +#endif reset_frame_rate_hack (); init_m68k (); /* must come after reset_frame_rate_hack (); */ diff --git a/ncr_scsi.cpp b/ncr_scsi.cpp index cc3274c8..44ba207b 100644 --- a/ncr_scsi.cpp +++ b/ncr_scsi.cpp @@ -397,9 +397,6 @@ static uae_u32 REGPARAM2 ncr_wget (struct ncr_state *ncr, uaecptr addr) #ifdef JIT special_mem |= S_READ; #endif - if (ncr->newncr) - return 0; - addr &= ncr->board_mask; v = (ncr_bget2 (ncr, addr) << 8) | ncr_bget2 (ncr, addr + 1); return v; } @@ -512,8 +509,6 @@ static void REGPARAM2 ncr_wput (struct ncr_state *ncr, uaecptr addr, uae_u32 w) } return; } - if (ncr->newncr) - return; ncr_bput2(ncr, addr, w >> 8); ncr_bput2 (ncr, addr + 1, w); } diff --git a/newcpu.cpp b/newcpu.cpp index be338e49..b621df9a 100644 --- a/newcpu.cpp +++ b/newcpu.cpp @@ -3147,6 +3147,7 @@ static void do_trace (void) } } + #ifdef WITH_PPC static void uae_ppc_poll_check(void) { @@ -3157,9 +3158,68 @@ static void uae_ppc_poll_check(void) return; uae_ppc_poll_queue(); checkcnt = 128; + return; +} +#endif + +static bool haltloop(void) +{ +#ifdef WITH_PPC + // m68k stopped? Move PPC emulator to main thread. + if (regs.halted < 0) { + uae_ppc_to_main_thread(); + } +#endif + + while (regs.halted) { + if (regs.halted >= 0) { + static int prevvpos; + if (vpos == 0 && prevvpos) { + prevvpos = 0; + sleep_millis_main(8); + } + if (vpos) + prevvpos = 1; + x_do_cycles(8 * CYCLE_UNIT); + } else { + x_do_cycles(16 * CYCLE_UNIT); + } + + if (regs.spcflags & SPCFLAG_COPPER) + do_copper(); + +#ifdef WITH_PPC + if (regs.halted < 0) + uae_ppc_emulate(); + else + uae_ppc_poll_check(); + if (ppc_state) { + int intr = intlev(); + ppc_interrupt(intr); + } +#endif + + if (regs.spcflags) { + if ((regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE))) + return true; + } + } + return false; +} + +#ifdef WITH_PPC +static bool uae_ppc_poll_check_halt(void) +{ + uae_ppc_poll_check(); + if (regs.halted) { + if (haltloop()) + return true; + } + return false; } #endif + // handle interrupt delay (few cycles) STATIC_INLINE bool time_for_interrupt (void) { @@ -3187,20 +3247,9 @@ static int do_specialties (int cycles) return 1; if (regs.spcflags & SPCFLAG_CHECK) { - while (regs.halted) { - if (vpos == 0) - sleep_millis_main(8); - x_do_cycles(8 * CYCLE_UNIT); - if (regs.spcflags & SPCFLAG_COPPER) - do_copper(); -#ifdef WITH_PPC - if (ppc_state) - ppc_interrupt(intlev()); -#endif - if (regs.spcflags) { - if ((regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE))) - return 1; - } + if (regs.halted) { + if (haltloop()) + return 1; } if (m68k_reset_delay) { int vsynccnt = 60; @@ -3276,8 +3325,10 @@ static int do_specialties (int cycles) if (regs.spcflags & SPCFLAG_COPPER) do_copper (); #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_check(); + if (ppc_state) { + if (uae_ppc_poll_check_halt()) + return true; + } #endif } @@ -3346,7 +3397,7 @@ static int do_specialties (int cycles) #ifdef WITH_PPC if (ppc_state) - uae_ppc_poll_check(); + uae_ppc_poll_check_halt(); #endif if (!uae_int_requested && !uaenet_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP) @@ -3412,6 +3463,19 @@ static int do_specialties (int cycles) return 0; } +#ifdef WITH_PPC +static void do_ppc(void) +{ + while (ppc_state && uae_ppc_poll_queue()) { + if (regs.spcflags) { + if (do_specialties(0)) { + return; + } + } + } +} +#endif + //static uae_u32 pcs[1000]; #if DEBUG_CD32CDTVIO @@ -3802,8 +3866,7 @@ static void m68k_run_jit (void) set_special (SPCFLAG_INT); } #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_queue(); + do_ppc(); #endif if (regs.spcflags) { if (do_specialties (0)) { @@ -3896,8 +3959,7 @@ retry: cpu_cycles = adjust_cycles (cpu_cycles); #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_queue(); + do_ppc(); #endif if (regs.spcflags) { @@ -3959,8 +4021,7 @@ retry: cpu_cycles = adjust_cycles (cpu_cycles); #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_queue(); + do_ppc(); #endif if (regs.spcflags) { @@ -4101,8 +4162,7 @@ static void m68k_run_3ce (void) (*cpufunctbl[opcode])(opcode); #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_queue(); + do_ppc(); #endif if (r->spcflags) { @@ -4138,8 +4198,7 @@ static void m68k_run_3p(void) do_cycles(cycles); #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_queue(); + do_ppc(); #endif if (r->spcflags) { @@ -4366,8 +4425,7 @@ static void m68k_run_2 (void) cpu_cycles = adjust_cycles (cpu_cycles); #ifdef WITH_PPC - if (ppc_state) - uae_ppc_poll_queue(); + do_ppc(); #endif if (r->spcflags) { @@ -6415,7 +6473,7 @@ static void write_dcache030x (uaecptr addr, uae_u32 val, int size) uae_u32 tag1, tag2; int aligned = addr & 3; - if (1 || !(regs.cacr & 0x100)) // data cache disabled? + if (!(regs.cacr & 0x100)) // data cache disabled? return; if (!cancache030 (addr)) return; @@ -6485,10 +6543,9 @@ uae_u32 read_dcache030 (uaecptr addr, int size) int lws1, lws2; uae_u32 tag1, tag2; int aligned = addr & 3; - int len = (1 << size) * 8; uae_u32 v1, v2; - if (1 || !(regs.cacr & 0x100) || !cancache030 (addr)) { // data cache disabled? + if (!(regs.cacr & 0x100) || !cancache030 (addr)) { // data cache disabled? if (currprefs.cpu_cycle_exact) { if (size == 2) return mem_access_delay_long_read_ce020 (addr); diff --git a/od-win32/mman.cpp b/od-win32/mman.cpp index 7d812d6f..0d617437 100644 --- a/od-win32/mman.cpp +++ b/od-win32/mman.cpp @@ -371,12 +371,14 @@ static int doinit_shm (void) addr = expansion_startaddress(addr, changed_prefs.z3fastmem_size); addr += changed_prefs.z3fastmem_size; addr = expansion_startaddress(addr, changed_prefs.rtgmem_size); - p96base_offset = addr; - // adjust p96mem_offset to beginning of natmem - // by subtracting start of original p96mem_offset from natmem_offset - if (p96base_offset >= 0x10000000) { - natmem_offset = natmem_offset_allocated - p96base_offset; - p96mem_offset = natmem_offset + p96base_offset; + if (gfxboard_is_z3(changed_prefs.rtgmem_type)) { + p96base_offset = addr; + // adjust p96mem_offset to beginning of natmem + // by subtracting start of original p96mem_offset from natmem_offset + if (p96base_offset >= 0x10000000) { + natmem_offset = natmem_offset_allocated - p96base_offset; + p96mem_offset = natmem_offset + p96base_offset; + } } } } diff --git a/od-win32/resources/resource.h b/od-win32/resources/resource.h index ead52eb1..1cf97cb2 100644 --- a/od-win32/resources/resource.h +++ b/od-win32/resources/resource.h @@ -533,6 +533,7 @@ #define IDC_SOUNDSETTINGS 1229 #define IDC_CPU_UNIMPLEMENTED 1229 #define IDC_8BIT 1230 +#define IDC_CPU_PPC 1230 #define IDC_16BIT 1231 #define IDC_11KHZ 1232 #define IDC_22KHZ 1233 @@ -662,7 +663,9 @@ #define IDC_RTCCHOOSER 1401 #define IDC_A4091ROMCHOOSER 1402 #define IDC_DELETE 1403 +#define IDC_CPUBOARDROMCHOOSER 1403 #define IDC_CONFIGLIST 1404 +#define IDC_CPUBOARDEXTROMCHOOSER 1404 #define IDC_EDITNAME 1405 #define IDC_EDITDESCRIPTION 1406 #define IDC_QUICKSAVE 1408 @@ -671,6 +674,8 @@ #define IDC_EDITPATH 1410 #define IDC_RTCFILE 1411 #define IDC_A4091ROMFILE 1412 +#define IDC_CPUBOARDEXTROMFILE 1413 +#define IDC_CPUBOARDROMFILE 1414 #define IDC_HDF_RDB 1500 #define IDC_HFSIZE 1501 #define IDC_HF_SIZE 1501 @@ -701,6 +706,7 @@ #define IDC_WINDOWEDTEXT 1512 #define IDC_MAPDRIVES_LIMIT 1512 #define IDC_HEIGHTTEXT 1513 +#define IDC_MAPDRIVES_NET2 1513 #define IDC_SETTINGSTEXT 1514 #define IDC_REFRESHTEXT 1515 #define IDC_SETTINGSTEXT2 1515 diff --git a/od-win32/resources/winuae.rc b/od-win32/resources/winuae.rc index eac6c765..08f75c9c 100644 --- a/od-win32/resources/winuae.rc +++ b/od-win32/resources/winuae.rc @@ -76,7 +76,7 @@ END // Dialog // -IDD_KICKSTART DIALOGEX 0, 0, 396, 243 +IDD_KICKSTART DIALOGEX 0, 0, 396, 279 STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD EXSTYLE WS_EX_CONTEXTHELP FONT 8, "MS Sans Serif", 0, 0, 0x1 @@ -92,7 +92,7 @@ BEGIN "Button",BS_AUTOCHECKBOX | WS_TABSTOP,87,77,104,12 CONTROL "ShapeShifter support [] Patches the system ROM for ShapeShifter compatibility.",IDC_KICKSHIFTER, "Button",BS_AUTOCHECKBOX | WS_TABSTOP,195,77,106,13 - GROUPBOX "Miscellaneous",IDC_STATIC,1,98,394,143 + GROUPBOX "Miscellaneous",IDC_STATIC,1,98,394,177 LTEXT "Cartridge ROM file:",IDC_FLASHTEXT2,12,112,265,10 COMBOBOX IDC_CARTFILE,12,125,361,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | CBS_SORT | WS_VSCROLL | WS_TABSTOP PUSHBUTTON "...",IDC_CARTCHOOSER,376,124,10,15 @@ -105,9 +105,15 @@ BEGIN COMBOBOX IDC_A2091ROMFILE,12,223,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | CBS_SORT | WS_VSCROLL | WS_TABSTOP PUSHBUTTON "...",IDC_A2091ROMCHOOSER,187,221,10,15 LTEXT "A590/A2091 SCSI ROM file:",IDC_STATIC,12,207,170,15,SS_CENTERIMAGE - LTEXT "A4091 SCSI ROM file:",IDC_STATIC,203,207,170,15,SS_CENTERIMAGE + LTEXT "Accelerator board SCSI ROM file:",IDC_STATIC,202,240,170,15,SS_CENTERIMAGE COMBOBOX IDC_A4091ROMFILE,202,223,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | CBS_SORT | WS_VSCROLL | WS_TABSTOP PUSHBUTTON "...",IDC_A4091ROMCHOOSER,376,221,10,15 + LTEXT "Accelerator board ROM file:",IDC_STATIC,12,240,170,15,SS_CENTERIMAGE + LTEXT "A4091 SCSI ROM file:",IDC_STATIC,202,207,170,15,SS_CENTERIMAGE + COMBOBOX IDC_CPUBOARDROMFILE,12,256,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | CBS_SORT | WS_VSCROLL | WS_TABSTOP + COMBOBOX IDC_CPUBOARDEXTROMFILE,202,256,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | CBS_SORT | WS_VSCROLL | WS_TABSTOP + PUSHBUTTON "...",IDC_CPUBOARDROMCHOOSER,187,255,10,15 + PUSHBUTTON "...",IDC_CPUBOARDEXTROMCHOOSER,376,255,10,15 END IDD_DISPLAY DIALOGEX 0, 0, 396, 298 @@ -211,11 +217,11 @@ BEGIN EDITTEXT IDC_CPUBOARDRAM,326,256,40,12,ES_CENTER | ES_READONLY END -IDD_CPU DIALOGEX 0, 0, 396, 283 +IDD_CPU DIALOGEX 0, 0, 396, 292 STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD FONT 8, "MS Sans Serif", 0, 0, 0x0 BEGIN - GROUPBOX "CPU",IDC_STATIC,1,1,129,175,BS_LEFT + GROUPBOX "CPU",IDC_STATIC,1,1,129,184,BS_LEFT CONTROL "68000",IDC_CPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,8,15,63,10 CONTROL "68010",IDC_CPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,29,63,10 CONTROL "68020",IDC_CPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,42,63,10 @@ -240,29 +246,30 @@ BEGIN EDITTEXT IDC_CPUTEXT,204,89,30,12,ES_CENTER | ES_READONLY RTEXT "CPU Idle",IDC_STATIC,239,90,62,9 CONTROL "",IDC_CPUIDLE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,308,85,69,21 - GROUPBOX "Cycle-exact CPU Emulation Speed",IDC_STATIC,136,121,258,55 + GROUPBOX "Cycle-exact CPU Emulation Speed",IDC_STATIC,136,121,258,64 RTEXT "CPU Frequency",IDC_STATIC,139,145,67,10,SS_CENTERIMAGE COMBOBOX IDC_CPU_FREQUENCY,215,144,89,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP EDITTEXT IDC_CPU_FREQUENCY2,312,143,70,15 - GROUPBOX "FPU",IDC_STATIC,1,181,129,99,BS_LEFT - CONTROL "None",IDC_FPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,8,195,87,10 - CONTROL "68881",IDC_FPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,209,87,10 - CONTROL "68882",IDC_FPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,222,87,10 - CONTROL "CPU internal",IDC_FPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,236,93,10 + GROUPBOX "FPU",IDC_STATIC,1,188,129,99,BS_LEFT + CONTROL "None",IDC_FPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,8,202,87,10 + CONTROL "68881",IDC_FPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,216,87,10 + CONTROL "68882",IDC_FPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,229,87,10 + CONTROL "CPU internal",IDC_FPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,243,93,10 CONTROL "More compatible [] More compatible but slower FPU emulation.",IDC_COMPATIBLE_FPU, - "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,252,117,10 + "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,259,117,10 CONTROL "Unimplemented FPU emu [] Emulate FPU unimplemented instructions",IDC_FPU_UNIMPLEMENTED, - "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,265,116,10 - GROUPBOX "Advanced JIT Settings",IDC_STATIC,136,181,258,99 - RTEXT "Cache size:",IDC_STATIC,143,200,66,10,SS_CENTERIMAGE - CONTROL "Slider1",IDC_CACHE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,212,194,115,20 - EDITTEXT IDC_CACHETEXT,331,199,30,12,ES_CENTER | ES_READONLY - CONTROL "Hard flush",IDC_HARDFLUSH,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,227,84,11 - CONTROL "Constant jump",IDC_CONSTJUMP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,241,84,11 - CONTROL "FPU support",IDC_JITFPU,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,255,84,11 - CONTROL "No flags",IDC_NOFLAGS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,243,227,68,11 - CONTROL "Direct",IDC_TRUST0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,315,227,72,10 - CONTROL "Indirect",IDC_TRUST1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,315,241,72,10 + "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,277,116,10 + GROUPBOX "Advanced JIT Settings",IDC_STATIC,136,188,258,99 + RTEXT "Cache size:",IDC_STATIC,143,207,66,10,SS_CENTERIMAGE + CONTROL "Slider1",IDC_CACHE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,212,201,115,20 + EDITTEXT IDC_CACHETEXT,331,206,30,12,ES_CENTER | ES_READONLY + CONTROL "Hard flush",IDC_HARDFLUSH,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,234,84,11 + CONTROL "Constant jump",IDC_CONSTJUMP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,248,84,11 + CONTROL "FPU support",IDC_JITFPU,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,262,84,11 + CONTROL "No flags",IDC_NOFLAGS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,243,234,68,11 + CONTROL "Direct",IDC_TRUST0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,315,234,72,10 + CONTROL "Indirect",IDC_TRUST1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,315,248,72,10 + CONTROL "PPC [] Automatically configure CyberStorm PPC or Blizzard PPC setup.",IDC_CPU_PPC,"Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,169,118,10 END IDD_FLOPPY DIALOGEX 0, 0, 396, 261 @@ -319,7 +326,7 @@ BEGIN CONTROL "FFS",IDC_FLOPPY_FFS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,300,242,34,15 END -IDD_HARDDISK DIALOGEX 0, 0, 396, 315 +IDD_HARDDISK DIALOGEX 0, 0, 396, 318 STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD EXSTYLE WS_EX_CONTEXTHELP FONT 8, "MS Sans Serif", 0, 0, 0x1 @@ -332,24 +339,24 @@ BEGIN PUSHBUTTON "Add SCSI Tape Drive",IDC_NEW_TAPE,135,176,126,15 PUSHBUTTON "&Properties",IDC_EDIT,267,176,60,15 PUSHBUTTON "Remove",IDC_REMOVE,334,176,60,15 - GROUPBOX "Options",IDC_STATIC,1,191,393,72 - CONTROL "Add PC drives at startup",IDC_MAPDRIVES,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,204,201,11 + GROUPBOX "Options",IDC_STATIC,1,193,393,72 + CONTROL "Add PC drives at startup",IDC_MAPDRIVES,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,206,201,11 CONTROL "Include removable drives..",IDC_MAPDRIVES_REMOVABLE, - "Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,217,201,11 - CONTROL "Include network drives..",IDC_MAPDRIVES_NET,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,231,201,11 - CONTROL "CDFS automount CD/DVD drives",IDC_MAPDRIVES_CD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,245,201,11 - CONTROL "Disable UAEFSDB-support",IDC_NOUAEFSDB,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,204,167,11 - CONTROL "Don't use Windows Recycle Bin",IDC_NORECYCLEBIN,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,217,167,11 + "Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,219,201,11 + CONTROL "Include network drives..",IDC_MAPDRIVES_NET,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,233,201,11 + CONTROL "CDFS automount CD/DVD drives",IDC_MAPDRIVES_CD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,247,201,11 + CONTROL "Disable UAEFSDB-support",IDC_NOUAEFSDB,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,206,167,11 + CONTROL "Don't use Windows Recycle Bin",IDC_NORECYCLEBIN,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,219,167,11 CONTROL "Automount removable drives [] Windows side insert or removal will immediately mount/remove it on Amiga side.",IDC_MAPDRIVES_AUTO, - "Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,231,167,11 + "Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,233,167,11 CONTROL "Limit size of directory drives to 1G [] Workaround for example old installers that calculate free space incorrectly if drive is large.",IDC_MAPDRIVES_LIMIT, - "Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,245,167,11 - GROUPBOX "Optical media options",IDC_STATIC,1,266,393,47 - LTEXT "CD drive/image",IDC_STATIC,5,280,70,10,SS_CENTERIMAGE - PUSHBUTTON "Select image file",IDC_CD_SELECT,177,278,98,15 - COMBOBOX IDC_CD_TYPE,282,279,71,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP - PUSHBUTTON "Eject",IDC_CD_EJECT,360,278,30,15 - COMBOBOX IDC_CD_TEXT,5,297,386,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP + "Button",BS_AUTOCHECKBOX | WS_TABSTOP,222,247,167,11 + GROUPBOX "Optical media options",IDC_STATIC,1,269,393,47 + LTEXT "CD drive/image",IDC_STATIC,5,283,70,10,SS_CENTERIMAGE + PUSHBUTTON "Select image file",IDC_CD_SELECT,177,281,98,15 + COMBOBOX IDC_CD_TYPE,282,282,71,50,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP + PUSHBUTTON "Eject",IDC_CD_EJECT,360,281,30,15 + COMBOBOX IDC_CD_TEXT,5,300,386,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP END IDD_SOUND DIALOGEX 0, 0, 396, 288 @@ -1363,6 +1370,7 @@ GUIDELINES DESIGNINFO BEGIN IDD_KICKSTART, DIALOG BEGIN + BOTTOMMARGIN, 243 END IDD_DISPLAY, DIALOG @@ -1376,7 +1384,7 @@ BEGIN IDD_CPU, DIALOG BEGIN - BOTTOMMARGIN, 282 + BOTTOMMARGIN, 291 END IDD_FLOPPY, DIALOG @@ -1385,6 +1393,7 @@ BEGIN IDD_HARDDISK, DIALOG BEGIN + BOTTOMMARGIN, 315 END IDD_SOUND, DIALOG diff --git a/od-win32/win32.h b/od-win32/win32.h index 5d9118d5..56ad71f3 100644 --- a/od-win32/win32.h +++ b/od-win32/win32.h @@ -20,12 +20,12 @@ #define LANG_DLL_FULL_VERSION_MATCH 1 #if WINUAEPUBLICBETA -#define WINUAEBETA _T("9") +#define WINUAEBETA _T("10") #else #define WINUAEBETA _T("") #endif -#define WINUAEDATE MAKEBD(2014, 8, 7) +#define WINUAEDATE MAKEBD(2014, 8, 10) //#define WINUAEEXTRA _T("AmiKit Preview") //#define WINUAEEXTRA _T("Amiga Forever Edition") diff --git a/od-win32/win32gfx.cpp b/od-win32/win32gfx.cpp index ba3f7eb4..5e6172a3 100644 --- a/od-win32/win32gfx.cpp +++ b/od-win32/win32gfx.cpp @@ -2651,7 +2651,7 @@ static void createstatuswindow (void) power_width = (int)(42 * scaleX); fps_width = (int)(64 * scaleX); idle_width = (int)(64 * scaleX); - if (is_ppc_cpu()) + if (is_ppc_cpu(&currprefs)) idle_width = 136; snd_width = (int)(72 * scaleX); joy_width = (int)(24 * scaleX); diff --git a/od-win32/win32gui.cpp b/od-win32/win32gui.cpp index ccd39b84..44520f24 100644 --- a/od-win32/win32gui.cpp +++ b/od-win32/win32gui.cpp @@ -1378,6 +1378,10 @@ static struct romdata *scan_single_rom_2 (struct zfile *f) rd = getromdatabydata (rombuf, size); } } + if (!rd) { + const TCHAR *name = my_getfilepart(zfile_getname(f)); + rd = getfrombydefaultname(name, size); + } if (!rd) { write_log (_T("!: Name='%s':%d\nCRC32=%08X SHA1=%s\n"), zfile_getname (f), size, get_crc32 (rombuf, size), get_sha1_txt (rombuf, size)); @@ -2661,6 +2665,14 @@ int DiskSelection_2 (HWND hDlg, WPARAM wParam, int flag, struct uae_prefs *prefs _tcscpy (workprefs.a4091romfile, full_path); fullpath (workprefs.a4091romfile, MAX_DPATH); break; + case IDC_CPUBOARDROMFILE: + _tcscpy(workprefs.acceleratorromfile, full_path); + fullpath(workprefs.acceleratorromfile, MAX_DPATH); + break; + case IDC_CPUBOARDEXTROMFILE: + _tcscpy(workprefs.acceleratorextromfile, full_path); + fullpath(workprefs.acceleratorextromfile, MAX_DPATH); + break; case IDC_STATEREC_PLAY: case IDC_STATEREC_RECORD: case IDC_STATEREC_SAVE: @@ -8196,6 +8208,11 @@ static INT_PTR CALLBACK MemoryDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LPARA v = SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_GETCURSEL, 0, 0L); if (v != CB_ERR) { workprefs.cpuboard_type = v; + if (is_ppc_cpu(&workprefs)) { + workprefs.ppc_mode = 2; + } else if (workprefs.ppc_mode == 2) { + workprefs.ppc_mode = 0; + } enable_for_memorydlg(hDlg); } break; @@ -8299,6 +8316,8 @@ static void values_from_kickstartdlg (HWND hDlg) getromfile (hDlg, IDC_CARTFILE, workprefs.cartfile, sizeof (workprefs.cartfile) / sizeof (TCHAR)); getromfile (hDlg, IDC_A2091ROMFILE, workprefs.a2091romfile, sizeof (workprefs.a2091romfile) / sizeof (TCHAR)); getromfile (hDlg, IDC_A4091ROMFILE, workprefs.a4091romfile, sizeof (workprefs.a4091romfile) / sizeof (TCHAR)); + getromfile(hDlg, IDC_CPUBOARDROMFILE, workprefs.acceleratorromfile, sizeof(workprefs.acceleratorromfile) / sizeof(TCHAR)); + getromfile(hDlg, IDC_CPUBOARDEXTROMFILE, workprefs.acceleratorextromfile, sizeof(workprefs.acceleratorextromfile) / sizeof(TCHAR)); } static void values_to_kickstartdlg (HWND hDlg) @@ -8317,7 +8336,11 @@ static void values_to_kickstartdlg (HWND hDlg) ROMTYPE_A2091BOOT | ROMTYPE_NONE); addromfiles (fkey, hDlg, IDC_A4091ROMFILE, workprefs.a4091romfile, ROMTYPE_A4091BOOT); - regclosetree (fkey); + addromfiles(fkey, hDlg, IDC_CPUBOARDROMFILE, workprefs.acceleratorromfile, + ROMTYPE_CPUBOARD); + addromfiles(fkey, hDlg, IDC_CPUBOARDEXTROMFILE, workprefs.acceleratorextromfile, + ROMTYPE_CPUBOARDEXT); + regclosetree(fkey); SetDlgItemText(hDlg, IDC_FLASHFILE, workprefs.flashfile); SetDlgItemText(hDlg, IDC_RTCFILE, workprefs.rtcfile); @@ -8347,7 +8370,9 @@ static void init_kickstart (HWND hDlg) ew (hDlg, IDC_A4091ROMFILE, workprefs.a4091); ew (hDlg, IDC_A2091ROMCHOOSER, workprefs.a2091); ew (hDlg, IDC_A2091ROMFILE, workprefs.a2091); - if (!regexiststree (NULL , _T("DetectedROMs"))) + ew(hDlg, IDC_CPUBOARDROMFILE, workprefs.cpuboard_type != 0); + ew(hDlg, IDC_CPUBOARDEXTROMFILE, workprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV_SCSI || workprefs.cpuboard_type == BOARD_BLIZZARD_1260_SCSI); + if (!regexiststree(NULL, _T("DetectedROMs"))) scan_roms (NULL, rp_isactive () ? 0 : 1); } @@ -8381,7 +8406,15 @@ static void kickstartfilebuttons (HWND hDlg, WPARAM wParam, TCHAR *path) break; case IDC_A4091ROMCHOOSER: DiskSelection(hDlg, IDC_A4091ROMFILE, 6, &workprefs, path); - values_to_kickstartdlg (hDlg); + values_to_kickstartdlg(hDlg); + break; + case IDC_CPUBOARDROMCHOOSER: + DiskSelection(hDlg, IDC_CPUBOARDROMFILE, 6, &workprefs, path); + values_to_kickstartdlg(hDlg); + break; + case IDC_CPUBOARDEXTROMCHOOSER: + DiskSelection(hDlg, IDC_CPUBOARDEXTROMFILE, 6, &workprefs, path); + values_to_kickstartdlg(hDlg); break; } } @@ -9076,13 +9109,14 @@ static void enable_for_cpudlg (HWND hDlg) #if 0 ew (hDlg, IDC_CPU_MULTIPLIER, workprefs.cpu_cycle_exact); #endif - ew (hDlg, IDC_CPU_FREQUENCY, workprefs.cpu_cycle_exact); - ew (hDlg, IDC_CPU_FREQUENCY2, workprefs.cpu_cycle_exact && !workprefs.cpu_clock_multiplier); + ew (hDlg, IDC_CPU_FREQUENCY, workprefs.cpu_cycle_exact && workprefs.m68k_speed >= 0); + ew (hDlg, IDC_CPU_FREQUENCY2, workprefs.cpu_cycle_exact && !workprefs.cpu_clock_multiplier && workprefs.m68k_speed >= 0); ew (hDlg, IDC_FPU1, workprefs.cpu_model < 68040 && (workprefs.cpu_model >= 68020 || !workprefs.cpu_compatible)); ew (hDlg, IDC_FPU2, workprefs.cpu_model < 68040 && (workprefs.cpu_model >= 68020 || !workprefs.cpu_compatible)); ew (hDlg, IDC_FPU3, workprefs.cpu_model >= 68040); ew (hDlg, IDC_MMUENABLE, workprefs.cpu_model >= 68030 && workprefs.cachesize == 0); + ew (hDlg, IDC_CPU_PPC, workprefs.cpu_model >= 68040 && (workprefs.ppc_mode == 1 || (workprefs.ppc_mode == 0 && !is_ppc_cpu(&workprefs)))); SendDlgItemMessage (hDlg, IDC_SPEED, TBM_SETRANGE, TRUE, workprefs.m68k_speed < 0 ? MAKELONG (-9, 0) : MAKELONG (-9, 50)); SendDlgItemMessage (hDlg, IDC_SPEED, TBM_SETPAGESIZE, 0, 1); @@ -9137,6 +9171,7 @@ static void values_to_cpudlg (HWND hDlg) (workprefs.cpu_model == 68040 && workprefs.mmu_model == 68040) || (workprefs.cpu_model == 68030 && workprefs.mmu_model == 68030)) && workprefs.cachesize == 0); + CheckDlgButton(hDlg, IDC_CPU_PPC, workprefs.ppc_mode || is_ppc_cpu(&workprefs)); if (workprefs.cpu_cycle_exact) { if (workprefs.cpu_clock_multiplier) { @@ -9251,6 +9286,15 @@ static void values_from_cpudlg (HWND hDlg) if (oldcache == 0 && candirect && workprefs.cachesize > 0) canbang = 1; #endif + if (ischecked(hDlg, IDC_CPU_PPC)) { + if (workprefs.ppc_mode == 0) + workprefs.ppc_mode = 1; + if (workprefs.ppc_mode == 1 && workprefs.cpu_model < 68040) + workprefs.ppc_mode = 0; + } else if (!ischecked(hDlg, IDC_CPU_PPC) && workprefs.ppc_mode == 1) { + workprefs.ppc_mode = 0; + } + workprefs.cpu_idle = SendMessage (GetDlgItem (hDlg, IDC_CPUIDLE), TBM_GETPOS, 0, 0); if (workprefs.cpu_idle > 0) workprefs.cpu_idle = (12 - workprefs.cpu_idle) * 15; @@ -17387,7 +17431,7 @@ void gui_led (int led, int on) on = 0; else on = 1; - if (is_ppc_cpu()) { + if (is_ppc_cpu(&currprefs)) { _tcscpy(ptr, _T("PPC: ")); if (ppc_state == PPC_STATE_ACTIVE) _tcscat(ptr, _T("RUN")); diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt index 9b104d17..05e25b83 100644 --- a/od-win32/winuaechangelog.txt +++ b/od-win32/winuaechangelog.txt @@ -18,6 +18,29 @@ Things that may happen in 2015: - restore only single input target to default. +Beta 10: + +- Added CyberStormI/II/II/PPC and Blizzard PPC flash rom images to rom scanner, name based detection only. + (Remember to click ROM rescan button) Now opens usual ROM missing dialog when flash rom image can't be opened. +- Added GUI support for manual accelerator board ROM image selection. +- NCR53C770 emulation spurious interrupt fix. +- Reset/exit froze the emulation if PPC CPU was in sleeping state. +- Map ROM checkbox was checked if 128M CPU slot memory was configured (old bug). +- 68030 more compatible/CE with MMU does not use data cache anymore, 68030 caches logical addresses (which + will get really difficult and complex to emulate), 68040+ caches physical addresses. +- CyberStorm PPC/Blizzard PPC board emulation improved, PowerUP also works. +- Do not map PPC board FFF00000 memory mirror if no on-board RAM installed. +- Generate CyberStorm/BPPC fake flash rom hardware idenfication data and serial if it is missing. +- If CyberStorm MK3/PPC flash image is 256k or larger, map it like BPPC does it. (Not sure if this is correct) +- Reset with Picasso IV enabled forced hard reset. +- Z2 RTG crash fixed (some configurations). +- Added PPC GUI option to CPU panel. If ticked, selects matching board automatically. Becomes ticked and disabled + if board was already selected. 68040/060 only. (CSPPC/BPPC flash boot code uses 68040+ only instructions) +- Move PPC thread to main thread when m68k gets disabled, improves performance of native PPC operating systems. + (No need to move IO access messages between threads) +- Disable RTG board if >2M chip ram configured and Z2 RTG configured. (Forgotten address conflict check) +- OSD CPU led changes to "PPC" when PPC is active and m68k is disabled. + Beta 9: - PearPC PPC emulator core added. Only because it was very easy to add, it may not be compatible enough. @@ -40,7 +63,7 @@ Beta 9: most other HD controller drivers do, code runs directly from ROM and same memory "bank" also has IO registers) - Memory allocation source clean up. Can break nearly anything.. - SCSI CD READ CD command didn't read audio tracks 2+. -- Entering debugger forze the emulator if m68k CPU was stopped with STOP instruction and all interrupts disabled. +- Entering debugger force the emulator if m68k CPU was stopped with STOP instruction and all interrupts disabled. - NCR53C770 emulation tweaks, fixes netbsd hang. Now it gets unexpected interrupt, no fix available yet. - Version bumped to 2.9.0 diff --git a/ppc/pearpc/cpu/cpu.h b/ppc/pearpc/cpu/cpu.h index ba96934a..64d0053e 100644 --- a/ppc/pearpc/cpu/cpu.h +++ b/ppc/pearpc/cpu/cpu.h @@ -29,6 +29,7 @@ uint64 ppc_get_timebase_frequency(int cpu); bool ppc_cpu_init(uint32); void ppc_cpu_init_config(); +void ppc_cpu_free(void); void ppc_cpu_stop(); void ppc_cpu_wakeup(); @@ -42,7 +43,8 @@ void ppc_cpu_cancel_ext_exception(); * May only be called from within a CPU thread. */ -void ppc_cpu_run(); +void ppc_cpu_run_continuous(); +void ppc_cpu_run_single(int); uint32 ppc_cpu_get_gpr(int cpu, int i); void ppc_cpu_set_gpr(int cpu, int i, uint32 newvalue); void ppc_cpu_set_msr(int cpu, uint32 newvalue); diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_alu.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_alu.cpp index eceeb175..c4cd3d18 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_alu.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_alu.cpp @@ -18,7 +18,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include "debug/tracers.h" +#include "tracers.h" #include "cpu/debug.h" #include "ppc_alu.h" #include "ppc_dec.h" diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_cpu.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_cpu.cpp index 801be36a..54653568 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_cpu.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_cpu.cpp @@ -25,13 +25,12 @@ #include "system/systhread.h" #include "system/arch/sysendian.h" //#include "tools/snprintf.h" -#include "debug/tracers.h" #include "cpu/cpu.h" #include "cpu/debug.h" #include "info.h" //#include "io/pic/pic.h" //#include "debug/debugger.h" -#include "debug/tracers.h" +#include "tracers.h" #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_fpu.h" @@ -78,40 +77,43 @@ void ppc_cpu_atomic_raise_dec_exception() sys_unlock_mutex(exception_mutex); } -void ppc_cpu_wakeup() -{ -} extern int ppc_cycle_count; -void ppc_hsync_handler(void) + +static void ppc_do_dec(int val) { -#if 0 - if (!ppc_state) - return; - uint64 oldpdec = gCPU.pdec; - //gCPU.ptb += ppc_cycle_count; - gCPU.pdec -= ppc_cycle_count; - if (gCPU.pdec > oldpdec) { - ppc_wakeup(); - sys_lock_mutex(exception_mutex); + if (gCPU.pdec == 0) { gCPU.exception_pending = true; gCPU.dec_exception = true; - gCPU.pdec=(uint64)0xffffffff*TB_TO_PTB_FACTOR; - sys_unlock_mutex(exception_mutex); + gCPU.pdec = (uint64)0xffffffff * TB_TO_PTB_FACTOR; + uae_ppc_wakeup(); + } else { + uint64 oldpdec = gCPU.pdec; + gCPU.pdec -= val; + if (gCPU.pdec > oldpdec) { + gCPU.pdec = 0; + } } -#endif } -void ppc_cpu_run() +void uae_ppc_hsync_handler(void) { -// gDebugger = new Debugger(); -// gDebugger->mAlwaysShowRegs = true; - PPC_CPU_TRACE("execution started at %08x\n", gCPU.pc); - uint ops=0; - gCPU.effective_code_page = 0xffffffff; -// ppc_fpu_test(); -// return; - while (true) { + if (ppc_state != PPC_STATE_SLEEP) + return; + if (gCPU.pdec == 0) { + uae_ppc_wakeup(); + } else { + ppc_do_dec(ppc_cycle_count); + } +} + +static uint ops = 0; + +void ppc_cpu_run_single(int count) +{ + while (count != 0) { + if (count > 0) + count--; gCPU.npc = gCPU.pc+4; if ((gCPU.pc & ~0xfff) == gCPU.effective_code_page) { gCPU.current_opc = ppc_word_from_BE(*((uint32*)(&gCPU.physical_code_page[gCPU.pc & 0xfff]))); @@ -133,15 +135,7 @@ void ppc_cpu_run() ppc_exec_opc(); ops++; gCPU.ptb++; -#if 1 - if (gCPU.pdec == 0) { - gCPU.exception_pending = true; - gCPU.dec_exception = true; - gCPU.pdec=(uint64)0xffffffff*TB_TO_PTB_FACTOR; - } else { - gCPU.pdec--; - } -#endif + ppc_do_dec(1); if ((ops & 0x3ffff)==0) { /* if (pic_check_interrupt()) { gCPU.exception_pending = true; @@ -179,7 +173,7 @@ void ppc_cpu_run() extern int debugger_active, pause_emulation; extern void sleep_millis(int); - while (debugger_active || pause_emulation) { + while ((debugger_active || pause_emulation) && count < 0) { sleep_millis(10); } @@ -202,6 +196,7 @@ void ppc_cpu_run() if (gCPU.dec_exception) { ppc_exception(PPC_EXC_DEC); gCPU.dec_exception = false; + //ht_printf("pdec exp %08x\n", gCPU.pc); gCPU.pc = gCPU.npc; gCPU.exception_pending = false; sys_unlock_mutex(exception_mutex); @@ -225,6 +220,14 @@ void ppc_cpu_run() } } +void ppc_cpu_run_continuous(void) +{ + PPC_CPU_TRACE("execution started at %08x\n", gCPU.pc); + gCPU.effective_code_page = 0xffffffff; + ops = 0; + ppc_cpu_run_single(-1); +} + void ppc_cpu_stop() { sys_lock_mutex(exception_mutex); @@ -269,9 +272,15 @@ void ppc_cpu_set_msr(int cpu, uint32 newvalue) gCPU.msr = newvalue; } +// Handle as CPU reset void ppc_cpu_set_pc(int cpu, uint32 newvalue) { + gCPU.srr[0] = gCPU.pc; + gCPU.srr[1] = gCPU.msr & 0xff73; gCPU.pc = newvalue; + gCPU.msr &= MSR_ILE | MSR_ME | MSR_IP; + if (gCPU.msr & MSR_ILE) + gCPU.msr |= MSR_LE; } uint32 ppc_cpu_get_pc(int cpu) @@ -301,7 +310,7 @@ void ppc_set_singlestep_v(bool v, const char *file, int line, const char *format vsprintf(buffer, format, arg); ht_printf("%s\n", buffer); va_end(arg); - ppc_crash(); + uae_ppc_crash(); gSinglestep = v; } @@ -319,6 +328,7 @@ bool ppc_cpu_init(uint32 pvr) memset(&gCPU, 0, sizeof gCPU); gCPU.pvr = pvr; //gConfig->getConfigInt(CPU_KEY_PVR); gCPU.hid[1] = 0x80000000; + gCPU.msr = 1 << MSR_IP; ppc_dec_init(); // initialize srs (mostly for prom) @@ -335,6 +345,11 @@ bool ppc_cpu_init(uint32 pvr) return true; } +void ppc_cpu_free(void) +{ + sys_destroy_mutex(&exception_mutex); +} + #if 0 void ppc_cpu_init_config() { diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_dec.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_dec.cpp index 4d2ea08a..10606430 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_dec.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_dec.cpp @@ -89,9 +89,9 @@ static void ppc_opc_invalid() return; } #endif - ht_printf("[PPC/DEC] Bad opcode: %08x (%u:%u)\n", + ht_printf("[PPC/DEC] Bad opcode: %08x (%u:%u) PC=%08x\n", gCPU.current_opc, PPC_OPC_MAIN(gCPU.current_opc), - PPC_OPC_EXT(gCPU.current_opc)); + PPC_OPC_EXT(gCPU.current_opc), gCPU.pc); SINGLESTEP("unknown instruction\n"); } diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_exc.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_exc.cpp index abf0b8c9..359cbb34 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_exc.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_exc.cpp @@ -25,7 +25,7 @@ */ #include "tools/snprintf.h" -#include "debug/tracers.h" +#include "tracers.h" #include "cpu/debug.h" #include "info.h" #include "ppc_cpu.h" diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_fpu.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_fpu.cpp index a40a4eb3..c3937850 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_fpu.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_fpu.cpp @@ -19,7 +19,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include "debug/tracers.h" +#include "tracers.h" #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_fpu.h" diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_mmu.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_mmu.cpp index 0891ecb1..c91f2ddb 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_mmu.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_mmu.cpp @@ -29,7 +29,7 @@ #include #include "system/arch/sysendian.h" //#include "tools/snprintf.h" -#include "debug/tracers.h" +#include "tracers.h" //#include "io/prom/prom.h" #include "io/io.h" #include "ppc_cpu.h" @@ -225,12 +225,14 @@ inline int FASTCALL ppc_effective_to_physical(uint32 addr, int flags, uint32 &re // ht_printf("TLB: STORE %d: %08x -> %08x\n", gCPU.tlb_last, addr, pap); #endif // update access bits + uint32 opte = pte; if (flags & PPC_MMU_WRITE) { pte |= PTE2_C | PTE2_R; } else { pte |= PTE2_R; } - ppc_write_physical_word(pteg_addr+4, pte); + if (pte != opte) + ppc_write_physical_word(pteg_addr+4, pte); return PPC_MMU_OK; } } @@ -287,12 +289,14 @@ inline int FASTCALL ppc_effective_to_physical(uint32 addr, int flags, uint32 &re result = PTE2_RPN(pte) | offset; // update access bits + uint32 opte = pte; if (flags & PPC_MMU_WRITE) { pte |= PTE2_C | PTE2_R; } else { pte |= PTE2_R; } - ppc_write_physical_word(pteg_addr+4, pte); + if (pte != opte) + ppc_write_physical_word(pteg_addr+4, pte); // PPC_MMU_WARN("hash function 2 used!\n"); // gSinglestep = true; return PPC_MMU_OK; diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_opc.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_opc.cpp index 68ce1b36..68d07360 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_opc.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_opc.cpp @@ -19,7 +19,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include "debug/tracers.h" +#include "tracers.h" #include "cpu/debug.h" //#include "io/pic/pic.h" #include "info.h" @@ -29,7 +29,7 @@ #include "ppc_opc.h" #include "ppc_dec.h" -extern void ppc_doze(void); +extern void uae_ppc_doze(void); void ppc_set_msr(uint32 newmsr) { @@ -52,7 +52,7 @@ void ppc_set_msr(uint32 newmsr) PPC_CPU_ERR("unsupported bits in MSR set: %08x @%08x\n", newmsr & PPC_CPU_UNSUPPORTED_MSR_BITS, gCPU.pc); } if (newmsr & MSR_POW) { - ppc_doze(); + uae_ppc_doze(); // doze(); newmsr &= ~MSR_POW; } @@ -275,7 +275,8 @@ void ppc_opc_mcrfs() */ void ppc_opc_mcrxr() { - PPC_OPC_ERR("mcrxr unimplemented.\n"); + gCPU.xer = 0; //no, this is not correct + //PPC_OPC_ERR("mcrxr unimplemented.\n"); } /* * mfcr Move from Condition Register @@ -666,6 +667,7 @@ void ppc_opc_mtspr() case 22: { gCPU.dec = gCPU.gpr[rS]; gCPU.pdec = gCPU.dec; + //ht_printf("pdec = %llx %08x\n", gCPU.pdec, gCPU.pc); gCPU.pdec *= TB_TO_PTB_FACTOR; return; } diff --git a/ppc/pearpc/cpu/cpu_generic/ppc_vec.cpp b/ppc/pearpc/cpu/cpu_generic/ppc_vec.cpp index ede83b2e..4ca100b0 100644 --- a/ppc/pearpc/cpu/cpu_generic/ppc_vec.cpp +++ b/ppc/pearpc/cpu/cpu_generic/ppc_vec.cpp @@ -36,7 +36,7 @@ #define exp2(x) pow(2, x) #endif /* HAS_EXP2 */ -#include "debug/tracers.h" +#include "tracers.h" #include "ppc_cpu.h" #include "ppc_dec.h" #include "ppc_fpu.h" diff --git a/ppc/pearpc/io/io.h b/ppc/pearpc/io/io.h index 202336e4..b694e9b8 100644 --- a/ppc/pearpc/io/io.h +++ b/ppc/pearpc/io/io.h @@ -33,7 +33,7 @@ //#include "io/pci/pci.h" //#include "io/cuda/cuda.h" //#include "io/nvram/nvram.h" -#include "debug/tracers.h" +#include "tracers.h" #define IO_MEM_ACCESS_OK 0 #define IO_MEM_ACCESS_EXC 1 diff --git a/ppc/pearpc/tracers.h b/ppc/pearpc/tracers.h new file mode 100644 index 00000000..6ddd0a29 --- /dev/null +++ b/ppc/pearpc/tracers.h @@ -0,0 +1,198 @@ +/* + * PearPC + * tracers.h + * + * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __TRACERS_H__ +#define __TRACERS_H__ + +#include "system/types.h" +#include "tools/snprintf.h" + +extern void uae_ppc_crash(void); + +#define PPC_CPU_TRACE(msg, ...) ht_printf("[CPU/CPU] " msg, ##__VA_ARGS__) +#define PPC_ALU_TRACE(msg, ...) ht_printf("[CPU/ALU] " msg, ##__VA_ARGS__) +#define PPC_FPU_TRACE(msg, ...) ht_printf("[CPU/FPU] " msg, ##__VA_ARGS__) +#define PPC_DEC_TRACE(msg, ...) ht_printf("[CPU/DEC] " msg, ##__VA_ARGS__) +#define PPC_ESC_TRACE(msg, ...) ht_printf("[CPU/ESC] " msg, ##__VA_ARGS__) +//#define PPC_EXC_TRACE(msg, ...) ht_printf("[CPU/EXC] " msg, ##__VA_ARGS__) +#define PPC_MMU_TRACE(msg, ...) ht_printf("[CPU/MMU] " msg, ##__VA_ARGS__) +#define PPC_OPC_TRACE(msg, ...) ht_printf("[CPU/OPC] " msg, ##__VA_ARGS__) +//#define IO_PROM_TRACE(msg, ...) ht_printf("[IO/PROM] " msg, ##__VA_ARGS__) +//#define IO_PROM_FS_TRACE(msg, ...) ht_printf("[IO/PROM/FS] " msg, ##__VA_ARGS__) +//#define IO_3C90X_TRACE(msg, ...) ht_printf("[IO/3c90x] " msg, ##__VA_ARGS__) +//#define IO_RTL8139_TRACE(msg, ...) ht_printf("[IO/rtl8139] " msg, ##__VA_ARGS__) +//#define IO_GRAPHIC_TRACE(msg, ...) ht_printf("[IO/GCARD] " msg, ##__VA_ARGS__) +//#define IO_CUDA_TRACE(msg, ...) ht_printf("[IO/CUDA] " msg, ##__VA_ARGS__) +//#define IO_PIC_TRACE(msg, ...) ht_printf("[IO/PIC] " msg, ##__VA_ARGS__) +//#define IO_PCI_TRACE(msg, ...) ht_printf("[IO/PCI] " msg, ##__VA_ARGS__) +//#define IO_MACIO_TRACE(msg, ...) ht_printf("[IO/MACIO] " msg, ##__VA_ARGS__) +//#define IO_NVRAM_TRACE(msg, ...) ht_printf("[IO/NVRAM] " msg, ##__VA_ARGS__) +//#define IO_IDE_TRACE(msg, ...) ht_printf("[IO/IDE] " msg, ##__VA_ARGS__) +//#define IO_USB_TRACE(msg, ...) ht_printf("[IO/USB] " msg, ##__VA_ARGS__) +#define IO_SERIAL_TRACE(msg, ...) ht_printf("[IO/SERIAL] " msg, ##__VA_ARGS__) +#define IO_CORE_TRACE(msg, ...) ht_printf("[IO/Generic] " msg, ##__VA_ARGS__) + +#define PPC_CPU_WARN(msg, ...) ht_printf("[CPU/CPU] " msg, ##__VA_ARGS__) +#define PPC_ALU_WARN(msg, ...) ht_printf("[CPU/ALU] " msg, ##__VA_ARGS__) +#define PPC_FPU_WARN(msg, ...) ht_printf("[CPU/FPU] " msg, ##__VA_ARGS__) +#define PPC_DEC_WARN(msg, ...) ht_printf("[CPU/DEC] " msg, ##__VA_ARGS__) +#define PPC_ESC_WARN(msg, ...) ht_printf("[CPU/ESC] " msg, ##__VA_ARGS__) +#define PPC_EXC_WARN(msg, ...) ht_printf("[CPU/EXC] " msg, ##__VA_ARGS__) +#define PPC_MMU_WARN(msg, ...) ht_printf("[CPU/MMU] " msg, ##__VA_ARGS__) +#define PPC_OPC_WARN(msg, ...) ht_printf("[CPU/OPC] " msg, ##__VA_ARGS__) +#define IO_PROM_WARN(msg, ...) ht_printf("[IO/PROM] " msg, ##__VA_ARGS__) +#define IO_PROM_FS_WARN(msg, ...) ht_printf("[IO/PROM/FS] " msg, ##__VA_ARGS__) +#define IO_3C90X_WARN(msg, ...) ht_printf("[IO/3c90x] " msg, ##__VA_ARGS__) +#define IO_RTL8139_WARN(msg, ...) ht_printf("[IO/rtl8139] " msg, ##__VA_ARGS__) +#define IO_GRAPHIC_WARN(msg, ...) ht_printf("[IO/GCARD] " msg, ##__VA_ARGS__) +#define IO_CUDA_WARN(msg, ...) ht_printf("[IO/CUDA] " msg, ##__VA_ARGS__) +#define IO_PIC_WARN(msg, ...) ht_printf("[IO/PIC] " msg, ##__VA_ARGS__) +#define IO_PCI_WARN(msg, ...) ht_printf("[IO/PCI] " msg, ##__VA_ARGS__) +#define IO_MACIO_WARN(msg, ...) ht_printf("[IO/MACIO] " msg, ##__VA_ARGS__) +#define IO_NVRAM_WARN(msg, ...) ht_printf("[IO/NVRAM] " msg, ##__VA_ARGS__) +#define IO_IDE_WARN(msg, ...) ht_printf("[IO/IDE] " msg, ##__VA_ARGS__) +#define IO_USB_WARN(msg, ...) ht_printf("[IO/USB] " msg, ##__VA_ARGS__) +#define IO_SERIAL_WARN(msg, ...) ht_printf("[IO/SERIAL] " msg, ##__VA_ARGS__) +#define IO_CORE_WARN(msg, ...) ht_printf("[IO/Generic] " msg, ##__VA_ARGS__) + +#define PPC_CPU_ERR(msg, ...) {ht_printf("[CPU/CPU] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_ALU_ERR(msg, ...) {ht_printf("[CPU/ALU] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_FPU_ERR(msg, ...) {ht_printf("[CPU/FPU] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_DEC_ERR(msg, ...) {ht_printf("[CPU/DEC] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_ESC_ERR(msg, ...) {ht_printf("[CPU/ESC] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_EXC_ERR(msg, ...) {ht_printf("[CPU/EXC] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_MMU_ERR(msg, ...) {ht_printf("[CPU/MMU] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define PPC_OPC_ERR(msg, ...) {ht_printf("[CPU/OPC] " msg, ##__VA_ARGS__); } +#define IO_PROM_ERR(msg, ...) {ht_printf("[IO/PROM] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_PROM_FS_ERR(msg, ...) {ht_printf("[IO/PROM/FS] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_3C90X_ERR(msg, ...) {ht_printf("[IO/3c90x] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_RTL8139_ERR(msg, ...) {ht_printf("[IO/rtl8139] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_GRAPHIC_ERR(msg, ...) {ht_printf("[IO/GCARD] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_CUDA_ERR(msg, ...) {ht_printf("[IO/CUDA] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_PIC_ERR(msg, ...) {ht_printf("[IO/PIC] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_PCI_ERR(msg, ...) {ht_printf("[IO/PCI] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_MACIO_ERR(msg, ...) {ht_printf("[IO/MACIO] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_NVRAM_ERR(msg, ...) {ht_printf("[IO/NVRAM] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_IDE_ERR(msg, ...) {ht_printf("[IO/IDE] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_USB_ERR(msg, ...) {ht_printf("[IO/IDE] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_SERIAL_ERR(msg, ...) {ht_printf("[IO/SERIAL] " msg, ##__VA_ARGS__); uae_ppc_crash(); } +#define IO_CORE_ERR(msg, ...) {ht_printf("[IO/Generic] " msg, ##__VA_ARGS__); uae_ppc_crash(); } + +/* + * + */ +#ifndef PPC_CPU_TRACE +#define PPC_CPU_TRACE(msg, ...) +#endif + +#ifndef PPC_ALU_TRACE +#define PPC_ALU_TRACE(msg, ...) +#endif + +#ifndef PPC_FPU_TRACE +#define PPC_FPU_TRACE(msg, ...) +#endif + +#ifndef PPC_DEC_TRACE +#define PPC_DEC_TRACE(msg, ...) +#endif + +#ifndef PPC_EXC_TRACE +#define PPC_EXC_TRACE(msg, ...) +#endif + +#ifndef PPC_ESC_TRACE +#define PPC_ESC_TRACE(msg, ...) +#endif + +#ifndef PPC_MMU_TRACE +#define PPC_MMU_TRACE(msg, ...) +#endif + +#ifndef PPC_OPC_TRACE +#define PPC_OPC_TRACE(msg, ...) +#endif + +#ifndef PPC_OPC_WARN +#define PPC_OPC_WARN(msg, ...) +#endif + +#ifndef IO_PROM_TRACE +#define IO_PROM_TRACE(msg, ...) +#endif + +#ifndef IO_PROM_FS_TRACE +#define IO_PROM_FS_TRACE(msg, ...) +#endif + +#ifndef IO_GRAPHIC_TRACE +#define IO_GRAPHIC_TRACE(msg, ...) +#endif + +#ifndef IO_CUDA_TRACE +#define IO_CUDA_TRACE(msg, ...) +#endif + +#ifndef IO_PIC_TRACE +#define IO_PIC_TRACE(msg, ...) +#endif + +#ifndef IO_PCI_TRACE +#define IO_PCI_TRACE(msg, ...) +#endif + +#ifndef IO_MACIO_TRACE +#define IO_MACIO_TRACE(msg, ...) +#endif + +#ifndef IO_ISA_TRACE +#define IO_ISA_TRACE(msg, ...) +#endif + +#ifndef IO_IDE_TRACE +#define IO_IDE_TRACE(msg, ...) +#endif + +#ifndef IO_CORE_TRACE +#define IO_CORE_TRACE(msg, ...) +#endif + +#ifndef IO_NVRAM_TRACE +#define IO_NVRAM_TRACE(msg, ...) +#endif + +#ifndef IO_USB_TRACE +#define IO_USB_TRACE(msg, ...) +#endif + +#ifndef IO_SERIAL_TRACE +#define IO_SERIAL_TRACE(msg, ...) +#endif + +#ifndef IO_3C90X_TRACE +#define IO_3C90X_TRACE(msg, ...) +#endif + +#ifndef IO_RTL8139_TRACE +#define IO_RTL8139_TRACE(msg, ...) +#endif + +#endif + diff --git a/ppc/ppc.cpp b/ppc/ppc.cpp index 400e82d0..57d0459d 100644 --- a/ppc/ppc.cpp +++ b/ppc/ppc.cpp @@ -18,25 +18,38 @@ volatile int ppc_state; -static bool ppc_thread_running; +static volatile bool ppc_thread_running; static smp_comm_pipe ppcrequests, ppcreturn; static smp_comm_pipe ppcquery, ppcreply; int ppc_cycle_count; +static volatile bool ppc_access; +static volatile int ppc_cpu_lock_state; +static bool ppc_main_thread; +static bool ppc_init_done; #define CSPPC_PVR 0x00090204 #define BLIZZPPC_PVR 0x00070101 +static void uae_ppc_cpu_reset(void) +{ + if (!ppc_init_done) { + ppc_cpu_init(currprefs.cpuboard_type == BOARD_BLIZZARDPPC ? BLIZZPPC_PVR : CSPPC_PVR); + ppc_init_done = true; + } + ppc_cpu_set_pc(0, 0xfff00100); + ppc_cycle_count = 2000; + ppc_state = PPC_STATE_ACTIVE; + ppc_cpu_lock_state = 0; +} + static void *ppc_thread(void *v) { for (;;) { uae_u32 v = read_comm_pipe_u32_blocking(&ppcrequests); - if (v == 0xfffffff) + if (v == 0xffffffff) break; - ppc_cpu_init(currprefs.cpuboard_type == BOARD_BLIZZARDPPC ? BLIZZPPC_PVR : CSPPC_PVR); - ppc_cpu_set_pc(0, 0xfff00100); - ppc_cycle_count = 240000000 / (hblank_hz * 4); - ppc_state = PPC_STATE_ACTIVE; - ppc_cpu_run(); + uae_ppc_cpu_reset(); + ppc_cpu_run_continuous(); if (ppc_state == PPC_STATE_ACTIVE || ppc_state == PPC_STATE_SLEEP) ppc_state = PPC_STATE_STOP; write_log(_T("ppc_cpu_run() exited.\n")); @@ -47,9 +60,36 @@ static void *ppc_thread(void *v) return NULL; } -void uae_ppc_poll_queue(void) +void uae_ppc_to_main_thread(void) { + if (ppc_thread_running) { + write_log(_T("PPC: transferring PPC emulation to main thread.\n")); + uae_ppc_cpu_stop(); + write_comm_pipe_u32(&ppcrequests, 0xffffffff, 1); + while (ppc_thread_running) + sleep_millis(2); + while (comm_pipe_has_data(&ppcquery)) + uae_ppc_poll_queue(); + write_log(_T("PPC: transfer complete.\n")); + } + ppc_state = PPC_STATE_ACTIVE; + ppc_main_thread = true; +} + +void uae_ppc_emulate(void) +{ + if (ppc_state == PPC_STATE_ACTIVE || ppc_state == PPC_STATE_SLEEP) + ppc_cpu_run_single(10); +} + +bool uae_ppc_poll_queue(void) +{ + // ppc locked? + if (ppc_cpu_lock_state < 0) + return false; + if (comm_pipe_has_data(&ppcquery)) { + ppc_access = true; uae_u32 addr = read_comm_pipe_u32_blocking(&ppcquery); uae_u32 size = read_comm_pipe_u32_blocking(&ppcquery); uae_u32 data = 0, data2 = 0; @@ -99,12 +139,16 @@ void uae_ppc_poll_queue(void) write_comm_pipe_u32(&ppcreply, data2, 0); write_comm_pipe_u32(&ppcreply, data, 1); } + ppc_access = false; } + if (ppc_cpu_lock_state > 0) + return true; + return false; } void uae_ppc_sync (void) { - while (comm_pipe_has_data(&ppcquery)); + while (ppc_thread_running && comm_pipe_has_data(&ppcquery)); } bool uae_ppc_direct_physical_memory_handle(uint32 addr, byte *&ptr) @@ -118,7 +162,9 @@ bool uae_ppc_direct_physical_memory_handle(uint32 addr, byte *&ptr) bool uae_ppc_io_mem_write(uint32 addr, uint32 data, int size) { - if (!valid_address(addr, size)) { + while (ppc_thread_running && ppc_cpu_lock_state < 0 && ppc_state); + + if (ppc_thread_running && !valid_address(addr, size)) { write_comm_pipe_u32(&ppcquery, addr, 0); write_comm_pipe_u32(&ppcquery, size | 0x80, 0); write_comm_pipe_u32(&ppcquery, data, 1); @@ -132,6 +178,11 @@ bool uae_ppc_io_mem_write(uint32 addr, uint32 data, int size) #endif return true; } +#if PPC_ACCESS_LOG > 0 + if (!ppc_thread_running && !valid_address(addr, size)) { + write_log(_T("PPC io write %08x = %08x %d\n"), addr, data, size); + } +#endif switch (size) { case 4: @@ -157,7 +208,9 @@ bool uae_ppc_io_mem_read(uint32 addr, uint32 &data, int size) { uint32 v; - if (!valid_address(addr, size)) { + while (ppc_thread_running && ppc_cpu_lock_state < 0 && ppc_state); + + if (ppc_thread_running && !valid_address(addr, size)) { write_comm_pipe_u32(&ppcquery, addr, 0); write_comm_pipe_u32(&ppcquery, size, 1); v = read_comm_pipe_u32_blocking(&ppcreply); @@ -168,7 +221,11 @@ bool uae_ppc_io_mem_read(uint32 addr, uint32 &data, int size) data = v; return true; } - +#if PPC_ACCESS_LOG > 0 + if (!ppc_thread_running && !valid_address(addr, size)) { + write_log(_T("PPC io read %08x=%08x %d\n"), addr, v, size); + } +#endif switch (size) { case 4: @@ -194,7 +251,9 @@ bool uae_ppc_io_mem_read(uint32 addr, uint32 &data, int size) bool uae_ppc_io_mem_write64(uint32 addr, uint64 data) { - if (!valid_address(addr, 8)) { + while (ppc_thread_running && ppc_cpu_lock_state < 0 && ppc_state); + + if (ppc_thread_running && !valid_address(addr, 8)) { #if PPC_ACCESS_LOG > 0 write_log(_T("PPC io write64 %08x = %08llx\n"), addr, data); #endif @@ -220,7 +279,10 @@ bool uae_ppc_io_mem_write64(uint32 addr, uint64 data) bool uae_ppc_io_mem_read64(uint32 addr, uint64 &data) { uae_u32 v1, v2; - if (!valid_address(addr, 8)) { + + while (ppc_thread_running && ppc_cpu_lock_state < 0 && ppc_state); + + if (ppc_thread_running && !valid_address(addr, 8)) { write_comm_pipe_u32(&ppcquery, addr, 0); write_comm_pipe_u32(&ppcquery, 8, 0); v1 = read_comm_pipe_u32_blocking(&ppcreply); @@ -240,14 +302,14 @@ bool uae_ppc_io_mem_read64(uint32 addr, uint64 &data) return true; } -void ppc_stop(void) +void uae_ppc_cpu_stop(void) { if (ppc_thread_running && ppc_state) { - if (ppc_state == PPC_STATE_SLEEP) - ppc_state = PPC_STATE_ACTIVE; write_log(_T("Stopping PPC.\n")); + uae_ppc_wakeup(); ppc_cpu_stop(); while (ppc_state != PPC_STATE_STOP && ppc_state != PPC_STATE_CRASH) { + uae_ppc_wakeup(); uae_ppc_poll_queue(); } read_comm_pipe_u32_blocking(&ppcreturn); @@ -255,21 +317,56 @@ void ppc_stop(void) } } -void ppc_reboot(void) +void uae_ppc_cpu_reboot(void) +{ + if (ppc_main_thread) { + uae_ppc_cpu_reset(); + } else { + write_log(_T("Starting PPC thread.\n")); + if (!ppc_thread_running) { + ppc_thread_running = true; + ppc_main_thread = false; + init_comm_pipe(&ppcrequests, 10, 1); + init_comm_pipe(&ppcreturn, 10, 1); + init_comm_pipe(&ppcreply, 100, 1); + init_comm_pipe(&ppcquery, 100, 1); + uae_start_thread(_T("ppc"), ppc_thread, NULL, NULL); + } + write_comm_pipe_u32(&ppcrequests, 1, 1); + } +} + +void uae_ppc_reset(bool hardreset) +{ + uae_ppc_cpu_stop(); + ppc_main_thread = false; + if (hardreset) { + if (ppc_init_done) + ppc_cpu_free(); + ppc_init_done = false; + } +} + +void uae_ppc_cpu_lock(void) { - write_log(_T("Starting PPC thread.\n")); - if (!ppc_thread_running) { - ppc_thread_running = true; - init_comm_pipe(&ppcrequests, 10, 1); - init_comm_pipe(&ppcreturn, 10, 1); - init_comm_pipe(&ppcreply, 100, 1); - init_comm_pipe(&ppcquery, 100, 1); - uae_start_thread(_T("ppc"), ppc_thread, NULL, NULL); + // when called, lock was already set by other CPU + if (ppc_access) { + // ppc accessing but m68k already locked + ppc_cpu_lock_state = -1; + } else { + // m68k accessing but ppc already locked + ppc_cpu_lock_state = 1; } - write_comm_pipe_u32(&ppcrequests, 1, 1); +} +bool uae_ppc_cpu_unlock(void) +{ + if (!ppc_cpu_lock_state) + return true; + ppc_cpu_lock_state = 0; + return false; } -void ppc_wakeup(void) +void uae_ppc_wakeup(void) { if (ppc_state == PPC_STATE_SLEEP) ppc_state = PPC_STATE_ACTIVE; @@ -278,11 +375,11 @@ void ppc_wakeup(void) void ppc_cpu_atomic_raise_ext_exception(void); void ppc_cpu_atomic_cancel_ext_exception(void); -void ppc_interrupt(bool active) +void uae_ppc_interrupt(bool active) { if (active) { ppc_cpu_atomic_raise_ext_exception(); - ppc_wakeup(); + uae_ppc_wakeup(); } else { ppc_cpu_atomic_cancel_ext_exception(); } @@ -290,15 +387,17 @@ void ppc_interrupt(bool active) // sleep until interrupt (or PPC stopped) -void ppc_doze(void) +void uae_ppc_doze(void) { + if (!ppc_thread_running) + return; ppc_state = PPC_STATE_SLEEP; while (ppc_state == PPC_STATE_SLEEP) { sleep_millis(2); } } -void ppc_crash(void) +void uae_ppc_crash(void) { ppc_state = PPC_STATE_CRASH; ppc_cpu_stop(); @@ -321,3 +420,8 @@ int sys_create_mutex(sys_mutex *m) uae_sem_init(m, 0, 1); return 1; } + +void sys_destroy_mutex(sys_mutex m) +{ + uae_sem_destroy(&m); +} \ No newline at end of file diff --git a/qemuvga/lsi53c710.cpp b/qemuvga/lsi53c710.cpp index 51967bc8..4c02bf00 100644 --- a/qemuvga/lsi53c710.cpp +++ b/qemuvga/lsi53c710.cpp @@ -267,24 +267,24 @@ typedef struct { uint8_t dwt; uint8_t sbcl; uint8_t script_active; -} LSIState; +} LSIState710; //#define TYPE_LSI53C810 "lsi53c810" //#define TYPE_LSI53C895A "lsi53c895a" -#define LSI53C895A(obj) (LSIState*)obj->lsistate - //((LSIState*)(OBJECT_CHECK(LSIState, (obj), TYPE_LSI53C895A))) +#define LSI53C895A(obj) (LSIState710*)obj->lsistate + //((LSIState710*)(OBJECT_CHECK(LSIState710, (obj), TYPE_LSI53C895A))) -static inline int lsi_irq_on_rsl(LSIState *s) +static inline int lsi_irq_on_rsl(LSIState710 *s) { return 0; //return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); } -static void lsi_soft_reset(LSIState *s) +static void lsi_soft_reset(LSIState710 *s) { DPRINTF("Reset\n"); s->carry = 0; - memset (s, 0, sizeof(LSIState)); + memset (s, 0, sizeof(LSIState710)); s->msg_action = 0; s->msg_len = 0; @@ -327,21 +327,21 @@ static void lsi_soft_reset(LSIState *s) } #if 0 -static int lsi_dma_40bit(LSIState *s) +static int lsi_dma_40bit(LSIState710 *s) { if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT) return 1; return 0; } -static int lsi_dma_ti64bit(LSIState *s) +static int lsi_dma_ti64bit(LSIState710 *s) { if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV) return 1; return 0; } -static int lsi_dma_64bit(LSIState *s) +static int lsi_dma_64bit(LSIState710 *s) { if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV) return 1; @@ -349,12 +349,12 @@ static int lsi_dma_64bit(LSIState *s) } #endif -static uint8_t lsi_reg_readb(LSIState *s, int offset); -static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val); -static void lsi_execute_script(LSIState *s); -static void lsi_reselect(LSIState *s, lsi_request *p); +static uint8_t lsi_reg_readb(LSIState710 *s, int offset); +static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val); +static void lsi_execute_script(LSIState710 *s); +static void lsi_reselect(LSIState710 *s, lsi_request *p); -static inline uint32_t read_dword(LSIState *s, uint32_t addr) +static inline uint32_t read_dword(LSIState710 *s, uint32_t addr) { uint32_t buf; @@ -362,12 +362,12 @@ static inline uint32_t read_dword(LSIState *s, uint32_t addr) return cpu_to_le32(buf); } -static void lsi_stop_script(LSIState *s) +static void lsi_stop_script(LSIState710 *s) { s->script_active = 0; } -static void lsi_update_irq(LSIState *s) +static void lsi_update_irq(LSIState710 *s) { PCIDevice *d = PCI_DEVICE(s); int level; @@ -414,7 +414,7 @@ static void lsi_update_irq(LSIState *s) } /* Stop SCRIPTS execution and raise a SCSI interrupt. */ -static void lsi_script_scsi_interrupt(LSIState *s, int stat0) +static void lsi_script_scsi_interrupt(LSIState710 *s, int stat0) { uint32_t mask0; //uint32_t mask1; @@ -436,7 +436,7 @@ static void lsi_script_scsi_interrupt(LSIState *s, int stat0) } /* Stop SCRIPTS execution and raise a DMA interrupt. */ -static void lsi_script_dma_interrupt(LSIState *s, int stat) +static void lsi_script_dma_interrupt(LSIState710 *s, int stat) { DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat); s->dstat |= stat; @@ -444,7 +444,7 @@ static void lsi_script_dma_interrupt(LSIState *s, int stat) lsi_stop_script(s); } -static inline void lsi_set_phase(LSIState *s, int phase) +static inline void lsi_set_phase(LSIState710 *s, int phase) { s->sstat2 = (s->sstat2 & ~PHASE_MASK) | phase; s->ctest0 &= ~1; @@ -453,7 +453,7 @@ static inline void lsi_set_phase(LSIState *s, int phase) s->sbcl &= ~LSI_SBCL_REQ; } -static void lsi_bad_phase(LSIState *s, int out, int new_phase) +static void lsi_bad_phase(LSIState710 *s, int out, int new_phase) { /* Trigger a phase mismatch. */ DPRINTF("Phase mismatch interrupt\n"); @@ -465,7 +465,7 @@ static void lsi_bad_phase(LSIState *s, int out, int new_phase) /* Resume SCRIPTS execution after a DMA operation. */ -static void lsi_resume_script(LSIState *s) +static void lsi_resume_script(LSIState710 *s) { if (s->waiting != 2) { s->waiting = 0; @@ -475,13 +475,13 @@ static void lsi_resume_script(LSIState *s) } } -static void lsi_disconnect(LSIState *s) +static void lsi_disconnect(LSIState710 *s) { s->scntl1 &= ~LSI_SCNTL1_CON; s->sstat2 &= ~PHASE_MASK; } -static void lsi_bad_selection(LSIState *s, uint32_t id) +static void lsi_bad_selection(LSIState710 *s, uint32_t id) { DPRINTF("Selected absent target %d\n", id); lsi_script_scsi_interrupt(s, LSI_SSTAT0_STO); @@ -489,7 +489,7 @@ static void lsi_bad_selection(LSIState *s, uint32_t id) } /* Initiate a SCSI layer data transfer. */ -static void lsi_do_dma(LSIState *s, int out) +static void lsi_do_dma(LSIState710 *s, int out) { PCIDevice *pci_dev; uint32_t count; @@ -546,7 +546,7 @@ static void lsi_do_dma(LSIState *s, int out) /* Add a command to the queue. */ -static void lsi_queue_command(LSIState *s) +static void lsi_queue_command(LSIState710 *s) { lsi_request *p = s->current; @@ -561,7 +561,7 @@ static void lsi_queue_command(LSIState *s) } /* Queue a byte for a MSG IN phase. */ -static void lsi_add_msg_byte(LSIState *s, uint8_t data) +static void lsi_add_msg_byte(LSIState710 *s, uint8_t data) { if (s->msg_len >= LSI_MAX_MSGIN_LEN) { BADF("MSG IN data too long\n"); @@ -572,7 +572,7 @@ static void lsi_add_msg_byte(LSIState *s, uint8_t data) } /* Perform reselection to continue a command. */ -static void lsi_reselect(LSIState *s, lsi_request *p) +static void lsi_reselect(LSIState710 *s, lsi_request *p) { int id; @@ -602,7 +602,7 @@ static void lsi_reselect(LSIState *s, lsi_request *p) } } -static lsi_request *lsi_find_by_tag(LSIState *s, uint32_t tag) +static lsi_request *lsi_find_by_tag(LSIState710 *s, uint32_t tag) { lsi_request *p; @@ -615,7 +615,7 @@ static lsi_request *lsi_find_by_tag(LSIState *s, uint32_t tag) return NULL; } -static void lsi_request_free(LSIState *s, lsi_request *p) +static void lsi_request_free(LSIState710 *s, lsi_request *p) { if (p == s->current) { s->current = NULL; @@ -627,7 +627,7 @@ static void lsi_request_free(LSIState *s, lsi_request *p) void lsi710_request_cancelled(SCSIRequest *req) { - LSIState *s = LSI53C895A(req->bus->qbus.parent); + LSIState710 *s = LSI53C895A(req->bus->qbus.parent); lsi_request *p = (lsi_request*)req->hba_private; req->hba_private = NULL; @@ -637,7 +637,7 @@ void lsi710_request_cancelled(SCSIRequest *req) /* Record that data is available for a queued command. Returns zero if the device was reselected, nonzero if the IO is deferred. */ -static int lsi_queue_req(LSIState *s, SCSIRequest *req, uint32_t len) +static int lsi_queue_req(LSIState710 *s, SCSIRequest *req, uint32_t len) { lsi_request *p = (lsi_request*)req->hba_private; @@ -666,7 +666,7 @@ static int lsi_queue_req(LSIState *s, SCSIRequest *req, uint32_t len) /* Callback to indicate that the SCSI layer has completed a command. */ void lsi710_command_complete(SCSIRequest *req, uint32_t status, size_t resid) { - LSIState *s = LSI53C895A(req->bus->qbus.parent); + LSIState710 *s = LSI53C895A(req->bus->qbus.parent); int out; out = (s->sstat2 & PHASE_MASK) == PHASE_DO; @@ -692,7 +692,7 @@ void lsi710_command_complete(SCSIRequest *req, uint32_t status, size_t resid) /* Callback to indicate that the SCSI layer has completed a transfer. */ void lsi710_transfer_data(SCSIRequest *req, uint32_t len) { - LSIState *s = LSI53C895A(req->bus->qbus.parent); + LSIState710 *s = LSI53C895A(req->bus->qbus.parent); int out; assert(req->hba_private); @@ -730,7 +730,7 @@ static int idbitstonum(int id) return num; } -static void lsi_do_command(LSIState *s) +static void lsi_do_command(LSIState710 *s) { SCSIDevice *dev; uint8_t buf[16]; @@ -783,7 +783,7 @@ static void lsi_do_command(LSIState *s) } } -static void lsi_do_status(LSIState *s) +static void lsi_do_status(LSIState710 *s) { uint8_t status; DPRINTF("Get status len=%d status=%d\n", s->dbc, s->status); @@ -798,7 +798,7 @@ static void lsi_do_status(LSIState *s) lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */ } -static void lsi_do_msgin(LSIState *s) +static void lsi_do_msgin(LSIState710 *s) { int len; DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len); @@ -835,7 +835,7 @@ static void lsi_do_msgin(LSIState *s) } /* Read the next byte during a MSGOUT phase. */ -static uint8_t lsi_get_msgbyte(LSIState *s) +static uint8_t lsi_get_msgbyte(LSIState710 *s) { uint8_t data; pci710_dma_read(PCI_DEVICE(s), s->dnad, &data, 1); @@ -845,13 +845,13 @@ static uint8_t lsi_get_msgbyte(LSIState *s) } /* Skip the next n bytes during a MSGOUT phase. */ -static void lsi_skip_msgbytes(LSIState *s, unsigned int n) +static void lsi_skip_msgbytes(LSIState710 *s, unsigned int n) { s->dnad += n; s->dbc -= n; } -static void lsi_do_msgout(LSIState *s) +static void lsi_do_msgout(LSIState710 *s) { uint8_t msg; int len; @@ -976,7 +976,7 @@ bad: } #define LSI_BUF_SIZE 4096 -static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count) +static void lsi_memcpy(LSIState710 *s, uint32_t dest, uint32_t src, int count) { PCIDevice *d = PCI_DEVICE(s); int n; @@ -993,7 +993,7 @@ static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count) } } -static void lsi_wait_reselect(LSIState *s) +static void lsi_wait_reselect(LSIState710 *s) { lsi_request *p; @@ -1010,7 +1010,7 @@ static void lsi_wait_reselect(LSIState *s) } } -static void lsi_execute_script(LSIState *s) +static void lsi_execute_script(LSIState710 *s) { PCIDevice *pci_dev = PCI_DEVICE(s); uint32_t insn; @@ -1456,7 +1456,7 @@ again: } #if 0 -static uint8_t lsi_reg_readb(LSIState *s, int offset) +static uint8_t lsi_reg_readb(LSIState710 *s, int offset) { uint8_t tmp; #define CASE_GET_REG24(name, addr) \ @@ -1631,7 +1631,7 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) } #endif -static uint8_t lsi_reg_readb2(LSIState *s, int offset) +static uint8_t lsi_reg_readb2(LSIState710 *s, int offset) { uint8_t tmp; #define CASE_GET_REG24(name, addr) \ @@ -1740,7 +1740,7 @@ static uint8_t lsi_reg_readb2(LSIState *s, int offset) write_log ("read unknown register %02X\n", offset); return 0; } -static uint8_t lsi_reg_readb(LSIState *s, int offset) +static uint8_t lsi_reg_readb(LSIState710 *s, int offset) { uint8_t v = lsi_reg_readb2(s, offset); #ifdef DEBUG_LSI_REG @@ -1749,7 +1749,7 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) return v; } -static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) +static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val) { #define CASE_SET_REG24(name, addr) \ case addr : s->name &= 0xffffff00; s->name |= val; break; \ @@ -1902,7 +1902,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) } #if 0 -static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) +static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val) { #define CASE_SET_REG24(name, addr) \ case addr : s->name &= 0xffffff00; s->name |= val; break; \ @@ -2143,7 +2143,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) void lsi710_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - LSIState *s = (LSIState*)opaque; + LSIState710 *s = (LSIState710*)opaque; lsi_reg_writeb(s, addr & 0xff, val); } @@ -2151,7 +2151,7 @@ void lsi710_mmio_write(void *opaque, hwaddr addr, uint64_t lsi710_mmio_read(void *opaque, hwaddr addr, unsigned size) { - LSIState *s = (LSIState*)opaque; + LSIState710 *s = (LSIState710*)opaque; return lsi_reg_readb(s, addr & 0xff); } @@ -2170,7 +2170,7 @@ static const MemoryRegionOps lsi_mmio_ops = { static void lsi_ram_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - LSIState *s = (LSIState*)opaque; + LSIState710 *s = (LSIState710*)opaque; uint32_t newval; uint32_t mask; int shift; @@ -2186,7 +2186,7 @@ static void lsi_ram_write(void *opaque, hwaddr addr, static uint64_t lsi_ram_read(void *opaque, hwaddr addr, unsigned size) { - LSIState *s = (LSIState*)opaque; + LSIState710 *s = (LSIState710*)opaque; uint32_t val; uint32_t mask; @@ -2205,14 +2205,14 @@ static const MemoryRegionOps lsi_ram_ops = { static uint64_t lsi_io_read(void *opaque, hwaddr addr, unsigned size) { - LSIState *s = (LSIState*)opaque; + LSIState710 *s = (LSIState710*)opaque; return lsi_reg_readb(s, addr & 0xff); } static void lsi_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - LSIState *s = (LSIState*)opaque; + LSIState710 *s = (LSIState710*)opaque; lsi_reg_writeb(s, addr & 0xff, val); } @@ -2229,7 +2229,7 @@ static const MemoryRegionOps lsi_io_ops = { void lsi710_scsi_reset(DeviceState *dev, void *privdata) { - LSIState *s = LSI53C895A(dev); + LSIState710 *s = LSI53C895A(dev); lsi_soft_reset(s); s->bus.privdata = privdata; @@ -2237,13 +2237,13 @@ void lsi710_scsi_reset(DeviceState *dev, void *privdata) void lsi710_scsi_init(DeviceState *dev) { - dev->lsistate = calloc (sizeof(LSIState), 1); + dev->lsistate = calloc (sizeof(LSIState710), 1); } #if 0 static void lsi_pre_save(void *opaque) { - LSIState *s = opaque; + LSIState710 *s = opaque; if (s->current) { assert(s->current->dma_buf == NULL); @@ -2259,85 +2259,85 @@ static const VMStateDescription vmstate_lsi_scsi = { .minimum_version_id_old = 0, .pre_save = lsi_pre_save, .fields = (VMStateField []) { - VMSTATE_PCI_DEVICE(parent_obj, LSIState), - - VMSTATE_INT32(carry, LSIState), - VMSTATE_INT32(status, LSIState), - VMSTATE_INT32(msg_action, LSIState), - VMSTATE_INT32(msg_len, LSIState), - VMSTATE_BUFFER(msg, LSIState), - VMSTATE_INT32(waiting, LSIState), - - VMSTATE_UINT32(dsa, LSIState), - VMSTATE_UINT32(temp, LSIState), - VMSTATE_UINT32(dnad, LSIState), - VMSTATE_UINT32(dbc, LSIState), - VMSTATE_UINT8(istat0, LSIState), - VMSTATE_UINT8(istat1, LSIState), - VMSTATE_UINT8(dcmd, LSIState), - VMSTATE_UINT8(dstat, LSIState), - VMSTATE_UINT8(dien, LSIState), - VMSTATE_UINT8(sist0, LSIState), - VMSTATE_UINT8(sist1, LSIState), - VMSTATE_UINT8(sien0, LSIState), - VMSTATE_UINT8(sien1, LSIState), - VMSTATE_UINT8(mbox0, LSIState), - VMSTATE_UINT8(mbox1, LSIState), - VMSTATE_UINT8(dfifo, LSIState), - VMSTATE_UINT8(ctest2, LSIState), - VMSTATE_UINT8(ctest3, LSIState), - VMSTATE_UINT8(ctest4, LSIState), - VMSTATE_UINT8(ctest5, LSIState), - VMSTATE_UINT8(ccntl0, LSIState), - VMSTATE_UINT8(ccntl1, LSIState), - VMSTATE_UINT32(dsp, LSIState), - VMSTATE_UINT32(dsps, LSIState), - VMSTATE_UINT8(dmode, LSIState), - VMSTATE_UINT8(dcntl, LSIState), - VMSTATE_UINT8(scntl0, LSIState), - VMSTATE_UINT8(scntl1, LSIState), - VMSTATE_UINT8(scntl2, LSIState), - VMSTATE_UINT8(scntl3, LSIState), - VMSTATE_UINT8(sstat0, LSIState), - VMSTATE_UINT8(sstat1, LSIState), - VMSTATE_UINT8(scid, LSIState), - VMSTATE_UINT8(sxfer, LSIState), - VMSTATE_UINT8(socl, LSIState), - VMSTATE_UINT8(sdid, LSIState), - VMSTATE_UINT8(ssid, LSIState), - VMSTATE_UINT8(sfbr, LSIState), - VMSTATE_UINT8(stest1, LSIState), - VMSTATE_UINT8(stest2, LSIState), - VMSTATE_UINT8(stest3, LSIState), - VMSTATE_UINT8(sidl, LSIState), - VMSTATE_UINT8(stime0, LSIState), - VMSTATE_UINT8(respid0, LSIState), - VMSTATE_UINT8(respid1, LSIState), - VMSTATE_UINT32(mmrs, LSIState), - VMSTATE_UINT32(mmws, LSIState), - VMSTATE_UINT32(sfs, LSIState), - VMSTATE_UINT32(drs, LSIState), - VMSTATE_UINT32(sbms, LSIState), - VMSTATE_UINT32(dbms, LSIState), - VMSTATE_UINT32(dnad64, LSIState), - VMSTATE_UINT32(pmjad1, LSIState), - VMSTATE_UINT32(pmjad2, LSIState), - VMSTATE_UINT32(rbc, LSIState), - VMSTATE_UINT32(ua, LSIState), - VMSTATE_UINT32(ia, LSIState), - VMSTATE_UINT32(sbc, LSIState), - VMSTATE_UINT32(csbc, LSIState), - VMSTATE_BUFFER_UNSAFE(scratch, LSIState, 0, 18 * sizeof(uint32_t)), - VMSTATE_UINT8(sbr, LSIState), - - VMSTATE_BUFFER_UNSAFE(script_ram, LSIState, 0, 2048 * sizeof(uint32_t)), + VMSTATE_PCI_DEVICE(parent_obj, LSIState710), + + VMSTATE_INT32(carry, LSIState710), + VMSTATE_INT32(status, LSIState710), + VMSTATE_INT32(msg_action, LSIState710), + VMSTATE_INT32(msg_len, LSIState710), + VMSTATE_BUFFER(msg, LSIState710), + VMSTATE_INT32(waiting, LSIState710), + + VMSTATE_UINT32(dsa, LSIState710), + VMSTATE_UINT32(temp, LSIState710), + VMSTATE_UINT32(dnad, LSIState710), + VMSTATE_UINT32(dbc, LSIState710), + VMSTATE_UINT8(istat0, LSIState710), + VMSTATE_UINT8(istat1, LSIState710), + VMSTATE_UINT8(dcmd, LSIState710), + VMSTATE_UINT8(dstat, LSIState710), + VMSTATE_UINT8(dien, LSIState710), + VMSTATE_UINT8(sist0, LSIState710), + VMSTATE_UINT8(sist1, LSIState710), + VMSTATE_UINT8(sien0, LSIState710), + VMSTATE_UINT8(sien1, LSIState710), + VMSTATE_UINT8(mbox0, LSIState710), + VMSTATE_UINT8(mbox1, LSIState710), + VMSTATE_UINT8(dfifo, LSIState710), + VMSTATE_UINT8(ctest2, LSIState710), + VMSTATE_UINT8(ctest3, LSIState710), + VMSTATE_UINT8(ctest4, LSIState710), + VMSTATE_UINT8(ctest5, LSIState710), + VMSTATE_UINT8(ccntl0, LSIState710), + VMSTATE_UINT8(ccntl1, LSIState710), + VMSTATE_UINT32(dsp, LSIState710), + VMSTATE_UINT32(dsps, LSIState710), + VMSTATE_UINT8(dmode, LSIState710), + VMSTATE_UINT8(dcntl, LSIState710), + VMSTATE_UINT8(scntl0, LSIState710), + VMSTATE_UINT8(scntl1, LSIState710), + VMSTATE_UINT8(scntl2, LSIState710), + VMSTATE_UINT8(scntl3, LSIState710), + VMSTATE_UINT8(sstat0, LSIState710), + VMSTATE_UINT8(sstat1, LSIState710), + VMSTATE_UINT8(scid, LSIState710), + VMSTATE_UINT8(sxfer, LSIState710), + VMSTATE_UINT8(socl, LSIState710), + VMSTATE_UINT8(sdid, LSIState710), + VMSTATE_UINT8(ssid, LSIState710), + VMSTATE_UINT8(sfbr, LSIState710), + VMSTATE_UINT8(stest1, LSIState710), + VMSTATE_UINT8(stest2, LSIState710), + VMSTATE_UINT8(stest3, LSIState710), + VMSTATE_UINT8(sidl, LSIState710), + VMSTATE_UINT8(stime0, LSIState710), + VMSTATE_UINT8(respid0, LSIState710), + VMSTATE_UINT8(respid1, LSIState710), + VMSTATE_UINT32(mmrs, LSIState710), + VMSTATE_UINT32(mmws, LSIState710), + VMSTATE_UINT32(sfs, LSIState710), + VMSTATE_UINT32(drs, LSIState710), + VMSTATE_UINT32(sbms, LSIState710), + VMSTATE_UINT32(dbms, LSIState710), + VMSTATE_UINT32(dnad64, LSIState710), + VMSTATE_UINT32(pmjad1, LSIState710), + VMSTATE_UINT32(pmjad2, LSIState710), + VMSTATE_UINT32(rbc, LSIState710), + VMSTATE_UINT32(ua, LSIState710), + VMSTATE_UINT32(ia, LSIState710), + VMSTATE_UINT32(sbc, LSIState710), + VMSTATE_UINT32(csbc, LSIState710), + VMSTATE_BUFFER_UNSAFE(scratch, LSIState710, 0, 18 * sizeof(uint32_t)), + VMSTATE_UINT8(sbr, LSIState710), + + VMSTATE_BUFFER_UNSAFE(script_ram, LSIState710, 0, 2048 * sizeof(uint32_t)), VMSTATE_END_OF_LIST() } }; static void lsi_scsi_uninit(PCIDevice *d) { - LSIState *s = LSI53C895A(d); + LSIState710 *s = LSI53C895A(d); memory_region_destroy(&s->mmio_io); memory_region_destroy(&s->ram_io); @@ -2356,7 +2356,7 @@ static const struct SCSIBusInfo lsi_scsi_info = { static int lsi_scsi_init(PCIDevice *dev) { - LSIState *s = LSI53C895A(dev); + LSIState710 *s = LSI53C895A(dev); DeviceState *d = DEVICE(dev); uint8_t *pci_conf; Error *err = NULL; @@ -2410,7 +2410,7 @@ static void lsi_class_init(ObjectClass *klass, void *data) static const TypeInfo lsi_info = { .name = TYPE_LSI53C895A, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(LSIState), + .instance_size = sizeof(LSIState710), .class_init = lsi_class_init, }; diff --git a/qemuvga/lsi53c895a.cpp b/qemuvga/lsi53c895a.cpp index 3dad3737..60fa2d5d 100644 --- a/qemuvga/lsi53c895a.cpp +++ b/qemuvga/lsi53c895a.cpp @@ -408,9 +408,19 @@ static void lsi_stop_script(LSIState *s) s->istat1 &= ~LSI_ISTAT1_SRUN; } -static void lsi_update_irq(LSIState *s) +static void do_irq(LSIState *s, int level) { PCIDevice *d = PCI_DEVICE(s); + if (level != s->last_level) { + DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n", + level, s->dstat, s->sist1, s->sist0); + s->last_level = level; + } + pci_set_irq(d, level); +} + +static void lsi_update_irq(LSIState *s) +{ int level; lsi_request *p; @@ -436,12 +446,7 @@ static void lsi_update_irq(LSIState *s) if (s->istat0 & LSI_ISTAT0_INTF) level = 1; - if (level != s->last_level) { - DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n", - level, s->dstat, s->sist1, s->sist0); - s->last_level = level; - } - pci_set_irq(d, level); + do_irq(s, level); if (!level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) { DPRINTF("Handled IRQs & disconnected, looking for pending " @@ -1492,7 +1497,7 @@ again: DPRINTF("SCRIPTS execution stopped\n"); } -static uint8_t lsi_reg_readb(LSIState *s, int offset) +static uint8_t lsi_reg_readb2(LSIState *s, int offset) { uint8_t tmp; #define CASE_GET_REG24(name, addr) \ @@ -1506,9 +1511,6 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) case addr + 2: return (s->name >> 16) & 0xff; \ case addr + 3: return (s->name >> 24) & 0xff; -#ifdef DEBUG_LSI_REG - DPRINTF("Read reg %x\n", offset); -#endif switch (offset) { case 0x00: /* SCNTL0 */ return s->scntl0; @@ -1667,6 +1669,15 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) #undef CASE_GET_REG32 } +static uint8_t lsi_reg_readb(LSIState *s, int offset) +{ + uint8_t v = lsi_reg_readb2(s, offset); +#ifdef DEBUG_LSI_REG + DPRINTF("Read reg %02x = %02x\n", offset, v); +#endif + return v; +} + static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) { #define CASE_SET_REG24(name, addr) \ @@ -1681,7 +1692,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break; #ifdef DEBUG_LSI_REG - DPRINTF("Write reg %x = %02x\n", offset, val); + DPRINTF("Write reg %02x = %02x\n", offset, val); #endif switch (offset) { case 0x00: /* SCNTL0 */ @@ -1740,7 +1751,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) CASE_SET_REG32(dsa, 0x10) case 0x14: /* ISTAT0 */ s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0); - if (val & LSI_ISTAT0_ABRT) { + if ((val & LSI_ISTAT0_ABRT) && !(val & LSI_ISTAT0_SRST)) { lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT); } if (val & LSI_ISTAT0_INTF) { @@ -1754,9 +1765,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) lsi_execute_script(s); } if (val & LSI_ISTAT0_SRST) { - if (s->last_level) - pci_set_irq(PCI_DEVICE(s), 0); - s->last_level = 0; + do_irq(s, 0); lsi_soft_reset(s); ;//qdev_reset_all(DEVICE(s)); } diff --git a/rommgr.cpp b/rommgr.cpp index 32f1023d..9aaf70ed 100644 --- a/rommgr.cpp +++ b/rommgr.cpp @@ -93,7 +93,7 @@ struct romdata *getromdatabypath (const TCHAR *path) return NULL; } -#define NEXT_ROM_ID 95 +#define NEXT_ROM_ID 100 static struct romheader romheaders[] = { { _T("Freezer Cartridges"), 1 }, @@ -300,11 +300,22 @@ static struct romdata roms[] = { 0xce270bc0, 0xe043c1aa,0x3bb06e06,0xd4dabff3,0x0a8c6317,0xabfef2bb }, ALTROMPN(92, 1, 1, 32768, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0xa6023f20, 0xdfb048d6, 0xbdc03587, 0x241e8121, 0x26aba603, 0xd69b0238) ALTROMPN(92, 1, 2, 32768, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0x9635a9cd, 0x47578b27, 0xc4ba6e54, 0x891930dd, 0xcb4b6a45, 0x5d6b31b2) - { _T("Blizzard SCSI Kit IV ROM"), 8, 5, 8, 5, _T("BSCSIIV\0"), 32768, 94, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, + { _T("Blizzard SCSI Kit IV ROM"), 8, 5, 8, 5, _T("BSCSIIV\0"), 32768, 94, 0, 0, ROMTYPE_CPUBOARDEXT, 0, 0, NULL, 0xf53a0fca, 0xefe17ca5,0x88c44a7f,0x0f8c62be,0x20f23278,0xcfe06727 }, { _T("Warp Engine A4000 ROM"), 0, 0, 0, 0, _T("WARPENGINE\0WARPENGINEA4000\0"), 32768, 93, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, 0x4deb574a, 0x6e6c95ff,0xe8448391,0xd36c5b68,0xc9065cb0,0x702a7d27 }, + { _T("CyberStorm MK I"), 0, 0, 0, 0, _T("CSMKI\0"), 65536, 95, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, + 0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk1.rom") }, + { _T("CyberStorm MK II"), 0, 0, 0, 0, _T("CSMKII\0"), 131072, 96, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, + 0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk2.rom") }, + { _T("CyberStorm MK III"), 0, 0, 0, 0, _T("CSMKIII\0"), 131072, 97, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, + 0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk3.rom") }, + { _T("CyberStorm PPC"), 0, 0, 0, 0, _T("CSPPC\0"), 131072, 98, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, + 0, 0, 0, 0, 0, 0, NULL, _T("cyberstormppc.rom") }, + { _T("Blizzard PPC"), 0, 0, 0, 0, _T("BPPC\0"), 524288, 99, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL, + 0, 0, 0, 0, 0, 0, NULL, _T("blizzardppc.rom") }, + { _T("Picasso IV ROM"), 7, 4, 7, 4, _T("PIV\0"), 131072, 91, 0, 0, ROMTYPE_PIV, 0, 0, NULL, 0xa8133e7e, 0xcafafb91,0x6f16b9f3,0xec9b49aa,0x4b40eb4e,0xeceb5b5b }, @@ -813,6 +824,18 @@ static int cmpsha1 (const uae_u8 *s1, const struct romdata *rd) return 0; } +struct romdata *getfrombydefaultname(const TCHAR *name, int size) +{ + int i = 0; + while (roms[i].name) { + if (notcrc32(roms[i].crc32) && roms[i].size >= size && roms[i].defaultfilename && !_tcsicmp(roms[i].defaultfilename, name)) { + return &roms[i]; + } + i++; + } + return NULL; +} + static struct romdata *checkromdata (const uae_u8 *sha1, int size, uae_u32 mask) { int i = 0; @@ -1031,7 +1054,7 @@ void romwarning (const int *ids) _tcscat (tmp2, _T("- ")); _tcscat (tmp2, tmp1); _tcscat (tmp2, _T("\n")); - if (rd->type & (ROMTYPE_A2091BOOT | ROMTYPE_A4091BOOT)) + if (rd->type & (ROMTYPE_A2091BOOT | ROMTYPE_A4091BOOT | ROMTYPE_CPUBOARDEXT | ROMTYPE_CPUBOARD | ROMTYPE_CD32CART)) exp++; } i++; @@ -1209,7 +1232,7 @@ struct zfile *read_rom (struct romdata *prd) } add = 2; } - if (get_crc32 (buf, size) == crc32) { + if (notcrc32(crc32) || get_crc32(buf, size) == crc32) { ok = 1; } if (!ok && (rd->type & ROMTYPE_AR)) { diff --git a/statusline.cpp b/statusline.cpp index 3d00cccc..135c2ebc 100644 --- a/statusline.cpp +++ b/statusline.cpp @@ -44,14 +44,14 @@ void statusline_getpos (int *x, int *y, int width, int height) } } -static const char *numbers = { /* ugly 0123456789CHD%+- */ - "+++++++--++++-+++++++++++++++++-++++++++++++++++++++++++++++++++++++++++++++-++++++-++++----++---+--------------" - "+xxxxx+--+xx+-+xxxxx++xxxxx++x+-+x++xxxxx++xxxxx++xxxxx++xxxxx++xxxxx++xxxx+-+x++x+-+xxx++-+xx+-+x---+----------" - "+x+++x+--++x+-+++++x++++++x++x+++x++x++++++x++++++++++x++x+++x++x+++x++x++++-+x++x+-+x++x+--+x++x+--+x+----+++--" - "+x+-+x+---+x+-+xxxxx++xxxxx++xxxxx++xxxxx++xxxxx+--++x+-+xxxxx++xxxxx++x+----+xxxx+-+x++x+----+x+--+xxx+--+xxx+-" - "+x+++x+---+x+-+x++++++++++x++++++x++++++x++x+++x+--+x+--+x+++x++++++x++x++++-+x++x+-+x++x+---+x+x+--+x+----+++--" - "+xxxxx+---+x+-+xxxxx++xxxxx+----+x++xxxxx++xxxxx+--+x+--+xxxxx++xxxxx++xxxx+-+x++x+-+xxx+---+x++xx--------------" - "+++++++---+++-++++++++++++++----+++++++++++++++++--+++--++++++++++++++++++++-++++++-++++------------------------" +static const char *numbers = { /* ugly 0123456789CHD%+-P */ + "+++++++--++++-+++++++++++++++++-++++++++++++++++++++++++++++++++++++++++++++-++++++-++++----++---+--------------+++++++" + "+xxxxx+--+xx+-+xxxxx++xxxxx++x+-+x++xxxxx++xxxxx++xxxxx++xxxxx++xxxxx++xxxx+-+x++x+-+xxx++-+xx+-+x---+----------+xxxxx+" + "+x+++x+--++x+-+++++x++++++x++x+++x++x++++++x++++++++++x++x+++x++x+++x++x++++-+x++x+-+x++x+--+x++x+--+x+----+++--+x---x+" + "+x+-+x+---+x+-+xxxxx++xxxxx++xxxxx++xxxxx++xxxxx+--++x+-+xxxxx++xxxxx++x+----+xxxx+-+x++x+----+x+--+xxx+--+xxx+-+xxxxx+" + "+x+++x+---+x+-+x++++++++++x++++++x++++++x++x+++x+--+x+--+x+++x++++++x++x++++-+x++x+-+x++x+---+x+x+--+x+----+++--+x+++++" + "+xxxxx+---+x+-+xxxxx++xxxxx+----+x++xxxxx++xxxxx+--+x+--+xxxxx++xxxxx++xxxx+-+x++x+-+xxx+---+x++xx--------------+x+----" + "+++++++---+++-++++++++++++++----+++++++++++++++++--+++--++++++++++++++++++++-++++++-++++------------------------+++----" }; STATIC_INLINE uae_u32 ledcolor (uae_u32 c, uae_u32 *rc, uae_u32 *gc, uae_u32 *bc, uae_u32 *a) @@ -170,13 +170,21 @@ void draw_status_line_single (uae_u8 *buf, int bpp, int y, int totalwidth, uae_u on_rgb = 0xcc0000; off_rgb = 0x000000; if (gui_data.cpu_halted) { - on_rgb = gui_data.cpu_halted < 0 ? 0x444444 : 0xcccc00; idle = 0; on = 1; - num1 = -1; - num2 = 11; - num3 = gui_data.cpu_halted < 0 ? 15 : gui_data.cpu_halted; - am = 2; + if (gui_data.cpu_halted < 0) { + on_rgb = 0xcc0000; + num1 = 16; // PPC + num2 = 16; + num3 = 10; + am = 3; + } else { + on_rgb = 0xcccc00; + num1 = -1; + num2 = 11; + num3 = gui_data.cpu_halted; + am = 2; + } } else { num1 = idle / 100; num2 = (idle - num1 * 100) / 10;