From: Toni Wilen Date: Sun, 10 Oct 2021 07:32:21 +0000 (+0300) Subject: Blitter cycle-exact changes. X-Git-Tag: 4900~46 X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=c010789b3d3c122fedd56656cfb8a357b73d5f8b;p=francis%2Fwinuae.git Blitter cycle-exact changes. --- diff --git a/blitter.cpp b/blitter.cpp index dc60cde4..f5a2c5bf 100644 --- a/blitter.cpp +++ b/blitter.cpp @@ -364,28 +364,6 @@ static void markidlecycle(int hpos) } } -static void reset_channel_mods (void) -{ - if (bltptxpos < 0) - return; - bltptxpos = -1; - switch (bltptxc) - { - case 1: - bltapt = bltptx; - break; - case 2: - bltbpt = bltptx; - break; - case 3: - bltcpt = bltptx; - break; - case 4: - bltdpt = bltptx; - break; - } -} - static void check_channel_mods(int hpos, int ch, uaecptr *pt) { static int blit_warned = 100; @@ -394,7 +372,14 @@ static void check_channel_mods(int hpos, int ch, uaecptr *pt) return; if (bltptxpos != hpos) return; - if (ch == bltptxc) { + // if CPU write and non-CE: skip + if (bltptxc < 0) { + if (currprefs.cpu_model >= 68020 || !currprefs.cpu_cycle_exact) { + bltptxpos = -1; + return; + } + } + if (ch == bltptxc || ch == -bltptxc) { if (blit_warned > 0) { write_log(_T("BLITTER: %08X -> %08X write to %cPT ignored! %08x\n"), bltptx, *pt, ch + 'A' - 1, m68k_getpc()); blit_warned--; @@ -1326,8 +1311,7 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va { bool written = false; int hsync = until_hpos < 0; - int hpos = last_blitter_hpos; - + if (hsync && blt_delayed_irq) { if (blt_delayed_irq > 0) blt_delayed_irq--; @@ -1337,18 +1321,26 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va } } - if (until_hpos < 0) { + if (until_hpos < 0 || until_hpos > maxhpos) { until_hpos = maxhpos; } + if (last_blitter_hpos > until_hpos) { + goto end; + } + + if (last_blitter_hpos == until_hpos) { + goto end; + } + if (immediate_blits) { if (!blt_info.blit_main) { return false; } if (dmaen(DMA_BLITTER)) { - blitter_doit(hpos); + blitter_doit(last_blitter_hpos); } - return false; + goto end; } if (log_blitter && blitter_delayed_debug) { @@ -1357,11 +1349,11 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va } if (!blitter_cycle_exact) { - return false; + goto end; } - - while (hpos < until_hpos) { + while (last_blitter_hpos < until_hpos) { + int hpos = last_blitter_hpos; // dma transfers and processing for (;;) { @@ -1493,22 +1485,22 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va blt_info.blit_queued = BLITTER_MAX_PIPELINED_CYCLES; - // copper bltsize write needs one cycle (any cycle) delay - // does not need free bus - if (blit_waitcyclecounter > 0) { - blit_waitcyclecounter--; - markidlecycle(hpos); - break; - } - - // final D idle cycle - // does not need free bus - if (blt_info.blit_finald > 1) { - blt_info.blit_finald--; - } - // cycle allocations for (;;) { + // copper bltsize write needs one cycle (any cycle) delay + // does not need free bus + if (blit_waitcyclecounter > 0) { + blit_waitcyclecounter--; + markidlecycle(hpos); + break; + } + + // final D idle cycle + // does not need free bus + if (blt_info.blit_finald > 1) { + blt_info.blit_finald--; + } + bool cant = blitter_cant_access(hpos); if (cant) { blit_misscyclecounter++; @@ -1516,10 +1508,10 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va } // CPU steals the cycle if CPU has waited long enough and current cyle is not free. - if (!(dmacon & DMA_BLITPRI) && blt_info.nasty_cnt >= BLIT_NASTY_CPU_STEAL_CYCLE_COUNT && ((cycle_line_slot[hpos] & CYCLE_MASK) != 0 || bitplane_dma_access(hpos, 0) != 0)) { + if (!(dmacon & DMA_BLITPRI) && blt_info.nasty_cnt >= BLIT_NASTY_CPU_STEAL_CYCLE_COUNT && currprefs.cpu_memory_cycle_exact && ((cycle_line_slot[hpos] & CYCLE_MASK) != 0 || bitplane_dma_access(hpos, 0) != 0)) { int offset = get_rga_pipeline(hpos, RGA_PIPELINE_OFFSET_BLITTER); + blitter_pipe[offset] = CYCLE_PIPE_BLITTER | CYCLE_PIPE_CPUSTEAL; cycle_line_pipe[offset] = CYCLE_PIPE_BLITTER | CYCLE_PIPE_CPUSTEAL; - blitter_pipe[offset] = cycle_line_pipe[offset]; blt_info.nasty_cnt = -1; break; } @@ -1528,7 +1520,7 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va // final D write int offset = get_rga_pipeline(hpos, RGA_PIPELINE_OFFSET_BLITTER); cycle_line_pipe[offset] = CYCLE_PIPE_BLITTER; - blitter_pipe[offset] = cycle_line_pipe[offset] | 4 | BLITTER_PIPELINE_ADDMOD | BLITTER_PIPELINE_LASTD; + blitter_pipe[offset] = CYCLE_PIPE_BLITTER | 4 | BLITTER_PIPELINE_ADDMOD | BLITTER_PIPELINE_LASTD; if (currprefs.chipset_mask & CSMASK_AGA) { blitter_done_all(hpos); } @@ -1589,7 +1581,6 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va } // finished? - uae_u16 clv = CYCLE_PIPE_BLITTER; if (blit_cyclecounter < -CYCLECOUNT_START) { v |= BLITTER_PIPELINE_FINISHED; if (!blt_info.blit_main) { @@ -1605,7 +1596,7 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va } } - cycle_line_pipe[offset] = clv; + cycle_line_pipe[offset] = CYCLE_PIPE_BLITTER; blitter_pipe[offset] = v; } break; @@ -1613,11 +1604,12 @@ static bool decide_blitter_maybe_write2(int until_hpos, uaecptr addr, uae_u32 va } - hpos++; + last_blitter_hpos++; bltptxpos = -1; } - last_blitter_hpos = until_hpos; +end: + bltptxpos = -1; if (hsync) { last_blitter_hpos = 0; } @@ -2018,6 +2010,8 @@ void blitter_slowdown (int ddfstrt, int ddfstop, int totalcycles, int freecycles void blitter_reset (void) { bltptxpos = -1; + blitter_cycle_exact = currprefs.blitter_cycle_exact; + immediate_blits = currprefs.immediate_blits; } #ifdef SAVESTATE diff --git a/cfgfile.cpp b/cfgfile.cpp index c3722be1..0543beff 100644 --- a/cfgfile.cpp +++ b/cfgfile.cpp @@ -8334,11 +8334,11 @@ static void set_68020_compa (struct uae_prefs *p, int compa, int cd32) switch (compa) { case 0: - p->blitter_cycle_exact = 1; p->m68k_speed = 0; if ((p->cpu_model == 68020 || p->cpu_model == 68030) && p->cachesize == 0) { p->cpu_cycle_exact = 1; p->cpu_memory_cycle_exact = 1; + p->blitter_cycle_exact = 1; if (p->cpu_model == 68020) p->cpu_clock_multiplier = 4 << 8; else @@ -8346,9 +8346,9 @@ static void set_68020_compa (struct uae_prefs *p, int compa, int cd32) } break; case 1: - p->blitter_cycle_exact = 1; p->m68k_speed = 0; if ((p->cpu_model == 68020 || p->cpu_model == 68030) && p->cachesize == 0) { + p->blitter_cycle_exact = 1; p->cpu_memory_cycle_exact = 1; if (p->cpu_model == 68020) p->cpu_clock_multiplier = 4 << 8; diff --git a/custom.cpp b/custom.cpp index 1305036b..165e7986 100644 --- a/custom.cpp +++ b/custom.cpp @@ -55,6 +55,7 @@ #define CYCLE_CONFLICT_LOGGING 0 #define SPEEDUP 1 + #define CUSTOM_DEBUG 0 #define SPRITE_DEBUG 0 #define SPRITE_DEBUG_MINY 0 @@ -3773,12 +3774,15 @@ static void decide_line_decision_fetches(int endhpos) static void decide_fetch_safe(int endhpos) { - if (!blt_info.blitter_dangerous_bpl) { + if (copper_enabled_thisline) { + update_copper(endhpos); + decide_blitter(endhpos); + } else if (!blt_info.blitter_dangerous_bpl) { decide_line_decision_fetches(endhpos); decide_blitter(endhpos); } else { int hpos = last_fetch_hpos; - while (hpos < endhpos) { + while (hpos <= endhpos) { decide_line_decision_fetches(hpos); decide_blitter(hpos); hpos++; @@ -7116,7 +7120,7 @@ static void BLTAPTH(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltapt; bltptxpos = hpos; - bltptxc = 1; + bltptxc = copper_access ? 1 : -1; bltapt = (bltapt & 0xffff) | ((uae_u32)v << 16); } static void BLTAPTL(int hpos, uae_u16 v) @@ -7124,7 +7128,7 @@ static void BLTAPTL(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltapt; bltptxpos = hpos; - bltptxc = 1; + bltptxc = copper_access ? 1 : -1; bltapt = (bltapt & ~0xffff) | (v & 0xFFFE); } static void BLTBPTH(int hpos, uae_u16 v) @@ -7132,7 +7136,7 @@ static void BLTBPTH(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltbpt; bltptxpos = hpos; - bltptxc = 2; + bltptxc = copper_access ? 2 : -2; bltbpt = (bltbpt & 0xffff) | ((uae_u32)v << 16); } static void BLTBPTL(int hpos, uae_u16 v) @@ -7140,7 +7144,7 @@ static void BLTBPTL(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltbpt; bltptxpos = hpos; - bltptxc = 2; + bltptxc = copper_access ? 2 : -2; bltbpt = (bltbpt & ~0xffff) | (v & 0xFFFE); } static void BLTCPTH(int hpos, uae_u16 v) @@ -7148,7 +7152,7 @@ static void BLTCPTH(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltcpt; bltptxpos = hpos; - bltptxc = 3; + bltptxc = copper_access ? 3 : -3; bltcpt = (bltcpt & 0xffff) | ((uae_u32)v << 16); } static void BLTCPTL(int hpos, uae_u16 v) @@ -7156,7 +7160,7 @@ static void BLTCPTL(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltcpt; bltptxpos = hpos; - bltptxc = 3; + bltptxc = copper_access ? 3 : -3; bltcpt = (bltcpt & ~0xffff) | (v & 0xFFFE); } static void BLTDPTH (int hpos, uae_u16 v) @@ -7164,7 +7168,7 @@ static void BLTDPTH (int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltdpt; bltptxpos = hpos; - bltptxc = 4; + bltptxc = copper_access ? 4 : -4; bltdpt = (bltdpt & 0xffff) | ((uae_u32)v << 16); } static void BLTDPTL(int hpos, uae_u16 v) @@ -7172,7 +7176,7 @@ static void BLTDPTL(int hpos, uae_u16 v) maybe_blit(hpos, 0); bltptx = bltdpt; bltptxpos = hpos; - bltptxc = 4; + bltptxc = copper_access ? 4 : -4; bltdpt = (bltdpt & ~0xffff) | (v & 0xFFFE); } @@ -7753,12 +7757,28 @@ static bool copper_cant_read(int hpos, uae_u16 alloc) } if (bitplane_dma_access(hpos, coffset)) { +#ifdef DEBUGGER + if (debug_dma) { + record_dma_event(DMA_EVENT_COPPERWANTED, hpos, vpos); + } +#endif return true; } int offset = get_rga_pipeline(hpos, coffset); - if (cycle_line_pipe[offset] != 0) { + uae_u16 v = cycle_line_pipe[offset]; + if (v != 0) { +#if CYCLE_CONFLICT_LOGGING + if ((v & CYCLE_PIPE_BLITTER) || (v & CYCLE_PIPE_CPUSTEAL) || (v & CYCLE_PIPE_SPRITE)) { + write_log(_T("Copper's cycle stolen by lower priority channel %04x!?\n"), v); + } +#endif +#ifdef DEBUGGER + if (debug_dma) { + record_dma_event(DMA_EVENT_COPPERWANTED, hpos, vpos); + } +#endif return true; } @@ -10938,11 +10958,7 @@ void vsync_event_done(void) // this prepares for new line static void hsync_handler_post(bool onvsync) { -#ifdef CPUEMU_13 - if (1 || currprefs.cpu_memory_cycle_exact || currprefs.blitter_cycle_exact) { - memset(cycle_line_slot, 0, maxhpos); - } -#endif + memset(cycle_line_slot, 0, maxhpos); // genlock active: // vertical: interlaced = toggles every other field, non-interlaced = both fields (normal) @@ -12633,7 +12649,7 @@ uae_u8 *save_custom(int *len, uae_u8 *dstptr, int full) } else { v = (blt_info.vblitsize << 6) | (blt_info.hblitsize & 63); } - SW (v); /* 058 BLTSIZE */ + SW(v); /* 058 BLTSIZE */ SW(bltcon0 & 0xff); /* 05A BLTCON0L (use BLTCON0 instead) */ SW(blt_info.vblitsize); /* 05C BLTSIZV */ SW(blt_info.hblitsize); /* 05E BLTSIZH */ @@ -12740,7 +12756,7 @@ uae_u8 *save_custom(int *len, uae_u8 *dstptr, int full) SW(0); /* 1F8 */ SW(0x8000 | (currprefs.ntscmode ? 1 : 0)); /* 1FA (re-used for NTSC) */ SW(fmode); /* 1FC FMODE */ - SW (last_custom_value); /* 1FE */ + SW(last_custom_value); /* 1FE */ *len = dst - dstbak; return dstbak; @@ -12750,7 +12766,7 @@ uae_u8 *save_custom(int *len, uae_u8 *dstptr, int full) #ifdef SAVESTATE -uae_u8 *restore_custom_agacolors (uae_u8 *src) +uae_u8 *restore_custom_agacolors(uae_u8 *src) { int i; @@ -12769,7 +12785,7 @@ uae_u8 *restore_custom_agacolors (uae_u8 *src) return src; } -uae_u8 *save_custom_agacolors (int *len, uae_u8 *dstptr) +uae_u8 *save_custom_agacolors(int *len, uae_u8 *dstptr) { uae_u8 *dstbak, *dst; @@ -12797,7 +12813,7 @@ uae_u8 *save_custom_agacolors (int *len, uae_u8 *dstptr) return dstbak; } -uae_u8 *restore_custom_sprite (int num, uae_u8 *src) +uae_u8 *restore_custom_sprite(int num, uae_u8 *src) { struct sprite *s = &spr[num]; memset (s, 0, sizeof (struct sprite)); @@ -12816,7 +12832,7 @@ uae_u8 *restore_custom_sprite (int num, uae_u8 *src) return src; } -uae_u8 *save_custom_sprite (int num, int *len, uae_u8 *dstptr) +uae_u8 *save_custom_sprite(int num, int *len, uae_u8 *dstptr) { uae_u8 *dstbak, *dst; struct sprite *s = &spr[num]; @@ -12824,31 +12840,31 @@ uae_u8 *save_custom_sprite (int num, int *len, uae_u8 *dstptr) if (dstptr) dstbak = dst = dstptr; else - dstbak = dst = xmalloc (uae_u8, 30); - SL (s->pt); /* 120-13E SPRxPT */ - SW (s->pos); /* 1x0 SPRxPOS */ - SW (s->ctl); /* 1x2 SPRxPOS */ - SW (s->data[0]); /* 1x4 SPRxDATA */ - SW (s->datb[0]); /* 1x6 SPRxDATB */ - SW (s->data[1]); - SW (s->datb[1]); - SW (s->data[2]); - SW (s->datb[2]); - SW (s->data[3]); - SW (s->datb[3]); - SB (s->armed ? 1 : 0); + dstbak = dst = xmalloc(uae_u8, 30); + SL(s->pt); /* 120-13E SPRxPT */ + SW(s->pos); /* 1x0 SPRxPOS */ + SW(s->ctl); /* 1x2 SPRxPOS */ + SW(s->data[0]); /* 1x4 SPRxDATA */ + SW(s->datb[0]); /* 1x6 SPRxDATB */ + SW(s->data[1]); + SW(s->datb[1]); + SW(s->data[2]); + SW(s->datb[2]); + SW(s->data[3]); + SW(s->datb[3]); + SB(s->armed ? 1 : 0); *len = dst - dstbak; return dstbak; } -uae_u8 *restore_custom_extra (uae_u8 *src) +uae_u8 *restore_custom_extra(uae_u8 *src) { - uae_u32 v = restore_u32 (); + uae_u32 v = restore_u32(); if (!(v & 1)) v = 0; currprefs.cs_compatible = changed_prefs.cs_compatible = v >> 24; - cia_set_overlay ((v & 2) != 0); + cia_set_overlay((v & 2) != 0); currprefs.genlock = changed_prefs.genlock = RBB; currprefs.cs_rtc = changed_prefs.cs_rtc = RB; @@ -12902,55 +12918,55 @@ uae_u8 *restore_custom_extra (uae_u8 *src) return src; } -uae_u8 *save_custom_extra (int *len, uae_u8 *dstptr) +uae_u8 *save_custom_extra(int *len, uae_u8 *dstptr) { uae_u8 *dstbak, *dst; if (dstptr) dstbak = dst = dstptr; else - dstbak = dst = xmalloc (uae_u8, 1000); - - SL ((currprefs.cs_compatible << 24) | (get_mem_bank_real(0) != &chipmem_bank ? 2 : 0) | 1); - SB (currprefs.genlock ? 1 : 0); - SB (currprefs.cs_rtc); - SL (currprefs.cs_rtc_adjust); - - SB (currprefs.cs_a1000ram ? 1 : 0); - SB (currprefs.cs_slowmemisfast ? 1 : 0); - - SB (is_board_enabled(&currprefs, ROMTYPE_A2091, 0) ? 1 : 0); - SB (is_board_enabled(&currprefs, ROMTYPE_A4091, 0) ? 1 : 0); - SB (0); - - SB (currprefs.cs_pcmcia ? 1 : 0); - SB (currprefs.cs_ciaatod); - SB (currprefs.cs_ciaoverlay ? 1 : 0); - - SB (currprefs.cs_agnusbltbusybug ? 1 : 0); - SB (currprefs.cs_denisenoehb ? 1 : 0); - - SB (currprefs.cs_agnusrev); - SB (currprefs.cs_deniserev); - SB (currprefs.cs_fatgaryrev); - SB (currprefs.cs_ramseyrev); - - SB (currprefs.cs_cd32c2p); - SB (currprefs.cs_cd32cd); - SB (currprefs.cs_cd32nvram); - SB (currprefs.cs_cdtvcd ? 1 : 0); - SB (currprefs.cs_cdtvram ? 1 : 0); - SB (0); - - SB (currprefs.cs_df0idhw ? 1 : 0); - SB (currprefs.cs_dipagnus ? 1 : 0); - SB (currprefs.cs_ide); - SB (currprefs.cs_mbdmac); - SB (currprefs.cs_ksmirror_a8 ? 1 : 0); - SB (currprefs.cs_ksmirror_e0 ? 1 : 0); - SB (currprefs.cs_resetwarning ? 1 : 0); - SB (currprefs.cs_z3autoconfig ? 1 : 0); - SB (currprefs.cs_1mchipjumper ? 1 : 0); + dstbak = dst = xmalloc(uae_u8, 1000); + + SL((currprefs.cs_compatible << 24) | (get_mem_bank_real(0) != &chipmem_bank ? 2 : 0) | 1); + SB(currprefs.genlock ? 1 : 0); + SB(currprefs.cs_rtc); + SL(currprefs.cs_rtc_adjust); + + SB(currprefs.cs_a1000ram ? 1 : 0); + SB(currprefs.cs_slowmemisfast ? 1 : 0); + + SB(is_board_enabled(&currprefs, ROMTYPE_A2091, 0) ? 1 : 0); + SB(is_board_enabled(&currprefs, ROMTYPE_A4091, 0) ? 1 : 0); + SB(0); + + SB(currprefs.cs_pcmcia ? 1 : 0); + SB(currprefs.cs_ciaatod); + SB(currprefs.cs_ciaoverlay ? 1 : 0); + + SB(currprefs.cs_agnusbltbusybug ? 1 : 0); + SB(currprefs.cs_denisenoehb ? 1 : 0); + + SB(currprefs.cs_agnusrev); + SB(currprefs.cs_deniserev); + SB(currprefs.cs_fatgaryrev); + SB(currprefs.cs_ramseyrev); + + SB(currprefs.cs_cd32c2p); + SB(currprefs.cs_cd32cd); + SB(currprefs.cs_cd32nvram); + SB(currprefs.cs_cdtvcd ? 1 : 0); + SB(currprefs.cs_cdtvram ? 1 : 0); + SB(0); + + SB(currprefs.cs_df0idhw ? 1 : 0); + SB(currprefs.cs_dipagnus ? 1 : 0); + SB(currprefs.cs_ide); + SB(currprefs.cs_mbdmac); + SB(currprefs.cs_ksmirror_a8 ? 1 : 0); + SB(currprefs.cs_ksmirror_e0 ? 1 : 0); + SB(currprefs.cs_resetwarning ? 1 : 0); + SB(currprefs.cs_z3autoconfig ? 1 : 0); + SB(currprefs.cs_1mchipjumper ? 1 : 0); SB(currprefs.cs_bytecustomwritebug ? 1 : 0); SB(currprefs.cs_color_burst ? 1 : 0); @@ -12963,21 +12979,21 @@ uae_u8 *save_custom_extra (int *len, uae_u8 *dstptr) return dstbak; } -uae_u8 *restore_custom_event_delay (uae_u8 *src) +uae_u8 *restore_custom_event_delay(uae_u8 *src) { - if (restore_u32 () != 1) + if (restore_u32() != 1) return src; - int cnt = restore_u8 (); + int cnt = restore_u8(); for (int i = 0; i < cnt; i++) { - uae_u8 type = restore_u8 (); - evt e = restore_u64 (); - uae_u32 data = restore_u32 (); + uae_u8 type = restore_u8(); + evt e = restore_u64(); + uae_u32 data = restore_u32(); if (type == 1) - event2_newevent_xx (-1, e, data, send_interrupt_do); + event2_newevent_xx(-1, e, data, send_interrupt_do); } return src; } -uae_u8 *save_custom_event_delay (int *len, uae_u8 *dstptr) +uae_u8 *save_custom_event_delay(int *len, uae_u8 *dstptr) { uae_u8 *dstbak, *dst; int cnt = 0; @@ -12994,16 +13010,16 @@ uae_u8 *save_custom_event_delay (int *len, uae_u8 *dstptr) if (dstptr) dstbak = dst = dstptr; else - dstbak = dst = xmalloc (uae_u8, 1000); + dstbak = dst = xmalloc(uae_u8, 1000); - save_u32 (1); - save_u8 (cnt); + save_u32(1); + save_u8(cnt); for (int i = ev2_misc; i < ev2_max; i++) { struct ev2 *e = &eventtab2[i]; if (e->active && e->handler == send_interrupt_do) { - save_u8 (1); - save_u64 (e->evtime - get_cycles ()); - save_u32 (e->data); + save_u8(1); + save_u64(e->evtime - get_cycles()); + save_u32(e->data); } } @@ -13013,38 +13029,38 @@ uae_u8 *save_custom_event_delay (int *len, uae_u8 *dstptr) } -uae_u8 *save_cycles (int *len, uae_u8 *dstptr) +uae_u8 *save_cycles(int *len, uae_u8 *dstptr) { uae_u8 *dstbak, *dst; if (dstptr) dstbak = dst = dstptr; else - dstbak = dst = xmalloc (uae_u8, 1000); - save_u32 (1); - save_u32 (CYCLE_UNIT); - save_u64 (get_cycles ()); - save_u32 (extra_cycle); - write_log (_T("SAVECYCLES %08lX\n"), get_cycles ()); + dstbak = dst = xmalloc(uae_u8, 1000); + save_u32(1); + save_u32(CYCLE_UNIT); + save_u64(get_cycles()); + save_u32(extra_cycle); + write_log(_T("SAVECYCLES %08lX\n"), get_cycles()); *len = dst - dstbak; return dstbak; } -uae_u8 *restore_cycles (uae_u8 *src) +uae_u8 *restore_cycles(uae_u8 *src) { - if (restore_u32 () != 1) + if (restore_u32() != 1) return src; - restore_u32 (); - start_cycles = restore_u64 (); - extra_cycle = restore_u32 (); + restore_u32(); + start_cycles = restore_u64(); + extra_cycle = restore_u32(); if (extra_cycle >= 2 * CYCLE_UNIT) extra_cycle = 0; - write_log (_T("RESTORECYCLES %08lX\n"), start_cycles); + write_log(_T("RESTORECYCLES %08lX\n"), start_cycles); return src; } #endif /* SAVESTATE */ -void check_prefs_changed_custom (void) +void check_prefs_changed_custom(void) { if (!config_changed) return; @@ -13052,12 +13068,12 @@ void check_prefs_changed_custom (void) if (currprefs.turbo_emulation_limit != changed_prefs.turbo_emulation_limit) { currprefs.turbo_emulation_limit = changed_prefs.turbo_emulation_limit; if (changed_prefs.turbo_emulation) { - warpmode (changed_prefs.turbo_emulation); + warpmode(changed_prefs.turbo_emulation); } } if (currprefs.turbo_emulation != changed_prefs.turbo_emulation) - warpmode (changed_prefs.turbo_emulation); - if (inputdevice_config_change_test ()) + warpmode(changed_prefs.turbo_emulation); + if (inputdevice_config_change_test()) inputdevice_copyconfig (&changed_prefs, &currprefs); currprefs.immediate_blits = changed_prefs.immediate_blits; currprefs.waiting_blits = changed_prefs.waiting_blits; diff --git a/main.cpp b/main.cpp index 6304b5bc..2e30fae6 100644 --- a/main.cpp +++ b/main.cpp @@ -342,6 +342,12 @@ void fixup_cpu (struct uae_prefs *p) error_log (_T("Immediate blitter and waiting blits can't be enabled simultaneously.\n")); p->waiting_blits = 0; } + + if (p->blitter_cycle_exact && !p->cpu_memory_cycle_exact) { + error_log(_T("Blitter cycle-exact requires at least CPU memory cycle-exact.\n")); + p->blitter_cycle_exact = 0; + } + if (p->cpu_memory_cycle_exact) p->cpu_compatible = true;