From: Toni Wilen Date: Thu, 28 May 2026 19:49:21 +0000 (+0300) Subject: 68020/030 AND/EOR/OR #x,CCR + T1 trace: trace exception is generated. X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=d0171312339b9a5f5522cf27bd5448f9304515f3;p=francis%2Fwinuae.git 68020/030 AND/EOR/OR #x,CCR + T1 trace: trace exception is generated. --- diff --git a/cpuemu_0.cpp b/cpuemu_0.cpp index 304068a3..a5b448dd 100644 --- a/cpuemu_0.cpp +++ b/cpuemu_0.cpp @@ -42728,6 +42728,7 @@ uae_u32 REGPARAM2 op_003c_2_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpc(4); @@ -42761,6 +42762,7 @@ uae_u32 REGPARAM2 op_023c_2_ff(uae_u32 opcode) uae_s16 src = get_diword(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpc(4); @@ -42793,6 +42795,7 @@ uae_u32 REGPARAM2 op_0a3c_2_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpc(4); @@ -47335,6 +47338,7 @@ uae_u32 REGPARAM2 op_003c_3_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpc(4); @@ -47368,6 +47372,7 @@ uae_u32 REGPARAM2 op_023c_3_ff(uae_u32 opcode) uae_s16 src = get_diword(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpc(4); @@ -47400,6 +47405,7 @@ uae_u32 REGPARAM2 op_0a3c_3_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpc(4); diff --git a/cpuemu_20.cpp b/cpuemu_20.cpp index e6fc1305..1f93d769 100644 --- a/cpuemu_20.cpp +++ b/cpuemu_20.cpp @@ -180,6 +180,7 @@ uae_u32 REGPARAM2 op_003c_20_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_word_020_prefetch(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpci(4); @@ -1725,6 +1726,7 @@ uae_u32 REGPARAM2 op_023c_20_ff(uae_u32 opcode) uae_s16 src = get_word_020_prefetch(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpci(4); @@ -4715,6 +4717,7 @@ uae_u32 REGPARAM2 op_0a3c_20_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_word_020_prefetch(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpci(4); diff --git a/cpuemu_21.cpp b/cpuemu_21.cpp index 85b7900c..1fc9bb21 100644 --- a/cpuemu_21.cpp +++ b/cpuemu_21.cpp @@ -197,6 +197,7 @@ void REGPARAM2 op_003c_21_ff(uae_u32 opcode) uae_s16 src = get_word_ce020_prefetch(2); /* OP zero */ src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); intlev_load(); @@ -1883,6 +1884,7 @@ void REGPARAM2 op_023c_21_ff(uae_u32 opcode) /* OP zero */ src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); intlev_load(); @@ -5118,6 +5120,7 @@ void REGPARAM2 op_0a3c_21_ff(uae_u32 opcode) uae_s16 src = get_word_ce020_prefetch(2); /* OP zero */ src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); intlev_load(); diff --git a/cpuemu_22.cpp b/cpuemu_22.cpp index ce9603fe..2cb42e23 100644 --- a/cpuemu_22.cpp +++ b/cpuemu_22.cpp @@ -180,6 +180,7 @@ uae_u32 REGPARAM2 op_003c_22_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_word_030_prefetch(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpci(4); @@ -1725,6 +1726,7 @@ uae_u32 REGPARAM2 op_023c_22_ff(uae_u32 opcode) uae_s16 src = get_word_030_prefetch(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpci(4); @@ -4715,6 +4717,7 @@ uae_u32 REGPARAM2 op_0a3c_22_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_word_030_prefetch(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpci(4); diff --git a/cpuemu_23.cpp b/cpuemu_23.cpp index 8a1fed69..b94d778f 100644 --- a/cpuemu_23.cpp +++ b/cpuemu_23.cpp @@ -197,6 +197,7 @@ void REGPARAM2 op_003c_23_ff(uae_u32 opcode) uae_s16 src = get_word_ce030_prefetch(2); /* OP zero */ src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); intlev_load(); @@ -1883,6 +1884,7 @@ void REGPARAM2 op_023c_23_ff(uae_u32 opcode) /* OP zero */ src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); intlev_load(); @@ -5118,6 +5120,7 @@ void REGPARAM2 op_0a3c_23_ff(uae_u32 opcode) uae_s16 src = get_word_ce030_prefetch(2); /* OP zero */ src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); intlev_load(); diff --git a/cpuemu_32.cpp b/cpuemu_32.cpp index 432f370f..bc5713da 100644 --- a/cpuemu_32.cpp +++ b/cpuemu_32.cpp @@ -193,6 +193,7 @@ uae_u32 REGPARAM2 op_003c_32_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iword_mmu030_state(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpci(4); @@ -1792,6 +1793,7 @@ uae_u32 REGPARAM2 op_023c_32_ff(uae_u32 opcode) uae_s16 src = get_iword_mmu030_state(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpci(4); @@ -4906,6 +4908,7 @@ uae_u32 REGPARAM2 op_0a3c_32_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iword_mmu030_state(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpci(4); diff --git a/cpuemu_34.cpp b/cpuemu_34.cpp index dd66fab7..5ba64dce 100644 --- a/cpuemu_34.cpp +++ b/cpuemu_34.cpp @@ -201,6 +201,7 @@ uae_u32 REGPARAM2 op_003c_34_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iword_mmu030c_state(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpci(4); @@ -1872,6 +1873,7 @@ uae_u32 REGPARAM2 op_023c_34_ff(uae_u32 opcode) uae_s16 src = get_iword_mmu030c_state(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpci(4); @@ -5108,6 +5110,7 @@ uae_u32 REGPARAM2 op_0a3c_34_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iword_mmu030c_state(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpci(4); diff --git a/cpuemu_35.cpp b/cpuemu_35.cpp index 608925e6..87ff009a 100644 --- a/cpuemu_35.cpp +++ b/cpuemu_35.cpp @@ -218,6 +218,7 @@ void REGPARAM2 op_003c_35_ff(uae_u32 opcode) uae_s16 src = get_iword_mmu030c_state(2); /* OP zero */ src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); intlev_load(); @@ -2030,6 +2031,7 @@ void REGPARAM2 op_023c_35_ff(uae_u32 opcode) /* OP zero */ src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); intlev_load(); @@ -5511,6 +5513,7 @@ void REGPARAM2 op_0a3c_35_ff(uae_u32 opcode) uae_s16 src = get_iword_mmu030c_state(2); /* OP zero */ src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); intlev_load(); diff --git a/cpuemu_40.cpp b/cpuemu_40.cpp index 88a29dff..62679150 100644 --- a/cpuemu_40.cpp +++ b/cpuemu_40.cpp @@ -40797,6 +40797,7 @@ uae_u32 REGPARAM2 op_003c_42_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpc(4); @@ -40828,6 +40829,7 @@ uae_u32 REGPARAM2 op_023c_42_ff(uae_u32 opcode) uae_s16 src = get_diword(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpc(4); @@ -40858,6 +40860,7 @@ uae_u32 REGPARAM2 op_0a3c_42_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpc(4); @@ -45141,6 +45144,7 @@ uae_u32 REGPARAM2 op_003c_43_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpc(4); @@ -45172,6 +45176,7 @@ uae_u32 REGPARAM2 op_023c_43_ff(uae_u32 opcode) uae_s16 src = get_diword(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpc(4); @@ -45202,6 +45207,7 @@ uae_u32 REGPARAM2 op_0a3c_43_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_diword(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpc(4); diff --git a/cpuemu_50.cpp b/cpuemu_50.cpp index 4df898cc..0dd820fd 100644 --- a/cpuemu_50.cpp +++ b/cpuemu_50.cpp @@ -40869,6 +40869,7 @@ uae_u32 REGPARAM2 op_003c_52_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iiword_jit(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpc(4); @@ -40900,6 +40901,7 @@ uae_u32 REGPARAM2 op_023c_52_ff(uae_u32 opcode) uae_s16 src = get_iiword_jit(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpc(4); @@ -40930,6 +40932,7 @@ uae_u32 REGPARAM2 op_0a3c_52_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iiword_jit(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpc(4); @@ -45231,6 +45234,7 @@ uae_u32 REGPARAM2 op_003c_53_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iiword_jit(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr |= src; MakeFromSR(); m68k_incpc(4); @@ -45262,6 +45266,7 @@ uae_u32 REGPARAM2 op_023c_53_ff(uae_u32 opcode) uae_s16 src = get_iiword_jit(2); src &= 0xFF; src |= 0xff00; + if(regs.t0) check_t0_trace(); regs.sr &= src; MakeFromSR(); m68k_incpc(4); @@ -45292,6 +45297,7 @@ uae_u32 REGPARAM2 op_0a3c_53_ff(uae_u32 opcode) MakeSR(); uae_s16 src = get_iiword_jit(2); src &= 0xFF; + if(regs.t0) check_t0_trace(); regs.sr ^= src; MakeFromSR(); m68k_incpc(4); diff --git a/gencpu.cpp b/gencpu.cpp index 71893bc4..caf26373 100644 --- a/gencpu.cpp +++ b/gencpu.cpp @@ -5575,8 +5575,12 @@ static void gen_opcode (unsigned int opcode) genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, cpu_level == 1 ? GF_NOREFILL : 0); if (curi->size == sz_byte) { out("src &= 0xFF;\n"); - if (curi->mnemo == i_ANDSR) + if (curi->mnemo == i_ANDSR) { out("src |= 0xff00;\n"); + } + if (cpu_level == 2 || cpu_level == 3) { + check_trace(); + } } else { check_trace(); }