From: Toni Wilen Date: Thu, 7 Aug 2014 17:38:58 +0000 (+0300) Subject: 2900b9 X-Git-Tag: 3000~89 X-Git-Url: https://git.unchartedbackwaters.co.uk/w/?a=commitdiff_plain;h=f53ba28af52c4f6ea401e85a842dd03ca0f323d3;p=francis%2Fwinuae.git 2900b9 --- diff --git a/a2065.cpp b/a2065.cpp index d554e308..a0027566 100644 --- a/a2065.cpp +++ b/a2065.cpp @@ -833,7 +833,7 @@ DECLARE_MEMORY_FUNCTIONS(a2065); static addrbank a2065_bank = { a2065_lget, a2065_wget, a2065_bget, a2065_lput, a2065_wput, a2065_bput, - default_xlate, default_check, NULL, _T("A2065 Z2 Ethernet"), + default_xlate, default_check, NULL, NULL, _T("A2065 Z2 Ethernet"), a2065_lgeti, a2065_wgeti, ABFLAG_IO }; diff --git a/a2091.cpp b/a2091.cpp index 0a7048d4..4580f9a7 100644 --- a/a2091.cpp +++ b/a2091.cpp @@ -1658,6 +1658,8 @@ static uae_u32 REGPARAM2 dmac_wgeti (struct wd_state *wd, uaecptr addr) addr &= 65535; if (addr >= ROM_OFFSET) v = (wd->rom[addr & wd->rom_mask] << 8) | wd->rom[(addr + 1) & wd->rom_mask]; + else + write_log(_T("Invalid DMAC instruction access %08x\n"), addr); return v; } static uae_u32 REGPARAM2 dmac_lgeti (struct wd_state *wd, uaecptr addr) @@ -1667,7 +1669,8 @@ static uae_u32 REGPARAM2 dmac_lgeti (struct wd_state *wd, uaecptr addr) special_mem |= S_READ; #endif addr &= 65535; - v = (dmac_wgeti (wd, addr) << 16) | dmac_wgeti (wd, addr + 2); + v = dmac_wgeti (wd, addr) << 16; + v |= dmac_wgeti (wd, addr + 2); return v; } @@ -1770,13 +1773,13 @@ static void REGPARAM2 dmac_a20912_lput (uaecptr addr, uae_u32 b) addrbank dmaca2091_bank = { dmac_a2091_lget, dmac_a2091_wget, dmac_a2091_bget, dmac_a2091_lput, dmac_a2091_wput, dmac_a2091_bput, - dmac_a2091_xlate, dmac_a2091_check, NULL, _T("A2091/A590"), + dmac_a2091_xlate, dmac_a2091_check, NULL, NULL, _T("A2091/A590"), dmac_a2091_lgeti, dmac_a2091_wgeti, ABFLAG_IO | ABFLAG_SAFE }; addrbank dmaca2091_2_bank = { dmac_a20912_lget, dmac_a20912_wget, dmac_a20912_bget, dmac_a20912_lput, dmac_a20912_wput, dmac_a20912_bput, - dmac_a20912_xlate, dmac_a20912_check, NULL, _T("A2091/A590 #2"), + dmac_a20912_xlate, dmac_a20912_check, NULL, NULL, _T("A2091/A590 #2"), dmac_a20912_lgeti, dmac_a20912_wgeti, ABFLAG_IO | ABFLAG_SAFE }; @@ -2017,7 +2020,7 @@ static void REGPARAM2 mbdmac_bput (uaecptr addr, uae_u32 b) addrbank mbdmac_a3000_bank = { mbdmac_lget, mbdmac_wget, mbdmac_bget, mbdmac_lput, mbdmac_wput, mbdmac_bput, - default_xlate, default_check, NULL, _T("A3000 DMAC"), + default_xlate, default_check, NULL, NULL, _T("A3000 DMAC"), dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE }; diff --git a/akiko.cpp b/akiko.cpp index d6586571..4984397b 100644 --- a/akiko.cpp +++ b/akiko.cpp @@ -1805,7 +1805,7 @@ static void REGPARAM2 akiko_lput (uaecptr addr, uae_u32 v) addrbank akiko_bank = { akiko_lget, akiko_wget, akiko_bget, akiko_lput, akiko_wput, akiko_bput, - default_xlate, default_check, NULL, _T("Akiko"), + default_xlate, default_check, NULL, NULL, _T("Akiko"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; diff --git a/ar.cpp b/ar.cpp index 8fe0f15a..ebc79105 100644 --- a/ar.cpp +++ b/ar.cpp @@ -461,19 +461,19 @@ static uae_u8 *REGPARAM2 hrtmem_xlate (uaecptr addr) static addrbank hrtmem_bank = { hrtmem_lget, hrtmem_wget, hrtmem_bget, hrtmem_lput, hrtmem_wput, hrtmem_bput, - hrtmem_xlate, hrtmem_check, NULL, _T("Cartridge Bank"), + hrtmem_xlate, hrtmem_check, NULL, NULL, _T("Cartridge Bank"), hrtmem_lget, hrtmem_wget, ABFLAG_RAM }; static addrbank hrtmem2_bank = { hrtmem2_lget, hrtmem2_wget, hrtmem2_bget, hrtmem2_lput, hrtmem2_wput, hrtmem2_bput, - hrtmem2_xlate, hrtmem2_check, NULL, _T("Cartridge Bank 2"), + hrtmem2_xlate, hrtmem2_check, NULL, NULL, _T("Cartridge Bank 2"), hrtmem2_lget, hrtmem2_wget, ABFLAG_RAM }; static addrbank hrtmem3_bank = { hrtmem3_lget, hrtmem3_wget, hrtmem3_bget, hrtmem3_lput, hrtmem3_wput, hrtmem3_bput, - hrtmem3_xlate, hrtmem3_check, NULL, _T("Cartridge Bank 3"), + hrtmem3_xlate, hrtmem3_check, NULL, NULL, _T("Cartridge Bank 3"), hrtmem3_lget, hrtmem3_wget, ABFLAG_RAM }; @@ -876,13 +876,13 @@ static uae_u8 *REGPARAM2 arrom_xlate (uaecptr addr) static addrbank arrom_bank = { arrom_lget, arrom_wget, arrom_bget, arrom_lput, arrom_wput, arrom_bput, - arrom_xlate, arrom_check, NULL, _T("Action Replay ROM"), + arrom_xlate, arrom_check, NULL, NULL, _T("Action Replay ROM"), arrom_lget, arrom_wget, ABFLAG_ROM }; static addrbank arram_bank = { arram_lget, arram_wget, arram_bget, arram_lput, arram_wput, arram_bput, - arram_xlate, arram_check, NULL, _T("Action Replay RAM"), + arram_xlate, arram_check, NULL, NULL, _T("Action Replay RAM"), arram_lget, arram_wget, ABFLAG_RAM }; @@ -1571,7 +1571,11 @@ static int superiv_init (struct romdata *rd, struct zfile *f) if (hrtmem2_size && !hrtmem2_size2) hrtmem2_size2 = hrtmem2_size; - hrtmemory = mapped_malloc (hrtmem_size, memname1); + hrtmem_bank.allocated = hrtmem_size; + hrtmem_bank.label = memname1; + hrtmem_mask = hrtmem_size - 1; + mapped_malloc (&hrtmem_bank); + hrtmemory = hrtmem_bank.baseaddr; memset (hrtmemory, 0x00, hrtmem_size); if (f) { zfile_fseek (f, 0, SEEK_SET); @@ -1579,20 +1583,23 @@ static int superiv_init (struct romdata *rd, struct zfile *f) zfile_fclose (f); } - hrtmem_mask = hrtmem_size - 1; hrtmem2_mask = hrtmem2_size - 1; - hrtmem3_mask = hrtmem3_size - 1; + hrtmem2_bank.allocated = hrtmem2_size; + hrtmem2_bank.label = memname2; if (hrtmem2_size) { - hrtmemory2 = mapped_malloc (hrtmem2_size, memname2); + mapped_malloc (&hrtmem2_bank); + hrtmemory2 = hrtmem2_bank.baseaddr; memset(hrtmemory2, 0, hrtmem2_size); } + + hrtmem3_bank.allocated = hrtmem3_size; + hrtmem3_bank.label = memname3; + hrtmem3_mask = hrtmem3_size - 1; if (hrtmem3_size) { - hrtmemory3 = mapped_malloc (hrtmem3_size, memname3); + mapped_malloc (&hrtmem3_bank); + hrtmemory3 = hrtmem3_bank.baseaddr; memset(hrtmemory3, 0, hrtmem3_size); } - hrtmem3_bank.baseaddr = hrtmemory3; - hrtmem2_bank.baseaddr = hrtmemory2; - hrtmem_bank.baseaddr = hrtmemory; if (flags & ROMTYPE_XPOWER) { hrtmon_custom = hrtmemory2 + 0xfc00; @@ -1725,12 +1732,9 @@ void action_replay_cleanup() free (armemory_rom); if (armemory_ram) free (armemory_ram); - if (hrtmemory) - mapped_free (hrtmemory); - if (hrtmemory2) - mapped_free (hrtmemory2); - if (hrtmemory3) - mapped_free (hrtmemory3); + mapped_free (&hrtmem_bank); + mapped_free (&hrtmem2_bank); + mapped_free (&hrtmem3_bank); armemory_rom = 0; armemory_ram = 0; @@ -1838,7 +1842,10 @@ int hrtmon_load (void) #endif cart_type = CART_HRTMON; } - hrtmemory = mapped_malloc (hrtmem_size, _T("hrtmem")); + hrtmem_bank.allocated = hrtmem_size; + hrtmem_bank.label = _T("hrtmem"); + mapped_malloc (&hrtmem_bank); + hrtmemory = hrtmem_bank.baseaddr; memset (hrtmemory, 0xff, 0x80000); zfile_fseek (f, 0, SEEK_SET); zfile_fread (hrtmemory, 1, 524288, f); diff --git a/arcadia.cpp b/arcadia.cpp index 5d4f0225..bf379ee7 100644 --- a/arcadia.cpp +++ b/arcadia.cpp @@ -327,7 +327,7 @@ static uae_u8 *REGPARAM2 arbb_xlate (uaecptr addr) static addrbank arcadia_boot_bank = { arbb_lget, arbb_wget, arbb_bget, arbb_lput, arbb_wput, arbb_bput, - arbb_xlate, arbb_check, NULL, _T("Arcadia BIOS"), + arbb_xlate, arbb_check, NULL, NULL, _T("Arcadia BIOS"), arbb_lget, arbb_wget, ABFLAG_ROM | ABFLAG_SAFE, arbb_mask }; @@ -407,7 +407,7 @@ static uae_u8 *REGPARAM2 arb_xlate (uaecptr addr) static addrbank arcadia_rom_bank = { arb_lget, arb_wget, arb_bget, arb_lput, arb_wput, arb_bput, - arb_xlate, arb_check, NULL, _T("Arcadia Game ROM"), + arb_xlate, arb_check, NULL, NULL, _T("Arcadia Game ROM"), arb_lget, arb_wget, ABFLAG_ROM | ABFLAG_SAFE, arb_mask }; diff --git a/autoconf.cpp b/autoconf.cpp index e2c77048..63f3fc98 100644 --- a/autoconf.cpp +++ b/autoconf.cpp @@ -27,29 +27,20 @@ uaecptr EXPANSION_bootcode, EXPANSION_nullfunc; /* ROM tag area memory access */ -uae_u8 *rtarea; uaecptr rtarea_base = RTAREA_DEFAULT; -static uae_u32 REGPARAM3 rtarea_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 rtarea_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 rtarea_bget (uaecptr) REGPARAM; -static void REGPARAM3 rtarea_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 rtarea_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 rtarea_bput (uaecptr, uae_u32) REGPARAM; -static uae_u8 *REGPARAM3 rtarea_xlate (uaecptr) REGPARAM; -static int REGPARAM3 rtarea_check (uaecptr addr, uae_u32 size) REGPARAM; - +DECLARE_MEMORY_FUNCTIONS(rtarea); addrbank rtarea_bank = { rtarea_lget, rtarea_wget, rtarea_bget, rtarea_lput, rtarea_wput, rtarea_bput, - rtarea_xlate, rtarea_check, NULL, _T("UAE Boot ROM"), + rtarea_xlate, rtarea_check, NULL, _T("rtarea"), _T("UAE Boot ROM"), rtarea_lget, rtarea_wget, ABFLAG_ROMIN }; static uae_u8 *REGPARAM2 rtarea_xlate (uaecptr addr) { addr &= 0xFFFF; - return rtarea + addr; + return rtarea_bank.baseaddr + addr; } static int REGPARAM2 rtarea_check (uaecptr addr, uae_u32 size) @@ -72,7 +63,7 @@ static uae_u32 REGPARAM2 rtarea_wget (uaecptr addr) special_mem |= S_READ; #endif addr &= 0xFFFF; - return (rtarea[addr] << 8) + rtarea[addr + 1]; + return (rtarea_bank.baseaddr[addr] << 8) + rtarea_bank.baseaddr[addr + 1]; } static uae_u32 REGPARAM2 rtarea_bget (uaecptr addr) { @@ -80,7 +71,7 @@ static uae_u32 REGPARAM2 rtarea_bget (uaecptr addr) special_mem |= S_READ; #endif addr &= 0xFFFF; - return rtarea[addr]; + return rtarea_bank.baseaddr[addr]; } #define RTAREA_WRITEOFFSET 0xfff0 @@ -93,7 +84,7 @@ static void REGPARAM2 rtarea_bput (uaecptr addr, uae_u32 value) addr &= 0xffff; if (addr < RTAREA_WRITEOFFSET) return; - rtarea[addr] = value; + rtarea_bank.baseaddr[addr] = value; } static void REGPARAM2 rtarea_wput (uaecptr addr, uae_u32 value) { @@ -132,27 +123,27 @@ uae_u32 addr (int ptr) void db (uae_u8 data) { - rtarea[rt_addr++] = data; + rtarea_bank.baseaddr[rt_addr++] = data; } void dw (uae_u16 data) { - rtarea[rt_addr++] = (uae_u8)(data >> 8); - rtarea[rt_addr++] = (uae_u8)data; + rtarea_bank.baseaddr[rt_addr++] = (uae_u8)(data >> 8); + rtarea_bank.baseaddr[rt_addr++] = (uae_u8)data; } void dl (uae_u32 data) { - rtarea[rt_addr++] = data >> 24; - rtarea[rt_addr++] = data >> 16; - rtarea[rt_addr++] = data >> 8; - rtarea[rt_addr++] = data; + rtarea_bank.baseaddr[rt_addr++] = data >> 24; + rtarea_bank.baseaddr[rt_addr++] = data >> 16; + rtarea_bank.baseaddr[rt_addr++] = data >> 8; + rtarea_bank.baseaddr[rt_addr++] = data; } uae_u8 dbg (uaecptr addr) { addr -= rtarea_base; - return rtarea[addr]; + return rtarea_bank.baseaddr[addr]; } /* store strings starting at the end of the rt area and working @@ -167,7 +158,7 @@ uae_u32 ds_ansi (const uae_char *str) return addr (rt_straddr); len = strlen (str) + 1; rt_straddr -= len; - strcpy ((uae_char*)rtarea + rt_straddr, str); + strcpy ((uae_char*)rtarea_bank.baseaddr + rt_straddr, str); return addr (rt_straddr); } @@ -187,8 +178,8 @@ uae_u32 ds_bstr_ansi (const uae_char *str) rt_straddr -= len; while (rt_straddr & 3) rt_straddr--; - rtarea[rt_straddr] = len - 2; - strcpy ((uae_char*)rtarea + rt_straddr + 1, str); + rtarea_bank.baseaddr[rt_straddr] = len - 2; + strcpy ((uae_char*)rtarea_bank.baseaddr + rt_straddr + 1, str); return addr (rt_straddr) >> 2; } @@ -235,12 +226,11 @@ static uae_u32 REGPARAM2 uae_puts (TrapContext *context) void rtarea_init_mem (void) { - rtarea = mapped_malloc (RTAREA_SIZE, _T("rtarea")); - if (!rtarea) { + rtarea_bank.allocated = RTAREA_SIZE; + if (!mapped_malloc (&rtarea_bank)) { write_log (_T("virtual memory exhausted (rtarea)!\n")); abort (); } - rtarea_bank.baseaddr = rtarea; } void rtarea_init (void) @@ -254,7 +244,7 @@ void rtarea_init (void) init_traps (); rtarea_init_mem (); - memset (rtarea, 0, RTAREA_SIZE); + memset (rtarea_bank.baseaddr, 0, RTAREA_SIZE); _stprintf (uaever, _T("uae-%d.%d.%d"), UAEMAJOR, UAEMINOR, UAESUBREV); @@ -304,7 +294,7 @@ volatile int uae_int_requested = 0; void set_uae_int_flag (void) { - rtarea[RTAREA_INT] = uae_int_requested & 1; + rtarea_bank.baseaddr[RTAREA_INT] = uae_int_requested & 1; } void rtarea_setup (void) diff --git a/blkdev_cdimage.cpp b/blkdev_cdimage.cpp index 2d0b79ab..8fde9a34 100644 --- a/blkdev_cdimage.cpp +++ b/blkdev_cdimage.cpp @@ -873,36 +873,34 @@ static int command_rawread (int unitnum, uae_u8 *data, int sector, int size, int goto end; } - if (isaudiotrack (&cdu->di.toc, sector)) { - if (sectortype != 0 && sectortype != 1) { - ret = -2; - goto end; - } - if (t->size != 2352) { - ret = -1; - goto end; - } - for (int i = 0; i < size; i++) { - do_read (cdu, t, data, sector, 0, t->size); - uae_u8 *p = data + t->size; - if (subs) { - uae_u8 subdata[SUB_CHANNEL_SIZE]; - getsub_deinterleaved (subdata, cdu, t, sector); - if (subs == 4) { // all, de-interleaved - memcpy (p, subdata, SUB_CHANNEL_SIZE); - p += SUB_CHANNEL_SIZE; - } else if (subs == 2) { // q-only - memcpy (p, subdata + SUB_ENTRY_SIZE, SUB_ENTRY_SIZE); - p += SUB_ENTRY_SIZE; - } else if (subs == 1) { // all, interleaved - sub_to_interleaved (subdata, p); - p += SUB_CHANNEL_SIZE; - } + if (sectortype != 0 && sectortype != 1) { + ret = -2; + goto end; + } + if (t->size != 2352) { + ret = -1; + goto end; + } + for (int i = 0; i < size; i++) { + do_read (cdu, t, data, sector, 0, t->size); + uae_u8 *p = data + t->size; + if (subs) { + uae_u8 subdata[SUB_CHANNEL_SIZE]; + getsub_deinterleaved (subdata, cdu, t, sector); + if (subs == 4) { // all, de-interleaved + memcpy (p, subdata, SUB_CHANNEL_SIZE); + p += SUB_CHANNEL_SIZE; + } else if (subs == 2) { // q-only + memcpy (p, subdata + SUB_ENTRY_SIZE, SUB_ENTRY_SIZE); + p += SUB_ENTRY_SIZE; + } else if (subs == 1) { // all, interleaved + sub_to_interleaved (subdata, p); + p += SUB_CHANNEL_SIZE; } - ret += p - data; - data = p; - sector++; } + ret += p - data; + data = p; + sector++; } } end: diff --git a/cd32_fmv.cpp b/cd32_fmv.cpp index bc8da77c..0a28f95b 100644 --- a/cd32_fmv.cpp +++ b/cd32_fmv.cpp @@ -187,7 +187,7 @@ static int fmv_video_debug = 0; #define CL_DRAM_PID 0xa1 // 0x0002 #define CL_DRAM_CPU_PC 0xa2 -static uae_u8 *rom, *ram, *audioram; +static uae_u8 *audioram; static const int fmv_rom_size = 262144; static const int fmv_ram_size = 524288; static const uaecptr fmv_start = 0x00200000; @@ -316,12 +316,38 @@ static bool cl450_checkint(bool enabled) void rethink_cd32fmv(void) { - if (!ram) + if (!fmv_ram_bank.baseaddr) return; cl450_checkint(true); l64111_checkint(true); } +DECLARE_MEMORY_FUNCTIONS(fmv); +static addrbank fmv_bank = { + fmv_lget, fmv_wget, fmv_bget, + fmv_lput, fmv_wput, fmv_bput, + default_xlate, default_check, NULL, NULL, _T("CD32 FMV IO"), + fmv_lget, fmv_wget, ABFLAG_IO +}; + +DECLARE_MEMORY_FUNCTIONS(fmv_rom); +static addrbank fmv_rom_bank = { + fmv_rom_lget, fmv_rom_wget, fmv_rom_bget, + fmv_rom_lput, fmv_rom_wput, fmv_rom_bput, + fmv_rom_xlate, fmv_rom_check, NULL, _T("fmv_rom"), _T("CD32 FMV ROM"), + fmv_rom_lget, fmv_rom_wget, ABFLAG_ROM +}; + +DECLARE_MEMORY_FUNCTIONS(fmv_ram); +static addrbank fmv_ram_bank = { + fmv_ram_lget, fmv_ram_wget, fmv_ram_bget, + fmv_ram_lput, fmv_ram_wput, fmv_ram_bput, + fmv_ram_xlate, fmv_ram_check, NULL, _T("fmv_ram"), _T("CD32 FMV RAM"), + fmv_ram_lget, fmv_ram_wget, ABFLAG_RAM +}; + +MEMORY_FUNCTIONS_NOJIT(fmv_rom); +MEMORY_FUNCTIONS_NOJIT(fmv_ram); #define L64111_FIFO_LOOKUP 96 #define L64111_FIFO_BYTES 128 @@ -359,6 +385,8 @@ static void l64111_setvolume(void) int volume = 32768; if (l64111_regs[A_CONTROL2] & (1 << 5) || (io_reg & IO_L64111_MUTE)) volume = 0; + if (!pcmaudio) + return; write_log(_T("L64111 mute %d\n"), volume ? 0 : 1); if (cda) cda->setvolume(currprefs.sound_volume_cd >= 0 ? currprefs.sound_volume_cd : currprefs.sound_volume, volume, volume); @@ -501,9 +529,10 @@ static void l64111_reset(void) l64111_regs[A_CONTROL3] = 1 << 7; // AUDIO STREAM_ID_IGNORE=1 l64111_init(); l64111_setvolume(); - if (pcmaudio) + if (pcmaudio) { memset(pcmaudio, 0, sizeof(struct fmv_pcmaudio) * L64111_CHANNEL_BUFFERS); - write_log(_T("L64111 reset\n")); + write_log(_T("L64111 reset\n")); + } } static uae_u8 *parse_audio_header(uae_u8 *p) @@ -751,10 +780,10 @@ static void cl450_set_status(uae_u16 mask) static void cl450_write_dram(int addr, uae_u16 w) { - if (!ram) + if (!fmv_ram_bank.baseaddr) return; - ram[addr * 2 + 0] = w >> 8; - ram[addr * 2 + 1] = w; + fmv_ram_bank.baseaddr[addr * 2 + 0] = w >> 8; + fmv_ram_bank.baseaddr[addr * 2 + 1] = w; } #if DUMP_VIDEO @@ -796,8 +825,8 @@ static void cl450_parse_frame(void) videodump = zfile_fopen(_T("c:\\temp\\1.mpg"), _T("wb")); zfile_fwrite(&ram[CL450_MPEG_BUFFER], 1, cl450_buffer_offset, videodump); #endif - memcpy(&ram[CL450_MPEG_DECODE_BUFFER] + libmpeg_offset, &ram[CL450_MPEG_BUFFER], cl450_buffer_offset); - mpeg2_buffer(mpeg_decoder, &ram[CL450_MPEG_DECODE_BUFFER] + libmpeg_offset, &ram[CL450_MPEG_DECODE_BUFFER] + libmpeg_offset + cl450_buffer_offset); + memcpy(&fmv_ram_bank.baseaddr[CL450_MPEG_DECODE_BUFFER] + libmpeg_offset, &fmv_ram_bank.baseaddr[CL450_MPEG_BUFFER], cl450_buffer_offset); + mpeg2_buffer(mpeg_decoder, &fmv_ram_bank.baseaddr[CL450_MPEG_DECODE_BUFFER] + libmpeg_offset, &fmv_ram_bank.baseaddr[CL450_MPEG_DECODE_BUFFER] + libmpeg_offset + cl450_buffer_offset); libmpeg_offset += cl450_buffer_offset; if (libmpeg_offset >= CL450_MPEG_DECODE_BUFFER_SIZE - CL450_MPEG_BUFFER_SIZE) libmpeg_offset = 0; @@ -842,7 +871,6 @@ static void cl450_parse_frame(void) static void cl450_reset(void) { - write_log(_T("CL450 reset\n")); cl450_play = 0; cl450_pending_interrupts = 0; cl450_interruptmask = 0; @@ -861,8 +889,10 @@ static void cl450_reset(void) memset(cl450_regs, 0, sizeof cl450_regs); if (mpeg_decoder) mpeg2_reset(mpeg_decoder, 1); - if (ram) - memset(ram, 0, 0x100); + if (fmv_ram_bank.baseaddr) { + memset(fmv_ram_bank.baseaddr, 0, 0x100); + write_log(_T("CL450 reset\n")); + } cl450_write_dram(CL_DRAM_VER, 0x0200); cl450_write_dram(CL_DRAM_PID, 0x0002); } @@ -882,7 +912,7 @@ static void cl450_init(void) cl450_scr = 0; cl450_write_dram(CL_DRAM_VER, 0x0200); cl450_write_dram(CL_DRAM_PID, 0x0002); - memset(ram + 0x10, 0, 0x100 - 0x10); + memset(fmv_ram_bank.baseaddr + 0x10, 0, 0x100 - 0x10); } static void cl450_newpacket(void) @@ -1084,8 +1114,8 @@ static uae_u16 cl450_wget (uaecptr addr) static void cl450_data_wput(uae_u16 v) { - ram[CL450_MPEG_BUFFER + cl450_buffer_offset + 0] = v >> 8; - ram[CL450_MPEG_BUFFER + cl450_buffer_offset + 1] = v; + fmv_ram_bank.baseaddr[CL450_MPEG_BUFFER + cl450_buffer_offset + 0] = v >> 8; + fmv_ram_bank.baseaddr[CL450_MPEG_BUFFER + cl450_buffer_offset + 1] = v; if (cl450_buffer_offset < CL450_MPEG_BUFFER_SIZE - 2) cl450_buffer_offset += 2; } @@ -1333,7 +1363,7 @@ void cd32_fmv_set_sync(double svpos) void cd32_fmv_hsync_handler(void) { - if (!ram) + if (!fmv_ram_bank.baseaddr) return; if (cl450_play > 0) @@ -1384,7 +1414,7 @@ void cd32_fmv_vsync_handler(void) int offset, needsectors; bool play0, play1; - if (!ram) + if (!fmv_ram_bank.baseaddr) return; if (cl450_buffer_offset == 0) { @@ -1431,45 +1461,17 @@ void cd32_fmv_vsync_handler(void) l64111_regs[A_CB_STATUS] -= PCM_SECTORS; } -addrbank fmv_bank = { - fmv_lget, fmv_wget, fmv_bget, - fmv_lput, fmv_wput, fmv_bput, - default_xlate, default_check, NULL, _T("CD32 FMV IO"), - fmv_lget, fmv_wget, ABFLAG_IO -}; - -MEMORY_FUNCTIONS_NOJIT(fmv_rom); - -addrbank fmv_rom_bank = { - fmv_rom_lget, fmv_rom_wget, fmv_rom_bget, - fmv_rom_lput, fmv_rom_wput, fmv_rom_bput, - fmv_rom_xlate, fmv_rom_check, NULL, _T("CD32 FMV ROM"), - fmv_rom_lget, fmv_rom_wget, ABFLAG_ROM -}; - - -MEMORY_FUNCTIONS_NOJIT(fmv_ram); - -addrbank fmv_ram_bank = { - fmv_ram_lget, fmv_ram_wget, fmv_ram_bget, - fmv_ram_lput, fmv_ram_wput, fmv_ram_bput, - fmv_ram_xlate, fmv_ram_check, NULL, _T("CD32 FMV RAM"), - fmv_ram_lget, fmv_ram_wget, ABFLAG_RAM -}; - void cd32_fmv_reset(void) { - if (ram) - memset(ram, 0, fmv_ram_size); + if (fmv_ram_bank.baseaddr) + memset(fmv_ram_bank.baseaddr, 0, fmv_ram_bank.allocated); cd32_fmv_state(0); } void cd32_fmv_free(void) { - mapped_free(rom); - rom = NULL; - mapped_free(ram); - ram = NULL; + mapped_free(&fmv_rom_bank); + mapped_free(&fmv_ram_bank); xfree(audioram); audioram = NULL; xfree(videoram); @@ -1510,15 +1512,19 @@ void cd32_fmv_init (uaecptr start) z = read_rom (rd); } } + fmv_rom_bank.mask = fmv_rom_size - 1; + fmv_rom_bank.allocated = fmv_rom_size; + fmv_ram_bank.mask = fmv_ram_size - 1; + fmv_ram_bank.allocated = fmv_ram_size; + if (z) { - rom = mapped_malloc(fmv_rom_size, _T("fmv_rom")); - if (rom) { + if (mapped_malloc(&fmv_rom_bank)) { int size = zfile_size(z); - zfile_fread (rom, size > fmv_rom_size ? fmv_rom_size : size, 1, z); + zfile_fread (fmv_rom_bank.baseaddr, size > fmv_rom_size ? fmv_rom_size : size, 1, z); } zfile_fclose (z); } - if (!rom) { + if (!fmv_rom_bank.baseaddr) { write_log(_T("CD32 FMV without ROM is not supported.\n")); return; } @@ -1526,8 +1532,7 @@ void cd32_fmv_init (uaecptr start) audioram = xmalloc(uae_u8, 262144); if (!videoram) videoram = xmalloc(struct cl450_videoram, CL450_VIDEO_BUFFERS); - if (!ram) - ram = mapped_malloc(fmv_ram_size, _T("fmv_ram")); + mapped_malloc(&fmv_ram_bank); if (!pcmaudio) pcmaudio = xcalloc(struct fmv_pcmaudio, L64111_CHANNEL_BUFFERS); @@ -1541,12 +1546,6 @@ void cd32_fmv_init (uaecptr start) mpeg_info = mpeg2_info(mpeg_decoder); } - fmv_rom_bank.mask = fmv_rom_size - 1; - fmv_rom_bank.baseaddr = rom; - fmv_rom_bank.allocated = fmv_rom_size; - fmv_ram_bank.mask = fmv_ram_size - 1; - fmv_ram_bank.baseaddr = ram; - fmv_ram_bank.allocated = fmv_ram_size; fmv_bank.mask = fmv_board_size - 1; map_banks(&fmv_rom_bank, (fmv_start + ROM_BASE) >> 16, fmv_rom_size >> 16, 0); map_banks(&fmv_ram_bank, (fmv_start + RAM_BASE) >> 16, fmv_ram_size >> 16, 0); diff --git a/cdtv.cpp b/cdtv.cpp index 59b45aa2..939449d2 100644 --- a/cdtv.cpp +++ b/cdtv.cpp @@ -1545,7 +1545,7 @@ static uae_u32 REGPARAM2 dmac_lgeti (uaecptr addr) addrbank dmac_bank = { dmac_lget, dmac_wget, dmac_bget, dmac_lput, dmac_wput, dmac_bput, - default_xlate, default_check, NULL, _T("CDTV DMAC/CD Controller"), + default_xlate, default_check, NULL, NULL, _T("CDTV DMAC/CD Controller"), dmac_lgeti, dmac_wgeti, ABFLAG_IO }; diff --git a/cfgfile.cpp b/cfgfile.cpp index fb3f85e4..26b3dbba 100644 --- a/cfgfile.cpp +++ b/cfgfile.cpp @@ -3510,7 +3510,7 @@ static int cfgfile_parse_hardware (struct uae_prefs *p, const TCHAR *option, TCH if (p->cpu_model >= 68020 && p->cachesize > 0) p->cpu_cycle_exact = p->blitter_cycle_exact = false; // if old version and CE and fastest possible: set to approximate - if (p->config_version < ((2 << 16) | (8 << 8) | (2 << 0)) && p->m68k_speed < 0) + if (p->cpu_cycle_exact && p->config_version < ((2 << 16) | (8 << 8) | (2 << 0)) && p->m68k_speed < 0) p->m68k_speed = 0; return 1; } diff --git a/cia.cpp b/cia.cpp index d36aa022..e7171e20 100644 --- a/cia.cpp +++ b/cia.cpp @@ -1595,19 +1595,11 @@ void dumpcia (void) /* CIA memory access */ -static uae_u32 REGPARAM3 cia_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 cia_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 cia_bget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 cia_lgeti (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 cia_wgeti (uaecptr) REGPARAM; -static void REGPARAM3 cia_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 cia_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 cia_bput (uaecptr, uae_u32) REGPARAM; - +DECLARE_MEMORY_FUNCTIONS(cia); addrbank cia_bank = { cia_lget, cia_wget, cia_bget, cia_lput, cia_wput, cia_bput, - default_xlate, default_check, NULL, _T("CIA"), + default_xlate, default_check, NULL, NULL, _T("CIA"), cia_lgeti, cia_wgeti, ABFLAG_IO, 0x3f01, 0xbfc000 }; @@ -1909,7 +1901,7 @@ static void REGPARAM3 clock_bput (uaecptr, uae_u32) REGPARAM; addrbank clock_bank = { clock_lget, clock_wget, clock_bget, clock_lput, clock_wput, clock_bput, - default_xlate, default_check, NULL, _T("Battery backed up clock (none)"), + default_xlate, default_check, NULL, NULL, _T("Battery backed up clock (none)"), dummy_lgeti, dummy_wgeti, ABFLAG_IO, 0x3f, 0xd80000 }; diff --git a/cpuboard.cpp b/cpuboard.cpp index 9a3ebcfc..f3783ea6 100644 --- a/cpuboard.cpp +++ b/cpuboard.cpp @@ -26,6 +26,10 @@ #include "debug.h" #include "flashrom.h" #include "uae.h" +#include "ppc.h" + +#define CPUBOARD_IO_LOG 0 +#define CPUBOARD_IRQ_LOG 0 #define F0_WAITSTATES (2 * CYCLE_UNIT) @@ -39,57 +43,85 @@ #define CSIII_REG_SHADOW 0x03 // 0x18 #define CSIII_REG_LOCK 0x04 // 0x20 #define CSIII_REG_INT 0x05 // 0x28 -#define CSIII_IPL_EMU 0x06 // 0x30 -#define CSIII_INT_LVL 0x07 // 0x38 -#define BPPC_MAGIC 0x13 +#define CSIII_REG_IPL_EMU 0x06 // 0x30 +#define CSIII_REG_INT_LVL 0x07 // 0x38 + +// BPPC only +#define BPPC_MAPROM_ON 0x12 +#define BPPC_MAPROM_OFF 0x13 +#define BPPC_UNLOCK_FLASH 0x92 +#define BPPC_LOCK_FLASH 0x93 +#define BPPC_MAGIC_UNLOCK 0x42 /* bit definitions */ -#define P5_SET_CLEAR 0x80 -/* REQ_RESET */ -#define P5_PPC_RESET 0x10 -#define P5_M68K_RESET 0x08 -#define P5_AMIGA_RESET 0x04 -#define P5_AUX_RESET 0x02 -#define P5_SCSI_RESET 0x01 -/* REG_IRQ */ -#define P5_IRQ_SCSI 0x01 -#define P5_IRQ_SCSI_EN 0x02 -#define P5_IRQ_PPC_1 0x08 -#define P5_IRQ_PPC_2 0x10 -/* REG_WAITSTATE */ -#define P5_PPC_WRITE 0x08 -#define P5_PPC_READ 0x04 -#define P5_M68K_WRITE 0x02 -#define P5_M68K_READ 0x01 -/* REG_SHADOW */ -#define P5_SELF_RESET 0x40 -#define P5_UNK 0x04 // something to do with flash chip -#define P5_SHADOW 0x01 // 1 = ks map rom to 0xfff80000 -/* REG_LOCK */ -#define P5_MAGIC1 0x60 // REG_SHADOW and flash write protection unlock sequence -#define P5_MAGIC2 0x50 -#define P5_MAGIC3 0x30 -#define P5_MAGIC4 0x70 -/* REG_INT */ -#define P5_ENABLE_IPL 0x02 -#define P5_INT_MASTER 0x01 // 1=m68k gets interrupts, 0=ppc gets interrupts. -/* IPL_EMU */ -#define P5_DISABLE_INT 0x40 // if set: all CPU interrupts disabled -#define P5_M68K_IPL2 0x20 -#define P5_M68K_IPL1 0x10 -#define P5_M68K_IPL0 0x08 -#define P5_PPC_IPL2 0x04 -#define P5_PPC_IPL1 0x02 -#define P5_PPC_IPL0 0x01 -#define P5_IPL_MASK 0x07 -/* INT_LVL */ -#define P5_LVL7 0x40 -#define P5_LVL6 0x20 -#define P5_LVL5 0x10 -#define P5_LVL4 0x08 -#define P5_LVL3 0x04 -#define P5_LVL2 0x02 -#define P5_LVL1 0x01 +#define P5_SET_CLEAR 0x80 + +/* REQ_RESET 0x00 */ +#define P5_PPC_RESET 0x10 +#define P5_M68K_RESET 0x08 +#define P5_AMIGA_RESET 0x04 +#define P5_AUX_RESET 0x02 +#define P5_SCSI_RESET 0x01 + +/* REG_IRQ 0x08 */ +#define P5_IRQ_SCSI 0x01 +#define P5_IRQ_SCSI_EN 0x02 +// 0x04 +#define P5_IRQ_PPC_1 0x08 +#define P5_IRQ_PPC_2 0x10 +// 0x20 +// 0x40 always cleared + +/* REG_WAITSTATE 0x10 */ +#define P5_PPC_WRITE 0x08 +#define P5_PPC_READ 0x04 +#define P5_M68K_WRITE 0x02 +#define P5_M68K_READ 0x01 + +/* REG_SHADOW 0x18 */ +#define P5_SELF_RESET 0x40 +// 0x20 +// 0x10 +// 0x08 always set +#define P5_FLASH 0x04 // Flash writable (CSMK3,CSPPC only) +// 0x02 (can be modified even when locked) +#define P5_SHADOW 0x01 // KS MAP ROM + +/* REG_LOCK 0x20. CSMK3,CSPPC only */ +#define P5_MAGIC1 0x60 // REG_SHADOW and flash write protection unlock sequence +#define P5_MAGIC2 0x50 +#define P5_MAGIC3 0x30 +#define P5_MAGIC4 0x70 +#define P5_GEN_INT2 0x01 + +/* REG_INT 0x28 */ +// 0x40 always set +// 0x20 +// 0x10 always cleared +// 0x08 +// 0x04 +#define P5_ENABLE_IPL 0x02 +#define P5_INT_MASTER 0x01 // 1=m68k gets interrupts, 0=ppc gets interrupts. + +/* IPL_EMU 0x30 */ +#define P5_DISABLE_INT 0x40 // if set: all CPU interrupts disabled? +#define P5_M68K_IPL2 0x20 +#define P5_M68K_IPL1 0x10 +#define P5_M68K_IPL0 0x08 +#define P5_M68k_IPL_MASK 0x38 +#define P5_PPC_IPL2 0x04 +#define P5_PPC_IPL1 0x02 +#define P5_PPC_IPL0 0x01 +#define P5_PPC_IPL_MASK 0x07 + +/* INT_LVL 0x38 */ +#define P5_LVL7 0x40 +#define P5_LVL6 0x20 +#define P5_LVL5 0x10 +#define P5_LVL4 0x08 +#define P5_LVL3 0x04 +#define P5_LVL2 0x02 +#define P5_LVL1 0x01 #define CS_RAM_BASE 0x0c000000 @@ -113,7 +145,80 @@ static void *flashrom; static struct zfile *flashrom_file; static int flash_unlocked; static int csmk2_flashaddressing; -static bool blizzardmaprom_bank_mapped; +static bool blizzardmaprom_bank_mapped, blizzardmaprom2_bank_mapped; + +static int ppc_irq_pending; +static bool ppc_int_interrupt; + +static void set_ppc_interrupt(int level) +{ + if (ppc_irq_pending > level) + return; +#if CPUBOARD_IRQ_LOG > 0 + write_log(_T("PPC interrupt set (%d)\n"), level); +#endif + ppc_interrupt(true); + ppc_irq_pending = level; +} +static void clear_ppc_interrupt(void) +{ + if (!ppc_irq_pending) + return; +#if CPUBOARD_IRQ_LOG > 0 + write_log(_T("PPC interrupt clear\n")); +#endif + ppc_interrupt(false); + ppc_irq_pending = 0; +} + +static void check_ppc_int_lvl(void) +{ + uae_u8 ipl; + uae_u8 il; + if (!(io_reg[CSIII_REG_INT] & P5_ENABLE_IPL)) { + ipl = (~io_reg[CSIII_REG_IPL_EMU]) & P5_PPC_IPL_MASK; + if (ipl < 7) { + il = (~io_reg[CSIII_REG_INT_LVL]) & 0x7f; + if (il) { + for (int i = ipl; i < 7; i++) { + if (il & (1 << i)) { + set_ppc_interrupt(i + 1); + return; + } + } + } + } + } + clear_ppc_interrupt(); +} + +bool ppc_interrupt(int new_m68k_ipl) +{ + uae_u8 ppcipl; + bool m68kint = (io_reg[CSIII_REG_INT] & P5_INT_MASTER) != 0; + bool active = (io_reg[CSIII_REG_IPL_EMU] & P5_DISABLE_INT) == 0; + bool iplemu = (io_reg[CSIII_REG_INT] & P5_ENABLE_IPL) == 0; + + if (!active) + return false; + + if (new_m68k_ipl < 0) + new_m68k_ipl = 0; + ppcipl = (io_reg[CSIII_REG_IPL_EMU] ^ 7) & 7; + + if (!m68kint && iplemu && active) { + if (new_m68k_ipl > ppcipl) { + set_ppc_interrupt(new_m68k_ipl); + } else { + clear_ppc_interrupt(); + } + io_reg[CSIII_REG_IPL_EMU] &= ~P5_M68k_IPL_MASK; + io_reg[CSIII_REG_IPL_EMU] |= (new_m68k_ipl << 3) ^ P5_M68k_IPL_MASK; + } + + return m68kint; +} + static bool is_blizzard(void) { @@ -150,7 +255,7 @@ DECLARE_MEMORY_FUNCTIONS(blizzardio); static addrbank blizzardio_bank = { blizzardio_lget, blizzardio_wget, blizzardio_bget, blizzardio_lput, blizzardio_wput, blizzardio_bput, - default_xlate, default_check, NULL, _T("CPUBoard IO"), + default_xlate, default_check, NULL, NULL, _T("CPUBoard IO"), blizzardio_wget, blizzardio_bget, ABFLAG_IO }; @@ -158,7 +263,7 @@ DECLARE_MEMORY_FUNCTIONS(blizzardram); static addrbank blizzardram_bank = { blizzardram_lget, blizzardram_wget, blizzardram_bget, blizzardram_lput, blizzardram_wput, blizzardram_bput, - blizzardram_xlate, blizzardram_check, NULL, _T("CPUBoard RAM"), + blizzardram_xlate, blizzardram_check, NULL, NULL, _T("CPUBoard RAM"), blizzardram_lget, blizzardram_wget, ABFLAG_RAM }; @@ -166,7 +271,7 @@ DECLARE_MEMORY_FUNCTIONS(blizzardea); static addrbank blizzardea_bank = { blizzardea_lget, blizzardea_wget, blizzardea_bget, blizzardea_lput, blizzardea_wput, blizzardea_bput, - blizzardea_xlate, blizzardea_check, NULL, _T("CPUBoard EA Autoconfig"), + blizzardea_xlate, blizzardea_check, NULL, _T("rom_ea"), _T("CPUBoard EA Autoconfig"), blizzardea_lget, blizzardea_wget, ABFLAG_IO | ABFLAG_SAFE }; @@ -174,7 +279,7 @@ DECLARE_MEMORY_FUNCTIONS(blizzarde8); static addrbank blizzarde8_bank = { blizzarde8_lget, blizzarde8_wget, blizzarde8_bget, blizzarde8_lput, blizzarde8_wput, blizzarde8_bput, - blizzarde8_xlate, blizzarde8_check, NULL, _T("CPUBoard E8 Autoconfig"), + blizzarde8_xlate, blizzarde8_check, NULL, NULL, _T("CPUBoard E8 Autoconfig"), blizzarde8_lget, blizzarde8_wget, ABFLAG_IO | ABFLAG_SAFE }; @@ -182,7 +287,7 @@ DECLARE_MEMORY_FUNCTIONS(blizzardf0); static addrbank blizzardf0_bank = { blizzardf0_lget, blizzardf0_wget, blizzardf0_bget, blizzardf0_lput, blizzardf0_wput, blizzardf0_bput, - blizzardf0_xlate, blizzardf0_check, NULL, _T("CPUBoard F00000"), + blizzardf0_xlate, blizzardf0_check, NULL, _T("rom_f0"), _T("CPUBoard F00000"), blizzardf0_lget, blizzardf0_wget, ABFLAG_ROM }; @@ -190,7 +295,7 @@ DECLARE_MEMORY_FUNCTIONS(blizzardram_nojit); static addrbank blizzardram_nojit_bank = { blizzardram_nojit_lget, blizzardram_nojit_wget, blizzardram_nojit_bget, blizzardram_nojit_lput, blizzardram_nojit_wput, blizzardram_nojit_bput, - blizzardram_nojit_xlate, blizzardram_nojit_check, NULL, _T("CPUBoard RAM"), + blizzardram_nojit_xlate, blizzardram_nojit_check, NULL, NULL, _T("CPUBoard RAM"), blizzardram_nojit_lget, blizzardram_nojit_wget, ABFLAG_RAM }; @@ -198,17 +303,43 @@ DECLARE_MEMORY_FUNCTIONS(blizzardmaprom); static addrbank blizzardmaprom_bank = { blizzardmaprom_lget, blizzardmaprom_wget, blizzardmaprom_bget, blizzardmaprom_lput, blizzardmaprom_wput, blizzardmaprom_bput, - blizzardmaprom_xlate, blizzardmaprom_check, NULL, _T("CPUBoard MAPROM"), + blizzardmaprom_xlate, blizzardmaprom_check, NULL, _T("maprom"), _T("CPUBoard MAPROM"), blizzardmaprom_lget, blizzardmaprom_wget, ABFLAG_RAM }; DECLARE_MEMORY_FUNCTIONS(blizzardmaprom2); static addrbank blizzardmaprom2_bank = { blizzardmaprom2_lget, blizzardmaprom2_wget, blizzardmaprom2_bget, blizzardmaprom2_lput, blizzardmaprom2_wput, blizzardmaprom2_bput, - blizzardmaprom2_xlate, blizzardmaprom2_check, NULL, _T("CPUBoard MAPROM2"), + blizzardmaprom2_xlate, blizzardmaprom2_check, NULL, _T("maprom2"), _T("CPUBoard MAPROM2"), blizzardmaprom2_lget, blizzardmaprom2_wget, ABFLAG_RAM }; +// hack to map F41000 SCSI SCRIPTS RAM to JIT friendly address +void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32 v) +{ + addr &= 0xffff; + addr += (CSIII_NCR & 0x7ffff); + blizzardf0_bank.baseaddr[addr] = v; +} +uae_u32 cyberstorm_scsi_ram_get(uaecptr addr) +{ + uae_u32 v; + addr &= 0xffff; + addr += (CSIII_NCR & 0x7ffff); + v = blizzardf0_bank.baseaddr[addr]; + return v; +} +uae_u8 *REGPARAM2 cyberstorm_scsi_ram_xlate(uaecptr addr) +{ + addr &= 0xffff; + addr += (CSIII_NCR & 0x7ffff); + return blizzardf0_bank.baseaddr + addr; +} +int REGPARAM2 cyberstorm_scsi_ram_check(uaecptr a, uae_u32 b) +{ + a &= 0xffff; + return a >= 0x1000 && a + b < 0x3000; +} MEMORY_FUNCTIONS(blizzardram); @@ -266,38 +397,12 @@ static void no_rom_protect(void) MEMORY_BGET(blizzardmaprom2, 1); MEMORY_WGET(blizzardmaprom2, 1); MEMORY_LGET(blizzardmaprom2, 1); +MEMORY_BPUT(blizzardmaprom2, 1); +MEMORY_WPUT(blizzardmaprom2, 1); +MEMORY_LPUT(blizzardmaprom2, 1); MEMORY_CHECK(blizzardmaprom2); MEMORY_XLATE(blizzardmaprom2); -static void REGPARAM2 blizzardmaprom2_lput(uaecptr addr, uae_u32 l) -{ - uae_u32 *m; -#ifdef JIT - special_mem |= S_WRITE; -#endif - addr &= blizzardmaprom2_bank.mask; - m = (uae_u32 *)(blizzardmaprom2_bank.baseaddr + addr); - do_put_mem_long(m, l); -} -static void REGPARAM2 blizzardmaprom2_wput(uaecptr addr, uae_u32 w) -{ - uae_u16 *m; -#ifdef JIT - special_mem |= S_WRITE; -#endif - addr &= blizzardmaprom2_bank.mask; - m = (uae_u16 *)(blizzardmaprom2_bank.baseaddr + addr); - do_put_mem_word(m, w); -} -static void REGPARAM2 blizzardmaprom2_bput(uaecptr addr, uae_u32 b) -{ -#ifdef JIT - special_mem |= S_WRITE; -#endif - addr &= blizzardmaprom2_bank.mask; - blizzardmaprom2_bank.baseaddr[addr] = b; -} - MEMORY_BGET(blizzardmaprom, 1); MEMORY_WGET(blizzardmaprom, 1); MEMORY_LGET(blizzardmaprom, 1); @@ -356,7 +461,6 @@ static void REGPARAM2 blizzardmaprom_bput(uaecptr addr, uae_u32 b) MEMORY_CHECK(blizzardea); MEMORY_XLATE(blizzardea); - static int REGPARAM2 blizzarde8_check(uaecptr addr, uae_u32 size) { return 0; @@ -373,10 +477,9 @@ static uae_u32 REGPARAM2 blizzardf0_lget(uaecptr addr) #endif uae_u32 *m; - regs.memory_waitstate_cycles += F0_WAITSTATES * 6; + //write_log(_T("F0 LONGGET %08x\n"), addr); - if (is_blizzardppc() && (flash_unlocked & 2)) - addr += 262144; + regs.memory_waitstate_cycles += F0_WAITSTATES * 6; addr &= blizzardf0_bank.mask; m = (uae_u32 *)(blizzardf0_bank.baseaddr + addr); @@ -391,9 +494,6 @@ static uae_u32 REGPARAM2 blizzardf0_wget(uaecptr addr) regs.memory_waitstate_cycles += F0_WAITSTATES * 3; - if (is_blizzardppc() && (flash_unlocked & 2)) - addr += 262144; - addr &= blizzardf0_bank.mask; m = (uae_u16 *)(blizzardf0_bank.baseaddr + addr); v = do_get_mem_word(m); @@ -409,44 +509,23 @@ static uae_u32 REGPARAM2 blizzardf0_bget(uaecptr addr) regs.memory_waitstate_cycles += F0_WAITSTATES * 1; if (is_csmk3() || is_blizzardppc()) { - if (is_blizzardppc() && (flash_unlocked & 2)) - addr += 262144; if (flash_unlocked) { return flash_read(flashrom, addr); } + } else if (is_csmk2()) { + addr &= 65535; + addr += 65536; + return flash_read(flashrom, addr); + } else if (is_csmk1()) { + addr &= 65535; + addr += 65536; + return flash_read(flashrom, addr); } addr &= blizzardf0_bank.mask; v = blizzardf0_bank.baseaddr[addr]; return v; } -// hack to map F41000 SCSI SCRIPTS RAM to JIT friendly address -void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32 v) -{ - addr &= 0xffff; - addr += (CSIII_NCR & 0x7ffff); - blizzardf0_bank.baseaddr[addr] = v; -} -uae_u32 cyberstorm_scsi_ram_get(uaecptr addr) -{ - uae_u32 v; - addr &= 0xffff; - addr += (CSIII_NCR & 0x7ffff); - v = blizzardf0_bank.baseaddr[addr]; - return v; -} -uae_u8 *REGPARAM2 cyberstorm_scsi_ram_xlate (uaecptr addr) -{ - addr &= 0xffff; - addr += (CSIII_NCR & 0x7ffff); - return blizzardf0_bank.baseaddr + addr; -} -int REGPARAM2 cyberstorm_scsi_ram_check (uaecptr a, uae_u32 b) -{ - a &= 0xffff; - return a >= 0x1000 && a + b < 0x3000; -} - static void REGPARAM2 blizzardf0_lput(uaecptr addr, uae_u32 b) { #ifdef JIT @@ -470,10 +549,18 @@ static void REGPARAM2 blizzardf0_bput(uaecptr addr, uae_u32 b) if (is_csmk3() || is_blizzardppc()) { if (flash_unlocked) { - if (is_blizzardppc() && (flash_unlocked & 2)) - addr += 262144; flash_write(flashrom, addr, b); } + } else if (is_csmk2()) { + addr &= 65535; + addr += 65536; + addr &= ~3; + addr |= csmk2_flashaddressing; + flash_write(flashrom, addr, b); + } else if (is_csmk1()) { + addr &= 65535; + addr += 65536; + flash_write(flashrom, addr, b); } } @@ -518,6 +605,8 @@ static uae_u32 REGPARAM2 blizzardea_bget(uaecptr addr) } else if (is_csmk1()) { if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) { v = cpuboard_ncr9x_scsi_get(addr); + } else if (flash_active(flashrom, addr)) { + v = flash_read(flashrom, addr); } else { v = blizzardea_bank.baseaddr[addr]; } @@ -561,6 +650,8 @@ static void REGPARAM2 blizzardea_bput(uaecptr addr, uae_u32 b) } else if (is_csmk1()) { if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) { cpuboard_ncr9x_scsi_put(addr, b); + } else { + flash_write(flashrom, addr, b); } } else if (is_csmk2()) { if (addr >= CYBERSTORM_MK2_SCSI_OFFSET) { @@ -676,8 +767,13 @@ static void cyberstormmk1_copymaprom(void) void cpuboard_rethink(void) { if (is_csmk3() || is_blizzardppc()) { - if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_SCSI_EN | P5_IRQ_SCSI))) + if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_SCSI_EN | P5_IRQ_SCSI))) { INTREQ(0x8000 | 0x0008); + } + if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_PPC_1 | P5_IRQ_PPC_2))) { + INTREQ(0x8000 | 0x0008); + } + ppc_interrupt(intlev()); } } @@ -733,12 +829,28 @@ static uae_u32 REGPARAM2 blizzardio_bget(uaecptr addr) if (bank == 0) { int reg = (addr & 0xff) / 8; v = io_reg[reg]; - if (reg == CSIII_REG_LOCK && is_blizzardppc()) - v |= 0x08; // BPPC special bit + if (reg == CSIII_REG_LOCK) { + v = 0x10; + if (is_blizzardppc()) + v |= 0x08; // BPPC identification + if (!ppc_irq_pending) + v |= 0x01; + } else if (reg == CSIII_REG_IRQ) { + v &= 0x3f; + } else if (reg == CSIII_REG_INT) { + v |= 0x40; + v &= ~0x10; + } else if (reg == CSIII_REG_SHADOW) { + v |= 0x08; + } +#if CPUBOARD_IO_LOG > 1 if (reg != CSIII_REG_IRQ) write_log(_T("CS IO BGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC); +#endif } else { +#if CPUBOARD_IO_LOG > 1 write_log(_T("CS IO BGET %08x=%02X PC=%08x\n"), addr, v & 0xff, M68K_GETPC); +#endif } } return v; @@ -774,12 +886,14 @@ static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v) #ifdef JIT special_mem |= S_WRITE; #endif - //write_log(_T("CS IO XBPUT %08x %02x PC=%08x\n"), addr, v & 0xff, M68K_GETPC); +#if CPUBOARD_IO_LOG > 2 + write_log(_T("CS IO XBPUT %08x %02x PC=%08x\n"), addr, v & 0xff, M68K_GETPC); +#endif if (is_csmk2()) { csmk2_flashaddressing = addr & 3; if (addr == 0x880000e3 && v == 0x2a) { maprom_state = 1; - write_log(_T("CSMKII MAPROM enabled\n")); + write_log(_T("CSMKII: MAPROM enabled\n")); cyberstormmk2_copymaprom(); } } else if (is_blizzard()) { @@ -787,84 +901,156 @@ static void REGPARAM2 blizzardio_bput(uaecptr addr, uae_u32 v) if (v != 0x42 || maprom_state || !currprefs.maprom) return; maprom_state = 1; - write_log(_T("Blizzard MAPROM enabled\n")); + write_log(_T("Blizzard: MAPROM enabled\n")); blizzard_copymaprom(); } } else if (is_csmk3() || is_blizzardppc()) { +#if CPUBOARD_IO_LOG > 1 write_log(_T("CS IO BPUT %08x %02x PC=%08x\n"), addr, v & 0xff, M68K_GETPC); +#endif uae_u32 bank = addr & 0x10000; if (bank == 0) { addr &= 0xff; if (is_blizzardppc()) { - if (addr == 0x92 && v == 0x42) - flash_unlocked |= 1; - if (addr == 0x93) - flash_unlocked &= ~1; - if (addr == 0x12) { + if (addr == BPPC_UNLOCK_FLASH && v == BPPC_MAGIC_UNLOCK) { + flash_unlocked = 1; + write_log(_T("BPPC: flash unlocked\n")); + } else if (addr == BPPC_LOCK_FLASH) { + flash_unlocked = 0; + write_log(_T("BPPC: flash locked\n")); + } else if (addr == BPPC_MAPROM_ON) { + write_log(_T("BPPC: maprom enabled\n")); maprom_state = 1; cyberstorm_copymaprom(); blizzardppc_maprom(); + } else if (addr == BPPC_MAPROM_OFF) { + write_log(_T("BPPC: maprom disabled\n")); + maprom_state = 0; + blizzardppc_maprom(); } } addr /= 8; uae_u8 oldval = io_reg[addr]; if (addr == CSIII_REG_LOCK) { + uae_u8 regval = io_reg[CSIII_REG_LOCK] & 0x0f; if (v == P5_MAGIC1) - io_reg[CSIII_REG_LOCK] = v; - else if (v == P5_MAGIC2 && io_reg[CSIII_REG_LOCK] == P5_MAGIC1) - io_reg[CSIII_REG_LOCK] = v; - else if (v == P5_MAGIC3 && io_reg[CSIII_REG_LOCK] == P5_MAGIC2) - io_reg[CSIII_REG_LOCK] = v; - else if (v == P5_MAGIC4 && io_reg[CSIII_REG_LOCK] == P5_MAGIC3) - io_reg[CSIII_REG_LOCK] = v; - else - io_reg[CSIII_REG_LOCK] = 0; - if (io_reg[CSIII_REG_LOCK] == P5_MAGIC3) - flash_unlocked |= 2; + regval |= P5_MAGIC1; + else if ((v & 0x70) == P5_MAGIC2 && (io_reg[CSIII_REG_LOCK] & 0x70) == P5_MAGIC1) + regval |= P5_MAGIC2; + else if ((v & 0x70) == P5_MAGIC3 && (io_reg[CSIII_REG_LOCK] & 0x70) == P5_MAGIC2) + regval |= P5_MAGIC3; + else if ((v & 0x70) == P5_MAGIC4 && (io_reg[CSIII_REG_LOCK] & 0x70) == P5_MAGIC3) + regval |= P5_MAGIC4; + if ((regval & 0x70) == P5_MAGIC3) + flash_unlocked = 1; else flash_unlocked &= ~2; + if (v & P5_GEN_INT2) { + if (v & 0x80) + regval |= P5_GEN_INT2; + else + regval &= ~P5_GEN_INT2; + write_log(_T("CSIII_REG_LOCK bit 0 = %d!\n"), (v & 0x80) ? 1 : 0); + ppc_int_interrupt = (v & 0x80) ? false : true; + if (ppc_int_interrupt) { + set_ppc_interrupt(2); + } else { + clear_ppc_interrupt(); + } + } + io_reg[CSIII_REG_LOCK] = regval; } else { uae_u32 regval; - if (addr == CSIII_REG_SHADOW && io_reg[CSIII_REG_LOCK] != P5_MAGIC3) - return; + // reg shadow is only writable if unlock sequence is active + if (addr == CSIII_REG_SHADOW) { + if (v & 2) { + // for some reason this unknown bit can be modified even when locked + io_reg[CSIII_REG_LOCK] &= ~2; + if (v & 0x80) + io_reg[CSIII_REG_LOCK] |= 2; + } + if (is_blizzardppc()) + return; + if ((io_reg[CSIII_REG_LOCK] & 0x70) != P5_MAGIC3) + return; + } if (v & 0x80) io_reg[addr] |= v & 0x7f; else io_reg[addr] &= ~v; regval = io_reg[addr]; if (addr == CSIII_REG_RESET) { + map_banks(&dummy_bank, 0xf00000 >> 16, 0x80000 >> 16, 0); + map_banks(&blizzardio_bank, 0xf60000 >> 16, 0x10000 >> 16, 0); if (regval & P5_SCSI_RESET) { - if (is_blizzardppc()) - map_banks(&ncr_bank_blizzardppc, 0xf40000 >> 16, 65536 >> 16, 0); - else - map_banks(&ncr_bank_cyberstorm, 0xf40000 >> 16, 65536 >> 16, 0); + map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x40000 >> 16, 0); + if (is_blizzardppc()) { + map_banks(&ncr_bank_blizzardppc, 0xf40000 >> 16, 0x10000 >> 16, 0); + } else { + map_banks(&ncr_bank_cyberstorm, 0xf40000 >> 16, 0x10000 >> 16, 0); + map_banks(&blizzardio_bank, 0xf50000 >> 16, 0x10000 >> 16, 0); + } } else { - map_banks(&dummy_bank, 0xf40000 >> 16, 65536 >> 16, 0); + map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x60000 >> 16, 0); } if (!(regval & P5_AMIGA_RESET)) { uae_reset(0, 0); io_reg[addr] |= P5_AMIGA_RESET; - write_log(_T("CPUBoard Amiga Reset\n")); + write_log(_T("CS: Amiga Reset\n")); } - if (!(oldval & P5_PPC_RESET) && (regval & P5_PPC_RESET)) { - static int warned; - write_log(_T("PPC reset cleared. Someone wants to run PPC programs..\n")); - if (!warned) { - gui_message(_T("WARNING: unemulated PPC CPU started!")); - warned = 1; - } + if ((oldval & P5_PPC_RESET) && !(regval & P5_PPC_RESET)) { + ppc_stop(); + } else if (!(oldval & P5_PPC_RESET) && (regval & P5_PPC_RESET)) { + ppc_reboot(); } - if (!(regval & P5_M68K_RESET)) { + if ((regval & P5_M68K_RESET) && !(oldval & P5_M68K_RESET)) { m68k_reset(); - io_reg[addr] |= P5_M68K_RESET; - write_log(_T("CPUBoard M68K Reset\n")); + write_log(_T("CS: M68K Reset\n")); + } else if (!(regval & P5_M68K_RESET) && (oldval & P5_M68K_RESET)) { + write_log(_T("CS: M68K Halted\n")); + if (!(regval & P5_PPC_RESET)) { + write_log(_T("CS: PPC is also halted. STOP.\n")); + cpu_halt(5); + } else { + // halt 68k, leave ppc message processing active. + cpu_halt(-1); + } } + } else if (addr == CSIII_REG_IPL_EMU) { +#if CPUBOARD_IRQ_LOG > 0 + regval &= ~P5_M68k_IPL_MASK; + regval |= oldval & P5_M68k_IPL_MASK; + io_reg[addr] = regval; + if ((regval & P5_DISABLE_INT) != (oldval & P5_DISABLE_INT)) + write_log(_T("CS: interrupt state: %s\n"), (regval & P5_DISABLE_INT) ? _T("disabled") : _T("enabled")); + if ((regval & P5_PPC_IPL_MASK) != (oldval & P5_PPC_IPL_MASK)) + write_log(_T("CS: PPC IPL %02x\n"), (~regval) & P5_PPC_IPL_MASK); +#endif + check_ppc_int_lvl(); + } else if (addr == CSIII_REG_INT) { +#if CPUBOARD_IRQ_LOG > 0 + if ((regval & P5_INT_MASTER) != (oldval & P5_INT_MASTER)) + write_log(_T("CS: interrupt master: %s\n"), (regval & P5_INT_MASTER) ? _T("m68k") : _T("ppc")); + if ((regval & P5_ENABLE_IPL) != (oldval & P5_ENABLE_IPL)) + write_log(_T("CS: IPL state: %s\n"), (regval & P5_ENABLE_IPL) ? _T("disabled") : _T("enabled")); +#endif + check_ppc_int_lvl(); + } else if (addr == CSIII_REG_INT_LVL) { +#if CPUBOARD_IRQ_LOG > 0 + if (regval != oldval) + write_log(_T("CS: interrupt level: %02x\n"), regval); +#endif + check_ppc_int_lvl(); } else if (addr == CSIII_REG_SHADOW) { if (is_csmk3() && ((oldval ^ regval) & 1)) { maprom_state = (regval & 1) ? 0 : 1; cyberstorm_copymaprom(); cyberstorm_maprom(); } + if ((regval & P5_FLASH) != (oldval & P5_FLASH)) { + flash_unlocked = (regval & P5_FLASH) ? 0 : 1; + write_log(_T("CS: Flash writable = %d\n"), flash_unlocked); + } // if ((oldval ^ regval) & 7) { // activate_debugger(); // } @@ -884,7 +1070,7 @@ static void REGPARAM2 blizzardio_wput(uaecptr addr, uae_u32 v) if((addr & 65535) == (BLIZZARD_BOARD_DISABLE & 65535)) { if (v != 0xcafe) return; - write_log(_T("Blizzard board disable!\n")); + write_log(_T("Blizzard: board disable!\n")); cpu_halt(4); // not much choice.. } } else if (is_csmk3() || is_blizzardppc()) { @@ -894,7 +1080,7 @@ static void REGPARAM2 blizzardio_wput(uaecptr addr, uae_u32 v) if (addr == CSMK2_BOARD_DISABLE) { if (v != 0xcafe) return; - write_log(_T("CSMK2 board disable!\n")); + write_log(_T("CSMK2: board disable!\n")); cpu_halt(4); // not much choice.. } } @@ -958,12 +1144,11 @@ void cpuboard_map(void) } else { map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x60000 >> 16, 0); map_banks(&blizzardio_bank, 0xf60000 >> 16, (2 * 65536) >> 16, 0); - map_banks(&blizzardf0_bank, 0xf70000 >> 16, 0x10000 >> 16, 0); blizzardppc_maprom(); } } if (is_csmk3()) { - map_banks(&blizzardf0_bank, 0xf00000 >> 16, 262144 >> 16, 0); + map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x40000 >> 16, 0); map_banks(&blizzardio_bank, 0xf50000 >> 16, (3 * 65536) >> 16, 0); cyberstorm_maprom(); if (!(io_reg[CSIII_REG_SHADOW] & P5_SHADOW)) @@ -1002,6 +1187,8 @@ void cpuboard_reset(bool hardreset) memset(io_reg, 0x7f, sizeof io_reg); io_reg[CSIII_REG_RESET] = 0x7f; io_reg[CSIII_REG_IRQ] = 0x7f; + io_reg[CSIII_REG_IPL_EMU] = 0x40; + io_reg[CSIII_REG_LOCK] = 0x0; } flash_unlocked = 0; @@ -1022,27 +1209,32 @@ void cpuboard_cleanup(void) flashrom_file = NULL; if (blizzard_jit) { - mapped_free(blizzardram_bank.baseaddr); + mapped_free(&blizzardram_bank); } else { xfree(blizzardram_nojit_bank.baseaddr); } if (blizzardmaprom_bank_mapped) - mapped_free(blizzardmaprom_bank.baseaddr); + mapped_free(&blizzardmaprom_bank); + if (blizzardmaprom2_bank_mapped) + mapped_free(&blizzardmaprom2_bank); blizzardram_bank.baseaddr = NULL; blizzardram_nojit_bank.baseaddr = NULL; blizzardmaprom_bank.baseaddr = NULL; blizzardmaprom2_bank.baseaddr = NULL; blizzardmaprom_bank_mapped = false; + blizzardmaprom2_bank_mapped = false; - mapped_free(blizzardf0_bank.baseaddr); + mapped_free(&blizzardf0_bank); blizzardf0_bank.baseaddr = NULL; - mapped_free(blizzardea_bank.baseaddr); + mapped_free(&blizzardea_bank); blizzardea_bank.baseaddr = NULL; cpuboard_size = cpuboard2_size = -1; + blizzardmaprom_bank.flags &= ~(ABFLAG_INDIRECT | ABFLAG_NOALLOC); + blizzardmaprom2_bank.flags &= ~(ABFLAG_INDIRECT | ABFLAG_NOALLOC); } void cpuboard_init(void) @@ -1069,8 +1261,10 @@ void cpuboard_init(void) blizzard_jit = 0 && BLIZZARD_RAM_BASE + blizzardram_bank.allocated <= max_z3fastmem && currprefs.jit_direct_compatible_memory; if (blizzard_jit) { - if (cpuboard_size) - blizzardram_bank.baseaddr = mapped_malloc(blizzardram_bank.allocated, _T("blizzard")); + if (cpuboard_size) { + blizzardram_bank.label = _T("blizzard"); + mapped_malloc(&blizzardram_bank); + } } else { if (cpuboard_size) blizzardram_bank.baseaddr = xmalloc(uae_u8, blizzardram_bank.allocated); @@ -1082,13 +1276,13 @@ void cpuboard_init(void) blizzardf0_bank.start = 0x00f00000; blizzardf0_bank.allocated = 524288; blizzardf0_bank.mask = blizzardf0_bank.allocated - 1; - blizzardf0_bank.baseaddr = mapped_malloc(blizzardf0_bank.allocated, _T("rom_f0")); + mapped_malloc(&blizzardf0_bank); if (!is_blizzardppc()) { blizzardea_bank.allocated = 2 * 65536; blizzardea_bank.mask = blizzardea_bank.allocated - 1; // Blizzard 12xx autoconfig ROM must be mapped at $ea0000-$ebffff, board requires it. - blizzardea_bank.baseaddr = mapped_malloc(blizzardea_bank.allocated, _T("rom_ea")); + mapped_malloc(&blizzardea_bank); } if (cpuboard_size > 2 * 524288) { @@ -1097,15 +1291,24 @@ void cpuboard_init(void) blizzardmaprom_bank.start = BLIZZARD_MAPROM_BASE; blizzardmaprom_bank.allocated = 524288; blizzardmaprom_bank.mask = 524288 - 1; + blizzardmaprom_bank.flags |= ABFLAG_INDIRECT | ABFLAG_NOALLOC; + mapped_malloc(&blizzardmaprom_bank); + blizzardmaprom_bank_mapped = true; } else { blizzardmaprom_bank.baseaddr = blizzardram_bank.baseaddr + cpuboard_size - 524288; blizzardmaprom_bank.start = CYBERSTORM_MAPROM_BASE; blizzardmaprom_bank.allocated = 524288; blizzardmaprom_bank.mask = 524288 - 1; + blizzardmaprom_bank.flags |= ABFLAG_INDIRECT | ABFLAG_NOALLOC; + mapped_malloc(&blizzardmaprom_bank); + blizzardmaprom_bank_mapped = true; blizzardmaprom2_bank.baseaddr = blizzardram_bank.baseaddr + cpuboard_size - 2 * 524288; blizzardmaprom2_bank.start = CYBERSTORM_MAPROM_BASE; blizzardmaprom2_bank.allocated = 524288; blizzardmaprom2_bank.mask = 524288 - 1; + blizzardmaprom2_bank.flags |= ABFLAG_INDIRECT | ABFLAG_NOALLOC; + mapped_malloc(&blizzardmaprom2_bank); + blizzardmaprom2_bank_mapped = true; } } @@ -1114,14 +1317,15 @@ void cpuboard_init(void) blizzardf0_bank.start = 0x00f00000; blizzardf0_bank.allocated = 65536; blizzardf0_bank.mask = blizzardf0_bank.allocated - 1; - blizzardf0_bank.baseaddr = mapped_malloc(blizzardf0_bank.allocated, _T("rom_f0")); - blizzardea_bank.allocated = 65536; + mapped_malloc(&blizzardf0_bank); + + blizzardea_bank.allocated = 2 * 65536; blizzardea_bank.mask = blizzardea_bank.allocated - 1; - blizzardea_bank.baseaddr = mapped_malloc(blizzardea_bank.allocated, _T("rom_ea")); + mapped_malloc(&blizzardea_bank); blizzardmaprom_bank.allocated = 524288; - blizzardmaprom_bank.baseaddr = mapped_malloc(blizzardmaprom_bank.allocated, _T("csmk1_maprom")); + mapped_malloc(&blizzardmaprom_bank); blizzardmaprom_bank.start = 0x07f80000; blizzardmaprom_bank.mask = 524288 - 1; blizzardmaprom_bank_mapped = true; @@ -1130,40 +1334,50 @@ void cpuboard_init(void) blizzardea_bank.allocated = 2 * 65536; blizzardea_bank.mask = blizzardea_bank.allocated - 1; - blizzardea_bank.baseaddr = mapped_malloc(blizzardea_bank.allocated, _T("rom_ea")); + mapped_malloc(&blizzardea_bank); blizzardf0_bank.start = 0x00f00000; blizzardf0_bank.allocated = 65536; blizzardf0_bank.mask = blizzardf0_bank.allocated - 1; - blizzardf0_bank.baseaddr = mapped_malloc(blizzardf0_bank.allocated, _T("rom_f0")); + mapped_malloc(&blizzardf0_bank); blizzardmaprom_bank.baseaddr = a3000hmem_bank.baseaddr + a3000hmem_bank.allocated - 524288; blizzardmaprom_bank.start = a3000hmem_bank.start + a3000hmem_bank.allocated - 524288; blizzardmaprom_bank.allocated = 524288; blizzardmaprom_bank.mask = 524288 - 1; + blizzardmaprom_bank.flags |= ABFLAG_INDIRECT | ABFLAG_NOALLOC; + mapped_malloc(&blizzardmaprom_bank); } else if (is_csmk3()) { blizzardram_bank.start = CS_RAM_BASE; blizzardram_bank.allocated = cpuboard_size; blizzardram_bank.mask = blizzardram_bank.allocated - 1; - if (cpuboard_size) - blizzardram_bank.baseaddr = mapped_malloc(blizzardram_bank.allocated, _T("cyberstorm")); + if (cpuboard_size) { + blizzardram_bank.label = _T("cyberstorm"); + mapped_malloc(&blizzardram_bank); + } blizzardf0_bank.start = 0x00f00000; blizzardf0_bank.allocated = 524288; blizzardf0_bank.mask = blizzardf0_bank.allocated - 1; - blizzardf0_bank.baseaddr = mapped_malloc(blizzardf0_bank.allocated, _T("rom_f0")); + mapped_malloc(&blizzardf0_bank); if (a3000hmem_bank.allocated > 2 * 524288) { + blizzardmaprom_bank.flags |= ABFLAG_INDIRECT | ABFLAG_NOALLOC; blizzardmaprom_bank.baseaddr = a3000hmem_bank.baseaddr + a3000hmem_bank.allocated - 1 * 524288; blizzardmaprom_bank.start = CYBERSTORM_MAPROM_BASE; blizzardmaprom_bank.allocated = 524288; blizzardmaprom_bank.mask = 524288 - 1; + mapped_malloc(&blizzardmaprom_bank); + blizzardmaprom_bank_mapped = true; + blizzardmaprom2_bank.flags |= ABFLAG_INDIRECT | ABFLAG_NOALLOC; blizzardmaprom2_bank.baseaddr = a3000hmem_bank.baseaddr + a3000hmem_bank.allocated - 2 * 524288; blizzardmaprom2_bank.start = CYBERSTORM_MAPROM_BASE; blizzardmaprom2_bank.allocated = 524288; blizzardmaprom2_bank.mask = 524288 - 1; + mapped_malloc(&blizzardmaprom2_bank); + blizzardmaprom2_bank_mapped = true; } } } @@ -1172,6 +1386,11 @@ void cpuboard_clear(void) { } +bool is_ppc_cpu(void) +{ + return currprefs.cpuboard_type == BOARD_CSPPC || currprefs.cpuboard_type == BOARD_BLIZZARDPPC; +} + bool cpuboard_maprom(void) { if (!currprefs.cpuboard_type || !cpuboard_size) @@ -1195,13 +1414,37 @@ bool cpuboard_08000000(struct uae_prefs *p) case BOARD_CSMK2: case BOARD_CSMK3: case BOARD_CSPPC: - case BOARD_BLIZZARDPPC: case BOARD_WARPENGINE_A4000: return true; } return false; } +static void fixserial(uae_u8 *rom, int size) +{ + uae_u32 cksum; + int i; + uae_u8 type = rom[16]; + uae_u8 bclock = rom[17]; // A=60MHz,BCD=66MHz + uae_u8 newtype = 0; + + if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) { + if (type == 'H' || type == 'I') + return; + newtype = 'H'; + } else if (currprefs.cpuboard_type == BOARD_CSPPC) { + if (type == 'E') + return; + newtype = 'E'; + } else if (currprefs.cpuboard_type == BOARD_CSMK3) { + if (type == 'F') + return; + newtype = 'F'; + } + if (!newtype) + return; +} + static struct zfile *flashfile_open(const TCHAR *name) { struct zfile *f; @@ -1319,7 +1562,7 @@ addrbank *cpuboard_autoconfig_init(void) blizzardea_bank.baseaddr[i * 2 + 0] = b; } } else if (is_csmk1()) { - f0rom_size = 65536; + f0rom_size = 131072; earom_size = 65536; for (int i = 0; i < 32768; i++) { uae_u8 b = 0xff; @@ -1327,6 +1570,13 @@ addrbank *cpuboard_autoconfig_init(void) blizzardea_bank.baseaddr[i * 2 + 0] = b; blizzardea_bank.baseaddr[i * 2 + 1] = 0xff; } + zfile_fread(blizzardea_bank.baseaddr + 65536, 65536, 1, autoconfig_rom); + if (zfile_needwrite(autoconfig_rom)) { + flashrom_file = autoconfig_rom; + autoconfig_rom = NULL; + } + flashrom = flash_new(blizzardea_bank.baseaddr, earom_size, earom_size, 0x20, flashrom_file); + memcpy(blizzardf0_bank.baseaddr, blizzardea_bank.baseaddr + 65536, 65536); } else if (is_csmk2()) { earom_size = 131072; f0rom_size = 65536; @@ -1335,19 +1585,23 @@ addrbank *cpuboard_autoconfig_init(void) flashrom_file = autoconfig_rom; autoconfig_rom = NULL; } - flashrom = flash_new(blizzardea_bank.baseaddr, earom_size, earom_size, flashrom_file); + flashrom = flash_new(blizzardea_bank.baseaddr, earom_size, earom_size, 0x20, flashrom_file); memcpy(blizzardf0_bank.baseaddr, blizzardea_bank.baseaddr + 65536, 65536); } else if (is_csmk3() || is_blizzardppc()) { f0rom_size = is_blizzardppc() ? 524288 : 131072; earom_size = 0; - memset(blizzardf0_bank.baseaddr, 0xff, f0rom_size); + // empty rom space must be cleared + memset(blizzardf0_bank.baseaddr, 0x00, f0rom_size); + if (is_blizzardppc()) // but empty config data must be 0xFF + memset(blizzardf0_bank.baseaddr + 0x50000, 0xff, 0x10000); zfile_fread(blizzardf0_bank.baseaddr, f0rom_size, 1, autoconfig_rom); autoconf = false; if (zfile_needwrite(autoconfig_rom)) { flashrom_file = autoconfig_rom; autoconfig_rom = NULL; } - flashrom = flash_new(blizzardf0_bank.baseaddr, f0rom_size, f0rom_size, flashrom_file); + fixserial(blizzardf0_bank.baseaddr, f0rom_size); + flashrom = flash_new(blizzardf0_bank.baseaddr, f0rom_size, f0rom_size, is_blizzardppc() ? 0xa4 : 0x20, flashrom_file); } else { // 1230 MK IV / 1240/60 f0rom_size = 65536; diff --git a/custom.cpp b/custom.cpp index 37131ce5..9ba79cd8 100644 --- a/custom.cpp +++ b/custom.cpp @@ -8263,7 +8263,7 @@ static void REGPARAM3 custom_bput (uaecptr, uae_u32) REGPARAM; addrbank custom_bank = { custom_lget, custom_wget, custom_bget, custom_lput, custom_wput, custom_bput, - default_xlate, default_check, NULL, _T("Custom chipset"), + default_xlate, default_check, NULL, NULL, _T("Custom chipset"), custom_lgeti, custom_wgeti, ABFLAG_IO, 0x1ff, 0xdff000 }; diff --git a/debug.cpp b/debug.cpp index 1ddf3805..92af3c3a 100644 --- a/debug.cpp +++ b/debug.cpp @@ -39,6 +39,7 @@ #include "cpummu.h" #include "cpummu030.h" #include "ar.h" +#include "ppc/ppcd.h" int debugger_active; static uaecptr skipaddr_start, skipaddr_end; @@ -4025,7 +4026,28 @@ static void m68k_modify (TCHAR **inptr) } } +static void ppc_disasm(uaecptr addr, uaecptr *nextpc, int cnt) +{ + PPCD_CB disa; + + while(cnt-- > 0) { + uae_u32 instr = get_long_debug(addr); + disa.pc = addr; + disa.instr = instr; + PPCDisasm(&disa); + TCHAR *mnemo = au(disa.mnemonic); + TCHAR *ops = au(disa.operands); + console_out_f(_T("%08X %08X %-12s%-30s\n"), addr, instr, mnemo, ops); + xfree(ops); + xfree(mnemo); + addr += 4; + } + if (nextpc) + *nextpc = addr; +} + static uaecptr nxdis, nxmem; +static bool ppcmode; static BOOL debug_line (TCHAR *input) { @@ -4119,6 +4141,13 @@ static BOOL debug_line (TCHAR *input) } else { uae_u32 daddr; int count; + if (*inptr == 'p') { + ppcmode = true; + next_char(&inptr); + } else if(*inptr == 'o') { + ppcmode = false; + next_char(&inptr); + } if (more_params (&inptr)) daddr = readhex (&inptr); else @@ -4127,7 +4156,11 @@ static BOOL debug_line (TCHAR *input) count = readhex (&inptr); else count = 10; - m68k_disasm (daddr, &nxdis, count); + if (ppcmode) { + ppc_disasm(daddr, &nxdis, count); + } else { + m68k_disasm (daddr, &nxdis, count); + } } } break; diff --git a/expansion.cpp b/expansion.cpp index 24782102..39a84ae9 100644 --- a/expansion.cpp +++ b/expansion.cpp @@ -233,30 +233,18 @@ static void addextrachip (uae_u32 sysbase) addrbank expamem_null; -static uae_u32 REGPARAM3 expamem_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 expamem_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 expamem_bget (uaecptr) REGPARAM; -static void REGPARAM3 expamem_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 expamem_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 expamem_bput (uaecptr, uae_u32) REGPARAM; - -static uae_u32 REGPARAM3 expamemz3_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 expamemz3_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 expamemz3_bget (uaecptr) REGPARAM; -static void REGPARAM3 expamemz3_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 expamemz3_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 expamemz3_bput (uaecptr, uae_u32) REGPARAM; - +DECLARE_MEMORY_FUNCTIONS(expamem); addrbank expamem_bank = { expamem_lget, expamem_wget, expamem_bget, expamem_lput, expamem_wput, expamem_bput, - default_xlate, default_check, NULL, _T("Autoconfig Z2"), + default_xlate, default_check, NULL, NULL, _T("Autoconfig Z2"), dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE }; -addrbank expamemz3_bank = { +DECLARE_MEMORY_FUNCTIONS(expamemz3); +static addrbank expamemz3_bank = { expamemz3_lget, expamemz3_wget, expamemz3_bget, expamemz3_lput, expamemz3_wput, expamemz3_bput, - default_xlate, default_check, NULL, _T("Autoconfig Z3"), + default_xlate, default_check, NULL, NULL, _T("Autoconfig Z3"), dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE }; @@ -598,25 +586,25 @@ MEMORY_FUNCTIONS_NOJIT(fastmem2_nojit); addrbank fastmem_bank = { fastmem_lget, fastmem_wget, fastmem_bget, fastmem_lput, fastmem_wput, fastmem_bput, - fastmem_xlate, fastmem_check, NULL, _T("Fast memory"), + fastmem_xlate, fastmem_check, NULL, _T("fast"), _T("Fast memory"), fastmem_lget, fastmem_wget, ABFLAG_RAM }; addrbank fastmem_nojit_bank = { fastmem_nojit_lget, fastmem_nojit_wget, fastmem_bget, fastmem_nojit_lput, fastmem_nojit_wput, fastmem_bput, - fastmem_nojit_xlate, fastmem_nojit_check, NULL, _T("Fast memory (nojit)"), + fastmem_nojit_xlate, fastmem_nojit_check, NULL, NULL, _T("Fast memory (nojit)"), fastmem_nojit_lget, fastmem_nojit_wget, ABFLAG_RAM }; addrbank fastmem2_bank = { fastmem2_lget, fastmem2_wget, fastmem2_bget, fastmem2_lput, fastmem2_wput, fastmem2_bput, - fastmem2_xlate, fastmem2_check, NULL, _T("Fast memory 2"), + fastmem2_xlate, fastmem2_check, NULL,_T("fast2"), _T("Fast memory 2"), fastmem2_lget, fastmem2_wget, ABFLAG_RAM }; addrbank fastmem2_nojit_bank = { fastmem2_nojit_lget, fastmem2_nojit_wget, fastmem2_nojit_bget, fastmem2_nojit_lput, fastmem2_nojit_wput, fastmem2_nojit_bput, - fastmem2_nojit_xlate, fastmem2_nojit_check, NULL, _T("Fast memory #2 (nojit)"), + fastmem2_nojit_xlate, fastmem2_nojit_check, NULL, NULL, _T("Fast memory #2 (nojit)"), fastmem2_nojit_lget, fastmem2_nojit_wget, ABFLAG_RAM }; @@ -634,14 +622,7 @@ static addrbank *fastbanks[] = * Catweasel ZorroII */ -static uae_u32 REGPARAM3 catweasel_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 catweasel_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 catweasel_bget (uaecptr) REGPARAM; -static void REGPARAM3 catweasel_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 catweasel_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 catweasel_bput (uaecptr, uae_u32) REGPARAM; -static int REGPARAM3 catweasel_check (uaecptr addr, uae_u32 size) REGPARAM; -static uae_u8 *REGPARAM3 catweasel_xlate (uaecptr addr) REGPARAM; +DECLARE_MEMORY_FUNCTIONS(catweasel); static uae_u32 catweasel_mask; static uae_u32 catweasel_start; @@ -714,7 +695,7 @@ static uae_u8 *REGPARAM2 catweasel_xlate (uaecptr addr) static addrbank catweasel_bank = { catweasel_lget, catweasel_wget, catweasel_bget, catweasel_lput, catweasel_wput, catweasel_bput, - catweasel_xlate, catweasel_check, NULL, _T("Catweasel"), + catweasel_xlate, catweasel_check, NULL, NULL, _T("Catweasel"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -766,15 +747,15 @@ static addrbank *expamem_init_catweasel (void) * This is very simple, the Amiga shouldn't be doing things with it. */ -static uae_u32 REGPARAM3 filesys_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 filesys_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 filesys_bget (uaecptr) REGPARAM; -static void REGPARAM3 filesys_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 filesys_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 filesys_bput (uaecptr, uae_u32) REGPARAM; +DECLARE_MEMORY_FUNCTIONS(filesys); +addrbank filesys_bank = { + filesys_lget, filesys_wget, filesys_bget, + filesys_lput, filesys_wput, filesys_bput, + default_xlate, default_check, NULL, _T("filesys"), _T("Filesystem Autoconfig Area"), + dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE | ABFLAG_INDIRECT +}; static uae_u32 filesys_start; /* Determined by the OS */ -uae_u8 *filesysory; static uae_u32 REGPARAM2 filesys_lget (uaecptr addr) { @@ -784,7 +765,7 @@ static uae_u32 REGPARAM2 filesys_lget (uaecptr addr) #endif addr -= filesys_start & 65535; addr &= 65535; - m = filesysory + addr; + m = filesys_bank.baseaddr + addr; #ifdef EXP_DEBUG write_log (_T("filesys_lget %x %x\n"), addr, do_get_mem_long ((uae_u32 *)m)); #endif @@ -799,7 +780,7 @@ static uae_u32 REGPARAM2 filesys_wget (uaecptr addr) #endif addr -= filesys_start & 65535; addr &= 65535; - m = filesysory + addr; + m = filesys_bank.baseaddr + addr; #ifdef EXP_DEBUG write_log (_T("filesys_wget %x %x\n"), addr, do_get_mem_word ((uae_u16 *)m)); #endif @@ -816,7 +797,7 @@ static uae_u32 REGPARAM2 filesys_bget (uaecptr addr) #ifdef EXP_DEBUG write_log (_T("filesys_bget %x %x\n"), addr, filesysory[addr]); #endif - return filesysory[addr]; + return filesys_bank.baseaddr[addr]; } static void REGPARAM2 filesys_lput (uaecptr addr, uae_u32 l) @@ -845,13 +826,6 @@ static void REGPARAM2 filesys_bput (uaecptr addr, uae_u32 b) #endif } -static addrbank filesys_bank = { - filesys_lget, filesys_wget, filesys_bget, - filesys_lput, filesys_wput, filesys_bput, - default_xlate, default_check, NULL, _T("Filesystem Autoconfig Area"), - dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE -}; - #endif /* FILESYS */ /* @@ -865,19 +839,19 @@ MEMORY_FUNCTIONS(z3chipmem); addrbank z3fastmem_bank = { z3fastmem_lget, z3fastmem_wget, z3fastmem_bget, z3fastmem_lput, z3fastmem_wput, z3fastmem_bput, - z3fastmem_xlate, z3fastmem_check, NULL, _T("Zorro III Fast RAM"), + z3fastmem_xlate, z3fastmem_check, NULL, _T("z3"), _T("Zorro III Fast RAM"), z3fastmem_lget, z3fastmem_wget, ABFLAG_RAM }; addrbank z3fastmem2_bank = { z3fastmem2_lget, z3fastmem2_wget, z3fastmem2_bget, z3fastmem2_lput, z3fastmem2_wput, z3fastmem2_bput, - z3fastmem2_xlate, z3fastmem2_check, NULL, _T("Zorro III Fast RAM #2"), + z3fastmem2_xlate, z3fastmem2_check, NULL, _T("z3_2"), _T("Zorro III Fast RAM #2"), z3fastmem2_lget, z3fastmem2_wget, ABFLAG_RAM }; addrbank z3chipmem_bank = { z3chipmem_lget, z3chipmem_wget, z3chipmem_bget, z3chipmem_lput, z3chipmem_wput, z3chipmem_bput, - z3chipmem_xlate, z3chipmem_check, NULL, _T("MegaChipRAM"), + z3chipmem_xlate, z3chipmem_check, NULL, _T("z3_chip"), _T("MegaChipRAM"), z3chipmem_lget, z3chipmem_wget, ABFLAG_RAM }; @@ -1030,7 +1004,7 @@ static addrbank* expamem_init_filesys (void) do_put_mem_word ((uae_u16 *)(expamem + FILESYS_DIAGAREA + FILESYS_BOOTPOINT), 0x4EF9); /* JMP */ do_put_mem_long ((uae_u32 *)(expamem + FILESYS_DIAGAREA + FILESYS_BOOTPOINT + 2), EXPANSION_bootcode); - memcpy (filesysory, expamem, 0x3000); + memcpy (filesys_bank.baseaddr, expamem, 0x3000); return NULL; } @@ -1198,13 +1172,9 @@ static size_t fast_filepos, fast2_filepos, z3_filepos, z3_filepos2, z3_fileposch void free_fastmemory (int boardnum) { if (!boardnum) { - if (fastmem_bank.baseaddr) - mapped_free (fastmem_bank.baseaddr); - fastmem_bank.baseaddr = 0; + mapped_free (&fastmem_bank); } else { - if (fastmem2_bank.baseaddr) - mapped_free (fastmem2_bank.baseaddr); - fastmem2_bank.baseaddr = 0; + mapped_free (&fastmem2_bank); } } @@ -1220,13 +1190,12 @@ static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, ad return false; while (alloc >= max * 1024 * 1024) { - uae_u8 *mem = mapped_malloc (alloc, name); - if (mem) { - bank->baseaddr = mem; + bank->mask = alloc - 1; + bank->allocated = alloc; + bank->label = name; + if (mapped_malloc (bank)) { *currpsize = alloc; *changedpsize = alloc; - bank->mask = alloc - 1; - bank->allocated = alloc; return true; } write_log (_T("Out of memory for %s, %d bytes.\n"), name, alloc); @@ -1287,7 +1256,7 @@ static void allocate_expamem (void) fastmem_nojit_bank.mask = fastmem_bank.mask; if (fastmem_bank.allocated) { - fastmem_bank.baseaddr = mapped_malloc (fastmem_bank.allocated, _T("fast")); + mapped_malloc (&fastmem_bank); fastmem_nojit_bank.baseaddr = fastmem_bank.baseaddr; if (fastmem_bank.baseaddr == 0) { write_log (_T("Out of memory for fastmem card.\n")); @@ -1308,7 +1277,7 @@ static void allocate_expamem (void) fastmem2_nojit_bank.mask = fastmem2_bank.mask; if (fastmem2_bank.allocated) { - fastmem2_bank.baseaddr = mapped_malloc (fastmem2_bank.allocated, _T("fast2")); + mapped_malloc (&fastmem2_bank); fastmem2_nojit_bank.baseaddr = fastmem2_bank.baseaddr; if (fastmem2_bank.baseaddr == 0) { write_log (_T("Out of memory for fastmem2 card.\n")); @@ -1320,21 +1289,18 @@ static void allocate_expamem (void) } if (z3fastmem_bank.allocated != currprefs.z3fastmem_size) { - if (z3fastmem_bank.baseaddr) - mapped_free (z3fastmem_bank.baseaddr); + mapped_free (&z3fastmem_bank); mapped_malloc_dynamic (&currprefs.z3fastmem_size, &changed_prefs.z3fastmem_size, &z3fastmem_bank, 1, _T("z3")); memory_hardreset (1); } if (z3fastmem2_bank.allocated != currprefs.z3fastmem2_size) { - if (z3fastmem2_bank.baseaddr) - mapped_free (z3fastmem2_bank.baseaddr); - z3fastmem2_bank.baseaddr = 0; + mapped_free (&z3fastmem2_bank); z3fastmem2_bank.allocated = currprefs.z3fastmem2_size; z3fastmem2_bank.mask = z3fastmem2_bank.allocated - 1; if (z3fastmem2_bank.allocated) { - z3fastmem2_bank.baseaddr = mapped_malloc (z3fastmem2_bank.allocated, _T("z3_2")); + mapped_malloc (&z3fastmem2_bank); if (z3fastmem2_bank.baseaddr == 0) { write_log (_T("Out of memory for 32 bit fast memory #2.\n")); z3fastmem2_bank.allocated = 0; @@ -1343,16 +1309,14 @@ static void allocate_expamem (void) memory_hardreset (1); } if (z3chipmem_bank.allocated != currprefs.z3chipmem_size) { - if (z3chipmem_bank.baseaddr) - mapped_free (z3chipmem_bank.baseaddr); + mapped_free (&z3chipmem_bank); mapped_malloc_dynamic (&currprefs.z3chipmem_size, &changed_prefs.z3chipmem_size, &z3chipmem_bank, 16, _T("z3_chip")); memory_hardreset (1); } #ifdef PICASSO96 if (gfxmem_bank.allocated != currprefs.rtgmem_size) { - if (gfxmem_bank.baseaddr) - mapped_free (gfxmem_bank.baseaddr); + mapped_free (&gfxmem_bank); mapped_malloc_dynamic (&currprefs.rtgmem_size, &changed_prefs.rtgmem_size, &gfxmem_bank, 1, currprefs.rtgmem_type ? _T("z3_gfx") : _T("z2_gfx")); memory_hardreset (1); } @@ -1759,44 +1723,35 @@ void expansion_init (void) #ifdef FILESYS filesys_start = 0; - filesysory = 0; #endif allocate_expamem (); #ifdef FILESYS - filesysory = mapped_malloc (0x10000, _T("filesys")); - if (!filesysory) { + filesys_bank.allocated = 0x10000; + if (!mapped_malloc (&filesys_bank)) { write_log (_T("virtual memory exhausted (filesysory)!\n")); exit (0); } - filesys_bank.baseaddr = filesysory; #endif } void expansion_cleanup (void) { - mapped_free (fastmem_bank.baseaddr); - fastmem_bank.baseaddr = NULL; + mapped_free (&fastmem_bank); fastmem_nojit_bank.baseaddr = NULL; - mapped_free (fastmem2_bank.baseaddr); - fastmem2_bank.baseaddr = NULL; + mapped_free (&fastmem2_bank); fastmem2_nojit_bank.baseaddr = NULL; - mapped_free (z3fastmem_bank.baseaddr); - z3fastmem_bank.baseaddr = NULL; - mapped_free (z3fastmem2_bank.baseaddr); - z3fastmem2_bank.baseaddr = NULL; - mapped_free (z3chipmem_bank.baseaddr); - z3chipmem_bank.baseaddr = NULL; + mapped_free (&z3fastmem_bank); + mapped_free (&z3fastmem2_bank); + mapped_free (&z3chipmem_bank); #ifdef PICASSO96 - mapped_free (gfxmem_bank.baseaddr); - gfxmem_bank.baseaddr = NULL; + mapped_free (&gfxmem_bank); #endif #ifdef FILESYS - mapped_free (filesysory); - filesysory = NULL; + mapped_free (&filesys_bank); #endif #ifdef CATWEASEL diff --git a/filesys.cpp b/filesys.cpp index 2f1bac95..ebc29390 100644 --- a/filesys.cpp +++ b/filesys.cpp @@ -6422,11 +6422,11 @@ error2: static void init_filesys_diagentry (void) { - do_put_mem_long ((uae_u32 *)(filesysory + 0x2100), EXPANSION_explibname); - do_put_mem_long ((uae_u32 *)(filesysory + 0x2104), filesys_configdev); - do_put_mem_long ((uae_u32 *)(filesysory + 0x2108), EXPANSION_doslibname); - do_put_mem_word ((uae_u16 *)(filesysory + 0x210e), nr_units ()); - do_put_mem_word ((uae_u16 *)(filesysory + 0x210c), 0); + do_put_mem_long ((uae_u32 *)(filesys_bank.baseaddr + 0x2100), EXPANSION_explibname); + do_put_mem_long ((uae_u32 *)(filesys_bank.baseaddr + 0x2104), filesys_configdev); + do_put_mem_long ((uae_u32 *)(filesys_bank.baseaddr + 0x2108), EXPANSION_doslibname); + do_put_mem_word ((uae_u16 *)(filesys_bank.baseaddr + 0x210e), nr_units ()); + do_put_mem_word ((uae_u16 *)(filesys_bank.baseaddr + 0x210c), 0); native2amiga_startup (); } diff --git a/flashrom.cpp b/flashrom.cpp index 052997e4..8b5c21c9 100644 --- a/flashrom.cpp +++ b/flashrom.cpp @@ -26,10 +26,12 @@ struct flashrom_data int mask; int state; int modified; + int sectorsize; + uae_u8 devicecode; struct zfile *zf; }; -void *flash_new(uae_u8 *rom, int flashsize, int allocsize, struct zfile *zf) +void *flash_new(uae_u8 *rom, int flashsize, int allocsize, uae_u8 devicecode, struct zfile *zf) { struct flashrom_data *fd = xcalloc(struct flashrom_data, 1); fd->flashsize = flashsize; @@ -37,6 +39,8 @@ void *flash_new(uae_u8 *rom, int flashsize, int allocsize, struct zfile *zf) fd->mask = fd->flashsize - 1; fd->zf = zf; fd->rom = rom; + fd->devicecode = devicecode; + fd->sectorsize = devicecode == 0x20 ? 16384 : 65536; return fd; } @@ -120,13 +124,13 @@ bool flash_write(void *fdv, uaecptr addr, uae_u8 v) #endif return true; } else if (fd->state == 6 && v == 0x30) { - int saddr = addr & ~0x3fff; + int saddr = addr & ~(fd->sectorsize - 1); if (saddr < fd->allocsize) - memset(fd->rom + saddr, 0xff, 0x4000); + memset(fd->rom + saddr, 0xff, fd->sectorsize); fd->state = 200; fd->modified = 1; #if FLASH_LOG - write_log(_T("flash sector %d erased (%08x)\n"), saddr / 0x4000, addr); + write_log(_T("flash sector %d erased (%08x)\n"), saddr / fd->sectorsize, addr); #endif return true; } @@ -150,7 +154,7 @@ uae_u32 flash_read(void *fdv, uaecptr addr) if (a == 0) v = 0x01; if (a == 1) - v = 0x20; + v = fd->devicecode; if (a == 2) v = 0x00; } else if (fd->state >= 200) { diff --git a/gayle.cpp b/gayle.cpp index d9706226..c411da8a 100644 --- a/gayle.cpp +++ b/gayle.cpp @@ -1514,17 +1514,11 @@ static void gayle_write (uaecptr addr, int val) gayle_write2 (addr, val); } -static uae_u32 REGPARAM3 gayle_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 gayle_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 gayle_bget (uaecptr) REGPARAM; -static void REGPARAM3 gayle_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 gayle_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 gayle_bput (uaecptr, uae_u32) REGPARAM; - +DECLARE_MEMORY_FUNCTIONS(gayle); addrbank gayle_bank = { gayle_lget, gayle_wget, gayle_bget, gayle_lput, gayle_wput, gayle_bput, - default_xlate, default_check, NULL, _T("Gayle (low)"), + default_xlate, default_check, NULL, NULL, _T("Gayle (low)"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -1715,17 +1709,11 @@ static uae_u32 gayle2_read (uaecptr addr) return v; } -static uae_u32 REGPARAM3 gayle2_lget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 gayle2_wget (uaecptr) REGPARAM; -static uae_u32 REGPARAM3 gayle2_bget (uaecptr) REGPARAM; -static void REGPARAM3 gayle2_lput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 gayle2_wput (uaecptr, uae_u32) REGPARAM; -static void REGPARAM3 gayle2_bput (uaecptr, uae_u32) REGPARAM; - +DECLARE_MEMORY_FUNCTIONS(gayle2); addrbank gayle2_bank = { gayle2_lget, gayle2_wget, gayle2_bget, gayle2_lput, gayle2_wput, gayle2_bput, - default_xlate, default_check, NULL, _T("Gayle (high)"), + default_xlate, default_check, NULL, NULL, _T("Gayle (high)"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -1931,7 +1919,7 @@ static void REGPARAM2 mbres_bput (uaecptr addr, uae_u32 value) addrbank mbres_bank = { mbres_lget, mbres_wget, mbres_bget, mbres_lput, mbres_wput, mbres_bput, - default_xlate, default_check, NULL, _T("Motherboard Resources"), + default_xlate, default_check, NULL, NULL, _T("Motherboard Resources"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -2509,7 +2497,7 @@ static uae_u8 *REGPARAM2 gayle_common_xlate (uaecptr addr) static addrbank gayle_common_bank = { gayle_common_lget, gayle_common_wget, gayle_common_bget, gayle_common_lput, gayle_common_wput, gayle_common_bput, - gayle_common_xlate, gayle_common_check, NULL, _T("Gayle PCMCIA Common"), + gayle_common_xlate, gayle_common_check, NULL, NULL, _T("Gayle PCMCIA Common"), gayle_common_lget, gayle_common_wget, ABFLAG_RAM | ABFLAG_SAFE }; @@ -2521,10 +2509,10 @@ static void REGPARAM3 gayle_attr_lput (uaecptr, uae_u32) REGPARAM; static void REGPARAM3 gayle_attr_wput (uaecptr, uae_u32) REGPARAM; static void REGPARAM3 gayle_attr_bput (uaecptr, uae_u32) REGPARAM; -addrbank gayle_attr_bank = { +static addrbank gayle_attr_bank = { gayle_attr_lget, gayle_attr_wget, gayle_attr_bget, gayle_attr_lput, gayle_attr_wput, gayle_attr_bput, - default_xlate, default_check, NULL, _T("Gayle PCMCIA Attribute/Misc"), + default_xlate, default_check, NULL, NULL, _T("Gayle PCMCIA Attribute/Misc"), dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE }; diff --git a/gencpu.cpp b/gencpu.cpp index 39e79caf..0452f1d5 100644 --- a/gencpu.cpp +++ b/gencpu.cpp @@ -2549,7 +2549,24 @@ static void resetvars (void) if (using_indirect) { // tracer getpc = "m68k_getpci ()"; - if (!using_ce020 && !using_prefetch_020) { + if (!using_ce020 && !using_prefetch_020 && !using_ce) { + // generic + indirect + disp020 = "x_get_disp_ea_020"; + prefetch_long = "get_iilong_jit"; + prefetch_word = "get_iiword_jit"; + nextw = "next_iiword_jit"; + nextl = "next_iilong_jit"; + srcli = "get_iilong_jit"; + srcwi = "get_iiword_jit"; + srcbi = "get_iibyte_jit"; + srcl = "x_get_long"; + dstl = "x_put_long"; + srcw = "x_get_word"; + dstw = "x_put_word"; + srcb = "x_get_byte"; + dstb = "x_put_byte"; + getpc = "m68k_getpc()"; // special jit support + } else if (!using_ce020 && !using_prefetch_020) { prefetch_word = "get_word_ce000_prefetch"; srcli = "x_get_ilong"; srcwi = "x_get_iword"; @@ -2769,7 +2786,7 @@ static void resetvars (void) dstb = "put_byte_prefetch"; getpc = "m68k_getpci ()"; } else { - // generic + // generic + direct prefetch_long = "get_dilong"; prefetch_word = "get_diword"; nextw = "next_diword"; @@ -3671,7 +3688,9 @@ static void gen_opcode (unsigned int opcode) case i_RTS: addop_ce020 (curi, 0); printf ("\tuaecptr pc = %s;\n", getpc); - if (using_ce020 == 1) { + if (using_indirect && !using_ce020 && !using_prefetch_020 && !using_ce) { + printf("\tm68k_do_rtsi_jit ();\n"); + } else if (using_ce020 == 1) { add_head_cycs (1); printf ("\tm68k_do_rts_ce020 ();\n"); } else if (using_ce020 == 2) { @@ -3806,7 +3825,9 @@ static void gen_opcode (unsigned int opcode) need_endlabel = 1; } addcycles000 (2); - if (using_ce020 == 1) { + if (using_indirect && !using_ce020 && !using_prefetch_020 && !using_ce) { + printf("\tm68k_do_bsri_jit (%s + %d, s);\n", getpc, m68k_pc_offset); + } else if (using_ce020 == 1) { printf ("\tm68k_do_bsr_ce020 (%s + %d, s);\n", getpc, m68k_pc_offset); } else if (using_ce020 == 2) { printf ("\tm68k_do_bsr_ce030 (%s + %d, s);\n", getpc, m68k_pc_offset); @@ -4770,7 +4791,7 @@ static void gen_opcode (unsigned int opcode) if (using_mmu == 68060 && (curi->mnemo == i_BFCHG || curi->mnemo == i_BFCLR || curi->mnemo == i_BFSET || curi->mnemo == i_BFINS)) { getb = "mmu060_get_rmw_bitfield"; putb = "mmu060_put_rmw_bitfield"; - } else if (using_mmu || using_ce020) { + } else if (using_mmu || using_ce020 || using_indirect) { getb = "x_get_bitfield"; putb = "x_put_bitfield"; } else { @@ -5272,9 +5293,9 @@ static void generate_one_opcode (int rp, const char *extra) char *name = ua (lookuptab[idx].name); if (generate_stbl) fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d%s), %d }, /* %s */\n", - (using_ce || using_ce020) ? "(cpuop_func*)" : "", - opcode, opcode_last_postfix[rp], - extra, opcode, name); + (using_ce || using_ce020) ? "(cpuop_func*)" : "", + opcode, opcode_last_postfix[rp], + extra, opcode, name); xfree (name); return; } @@ -5439,7 +5460,7 @@ static void generate_cpu (int id, int mode) } postfix = id; - if (id == 0 || id == 11 || id == 13 || id == 20 || id == 21 || id == 22 || id == 23 || id == 31 || id == 32 || id == 33) { + if (id == 0 || id == 11 || id == 13 || id == 20 || id == 21 || id == 22 || id == 23 || id == 31 || id == 32 || id == 33 || id == 40) { if (generate_stbl) fprintf (stblfile, "#ifdef CPUEMU_%d%s\n", postfix, extraup); postfix2 = postfix; @@ -5535,20 +5556,27 @@ static void generate_cpu (int id, int mode) read_counts (); for (rp = 0; rp < nr_cpuop_funcs; rp++) opcode_next_clev[rp] = cpu_level; - } else { - cpu_level = 5 - id; // "generic" + } else if (id < 6) { + cpu_level = 5 - (id - 0); // "generic" + direct + } else if (id >= 40 && id < 46) { + cpu_level = 5 - (id - 40); // "generic" + indirect + if (id == 40) { + read_counts(); + for (rp = 0; rp < nr_cpuop_funcs; rp++) + opcode_next_clev[rp] = cpu_level; + } } - using_indirect = using_ce || using_ce020 || using_prefetch_020; + using_indirect = using_ce || using_ce020 || using_prefetch_020 || id >= 40; if (generate_stbl) { - if ((id > 0 && id < 10) || (id >= 20)) + if ((id > 0 && id < 6) || (id >= 20 && id < 40) || (id > 40 && id < 46)) fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n"); fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d%s)[] = {\n", postfix, extra); } endlabelno = id * 10000; generate_func (extra); if (generate_stbl) { - if ((id > 0 && id < 10) || (id >= 20)) + if ((id > 0 && id < 6) || (id >= 20 && id < 40) || (id > 40 && id < 46)) fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n"); if (postfix2 >= 0) fprintf (stblfile, "#endif /* CPUEMU_%d%s */\n", postfix2, extraup); @@ -5583,8 +5611,8 @@ int main(int argc, char *argv[]) using_exception_3 = 1; using_ce = 0; - for (i = 0; i <= 33; i++) { - if ((i >= 6 && i < 11) || (i > 14 && i < 20) || (i > 24 && i < 31)) + for (i = 0; i <= 45; i++) { + if ((i >= 6 && i < 11) || (i > 14 && i < 20) || (i > 24 && i < 31) || (i > 33 && i < 40)) continue; generate_stbl = 1; generate_cpu (i, 0); diff --git a/gfxboard.cpp b/gfxboard.cpp index 54b52076..9286ab74 100644 --- a/gfxboard.cpp +++ b/gfxboard.cpp @@ -214,7 +214,10 @@ static void init_board (void) vram_offset[0] = vram_offset[1] = 0; vram_enabled = true; vram_offset_enabled = false; - vram = mapped_malloc (vramsize, board->z3 ? _T("z3_gfx") : _T("z2_gfx")); + gfxmem_bank.label = board->z3 ? _T("z3_gfx") : _T("z2_gfx"); + gfxmem_bank.allocated = vramsize; + mapped_malloc (&gfxmem_bank); + vram = gfxmem_bank.baseaddr; vramrealstart = vram; vram += vram_start_offset; gfxmem_bank.baseaddr = vram; @@ -1512,8 +1515,8 @@ void gfxboard_reset (void) gfxmem_bank.mask = currprefs.rtgmem_size - 1; } if (vram) { - mapped_free (vramrealstart); - gfxmem_bank.baseaddr = NULL; + gfxmem_bank.baseaddr = vramrealstart; + mapped_free (&gfxmem_bank); } vram = NULL; vramrealstart = NULL; @@ -1538,38 +1541,38 @@ void gfxboard_reset (void) static addrbank gfxboard_bank_memory = { gfxboard_lget_mem, gfxboard_wget_mem, gfxboard_bget_mem, gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem, - gfxboard_xlate, gfxboard_check, NULL, NULL, + gfxboard_xlate, gfxboard_check, NULL, NULL, NULL, gfxboard_lget_mem, gfxboard_wget_mem, ABFLAG_RAM }; static addrbank gfxboard_bank_memory_nojit = { gfxboard_lget_mem_nojit, gfxboard_wget_mem_nojit, gfxboard_bget_mem_nojit, gfxboard_lput_mem_nojit, gfxboard_wput_mem_nojit, gfxboard_bput_mem_nojit, - gfxboard_xlate, gfxboard_check, NULL, NULL, + gfxboard_xlate, gfxboard_check, NULL, NULL, NULL, gfxboard_lget_mem_nojit, gfxboard_wget_mem_nojit, ABFLAG_RAM }; static addrbank gfxboard_bank_wbsmemory = { gfxboard_lget_wbsmem, gfxboard_wget_wbsmem, gfxboard_bget_bsmem, gfxboard_lput_wbsmem, gfxboard_wput_wbsmem, gfxboard_bput_bsmem, - gfxboard_xlate, gfxboard_check, NULL, NULL, + gfxboard_xlate, gfxboard_check, NULL, NULL, NULL, gfxboard_lget_wbsmem, gfxboard_wget_wbsmem, ABFLAG_RAM }; static addrbank gfxboard_bank_lbsmemory = { gfxboard_lget_lbsmem, gfxboard_wget_lbsmem, gfxboard_bget_bsmem, gfxboard_lput_lbsmem, gfxboard_wput_lbsmem, gfxboard_bput_bsmem, - gfxboard_xlate, gfxboard_check, NULL, NULL, + gfxboard_xlate, gfxboard_check, NULL, NULL, NULL, gfxboard_lget_lbsmem, gfxboard_wget_lbsmem, ABFLAG_RAM }; static addrbank gfxboard_bank_nbsmemory = { gfxboard_lget_nbsmem, gfxboard_wget_nbsmem, gfxboard_bget_bsmem, gfxboard_lput_nbsmem, gfxboard_wput_nbsmem, gfxboard_bput_bsmem, - gfxboard_xlate, gfxboard_check, NULL, _T("Picasso IV banked VRAM"), + gfxboard_xlate, gfxboard_check, NULL, NULL, _T("Picasso IV banked VRAM"), gfxboard_lget_nbsmem, gfxboard_wget_nbsmem, ABFLAG_RAM }; static addrbank gfxboard_bank_registers = { gfxboard_lget_regs, gfxboard_wget_regs, gfxboard_bget_regs, gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs, - default_xlate, default_check, NULL, NULL, + default_xlate, default_check, NULL, NULL, NULL, dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE }; @@ -1918,7 +1921,7 @@ static void REGPARAM2 gfxboards_bput_regs (uaecptr addr, uae_u32 v) addrbank gfxboard_bank_special = { gfxboards_lget_regs, gfxboards_wget_regs, gfxboards_bget_regs, gfxboards_lput_regs, gfxboards_wput_regs, gfxboards_bput_regs, - default_xlate, default_check, NULL, _T("Picasso IV MISC"), + default_xlate, default_check, NULL, NULL, _T("Picasso IV MISC"), dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE }; bool gfxboard_is_z3 (int type) @@ -2127,20 +2130,18 @@ addrbank *gfxboard_init_memory (void) addrbank *gfxboard_init_memory_p4_z2 (void) { - if (board->z3) { - expamem_next (); - return NULL; - } + if (board->z3) + return &expamem_null; + copyp4autoconfig (64); return &gfxboard_bank_memory; } addrbank *gfxboard_init_registers (void) { - if (!board->model_registers) { - expamem_next (); - return NULL; - } + if (!board->model_registers) + return &expamem_null; + memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE); ew (0x00, 0xc0 | 0x01); // 64k Z2 ew (0x04, board->model_registers); diff --git a/include/cpu_prefetch.h b/include/cpu_prefetch.h index 57e03a90..4fd2995b 100644 --- a/include/cpu_prefetch.h +++ b/include/cpu_prefetch.h @@ -37,8 +37,10 @@ STATIC_INLINE uae_u32 get_long_020_prefetch (int o) // only for CPU internal cycles STATIC_INLINE void do_cycles_ce020_internal(int clocks) { - if (currprefs.m68k_speed < 0) + if (currprefs.m68k_speed < 0) { + regs.ce020extracycles += clocks; return; + } int cycs = clocks * cpucycleunit; if (regs.ce020memcycles > 0) { if (regs.ce020memcycles >= cycs) { diff --git a/include/cpuboard.h b/include/cpuboard.h index 53689a8b..77ec3541 100644 --- a/include/cpuboard.h +++ b/include/cpuboard.h @@ -9,6 +9,9 @@ extern void cpuboard_clear(void); extern void cpuboard_vsync(void); extern void cpuboard_rethink(void); extern bool cpuboard_08000000(struct uae_prefs *p); +extern bool is_ppc_cpu(void); + +extern bool ppc_interrupt(int new_m68k_ipl); extern void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32); extern uae_u32 cyberstorm_scsi_ram_get(uaecptr addr); diff --git a/include/flashrom.h b/include/flashrom.h index 64609f2e..bf745c8b 100644 --- a/include/flashrom.h +++ b/include/flashrom.h @@ -1,5 +1,5 @@ -void *flash_new(uae_u8 *rom, int flashsize, int allocsize, struct zfile *zf); +void *flash_new(uae_u8 *rom, int flashsize, int allocsize, uae_u8 devicecode, struct zfile *zf); void flash_free(void *fdv); bool flash_write(void *fdv, uaecptr addr, uae_u8 v); diff --git a/include/memory.h b/include/memory.h index 08d5fdc5..c833f1d1 100644 --- a/include/memory.h +++ b/include/memory.h @@ -69,7 +69,7 @@ extern uaecptr rtarea_base; extern uae_u8* baseaddr[]; -enum { ABFLAG_UNK = 0, ABFLAG_RAM = 1, ABFLAG_ROM = 2, ABFLAG_ROMIN = 4, ABFLAG_IO = 8, ABFLAG_NONE = 16, ABFLAG_SAFE = 32 }; +enum { ABFLAG_UNK = 0, ABFLAG_RAM = 1, ABFLAG_ROM = 2, ABFLAG_ROMIN = 4, ABFLAG_IO = 8, ABFLAG_NONE = 16, ABFLAG_SAFE = 32, ABFLAG_INDIRECT = 64, ABFLAG_NOALLOC = 128 }; typedef struct { /* These ones should be self-explanatory... */ mem_get_func lget, wget, bget; @@ -89,6 +89,7 @@ typedef struct { ourselves. This holds the memory address where the start of memory is for this particular bank. */ uae_u8 *baseaddr; + const TCHAR *label; const TCHAR *name; /* for instruction opcode/operand fetches */ mem_get_func lgeti, wgeti; @@ -292,9 +293,6 @@ MEMORY_BPUT(name, 1); \ MEMORY_CHECK(name); \ MEMORY_XLATE(name); -extern uae_u8 *filesysory; -extern uae_u8 *rtarea; - extern addrbank chipmem_bank; extern addrbank chipmem_agnus_bank; extern addrbank chipmem_bank_ce2; @@ -303,6 +301,7 @@ extern addrbank custom_bank; extern addrbank clock_bank; extern addrbank cia_bank; extern addrbank rtarea_bank; +extern addrbank filesys_bank; extern addrbank expamem_bank; extern addrbank expamem_null; extern addrbank fastmem_bank; @@ -539,8 +538,8 @@ extern shmpiece *shm_start; #endif -extern uae_u8 *mapped_malloc (size_t, const TCHAR*); -extern void mapped_free (uae_u8 *); +extern bool mapped_malloc (addrbank*); +extern void mapped_free (addrbank*); extern void clearexec (void); extern void mapkick (void); extern void a3000_fakekick (int); diff --git a/include/newcpu.h b/include/newcpu.h index 98c88c25..89c13b1a 100644 --- a/include/newcpu.h +++ b/include/newcpu.h @@ -203,6 +203,7 @@ struct regstruct uae_u32 cacheholdingdata020; uae_u32 cacheholdingaddr020; int ce020memcycles; + int ce020extracycles; bool ce020memcycle_data; int ce020_tail; frame_time_t ce020_tail_cycles; @@ -250,7 +251,7 @@ STATIC_INLINE uae_u32 munge24 (uae_u32 x) extern int mmu_enabled, mmu_triggered; extern int cpu_cycles; extern int cpucycleunit; -extern bool m68k_pc_indirect; +extern int m68k_pc_indirect; STATIC_INLINE void set_special (uae_u32 x) { regs.spcflags |= x; @@ -265,6 +266,29 @@ STATIC_INLINE void unset_special (uae_u32 x) #define m68k_dreg(r,num) ((r).regs[(num)]) #define m68k_areg(r,num) (((r).regs + 8)[(num)]) +extern uae_u32(*x_prefetch)(int); +extern uae_u32(*x_get_byte)(uaecptr addr); +extern uae_u32(*x_get_word)(uaecptr addr); +extern uae_u32(*x_get_long)(uaecptr addr); +extern void(*x_put_byte)(uaecptr addr, uae_u32 v); +extern void(*x_put_word)(uaecptr addr, uae_u32 v); +extern void(*x_put_long)(uaecptr addr, uae_u32 v); +extern uae_u32(*x_next_iword)(void); +extern uae_u32(*x_next_ilong)(void); +extern uae_u32(*x_get_ilong)(int); +extern uae_u32(*x_get_iword)(int); +extern uae_u32(*x_get_ibyte)(int); + +extern uae_u32(*x_cp_get_byte)(uaecptr addr); +extern uae_u32(*x_cp_get_word)(uaecptr addr); +extern uae_u32(*x_cp_get_long)(uaecptr addr); +extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v); +extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v); +extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v); +extern uae_u32(*x_cp_next_iword)(void); +extern uae_u32(*x_cp_next_ilong)(void); + +extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM; /* direct (regs.pc_p) access */ @@ -342,7 +366,7 @@ STATIC_INLINE void m68k_incpci(int o) STATIC_INLINE uae_u32 get_iibyte(int o) { - return get_wordi(m68k_getpci() + (o) + 1); + return get_wordi(m68k_getpci() + (o)) & 0xff; } STATIC_INLINE uae_u32 get_iiword(int o) { @@ -397,11 +421,50 @@ STATIC_INLINE void m68k_do_rtsi(void) m68k_areg(regs, 7) += 4; } +/* indirect jit friendly versions */ + +STATIC_INLINE uae_u32 get_iibyte_jit(int o) +{ + return get_wordi(m68k_getpc() + (o)) & 0xff; +} +STATIC_INLINE uae_u32 get_iiword_jit(int o) +{ + return get_wordi(m68k_getpc() + (o)); +} +STATIC_INLINE uae_u32 get_iilong_jit(int o) +{ + return get_longi(m68k_getpc() + (o)); +} +STATIC_INLINE uae_u32 next_iiword_jit(void) +{ + uae_u32 r = get_wordi(m68k_getpc()); + m68k_incpc(2); + return r; +} +STATIC_INLINE uae_u32 next_iilong_jit(void) +{ + uae_u32 r = get_longi(m68k_getpc()); + m68k_incpc(4); + return r; +} +STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset) +{ + m68k_areg(regs, 7) -= 4; + x_put_long(m68k_areg(regs, 7), oldpc); + m68k_incpc(offset); +} +STATIC_INLINE void m68k_do_rtsi_jit(void) +{ + uae_u32 newpc = x_get_long(m68k_areg(regs, 7)); + m68k_setpc(newpc); + m68k_areg(regs, 7) += 4; +} + /* common access */ STATIC_INLINE void m68k_incpc_normal(int o) { - if (m68k_pc_indirect) + if (m68k_pc_indirect > 0) m68k_incpci(o); else m68k_incpc(o); @@ -409,39 +472,14 @@ STATIC_INLINE void m68k_incpc_normal(int o) STATIC_INLINE void m68k_setpc_normal(uaecptr pc) { - if (m68k_pc_indirect) { + if (m68k_pc_indirect > 0) { regs.pc_p = regs.pc_oldp = 0; m68k_setpci(pc); - } - else { + } else { m68k_setpc(pc); } } -extern uae_u32 (*x_prefetch)(int); -extern uae_u32 (*x_get_byte)(uaecptr addr); -extern uae_u32 (*x_get_word)(uaecptr addr); -extern uae_u32 (*x_get_long)(uaecptr addr); -extern void (*x_put_byte)(uaecptr addr, uae_u32 v); -extern void (*x_put_word)(uaecptr addr, uae_u32 v); -extern void (*x_put_long)(uaecptr addr, uae_u32 v); -extern uae_u32 (*x_next_iword)(void); -extern uae_u32 (*x_next_ilong)(void); -extern uae_u32 (*x_get_ilong)(int); -extern uae_u32 (*x_get_iword)(int); -extern uae_u32 (*x_get_ibyte)(int); - -extern uae_u32 (*x_cp_get_byte)(uaecptr addr); -extern uae_u32 (*x_cp_get_word)(uaecptr addr); -extern uae_u32 (*x_cp_get_long)(uaecptr addr); -extern void (*x_cp_put_byte)(uaecptr addr, uae_u32 v); -extern void (*x_cp_put_word)(uaecptr addr, uae_u32 v); -extern void (*x_cp_put_long)(uaecptr addr, uae_u32 v); -extern uae_u32 (*x_cp_next_iword)(void); -extern uae_u32 (*x_cp_next_ilong)(void); - -extern uae_u32 (REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM; - extern void write_dcache030(uaecptr, uae_u32, int); extern uae_u32 read_dcache030(uaecptr, int); extern uae_u32 get_word_icache030(uaecptr addr); @@ -548,37 +586,45 @@ extern void fill_prefetch_030 (void); /* 68060 */ extern const struct cputbl op_smalltbl_0_ff[]; +extern const struct cputbl op_smalltbl_40_ff[]; extern const struct cputbl op_smalltbl_23_ff[]; // CE extern const struct cputbl op_smalltbl_33_ff[]; // MMU /* 68040 */ extern const struct cputbl op_smalltbl_1_ff[]; +extern const struct cputbl op_smalltbl_41_ff[]; extern const struct cputbl op_smalltbl_24_ff[]; // CE extern const struct cputbl op_smalltbl_31_ff[]; // MMU /* 68030 */ extern const struct cputbl op_smalltbl_2_ff[]; +extern const struct cputbl op_smalltbl_42_ff[]; extern const struct cputbl op_smalltbl_22_ff[]; // CE extern const struct cputbl op_smalltbl_32_ff[]; // MMU /* 68020 */ extern const struct cputbl op_smalltbl_3_ff[]; +extern const struct cputbl op_smalltbl_43_ff[]; extern const struct cputbl op_smalltbl_20_ff[]; // prefetch extern const struct cputbl op_smalltbl_21_ff[]; // CE /* 68010 */ extern const struct cputbl op_smalltbl_4_ff[]; +extern const struct cputbl op_smalltbl_44_ff[]; extern const struct cputbl op_smalltbl_11_ff[]; // prefetch extern const struct cputbl op_smalltbl_13_ff[]; // CE /* 68000 */ extern const struct cputbl op_smalltbl_5_ff[]; +extern const struct cputbl op_smalltbl_45_ff[]; extern const struct cputbl op_smalltbl_12_ff[]; // prefetch extern const struct cputbl op_smalltbl_14_ff[]; // CE extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl"); #ifdef JIT -extern void flush_icache (uaecptr, int); -extern void compemu_reset (void); +extern void flush_icache(uaecptr, int); +extern void flush_icache_hard(uaecptr, int); +extern void compemu_reset(void); extern bool check_prefs_changed_comp (void); #else #define flush_icache(uaecptr, int) do {} while (0) +#define flush_icache_hard(uaecptr, int) do {} while (0) #endif extern void flush_dcache (uaecptr, int); extern void flush_mmu (uaecptr, int); diff --git a/include/options.h b/include/options.h index f95b8017..a7c75586 100644 --- a/include/options.h +++ b/include/options.h @@ -11,8 +11,8 @@ #define OPTIONS_H #define UAEMAJOR 2 -#define UAEMINOR 8 -#define UAESUBREV 2 +#define UAEMINOR 9 +#define UAESUBREV 0 typedef enum { KBD_LANG_US, KBD_LANG_DK, KBD_LANG_DE, KBD_LANG_SE, KBD_LANG_FR, KBD_LANG_IT, KBD_LANG_ES } KbdLang; diff --git a/include/ppc.h b/include/ppc.h new file mode 100644 index 00000000..d9ed137b --- /dev/null +++ b/include/ppc.h @@ -0,0 +1,15 @@ + +void ppc_reboot(void); +void ppc_stop(void); +void uae_ppc_poll_queue(void); +void ppc_interrupt(bool active); + +void ppc_hsync_handler(void); +void ppc_wakeup(void); + +#define PPC_STATE_STOP 0 +#define PPC_STATE_ACTIVE 1 +#define PPC_STATE_SLEEP 2 +#define PPC_STATE_CRASH 3 + +extern volatile int ppc_state; diff --git a/jit/compemu.h b/jit/compemu.h index bedd3778..8636de22 100644 --- a/jit/compemu.h +++ b/jit/compemu.h @@ -96,6 +96,7 @@ extern int get_cache_state(void); extern uae_u32 get_jitted_size(void); #ifdef JIT extern void flush_icache(uaecptr ptr, int n); +extern void flush_icache_hard(uaecptr ptr, int n); #endif extern void alloc_cache(void); extern void compile_block(cpu_history* pc_hist, int blocklen, int totcyles); diff --git a/jit/compemu_support.cpp b/jit/compemu_support.cpp index be5781f7..311a391d 100644 --- a/jit/compemu_support.cpp +++ b/jit/compemu_support.cpp @@ -102,10 +102,6 @@ extern const struct cputbl op_smalltbl_4_nf[]; extern const struct cputbl op_smalltbl_5_nf[]; #endif -static void flush_icache_hard(uae_u32 ptr, int n); - - - static bigstate live; static smallstate empty_ss; static smallstate default_ss; @@ -5797,7 +5793,7 @@ void build_comp(void) } -static void flush_icache_hard(uae_u32 ptr, int n) +void flush_icache_hard(uaecptr ptr, int n) { blockinfo* bi; diff --git a/main.cpp b/main.cpp index 6ccf77e3..fc192691 100644 --- a/main.cpp +++ b/main.cpp @@ -61,6 +61,7 @@ #include "uaenative.h" #include "tabletlibrary.h" #include "cpuboard.h" +#include "ppc.h" #ifdef RETROPLATFORM #include "rp.h" #endif @@ -904,6 +905,9 @@ void reset_all_systems (void) native2amiga_reset (); dongle_reset (); sampler_init (); +#ifdef WITH_PPC + ppc_stop(); +#endif } /* Okay, this stuff looks strange, but it is here to encourage people who diff --git a/memory.cpp b/memory.cpp index 35ab25e6..67999498 100644 --- a/memory.cpp +++ b/memory.cpp @@ -1018,28 +1018,28 @@ uae_u8 *REGPARAM2 default_xlate (uaecptr a) addrbank dummy_bank = { dummy_lget, dummy_wget, dummy_bget, dummy_lput, dummy_wput, dummy_bput, - default_xlate, dummy_check, NULL, NULL, + default_xlate, dummy_check, NULL, NULL, NULL, dummy_lgeti, dummy_wgeti, ABFLAG_NONE }; addrbank ones_bank = { ones_get, ones_get, ones_get, none_put, none_put, none_put, - default_xlate, dummy_check, NULL, _T("Ones"), + default_xlate, dummy_check, NULL, NULL, _T("Ones"), dummy_lgeti, dummy_wgeti, ABFLAG_NONE }; addrbank chipmem_bank = { chipmem_lget, chipmem_wget, chipmem_bget, chipmem_lput, chipmem_wput, chipmem_bput, - chipmem_xlate, chipmem_check, NULL, _T("Chip memory"), + chipmem_xlate, chipmem_check, NULL, _T("chip"), _T("Chip memory"), chipmem_lget, chipmem_wget, ABFLAG_RAM }; addrbank chipmem_dummy_bank = { chipmem_dummy_lget, chipmem_dummy_wget, chipmem_dummy_bget, chipmem_dummy_lput, chipmem_dummy_wput, chipmem_dummy_bput, - default_xlate, dummy_check, NULL, _T("Dummy Chip memory"), + default_xlate, dummy_check, NULL, NULL, _T("Dummy Chip memory"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -1048,7 +1048,7 @@ addrbank chipmem_dummy_bank = { addrbank chipmem_bank_ce2 = { chipmem_lget_ce2, chipmem_wget_ce2, chipmem_bget_ce2, chipmem_lput_ce2, chipmem_wput_ce2, chipmem_bput_ce2, - chipmem_xlate, chipmem_check, NULL, _T("Chip memory (68020 'ce')"), + chipmem_xlate, chipmem_check, NULL, NULL, _T("Chip memory (68020 'ce')"), chipmem_lget_ce2, chipmem_wget_ce2, ABFLAG_RAM }; #endif @@ -1056,55 +1056,55 @@ addrbank chipmem_bank_ce2 = { addrbank bogomem_bank = { bogomem_lget, bogomem_wget, bogomem_bget, bogomem_lput, bogomem_wput, bogomem_bput, - bogomem_xlate, bogomem_check, NULL, _T("Slow memory"), + bogomem_xlate, bogomem_check, NULL, _T("bogo"), _T("Slow memory"), bogomem_lget, bogomem_wget, ABFLAG_RAM }; addrbank cardmem_bank = { cardmem_lget, cardmem_wget, cardmem_bget, cardmem_lput, cardmem_wput, cardmem_bput, - cardmem_xlate, cardmem_check, NULL, _T("CDTV memory card"), + cardmem_xlate, cardmem_check, NULL, _T("rom_e0"), _T("CDTV memory card"), cardmem_lget, cardmem_wget, ABFLAG_RAM }; addrbank a3000lmem_bank = { a3000lmem_lget, a3000lmem_wget, a3000lmem_bget, a3000lmem_lput, a3000lmem_wput, a3000lmem_bput, - a3000lmem_xlate, a3000lmem_check, NULL, _T("RAMSEY memory (low)"), + a3000lmem_xlate, a3000lmem_check, NULL, _T("ramsey_low"), _T("RAMSEY memory (low)"), a3000lmem_lget, a3000lmem_wget, ABFLAG_RAM }; addrbank a3000hmem_bank = { a3000hmem_lget, a3000hmem_wget, a3000hmem_bget, a3000hmem_lput, a3000hmem_wput, a3000hmem_bput, - a3000hmem_xlate, a3000hmem_check, NULL, _T("RAMSEY memory (high)"), + a3000hmem_xlate, a3000hmem_check, NULL, _T("ramsey_high"), _T("RAMSEY memory (high)"), a3000hmem_lget, a3000hmem_wget, ABFLAG_RAM }; addrbank kickmem_bank = { kickmem_lget, kickmem_wget, kickmem_bget, kickmem_lput, kickmem_wput, kickmem_bput, - kickmem_xlate, kickmem_check, NULL, _T("Kickstart ROM"), + kickmem_xlate, kickmem_check, NULL, _T("kick"), _T("Kickstart ROM"), kickmem_lget, kickmem_wget, ABFLAG_ROM }; addrbank kickram_bank = { kickmem_lget, kickmem_wget, kickmem_bget, kickmem2_lput, kickmem2_wput, kickmem2_bput, - kickmem_xlate, kickmem_check, NULL, _T("Kickstart Shadow RAM"), + kickmem_xlate, kickmem_check, NULL, NULL, _T("Kickstart Shadow RAM"), kickmem_lget, kickmem_wget, ABFLAG_UNK | ABFLAG_SAFE }; addrbank extendedkickmem_bank = { extendedkickmem_lget, extendedkickmem_wget, extendedkickmem_bget, extendedkickmem_lput, extendedkickmem_wput, extendedkickmem_bput, - extendedkickmem_xlate, extendedkickmem_check, NULL, _T("Extended Kickstart ROM"), + extendedkickmem_xlate, extendedkickmem_check, NULL, NULL, _T("Extended Kickstart ROM"), extendedkickmem_lget, extendedkickmem_wget, ABFLAG_ROM }; addrbank extendedkickmem2_bank = { extendedkickmem2_lget, extendedkickmem2_wget, extendedkickmem2_bget, extendedkickmem2_lput, extendedkickmem2_wput, extendedkickmem2_bput, - extendedkickmem2_xlate, extendedkickmem2_check, NULL, _T("Extended 2nd Kickstart ROM"), + extendedkickmem2_xlate, extendedkickmem2_check, NULL, _T("rom_a8"), _T("Extended 2nd Kickstart ROM"), extendedkickmem2_lget, extendedkickmem2_wget, ABFLAG_ROM }; @@ -1114,13 +1114,13 @@ MEMORY_FUNCTIONS(custmem2); addrbank custmem1_bank = { custmem1_lget, custmem1_wget, custmem1_bget, custmem1_lput, custmem1_wput, custmem1_bput, - custmem1_xlate, custmem1_check, NULL, _T("Non-autoconfig RAM #1"), + custmem1_xlate, custmem1_check, NULL, _T("custmem1"), _T("Non-autoconfig RAM #1"), custmem1_lget, custmem1_wget, ABFLAG_RAM }; addrbank custmem2_bank = { custmem2_lget, custmem2_wget, custmem2_bget, custmem2_lput, custmem2_wput, custmem2_bput, - custmem2_xlate, custmem2_check, NULL, _T("Non-autoconfig RAM #2"), + custmem2_xlate, custmem2_check, NULL, _T("custmem2"), _T("Non-autoconfig RAM #2"), custmem2_lget, custmem2_wget, ABFLAG_RAM }; @@ -1141,8 +1141,9 @@ void a3000_fakekick (int map) memcpy (kickmem_bank.baseaddr, fkickmemory, fkickmem_size / 2); memcpy (kickmem_bank.baseaddr + fkickmem_size / 2, fkickmemory, fkickmem_size / 2); extendedkickmem_bank.allocated = 65536; + extendedkickmem_bank.label = _T("rom_f0"); extendedkickmem_bank.mask = extendedkickmem_bank.allocated - 1; - extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_f0")); + mapped_malloc (&extendedkickmem_bank); memcpy (extendedkickmem_bank.baseaddr, fkickmemory + fkickmem_size / 2, 65536); map_banks (&extendedkickmem_bank, 0xf0, 1, 1); a3000_f0 = 1; @@ -1153,8 +1154,7 @@ void a3000_fakekick (int map) } else { if (a3000_f0) { map_banks (&dummy_bank, 0xf0, 1, 1); - mapped_free (extendedkickmem_bank.baseaddr); - extendedkickmem_bank.baseaddr = NULL; + mapped_free (&extendedkickmem_bank); a3000_f0 = 0; } if (kickstore) @@ -1292,11 +1292,13 @@ static bool load_extendedkickstart (const TCHAR *romextfile, int type) zfile_fseek (f, off, SEEK_SET); switch (extendedkickmem_type) { case EXTENDED_ROM_CDTV: - extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_f0")); + extendedkickmem_bank.label = _T("rom_f0"); + mapped_malloc (&extendedkickmem_bank); extendedkickmem_bank.start = 0xf00000; break; case EXTENDED_ROM_CD32: - extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_e0")); + extendedkickmem_bank.label = _T("rom_e0"); + mapped_malloc (&extendedkickmem_bank); extendedkickmem_bank.start = 0xe00000; break; } @@ -1400,8 +1402,9 @@ static bool load_kickstart_replacement (void) extendedkickmem_bank.allocated = ROM_SIZE_512; extendedkickmem_bank.mask = ROM_SIZE_512 - 1; + extendedkickmem_bank.label = _T("rom_e0"); extendedkickmem_type = EXTENDED_ROM_KS; - extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_e0")); + mapped_malloc (&extendedkickmem_bank); read_kickstart (f, extendedkickmem_bank.baseaddr, ROM_SIZE_512, 0, 1); kickmem_bank.allocated = ROM_SIZE_512; @@ -1493,20 +1496,21 @@ static int load_kickstart (void) if (currprefs.cs_cdtvcd || currprefs.cs_cdtvram) { extendedkickmem_type = EXTENDED_ROM_CDTV; extendedkickmem_bank.allocated *= 2; - extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_f0")); + extendedkickmem_bank.label = _T("rom_f0"); extendedkickmem_bank.start = 0xf00000; } else { extendedkickmem_type = EXTENDED_ROM_KS; - extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_e0")); + extendedkickmem_bank.label = _T("rom_e0"); extendedkickmem_bank.start = 0xe00000; } + mapped_malloc (&extendedkickmem_bank); zfile_fseek (f, extpos, SEEK_SET); read_kickstart (f, extendedkickmem_bank.baseaddr, extendedkickmem_bank.allocated, 0, 1); extendedkickmem_bank.mask = extendedkickmem_bank.allocated - 1; } if (filesize > ROM_SIZE_512 * 2) { extendedkickmem2_bank.allocated = ROM_SIZE_512 * 2; - extendedkickmem2_bank.baseaddr = mapped_malloc (extendedkickmem2_bank.allocated, _T("rom_a8")); + mapped_malloc (&extendedkickmem2_bank); zfile_fseek (f, extpos + ROM_SIZE_512, SEEK_SET); read_kickstart (f, extendedkickmem2_bank.baseaddr, ROM_SIZE_512, 0, 1); zfile_fseek (f, extpos + ROM_SIZE_512 * 2, SEEK_SET); @@ -1600,28 +1604,23 @@ static void delete_shmmaps (uae_u32 start, uae_u32 size) write_log (_T("NATMEM WARNING: size mismatch mapping at %08x (size %08x, delsize %08x)\n"),start,x->size,size); size = x->size; } -#if 0 - dumplist (); - nocanbang (); - return; + + shmdt (x->native_address); + size -= x->size; + start += x->size; + if (x->next) + x->next->prev = x->prev; /* remove this one from the list */ + if (x->prev) + x->prev->next = x->next; + else + shm_start = x->next; + xfree (x); + } else { + size -= 0x10000; + start += 0x10000; } -#endif - shmdt (x->native_address); - size -= x->size; - start += x->size; - if (x->next) - x->next->prev = x->prev; /* remove this one from the list */ - if (x->prev) - x->prev->next = x->next; - else - shm_start = x->next; - xfree (x); - } else { - size -= 0x10000; - start += 0x10000; } } -} static void add_shmmaps (uae_u32 start, addrbank *what) { @@ -1642,7 +1641,7 @@ static void add_shmmaps (uae_u32 start, addrbank *what) y = xmalloc (shmpiece, 1); *y = *x; base = ((uae_u8 *) NATMEM_OFFSET) + start; - y->native_address = (uae_u8*)shmat (y->id, base, 0); + y->native_address = (uae_u8*)shmat (what, y->id, base, 0); if (y->native_address == (void *) -1) { write_log (_T("NATMEM: Failure to map existing at %08x (%p)\n"), start, base); dumplist (); @@ -1656,52 +1655,60 @@ static void add_shmmaps (uae_u32 start, addrbank *what) shm_start = y; } -uae_u8 *mapped_malloc (size_t s, const TCHAR *file) +bool mapped_malloc (addrbank *ab) { int id; void *answer; shmpiece *x; - bool rtgmem = !_tcsicmp(file, _T("z3_gfx")) || !_tcsicmp(file, _T("z2_gfx")); + bool rtgmem = ab->label && (!_tcsicmp(ab->label, _T("z3_gfx")) || !_tcsicmp(ab->label, _T("z2_gfx"))); static int recurse; + ab->startmask = ab->start; if (!needmman () && (!rtgmem || currprefs.cpu_model < 68020)) { nocanbang (); - return xcalloc (uae_u8, s + 4); + if (ab->flags & ABFLAG_NOALLOC) + return true; + ab->baseaddr = xcalloc (uae_u8, ab->allocated + 4); + return ab->baseaddr != NULL; } - id = shmget (IPC_PRIVATE, s, 0x1ff, file); + id = shmget (IPC_PRIVATE, ab->allocated, 0x1ff, ab->label); if (id == -1) { - uae_u8 *p; nocanbang (); if (recurse) return NULL; recurse++; - p = mapped_malloc (s, file); + mapped_malloc (ab); recurse--; - return p; + return ab->baseaddr != NULL; + } + if (!(ab->flags & ABFLAG_NOALLOC)) { + answer = shmat (ab, id, 0, 0); + shmctl (id, IPC_RMID, NULL); + } else { + answer = ab->baseaddr; } - answer = shmat (id, 0, 0); - shmctl (id, IPC_RMID, NULL); if (answer != (void *) -1) { x = xmalloc (shmpiece, 1); x->native_address = (uae_u8*)answer; x->id = id; - x->size = s; - x->name = file; + x->size = ab->allocated; + x->name = ab->label; x->next = shm_start; x->prev = NULL; if (x->next) x->next->prev = x; shm_start = x; - return (uae_u8*)answer; + ab->baseaddr = x->native_address; + return ab->baseaddr != NULL; } if (recurse) return NULL; nocanbang (); recurse++; - uae_u8 *r = mapped_malloc (s, file); + mapped_malloc (ab); recurse--; - return r; + return ab->baseaddr != NULL; } #endif @@ -1731,10 +1738,8 @@ static void allocate_memory (void) (currprefs.chipset_mask & CSMASK_ECS_AGNUS) && !(currprefs.chipset_mask & CSMASK_AGA) && currprefs.cpu_model < 68020) { if ((chipmem_bank.allocated != currprefs.chipmem_size || bogomem_bank.allocated != currprefs.bogomem_size)) { int memsize1, memsize2; - mapped_free (chipmem_bank.baseaddr); - chipmem_bank.baseaddr = 0; - mapped_free (bogomem_bank.baseaddr); - bogomem_bank.baseaddr = NULL; + mapped_free (&chipmem_bank); + mapped_free (&bogomem_bank); bogomem_bank.allocated = 0; memsize1 = chipmem_bank.allocated = currprefs.chipmem_size; memsize2 = bogomem_bank.allocated = currprefs.bogomem_size; @@ -1742,7 +1747,9 @@ static void allocate_memory (void) chipmem_bank.start = chipmem_start_addr; chipmem_full_mask = bogomem_bank.allocated * 2 - 1; chipmem_full_size = 0x80000 * 2; - chipmem_bank.baseaddr = mapped_malloc (memsize1 + memsize2, _T("chip")); + chipmem_bank.allocated = memsize1 + memsize2; + mapped_malloc (&chipmem_bank); + chipmem_bank.allocated = currprefs.chipmem_size; bogomem_bank.baseaddr = chipmem_bank.baseaddr + memsize1; bogomem_bank.mask = bogomem_bank.allocated - 1; bogomem_bank.start = bogomem_start_addr; @@ -1758,8 +1765,7 @@ static void allocate_memory (void) if (chipmem_bank.allocated != currprefs.chipmem_size) { int memsize; - mapped_free (chipmem_bank.baseaddr); - chipmem_bank.baseaddr = 0; + mapped_free (&chipmem_bank); if (currprefs.chipmem_size > 2 * 1024 * 1024) { if (currprefs.fastmem_size >= 524288) free_fastmemory (0); @@ -1774,7 +1780,9 @@ static void allocate_memory (void) memsize = 0x100000; if (memsize > 0x100000 && memsize < 0x200000) memsize = 0x200000; - chipmem_bank.baseaddr = mapped_malloc (memsize, _T("chip")); + chipmem_bank.allocated = memsize; + mapped_malloc (&chipmem_bank); + chipmem_bank.allocated = currprefs.chipmem_size; if (chipmem_bank.baseaddr == 0) { write_log (_T("Fatal error: out of memory for chipmem.\n")); chipmem_bank.allocated = 0; @@ -1795,8 +1803,7 @@ static void allocate_memory (void) if (bogomem_bank.allocated != currprefs.bogomem_size) { if (!(bogomem_bank.allocated == 0x200000 && currprefs.bogomem_size == 0x180000)) { - mapped_free (bogomem_bank.baseaddr); - bogomem_bank.baseaddr = NULL; + mapped_free (&bogomem_bank); bogomem_bank.allocated = 0; bogomem_bank.allocated = currprefs.bogomem_size; @@ -1806,8 +1813,7 @@ static void allocate_memory (void) bogomem_bank.start = bogomem_start_addr; if (bogomem_bank.allocated) { - bogomem_bank.baseaddr = mapped_malloc (bogomem_bank.allocated, _T("bogo")); - if (bogomem_bank.baseaddr == 0) { + if (!mapped_malloc (&bogomem_bank)) { write_log (_T("Out of memory for bogomem.\n")); bogomem_bank.allocated = 0; } @@ -1816,15 +1822,13 @@ static void allocate_memory (void) } } if (a3000lmem_bank.allocated != currprefs.mbresmem_low_size) { - mapped_free (a3000lmem_bank.baseaddr); - a3000lmem_bank.baseaddr = NULL; + mapped_free (&a3000lmem_bank); a3000lmem_bank.allocated = currprefs.mbresmem_low_size; a3000lmem_bank.mask = a3000lmem_bank.allocated - 1; a3000lmem_bank.start = 0x08000000 - a3000lmem_bank.allocated; if (a3000lmem_bank.allocated) { - a3000lmem_bank.baseaddr = mapped_malloc (a3000lmem_bank.allocated, _T("ramsey_low")); - if (a3000lmem_bank.baseaddr == 0) { + if (!mapped_malloc (&a3000lmem_bank)) { write_log (_T("Out of memory for a3000lowmem.\n")); a3000lmem_bank.allocated = 0; } @@ -1832,15 +1836,13 @@ static void allocate_memory (void) need_hardreset = true; } if (a3000hmem_bank.allocated != currprefs.mbresmem_high_size) { - mapped_free (a3000hmem_bank.baseaddr); - a3000hmem_bank.baseaddr = NULL; + mapped_free (&a3000hmem_bank); a3000hmem_bank.allocated = currprefs.mbresmem_high_size; a3000hmem_bank.mask = a3000hmem_bank.allocated - 1; a3000hmem_bank.start = 0x08000000; if (a3000hmem_bank.allocated) { - a3000hmem_bank.baseaddr = mapped_malloc (a3000hmem_bank.allocated, _T("ramsey_high")); - if (a3000hmem_bank.baseaddr == 0) { + if (!mapped_malloc (&a3000hmem_bank)) { write_log (_T("Out of memory for a3000highmem.\n")); a3000hmem_bank.allocated = 0; } @@ -1849,15 +1851,14 @@ static void allocate_memory (void) } #ifdef CDTV if (cardmem_bank.allocated != currprefs.cs_cdtvcard * 1024) { - mapped_free (cardmem_bank.baseaddr); + mapped_free (&cardmem_bank); cardmem_bank.baseaddr = NULL; cardmem_bank.allocated = currprefs.cs_cdtvcard * 1024; cardmem_bank.mask = cardmem_bank.allocated - 1; cardmem_bank.start = 0xe00000; if (cardmem_bank.allocated) { - cardmem_bank.baseaddr = mapped_malloc (cardmem_bank.allocated, _T("rom_e0")); - if (cardmem_bank.baseaddr == 0) { + if (!mapped_malloc (&cardmem_bank)) { write_log (_T("Out of memory for cardmem.\n")); cardmem_bank.allocated = 0; } @@ -1866,27 +1867,23 @@ static void allocate_memory (void) } #endif if (custmem1_bank.allocated != currprefs.custom_memory_sizes[0]) { - mapped_free (custmem1_bank.baseaddr); - custmem1_bank.baseaddr = NULL; + mapped_free (&custmem1_bank); custmem1_bank.allocated = currprefs.custom_memory_sizes[0]; // custmem1 and 2 can have non-power of 2 size so only set correct mask if size is power of 2. custmem1_bank.mask = singlebit (custmem1_bank.allocated) ? custmem1_bank.allocated - 1 : -1; custmem1_bank.start = currprefs.custom_memory_addrs[0]; if (custmem1_bank.allocated) { - custmem1_bank.baseaddr = mapped_malloc (custmem1_bank.allocated, _T("custmem1")); - if (!custmem1_bank.baseaddr) + if (!mapped_malloc (&custmem1_bank)) custmem1_bank.allocated = 0; } } if (custmem2_bank.allocated != currprefs.custom_memory_sizes[1]) { - mapped_free (custmem2_bank.baseaddr); - custmem2_bank.baseaddr = NULL; + mapped_free (&custmem2_bank); custmem2_bank.allocated = currprefs.custom_memory_sizes[1]; custmem2_bank.mask = singlebit (custmem2_bank.allocated) ? custmem2_bank.allocated - 1 : -1; custmem2_bank.start = currprefs.custom_memory_addrs[1]; if (custmem2_bank.allocated) { - custmem2_bank.baseaddr = mapped_malloc (custmem2_bank.allocated, _T("custmem2")); - if (!custmem2_bank.baseaddr) + if (!mapped_malloc (&custmem2_bank)) custmem2_bank.allocated = 0; } } @@ -1894,7 +1891,7 @@ static void allocate_memory (void) if (savestate_state == STATE_RESTORE) { if (bootrom_filepos) { protect_roms (false); - restore_ram (bootrom_filepos, rtarea); + restore_ram (bootrom_filepos, rtarea_bank.baseaddr); protect_roms (true); } restore_ram (chip_filepos, chipmem_bank.baseaddr); @@ -2114,10 +2111,9 @@ void memory_reset (void) memcpy (currprefs.romfile, changed_prefs.romfile, sizeof currprefs.romfile); memcpy (currprefs.romextfile, changed_prefs.romextfile, sizeof currprefs.romextfile); need_hardreset = true; - mapped_free (extendedkickmem_bank.baseaddr); - extendedkickmem_bank.baseaddr = NULL; + mapped_free (&extendedkickmem_bank); + mapped_free (&extendedkickmem2_bank); extendedkickmem_bank.allocated = 0; - extendedkickmem2_bank.baseaddr = NULL; extendedkickmem2_bank.allocated = 0; extendedkickmem_type = 0; load_extendedkickstart (currprefs.romextfile, 0); @@ -2378,7 +2374,8 @@ void memory_init (void) custmem1_bank.baseaddr = NULL; custmem2_bank.baseaddr = NULL; - kickmem_bank.baseaddr = mapped_malloc (ROM_SIZE_512, _T("kick")); + kickmem_bank.allocated = ROM_SIZE_512; + mapped_malloc (&kickmem_bank); memset (kickmem_bank.baseaddr, 0, ROM_SIZE_512); _tcscpy (currprefs.romfile, _T("")); currprefs.romextfile[0] = 0; @@ -2396,20 +2393,20 @@ void memory_init (void) void memory_cleanup (void) { - mapped_free (a3000lmem_bank.baseaddr); - mapped_free (a3000hmem_bank.baseaddr); - mapped_free (bogomem_bank.baseaddr); - mapped_free (kickmem_bank.baseaddr); + mapped_free (&a3000lmem_bank); + mapped_free (&a3000hmem_bank); + mapped_free (&bogomem_bank); + mapped_free (&kickmem_bank); xfree (a1000_bootrom); - mapped_free (chipmem_bank.baseaddr); + mapped_free (&chipmem_bank); #ifdef CDTV if (cardmem_bank.baseaddr) { cdtv_savecardmem (cardmem_bank.baseaddr, cardmem_bank.allocated); - mapped_free (cardmem_bank.baseaddr); + mapped_free (&cardmem_bank); } #endif - mapped_free (custmem1_bank.baseaddr); - mapped_free (custmem2_bank.baseaddr); + mapped_free (&custmem1_bank); + mapped_free (&custmem2_bank); bogomem_bank.baseaddr = NULL; kickmem_bank.baseaddr = NULL; @@ -2462,7 +2459,7 @@ static void map_banks2 (addrbank *bank, int start, int size, int realsize, int q if (quick <= 0) old = debug_bankchange (-1); - flush_icache (0, 3); /* Sure don't want to keep any old mappings around! */ + flush_icache_hard (0, 3); /* Sure don't want to keep any old mappings around! */ #ifdef NATMEM_OFFSET if (!quick) delete_shmmaps (start << 16, size << 16); @@ -2543,7 +2540,7 @@ uae_u8 *save_bootrom (int *len) if (!uae_boot_rom) return 0; *len = uae_boot_rom_size; - return rtarea; + return rtarea_bank.baseaddr; } uae_u8 *save_cram (int *len) diff --git a/ncr9x_scsi.cpp b/ncr9x_scsi.cpp index 22222a67..d26e3810 100644 --- a/ncr9x_scsi.cpp +++ b/ncr9x_scsi.cpp @@ -515,7 +515,7 @@ static uae_u32 REGPARAM2 bncr9x_lget(uaecptr addr) static addrbank ncr9x_bank_blizzard = { bncr9x_lget, bncr9x_wget, bncr9x_bget, bncr9x_lput, bncr9x_wput, bncr9x_bput, - default_xlate, default_check, NULL, _T("53C94/FAS216"), + default_xlate, default_check, NULL, NULL, _T("53C94/FAS216"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; diff --git a/ncr_scsi.cpp b/ncr_scsi.cpp index 9a4d18e4..cc3274c8 100644 --- a/ncr_scsi.cpp +++ b/ncr_scsi.cpp @@ -452,7 +452,7 @@ DECLARE_MEMORY_FUNCTIONS(ncr4) static addrbank ncr_bank_a4091 = { ncr4_lget, ncr4_wget, ncr4_bget, ncr4_lput, ncr4_wput, ncr4_bput, - default_xlate, default_check, NULL, _T("A4091"), + default_xlate, default_check, NULL, NULL, _T("A4091"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -461,7 +461,7 @@ DECLARE_MEMORY_FUNCTIONS(ncr42) static addrbank ncr_bank_a4091_2 = { ncr42_lget, ncr42_wget, ncr42_bget, ncr42_lput, ncr42_wput, ncr42_bput, - default_xlate, default_check, NULL, _T("A4091 #2"), + default_xlate, default_check, NULL, NULL, _T("A4091 #2"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; @@ -680,21 +680,21 @@ static uae_u32 REGPARAM2 bppc_lget(uaecptr addr) static addrbank ncr_bank_warpengine = { we_lget, we_wget, we_bget, we_lput, we_wput, we_bput, - default_xlate, default_check, NULL, _T("Warp Engine SCSI"), + default_xlate, default_check, NULL, NULL, _T("Warp Engine SCSI"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; addrbank ncr_bank_cyberstorm = { cs_lget, cs_wget, cs_bget, cs_lput, cs_wput, cs_bput, - cyberstorm_scsi_ram_xlate, cyberstorm_scsi_ram_check, NULL, _T("CyberStorm SCSI"), + cyberstorm_scsi_ram_xlate, cyberstorm_scsi_ram_check, NULL, NULL, _T("CyberStorm SCSI"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; addrbank ncr_bank_blizzardppc = { bppc_lget, bppc_wget, bppc_bget, bppc_lput, bppc_wput, bppc_bput, - default_xlate, default_check, NULL, _T("Blizzard PPC SCSI"), + default_xlate, default_check, NULL, NULL, _T("Blizzard PPC SCSI"), dummy_lgeti, dummy_wgeti, ABFLAG_IO }; diff --git a/newcpu.cpp b/newcpu.cpp index 9ab68249..be338e49 100644 --- a/newcpu.cpp +++ b/newcpu.cpp @@ -37,6 +37,8 @@ #include "audio.h" #include "md-fpp.h" #include "statusline.h" +#include "ppc.h" +#include "cpuboard.h" #ifdef JIT #include "jit/compemu.h" #include @@ -60,7 +62,7 @@ static int last_instructionaccess_for_exception_3; int mmu_enabled, mmu_triggered; int cpu_cycles; static int baseclock; -bool m68k_pc_indirect; +int m68k_pc_indirect; bool m68k_interrupt_delay; static bool m68k_reset_delay; static int cpu_prefs_changed_flag; @@ -707,6 +709,34 @@ static void do_cycles_ce020_post (unsigned long cycles, uae_u32 v) do_cycles_ce020 (cycles); } +static void set_x_ifetches(void) +{ + if (m68k_pc_indirect) { + if (currprefs.cachesize) { + // indirect via addrbank + x_get_ilong = get_iilong_jit; + x_get_iword = get_iiword_jit; + x_get_ibyte = get_iibyte_jit; + x_next_iword = next_iiword_jit; + x_next_ilong = next_iilong_jit; + } else { + // indirect via addrbank + x_get_ilong = get_iilong; + x_get_iword = get_iiword; + x_get_ibyte = get_iibyte; + x_next_iword = next_iiword; + x_next_ilong = next_iilong; + } + } else { + // direct to memory + x_get_ilong = get_dilong; + x_get_iword = get_diword; + x_get_ibyte = get_dibyte; + x_next_iword = next_diword; + x_next_ilong = next_dilong; + } +} + // indirect memory access functions static void set_x_funcs (void) { @@ -827,11 +857,7 @@ static void set_x_funcs (void) } else if (currprefs.cpu_model < 68040) { // JIT or 68030+ does not have real prefetch only emulation x_prefetch = NULL; - x_get_ilong = get_dilong; - x_get_iword = get_diword; - x_get_ibyte = get_dibyte; - x_next_iword = next_diword; - x_next_ilong = next_dilong; + set_x_ifetches(); x_put_long = put_long; x_put_word = put_word; x_put_byte = put_byte; @@ -860,11 +886,7 @@ static void set_x_funcs (void) } } else { x_prefetch = NULL; - x_get_ilong = get_dilong; - x_get_iword = get_diword; - x_get_ibyte = get_dibyte; - x_next_iword = next_diword; - x_next_ilong = next_dilong; + set_x_ifetches(); x_put_long = put_long; x_put_word = put_word; x_put_byte = put_byte; @@ -1116,96 +1138,54 @@ static uae_u32 REGPARAM2 op_unimpl_1 (uae_u32 opcode) return 4; } +// generic+direct, generic+indirect, more compatible, cycle-exact, mmu +static const struct cputbl *cputbls[6][5] = +{ + // 68000 + { op_smalltbl_5_ff, op_smalltbl_45_ff, op_smalltbl_12_ff, op_smalltbl_14_ff, NULL }, + // 68010 + { op_smalltbl_4_ff, op_smalltbl_44_ff, op_smalltbl_11_ff, op_smalltbl_13_ff, NULL }, + // 68020 + { op_smalltbl_3_ff, op_smalltbl_43_ff, op_smalltbl_20_ff, op_smalltbl_21_ff, NULL }, + // 68030 + { op_smalltbl_2_ff, op_smalltbl_42_ff, op_smalltbl_42_ff, op_smalltbl_22_ff, op_smalltbl_32_ff }, + // 68040 + { op_smalltbl_1_ff, op_smalltbl_41_ff, op_smalltbl_24_ff, op_smalltbl_24_ff, op_smalltbl_31_ff }, + // 68060 + { op_smalltbl_0_ff, op_smalltbl_40_ff, op_smalltbl_23_ff, op_smalltbl_23_ff, op_smalltbl_33_ff } +}; + static void build_cpufunctbl (void) { int i, opcnt; unsigned long opcode; const struct cputbl *tbl = 0; - int lvl; + int lvl, mode; - switch (currprefs.cpu_model) - { -#ifdef CPUEMU_0 -#ifndef CPUEMU_68000_ONLY - case 68060: - lvl = 5; - tbl = op_smalltbl_0_ff; - if (!currprefs.cachesize) { - if (currprefs.cpu_cycle_exact) - tbl = op_smalltbl_23_ff; - if (currprefs.cpu_compatible) - tbl = op_smalltbl_23_ff; - if (currprefs.mmu_model) - tbl = op_smalltbl_33_ff; - } - break; - case 68040: - lvl = 4; - tbl = op_smalltbl_1_ff; - if (!currprefs.cachesize) { - if (currprefs.cpu_cycle_exact) - tbl = op_smalltbl_24_ff; - if (currprefs.cpu_compatible) - tbl = op_smalltbl_24_ff; - if (currprefs.mmu_model) - tbl = op_smalltbl_31_ff; - } - break; - case 68030: - lvl = 3; - tbl = op_smalltbl_2_ff; - if (!currprefs.cachesize) { - if (currprefs.cpu_cycle_exact) - tbl = op_smalltbl_22_ff; - if (currprefs.mmu_model) - tbl = op_smalltbl_32_ff; - } - break; - case 68020: - lvl = 2; - tbl = op_smalltbl_3_ff; - if (!currprefs.cachesize) { -#ifdef CPUEMU_20 - if (currprefs.cpu_compatible) - tbl = op_smalltbl_20_ff; -#endif -#ifdef CPUEMU_21 - if (currprefs.cpu_cycle_exact) - tbl = op_smalltbl_21_ff; -#endif + if (!currprefs.cachesize) { + if (currprefs.mmu_model) + mode = 4; + else if (currprefs.cpu_cycle_exact) + mode = 3; + else if (currprefs.cpu_compatible) + mode = 2; + else + mode = 0; + m68k_pc_indirect = mode != 0 ? 1 : 0; + } else { + mode = 0; + m68k_pc_indirect = 0; + if (currprefs.comptrustbyte) { + mode = 1; + m68k_pc_indirect = -1; } - break; - case 68010: - lvl = 1; - tbl = op_smalltbl_4_ff; -#ifdef CPUEMU_11 - if (currprefs.cpu_compatible) - tbl = op_smalltbl_11_ff; /* prefetch */ -#endif -#ifdef CPUEMU_13 - if (currprefs.cpu_cycle_exact) - tbl = op_smalltbl_13_ff; /* prefetch and cycle-exact */ -#endif - break; -#endif -#endif - default: - changed_prefs.cpu_model = currprefs.cpu_model = 68000; - case 68000: - lvl = 0; - tbl = op_smalltbl_5_ff; -#ifdef CPUEMU_11 - if (currprefs.cpu_compatible) - tbl = op_smalltbl_12_ff; /* prefetch */ -#endif -#ifdef CPUEMU_13 - if (currprefs.cpu_cycle_exact) - tbl = op_smalltbl_14_ff; /* prefetch and cycle-exact */ -#endif - break; } + lvl = (currprefs.cpu_model - 68000) / 10; + if (lvl == 6) + lvl = 5; + tbl = cputbls[lvl][mode]; - if (tbl == 0) { + if (tbl == NULL) { write_log (_T("no CPU emulation cores available CPU=%d!"), currprefs.cpu_model); abort (); } @@ -1281,7 +1261,7 @@ static void build_cpufunctbl (void) } m68k_interrupt_delay = false; if (currprefs.cpu_cycle_exact) { - if (tbl == op_smalltbl_13_ff || tbl == op_smalltbl_21_ff || tbl == op_smalltbl_22_ff) + if (tbl == op_smalltbl_14_ff || tbl == op_smalltbl_13_ff || tbl == op_smalltbl_21_ff || tbl == op_smalltbl_22_ff) m68k_interrupt_delay = true; } @@ -1297,6 +1277,8 @@ static void build_cpufunctbl (void) write_log(_T(" fake prefetch")); } } + if (currprefs.m68k_speed < 0) + write_log(_T(" fast")); if (currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) { write_log(_T(" no unimplemented integer instructions")); } @@ -1309,9 +1291,6 @@ static void build_cpufunctbl (void) } write_log(_T("\n")); - m68k_pc_indirect = (currprefs.mmu_model || currprefs.cpu_compatible) && !currprefs.cachesize; - if (tbl == op_smalltbl_0_ff || tbl == op_smalltbl_1_ff || tbl == op_smalltbl_2_ff || tbl == op_smalltbl_3_ff || tbl == op_smalltbl_4_ff || tbl == op_smalltbl_5_ff) - m68k_pc_indirect = false; set_cpu_caches (true); } @@ -1328,11 +1307,18 @@ static void update_68k_cycles (void) cycles_mult = (unsigned long)(CYCLES_DIV * 1000 / (1000 + currprefs.m68k_speed_throttle)); } } - if (currprefs.m68k_speed == 0 && currprefs.cpu_model >= 68020) { - if (!cycles_mult) - cycles_mult = CYCLES_DIV / 4; - else - cycles_mult /= 4; + if (currprefs.m68k_speed == 0) { + if (currprefs.cpu_model >= 68040) { + if (!cycles_mult) + cycles_mult = CYCLES_DIV / 8; + else + cycles_mult /= 8; + } else if (currprefs.cpu_model >= 68020) { + if (!cycles_mult) + cycles_mult = CYCLES_DIV / 4; + else + cycles_mult /= 4; + } } currprefs.cpu_clock_multiplier = changed_prefs.cpu_clock_multiplier; @@ -1346,10 +1332,14 @@ static void update_68k_cycles (void) } else { cpucycleunit = CYCLE_UNIT * currprefs.cpu_clock_multiplier; } + if (currprefs.cpu_model >= 68040) + cpucycleunit /= 2; } else if (currprefs.cpu_frequency) { cpucycleunit = CYCLE_UNIT * baseclock / currprefs.cpu_frequency; } else if (currprefs.cpu_cycle_exact && currprefs.cpu_clock_multiplier == 0) { - if (currprefs.cpu_model >= 68030) { + if (currprefs.cpu_model >= 68040) { + cpucycleunit = CYCLE_UNIT / 16; + } if (currprefs.cpu_model == 68030) { cpucycleunit = CYCLE_UNIT / 8; } else if (currprefs.cpu_model == 68020) { cpucycleunit = CYCLE_UNIT / 4; @@ -2786,7 +2776,7 @@ static void m68k_reset2(bool hardreset) } regs.halted = 0; - gui_data.cpu_halted = false; + gui_data.cpu_halted = 0; gui_led (LED_CPU, 0); /* 68060 FPU is not compatible with 68040, @@ -3157,6 +3147,19 @@ static void do_trace (void) } } +#ifdef WITH_PPC +static void uae_ppc_poll_check(void) +{ + static int checkcnt; + + checkcnt--; + if (checkcnt > 0) + return; + uae_ppc_poll_queue(); + checkcnt = 128; +} +#endif + // handle interrupt delay (few cycles) STATIC_INLINE bool time_for_interrupt (void) { @@ -3184,6 +3187,21 @@ static int do_specialties (int cycles) return 1; if (regs.spcflags & SPCFLAG_CHECK) { + while (regs.halted) { + if (vpos == 0) + sleep_millis_main(8); + x_do_cycles(8 * CYCLE_UNIT); + if (regs.spcflags & SPCFLAG_COPPER) + do_copper(); +#ifdef WITH_PPC + if (ppc_state) + ppc_interrupt(intlev()); +#endif + if (regs.spcflags) { + if ((regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE))) + return 1; + } + } if (m68k_reset_delay) { int vsynccnt = 60; int vsyncstate = -1; @@ -3257,6 +3275,10 @@ static int do_specialties (int cycles) x_do_cycles (c * CYCLE_UNIT); if (regs.spcflags & SPCFLAG_COPPER) do_copper (); +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_check(); +#endif } if (regs.spcflags & SPCFLAG_DOTRACE) @@ -3267,7 +3289,7 @@ static int do_specialties (int cycles) Exception (3); } - while (regs.spcflags & SPCFLAG_STOP) { + while ((regs.spcflags & SPCFLAG_STOP) && !(regs.spcflags & SPCFLAG_BRK)) { if (uae_int_requested || uaenet_int_requested) { INTREQ_f (0x8008); @@ -3303,8 +3325,17 @@ static int do_specialties (int cycles) if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) { int intr = intlev (); unset_special (SPCFLAG_INT | SPCFLAG_DOINT); - if (intr > 0 && intr > regs.intmask) - do_interrupt (intr); +#ifdef WITH_PPC + bool m68kint = true; + if (ppc_state) + m68kint = ppc_interrupt(intr); + if (m68kint) { +#endif + if (intr > 0 && intr > regs.intmask) + do_interrupt (intr); +#ifdef WITH_PPC + } +#endif } } @@ -3313,7 +3344,16 @@ static int do_specialties (int cycles) return 1; } - if (!uae_int_requested && !uaenet_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP)) { +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_check(); +#endif + + if (!uae_int_requested && !uaenet_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP) +#ifdef WITH_PPC + && ppc_state != PPC_STATE_ACTIVE +#endif + ) { /* sleep 1ms if STOP-instruction is executed * but only if we have free frametime left to prevent slowdown */ @@ -3462,6 +3502,10 @@ STATIC_INLINE void wait_memory_cycles (void) x_do_cycles(regs.memory_waitstate_cycles); regs.memory_waitstate_cycles = 0; } + if (regs.ce020extracycles >= 16) { + regs.ce020extracycles = 0; + x_do_cycles(4 * CYCLE_UNIT); + } } STATIC_INLINE int adjust_cycles (int cycles) @@ -3677,18 +3721,27 @@ void exec_nostats (void) for (;;) { - uae_u16 opcode = get_diword (0); + uae_u16 opcode; + if (currprefs.cpu_compatible) { + opcode = get_word_020_prefetchf(m68k_getpc()); + } + else { + opcode = x_get_iword(0); + } cpu_cycles = (*cpufunctbl[opcode])(opcode); cpu_cycles = adjust_cycles (cpu_cycles); do_cycles (cpu_cycles); - if (end_block (opcode) || r->spcflags || uae_int_requested || uaenet_int_requested) +#ifdef WITH_PPC + if (ppc_state) + ppc_interrupt(intlev()); +#endif + + if (end_block(opcode) || r->spcflags || uae_int_requested || uaenet_int_requested) return; /* We will deal with the spcflags in the caller */ } } -static int triggered; - void execute_normal (void) { struct regstruct *r = ®s; @@ -3711,7 +3764,7 @@ void execute_normal (void) if (currprefs.cpu_compatible) { opcode = get_word_020_prefetchf (regs.instruction_pc); } else { - opcode = get_diword (0); + opcode = x_get_iword(0); } special_mem = DISTRUST_CONSISTENT_MEM; @@ -3729,6 +3782,11 @@ void execute_normal (void) } /* No need to check regs.spcflags, because if they were set, we'd have ended up inside that "if" */ + +#ifdef WITH_PPC + if (ppc_state) + ppc_interrupt(intlev()); +#endif } } @@ -3743,6 +3801,10 @@ static void m68k_run_jit (void) INTREQ_f (0x8008); set_special (SPCFLAG_INT); } +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_queue(); +#endif if (regs.spcflags) { if (do_specialties (0)) { return; @@ -3795,19 +3857,13 @@ void cpu_halt (int id) write_log (_T("CPU halted: reason = %d\n"), id); regs.halted = id; gui_data.cpu_halted = id; - gui_led (LED_CPU, 0); - regs.intmask = 7; - MakeSR (); - audio_deactivate (); - } - while (regs.halted) { - if (vpos == 0) - sleep_millis_main (8); - x_do_cycles (100 * CYCLE_UNIT); - if (regs.spcflags) { - if ((regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE))) - return; + gui_led(LED_CPU, 0); + if (id >= 0) { + regs.intmask = 7; + MakeSR (); + audio_deactivate (); } + set_special(SPCFLAG_CHECK); } } @@ -3838,6 +3894,12 @@ retry: cpu_cycles = (*cpufunctbl[opcode])(opcode); cpu_cycles = adjust_cycles (cpu_cycles); + +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_queue(); +#endif + if (regs.spcflags) { if (do_specialties (cpu_cycles)) return; @@ -3896,6 +3958,11 @@ retry: cpu_cycles = (*cpufunctbl[opcode])(opcode); cpu_cycles = adjust_cycles (cpu_cycles); +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_queue(); +#endif + if (regs.spcflags) { if (do_specialties (cpu_cycles)) return; @@ -4016,14 +4083,13 @@ insretry: #endif -/* "cycle exact" 68040+ */ +/* "cycle exact" 68040/060 */ static void m68k_run_3ce (void) { struct regstruct *r = ®s; uae_u16 opcode; bool exit = false; - int cycles; for (;;) { r->instruction_pc = m68k_getpc(); @@ -4034,9 +4100,10 @@ static void m68k_run_3ce (void) (*cpufunctbl[opcode])(opcode); - cpu_cycles = 4 * CYCLE_UNIT; - cycles = adjust_cycles(cpu_cycles); - do_cycles(cycles); +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_queue(); +#endif if (r->spcflags) { if (do_specialties (0)) @@ -4048,7 +4115,7 @@ static void m68k_run_3ce (void) } } -/* "prefetch" 68040+ */ +/* "prefetch" 68040/060 */ static void m68k_run_3p(void) { @@ -4066,10 +4133,15 @@ static void m68k_run_3p(void) (*cpufunctbl[opcode])(opcode); - cpu_cycles = 4 * CYCLE_UNIT; + cpu_cycles = 1 * CYCLE_UNIT; cycles = adjust_cycles(cpu_cycles); do_cycles(cycles); +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_queue(); +#endif + if (r->spcflags) { if (do_specialties(0)) exit = true; @@ -4273,7 +4345,7 @@ static void m68k_run_2 (void) for (;;) { r->instruction_pc = m68k_getpc (); - uae_u16 opcode = get_diword (0); + uae_u16 opcode = x_get_iword(0); count_instr (opcode); // if (regs.s == 0 && regs.regs[15] < 0x10040000 && regs.regs[15] > 0x10000000) @@ -4289,8 +4361,15 @@ static void m68k_run_2 (void) // write_log (_T("%08x %04X %d "), r->instruction_pc, opcode, cpu_cycles); do_cycles (cpu_cycles); + cpu_cycles = (*cpufunctbl[opcode])(opcode); cpu_cycles = adjust_cycles (cpu_cycles); + +#ifdef WITH_PPC + if (ppc_state) + uae_ppc_poll_queue(); +#endif + if (r->spcflags) { if (do_specialties (cpu_cycles)) { break; @@ -4928,7 +5007,8 @@ void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr pc, uaecptr *nextpc, int cn p = instrname + _tcslen(instrname); if (lookup->mnemo == i_BFFFO || lookup->mnemo == i_BFEXTS || lookup->mnemo == i_BFEXTU) _stprintf(p, _T(",D%d"), reg); - } else if (lookup->mnemo == i_CPUSHA || lookup->mnemo == i_CPUSHL || lookup->mnemo == i_CPUSHP) { + } else if (lookup->mnemo == i_CPUSHA || lookup->mnemo == i_CPUSHL || lookup->mnemo == i_CPUSHP || + lookup->mnemo == i_CINVA || lookup->mnemo == i_CINVL || lookup->mnemo == i_CINVP) { if ((opcode & 0xc0) == 0xc0) _tcscat(instrname, _T("BC")); else if (opcode & 0x80) @@ -4937,7 +5017,7 @@ void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr pc, uaecptr *nextpc, int cn _tcscat(instrname, _T("DC")); else _tcscat(instrname, _T("?")); - if (lookup->mnemo == i_CPUSHL || lookup->mnemo == i_CPUSHP) { + if (lookup->mnemo == i_CPUSHL || lookup->mnemo == i_CPUSHP || lookup->mnemo == i_CINVL || lookup->mnemo == i_CINVP) { TCHAR *p = instrname + _tcslen(instrname); _stprintf(p, _T(",(A%d)"), opcode & 7); } @@ -6545,6 +6625,7 @@ uae_u32 fill_icache040(uae_u32 addr) regs.prefetch020[1] = get_longi(addr2 + 4); regs.prefetch020[2] = get_longi(addr2 + 8); regs.prefetch020[3] = get_longi(addr2 + 12); + x_do_cycles(4 * cpucycleunit); } return regs.prefetch020[lws]; } @@ -6558,6 +6639,7 @@ uae_u32 fill_icache040(uae_u32 addr) if (c->valid[i] && c->tag[i] == tag) { // cache hit icachelinecnt++; + x_do_cycles(1 * cpucycleunit); return c->data[i][lws]; } } @@ -6583,6 +6665,7 @@ uae_u32 fill_icache040(uae_u32 addr) c->data[line][1] = get_longi(addr + 4); c->data[line][2] = get_longi(addr + 8); c->data[line][3] = get_longi(addr + 12); + x_do_cycles(4 * cpucycleunit); } return c->data[line][lws]; } @@ -6725,10 +6808,23 @@ uae_u32 get_iword_cache_040(int o) return get_word_icache040(m68k_getpci() + o); } +STATIC_INLINE bool nocache040(uaecptr addr) +{ + if (!currprefs.cpu_cycle_exact) + return false; + if (!(regs.cacr & 0x80000000)) + return true; + if (addr >= 0xd80000 && addr < 0xc00000) + return true; + if (addr >= 0xe80000 && addr < 0xf00000) + return true; + return false; +} + void put_long_cache_040(uaecptr addr, uae_u32 v) { #if 1 - if (currprefs.cpu_cycle_exact) + if (nocache040(addr)) mem_access_delay_long_write_ce020(addr, v); else put_long(addr, v); @@ -6768,7 +6864,7 @@ void put_long_cache_040(uaecptr addr, uae_u32 v) void put_word_cache_040(uaecptr addr, uae_u32 v) { #if 1 - if (currprefs.cpu_cycle_exact) + if (nocache040(addr)) mem_access_delay_word_write_ce020(addr, v); else put_word(addr, v); @@ -6794,7 +6890,7 @@ void put_word_cache_040(uaecptr addr, uae_u32 v) void put_byte_cache_040(uaecptr addr, uae_u32 v) { #if 1 - if (currprefs.cpu_cycle_exact) + if (nocache040(addr)) mem_access_delay_byte_write_ce020(addr, v); else put_byte(addr, v); @@ -6817,7 +6913,7 @@ void put_byte_cache_040(uaecptr addr, uae_u32 v) uae_u32 get_long_cache_040(uaecptr addr) { #if 1 - if (currprefs.cpu_cycle_exact) + if (nocache040(addr)) return mem_access_delay_long_read_ce020(addr); else return get_long(addr); @@ -6833,7 +6929,7 @@ uae_u32 get_long_cache_040(uaecptr addr) uae_u32 get_word_cache_040(uaecptr addr) { #if 1 - if (currprefs.cpu_cycle_exact) + if (nocache040(addr)) return mem_access_delay_word_read_ce020(addr); else return get_word(addr); @@ -6845,7 +6941,7 @@ uae_u32 get_word_cache_040(uaecptr addr) uae_u32 get_byte_cache_040(uaecptr addr) { #if 1 - if (currprefs.cpu_cycle_exact) + if (nocache040(addr)) return mem_access_delay_byte_read_ce020(addr); else return get_byte(addr); diff --git a/od-win32/mman.cpp b/od-win32/mman.cpp index 9c51348f..7d812d6f 100644 --- a/od-win32/mman.cpp +++ b/od-win32/mman.cpp @@ -6,8 +6,8 @@ #include "sysconfig.h" #include "sysdeps.h" -#include "sys/mman.h" #include "memory.h" +#include "sys/mman.h" #include "options.h" #include "autoconf.h" #include "gfxboard.h" @@ -437,24 +437,27 @@ void free_shm (void) clear_shm (); } -void mapped_free (uae_u8 *mem) +void mapped_free (addrbank *ab) { shmpiece *x = shm_start; - if (mem == NULL) + if (ab->baseaddr == NULL) return; - if (!currprefs.jit_direct_compatible_memory && mem != rtgmem_mapped_memory) { - xfree(mem); + if (!currprefs.jit_direct_compatible_memory && ab->baseaddr != rtgmem_mapped_memory) { + if (!(ab->flags & ABFLAG_NOALLOC)) { + xfree(ab->baseaddr); + ab->baseaddr = NULL; + } return; } - if (mem == rtgmem_mapped_memory) + if (ab->baseaddr == rtgmem_mapped_memory) rtgmem_mapped_memory = NULL; - if (mem == filesysory) { + if (ab->flags & ABFLAG_INDIRECT) { while(x) { - if (mem == x->native_address) { + if (ab->baseaddr == x->native_address) { int shmid = x->id; shmids[shmid].key = -1; shmids[shmid].name[0] = '\0'; @@ -462,26 +465,32 @@ void mapped_free (uae_u8 *mem) shmids[shmid].attached = 0; shmids[shmid].mode = 0; shmids[shmid].natmembase = 0; + if (!(ab->flags & ABFLAG_NOALLOC)) { + xfree(ab->baseaddr); + ab->baseaddr = NULL; + } } x = x->next; } + ab->baseaddr = NULL; return; } while(x) { - if(mem == x->native_address) + if(ab->baseaddr == x->native_address) shmdt (x->native_address); x = x->next; } x = shm_start; while(x) { struct shmid_ds blah; - if (mem == x->native_address) { + if (ab->baseaddr == x->native_address) { if (shmctl (x->id, IPC_STAT, &blah) == 0) shmctl (x->id, IPC_RMID, &blah); } x = x->next; } + ab->baseaddr = NULL; } static key_t get_next_shmkey (void) @@ -513,7 +522,7 @@ int mprotect (void *addr, size_t len, int prot) return result; } -void *shmat (int shmid, void *shmaddr, int shmflg) +void *shmat (addrbank *ab, int shmid, void *shmaddr, int shmflg) { void *result = (void *)-1; BOOL got = FALSE, readonly = FALSE, maprom = FALSE; @@ -526,6 +535,13 @@ void *shmat (int shmid, void *shmaddr, int shmflg) if (shmids[shmid].attached) return shmids[shmid].attached; + if (ab->flags & ABFLAG_INDIRECT) { + result = xcalloc (uae_u8, size); + shmids[shmid].attached = result; + shmids[shmid].fake = true; + return result; + } + if ((uae_u8*)shmaddr < natmem_offset) { if(!_tcscmp (shmids[shmid].name, _T("chip"))) { shmaddr=natmem_offset; @@ -639,6 +655,7 @@ void *shmat (int shmid, void *shmaddr, int shmflg) got = TRUE; if (currprefs.bogomem_size <= 0x100000) size += BARRIER; +#if 0 } else if(!_tcscmp (shmids[shmid].name, _T("filesys"))) { static uae_u8 *filesysptr; if (filesysptr == NULL) @@ -647,6 +664,7 @@ void *shmat (int shmid, void *shmaddr, int shmflg) shmids[shmid].attached = result; shmids[shmid].fake = true; return result; +#endif } else if(!_tcscmp (shmids[shmid].name, _T("custmem1"))) { shmaddr=natmem_offset + currprefs.custom_memory_addrs[0]; got = TRUE; diff --git a/od-win32/picasso96_win.cpp b/od-win32/picasso96_win.cpp index 1acc2740..635d1479 100644 --- a/od-win32/picasso96_win.cpp +++ b/od-win32/picasso96_win.cpp @@ -4285,7 +4285,7 @@ MEMORY_FUNCTIONS(gfxmem); addrbank gfxmem_bank = { gfxmem_lget, gfxmem_wget, gfxmem_bget, gfxmem_lput, gfxmem_wput, gfxmem_bput, - gfxmem_xlate, gfxmem_check, NULL, _T("RTG RAM"), + gfxmem_xlate, gfxmem_check, NULL, NULL, _T("RTG RAM"), dummy_lgeti, dummy_wgeti, ABFLAG_RAM }; diff --git a/od-win32/resources/winuae.rc b/od-win32/resources/winuae.rc index 6585a957..eac6c765 100644 --- a/od-win32/resources/winuae.rc +++ b/od-win32/resources/winuae.rc @@ -1215,8 +1215,8 @@ END // VS_VERSION_INFO VERSIONINFO - FILEVERSION 2,8,2,0 - PRODUCTVERSION 2,8,2,0 + FILEVERSION 2,9,0,0 + PRODUCTVERSION 2,9,0,0 FILEFLAGSMASK 0x3fL #ifdef _DEBUG FILEFLAGS 0x1L @@ -1232,12 +1232,12 @@ BEGIN BLOCK "040904b0" BEGIN VALUE "FileDescription", "WinUAE" - VALUE "FileVersion", "2.8.2.0" + VALUE "FileVersion", "2.9.0.0" VALUE "InternalName", "WinUAE" VALUE "LegalCopyright", "© 1996-2014 under the GNU Public License (GPL)" VALUE "OriginalFilename", "WinUAE.exe" VALUE "ProductName", "WinUAE" - VALUE "ProductVersion", "2.8.2.0" + VALUE "ProductVersion", "2.9.0.0" END END BLOCK "VarFileInfo" diff --git a/od-win32/sys/mman.h b/od-win32/sys/mman.h index 1925b551..1c1373be 100644 --- a/od-win32/sys/mman.h +++ b/od-win32/sys/mman.h @@ -32,7 +32,7 @@ struct shmid_ds { }; int mprotect (void *addr, size_t len, int prot); -void *shmat (int shmid, LPVOID shmaddr, int shmflg); +void *shmat (addrbank *ab, int shmid, LPVOID shmaddr, int shmflg); int shmdt (const void *shmaddr); int shmget (key_t key, size_t size, int shmflg, const TCHAR*); int shmctl (int shmid, int cmd, struct shmid_ds *buf); diff --git a/od-win32/sysconfig.h b/od-win32/sysconfig.h index 5534a7fd..dbb7b3ad 100644 --- a/od-win32/sysconfig.h +++ b/od-win32/sysconfig.h @@ -11,7 +11,7 @@ #define DRIVESOUND #define GFXFILTER #define X86_MSVC_ASSEMBLY -//#define X86_MSVC_ASSEMBLY_MEMACCESS +#define X86_MSVC_ASSEMBLY_MEMACCESS #define OPTIMIZED_FLAGS #define __i386__ #define WINDOWS @@ -50,7 +50,7 @@ #define WITH_SOFTFLOAT #define MMUEMU /* Aranym 68040 MMU */ #define FULLMMU /* Aranym 68040 MMU */ -#define CPUEMU_0 /* generic 680x0 emulation */ +#define CPUEMU_0 /* generic 680x0 emulation with direct memory access */ #define CPUEMU_11 /* 68000/68010 prefetch emulation */ #define CPUEMU_13 /* 68000/68010 cycle-exact cpu&blitter */ #define CPUEMU_20 /* 68020 prefetch */ @@ -60,6 +60,7 @@ #define CPUEMU_31 /* Aranym 68040 MMU */ #define CPUEMU_32 /* Previous 68030 MMU */ #define CPUEMU_33 /* 68060 MMU */ +#define CPUEMU_40 /* generic 680x0 with indirect memory access */ #define ACTION_REPLAY /* Action Replay 1/2/3 support */ #define PICASSO96 /* Picasso96 display card emulation */ #define UAEGFX_INTERNAL /* built-in libs:picasso96/uaegfx.card */ @@ -87,6 +88,7 @@ #define WITH_SLIRP #define WITH_TABLETLIBRARY #define WITH_UAENET_PCAP +#define WITH_PPC #else @@ -138,6 +140,7 @@ #include #ifdef WIN64 +#undef X86_MSVC_ASSEMBLY_MEMACCESS #undef X86_MSVC_ASSEMBLY #undef JIT #define X64_MSVC_ASSEMBLY diff --git a/od-win32/win32.h b/od-win32/win32.h index cf28c2c7..5d9118d5 100644 --- a/od-win32/win32.h +++ b/od-win32/win32.h @@ -20,12 +20,12 @@ #define LANG_DLL_FULL_VERSION_MATCH 1 #if WINUAEPUBLICBETA -#define WINUAEBETA _T("8") +#define WINUAEBETA _T("9") #else #define WINUAEBETA _T("") #endif -#define WINUAEDATE MAKEBD(2014, 7, 31) +#define WINUAEDATE MAKEBD(2014, 8, 7) //#define WINUAEEXTRA _T("AmiKit Preview") //#define WINUAEEXTRA _T("Amiga Forever Edition") diff --git a/od-win32/win32gfx.cpp b/od-win32/win32gfx.cpp index 3665205a..ba3f7eb4 100644 --- a/od-win32/win32gfx.cpp +++ b/od-win32/win32gfx.cpp @@ -52,6 +52,7 @@ #include "lcd.h" #include "sampler.h" #include "gfxboard.h" +#include "cpuboard.h" #ifdef RETROPLATFORM #include "rp.h" #endif @@ -2650,6 +2651,8 @@ static void createstatuswindow (void) power_width = (int)(42 * scaleX); fps_width = (int)(64 * scaleX); idle_width = (int)(64 * scaleX); + if (is_ppc_cpu()) + idle_width = 136; snd_width = (int)(72 * scaleX); joy_width = (int)(24 * scaleX); GetClientRect (hMainWnd, &rc); diff --git a/od-win32/win32gui.cpp b/od-win32/win32gui.cpp index 6d890f76..ccd39b84 100644 --- a/od-win32/win32gui.cpp +++ b/od-win32/win32gui.cpp @@ -91,6 +91,7 @@ #include "zarchive.h" #include "gfxboard.h" #include "win32_uaenet.h" +#include "ppc.h" #ifdef RETROPLATFORM #include "rp.h" #endif @@ -8173,8 +8174,8 @@ static INT_PTR CALLBACK MemoryDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LPARA SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm MK I")); SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm MK II")); SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm MK III")); - SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm PPC (NO PPC CPU!)")); - SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Blizzard PPC (NO PPC CPU!)")); + SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm PPC")); + SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Blizzard PPC")); SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Warp Engine A4000")); case WM_USER: @@ -17290,10 +17291,11 @@ void gui_fps (int fps, int idle, int color) gui_led (LED_SND, (gui_data.sndbuf_status > 1 || gui_data.sndbuf_status < 0) ? 0 : 1); } +#define LED_STRING_WIDTH 40 void gui_led (int led, int on) { WORD type; - static TCHAR drive_text[NUM_LEDS * 16]; + static TCHAR drive_text[NUM_LEDS * LED_STRING_WIDTH]; static TCHAR dfx[4][300]; TCHAR *ptr, *tt, *p; int pos = -1, j; @@ -17316,7 +17318,7 @@ void gui_led (int led, int on) tt = NULL; if (led >= LED_DF0 && led <= LED_DF3) { pos = 6 + (led - LED_DF0); - ptr = drive_text + pos * 16; + ptr = drive_text + pos * LED_STRING_WIDTH; if (gui_data.drive_disabled[led - 1]) _tcscpy (ptr, _T("")); else @@ -17339,17 +17341,17 @@ void gui_led (int led, int on) writing = 1; } else if (led == LED_POWER) { pos = 3; - ptr = _tcscpy (drive_text + pos * 16, _T("Power")); + ptr = _tcscpy(drive_text + pos * LED_STRING_WIDTH, _T("Power")); center = 1; } else if (led == LED_HD) { pos = 4; - ptr = _tcscpy (drive_text + pos * 16, _T("HD")); + ptr = _tcscpy(drive_text + pos * LED_STRING_WIDTH, _T("HD")); center = 1; if (on > 1) writing = 1; } else if (led == LED_CD) { pos = 5; - ptr = _tcscpy (drive_text + pos * 16, _T("CD")); + ptr = _tcscpy(drive_text + pos * LED_STRING_WIDTH, _T("CD")); center = 1; if (on >= 0) { if (on & LED_CD_AUDIO) @@ -17362,14 +17364,14 @@ void gui_led (int led, int on) double fps = (double)gui_data.fps / 10.0; extern double p96vblank; pos = 2; - ptr = drive_text + pos * 16; + ptr = drive_text + pos * LED_STRING_WIDTH; if (fps > 999.9) fps = 999.9; if (picasso_on) _stprintf (ptr, _T("%.1f [%.1f]"), p96vblank, fps); else _stprintf (ptr, _T("FPS: %.1f"), fps); - if (gui_data.cpu_halted) { + if (gui_data.cpu_halted > 0) { _stprintf (ptr, _T("HALT%d"), gui_data.cpu_halted); center = 1; } @@ -17380,15 +17382,36 @@ void gui_led (int led, int on) on = 1; } else if (led == LED_CPU) { pos = 1; - ptr = drive_text + pos * 16; - _stprintf (ptr, _T("CPU: %.0f%%"), (double)((gui_data.idle) / 10.0)); + ptr = drive_text + pos * LED_STRING_WIDTH; if (pause_emulation) on = 0; else on = 1; + if (is_ppc_cpu()) { + _tcscpy(ptr, _T("PPC: ")); + if (ppc_state == PPC_STATE_ACTIVE) + _tcscat(ptr, _T("RUN")); + else if (ppc_state == PPC_STATE_CRASH) + _tcscat(ptr, _T("CRASH")); + else if (ppc_state == PPC_STATE_SLEEP) + _tcscat(ptr, _T("SLEEP")); + else + _tcscat(ptr, _T("STOP")); + p = ptr + _tcslen(ptr); + if (gui_data.cpu_halted < 0) + _tcscpy(p, _T(" 68K: STOP")); + else + _stprintf(p, _T(" 68K: %.0f%%"), (double)((gui_data.idle) / 10.0)); + } else { + if (gui_data.cpu_halted < 0) { + _tcscpy(ptr, _T("STOP")); + } else { + _stprintf(ptr, _T("CPU: %.0f%%"), (double)((gui_data.idle) / 10.0)); + } + } } else if (led == LED_SND && gui_data.drive_disabled[3]) { pos = 0; - ptr = drive_text + pos * 16; + ptr = drive_text + pos * LED_STRING_WIDTH; if (gui_data.sndbuf_status < 3 && !pause_emulation) { _stprintf (ptr, _T("SND: %+.0f%%"), (double)((gui_data.sndbuf) / 10.0)); } else { @@ -17398,7 +17421,7 @@ void gui_led (int led, int on) } } else if (led == LED_MD) { pos = 6 + 3; - ptr = _tcscpy (drive_text + pos * 16, _T("NV")); + ptr = _tcscpy(drive_text + pos * LED_STRING_WIDTH, _T("NV")); } if (on < 0) diff --git a/od-win32/winuae_msvc11/winuae_msvc.vcxproj b/od-win32/winuae_msvc11/winuae_msvc.vcxproj index cc8eb08f..ddccd218 100644 --- a/od-win32/winuae_msvc11/winuae_msvc.vcxproj +++ b/od-win32/winuae_msvc11/winuae_msvc.vcxproj @@ -187,7 +187,7 @@ %(AdditionalOptions) Disabled - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;_DEBUG;WIN32_IE=0x0700;WIN32;_CRT_SECURE_NO_WARNINGS;D3D_DEBUG_INFO;%(PreprocessorDefinitions) false false @@ -255,7 +255,7 @@ %(AdditionalOptions) Disabled - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;_DEBUG;WIN32_IE=0x0700;WIN32;WIN64;_CRT_SECURE_NO_WARNINGS;D3D_DEBUG_INFO;%(PreprocessorDefinitions) Sync EnableFastChecks @@ -319,7 +319,7 @@ Speed true false - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;..\..\ppc\pearpc;:%(AdditionalIncludeDirectories) WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;%(PreprocessorDefinitions) true Sync @@ -397,7 +397,7 @@ Neither false false - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;_WIN32_IE=0x0700;WIN32;%(PreprocessorDefinitions) true Sync @@ -475,7 +475,7 @@ Speed true false - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;..\..\ppc\pearpc;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;WIN64;%(PreprocessorDefinitions) true Sync @@ -505,7 +505,7 @@ 0x0409 - ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;vfw32.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;portaudio_x64.lib;packet.lib;wpcap.lib;openal32.lib;libpng15.lib;lglcd.lib;wtsapi32.lib;enet_x64.lib;prowizard_x64.lib;lzmalib.lib;libFLAC_static.lib;avrt.lib;hid.lib;Iphlpapi.lib;luastatic.lib;libmpeg2_ff.lib;%(AdditionalDependencies) + ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;vfw32.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;portaudio_x64.lib;packet.lib;wpcap.lib;openal32.lib;libpng15.lib;lglcd.lib;wtsapi32.lib;enet_x64.lib;prowizard_x64.lib;lzmalib.lib;libFLAC_static.lib;avrt.lib;hid.lib;Iphlpapi.lib;luastatic.lib;libmpeg2_ff.lib;softfloat_x64.lib;%(AdditionalDependencies) NotSet $(OutDir)$(TargetName)$(TargetExt) true @@ -547,7 +547,7 @@ Speed true false - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;WIN64;%(PreprocessorDefinitions) true Sync @@ -618,7 +618,7 @@ Speed true true - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;%(PreprocessorDefinitions) true Sync @@ -693,7 +693,7 @@ Speed true true - ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;%(AdditionalIncludeDirectories) + ..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\slirp;..\..\ppc\pearpc;%(AdditionalIncludeDirectories) WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;WIN64;%(PreprocessorDefinitions) true Sync @@ -724,7 +724,7 @@ 0x0409 - ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;vfw32.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;portaudio_x64.lib;packet.lib;wpcap.lib;openal32.lib;libpng15.lib;lglcd.lib;wtsapi32.lib;enet_x64.lib;prowizard_x64.lib;lzmalib.lib;libFLAC_static.lib;avrt.lib;hid.lib;Iphlpapi.lib;luastatic.lib;libmpeg2_ff.lib;%(AdditionalDependencies) + ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;vfw32.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;portaudio_x64.lib;packet.lib;wpcap.lib;openal32.lib;libpng15.lib;lglcd.lib;wtsapi32.lib;enet_x64.lib;prowizard_x64.lib;lzmalib.lib;libFLAC_static.lib;avrt.lib;hid.lib;Iphlpapi.lib;luastatic.lib;libmpeg2_ff.lib;softfloat_x64.lib;%(AdditionalDependencies) NotSet $(OutDir)$(TargetName)$(TargetExt) true @@ -795,6 +795,7 @@ + @@ -806,6 +807,17 @@ + + + + + + + + + + + diff --git a/od-win32/winuae_msvc11/winuae_msvc.vcxproj.filters b/od-win32/winuae_msvc11/winuae_msvc.vcxproj.filters index 2d6d18cc..4aafcf84 100644 --- a/od-win32/winuae_msvc11/winuae_msvc.vcxproj.filters +++ b/od-win32/winuae_msvc11/winuae_msvc.vcxproj.filters @@ -53,6 +53,9 @@ {61d78a16-0513-4885-b23d-534829071ac0} + + {a238ed36-3d5f-4fd0-afd7-a34029119da7} + @@ -673,6 +676,42 @@ qemu + + ppc + + + ppc + + + common + + + ppc + + + ppc + + + ppc + + + ppc + + + ppc + + + ppc + + + ppc + + + ppc + + + ppc + diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt index c0c33595..9b104d17 100644 --- a/od-win32/winuaechangelog.txt +++ b/od-win32/winuaechangelog.txt @@ -18,6 +18,48 @@ Things that may happen in 2015: - restore only single input target to default. +Beta 9: + +- PearPC PPC emulator core added. Only because it was very easy to add, it may not be compatible enough. + (and it isn't, at least not fully compatible, at least it has some unimplemented instructions, some + programs or operating system surely won't work) +- PPC disassembler added to debugger ("dp", PPC mode is remembered, use "do" to switch back to m68k) +- Windowed mode status bar shows PPC state (if CyberStorm PPC or Blizzard PPC selected). Shows 4 possible states: + STOP (inactive), RUN (executing instructions), SLEEP (low power state, waiting for interrupt), CRASH + (CPU emulator detected something bad, like invalid instruction etc) +- BlizzardPPC memory GUI adjustment fixed. +- Fixed 68020/030 CE + fastest possible hang if program executed loop that didn't do any memory accesses. +- 68040/060 CINVx instruction was still disassembled strangely. +- Adjusted 68040/060 "cycle-exact" mode timing, also if data cache is enabled, emulate all data memory accesses as + immediate. (until data cache is emulated fully) +- CyberStorm MKII F0 ROM section of flash rom is now flashable. (third party mk2diag flash updater works) +- Blizzard PPC flash rom chip emulation now works correctly (was wrong mapping and wrong flash chip device code..) +- Added special JIT indirect CPU core that supports code execution from non-linear and/or aliased memory. Technically also + should allow to emulate A2091/A590 but it still crashes for some reason. (But at least now it executes some ROM code before + accessing invalid memory. A2091/A590 is perfect test case because it does not copy driver code from autoconfig ROM to RAM like + most other HD controller drivers do, code runs directly from ROM and same memory "bank" also has IO registers) +- Memory allocation source clean up. Can break nearly anything.. +- SCSI CD READ CD command didn't read audio tracks 2+. +- Entering debugger forze the emulator if m68k CPU was stopped with STOP instruction and all interrupts disabled. +- NCR53C770 emulation tweaks, fixes netbsd hang. Now it gets unexpected interrupt, no fix available yet. +- Version bumped to 2.9.0 + +PPC Notes: + +Only a proof of concept currently. +Automatically enabled when CyberStorm PPC or Blizzard PPC emulation is selected. +Only PearPC interpretive PPC emulation is currently supported. Speed is totally irrelevant at this point. +PPC emulator runs in separate thread, it requires special handling with PPC IO accesses, IO accesses are serialized and sent to m68k-side. +Plain memory accesses are direct. (This assumes M68K is still doing Amiga housekeeping duties and PPC is mainly used as a co-processor, +probably will cause huge performance hit if PPC does everything, for example when running PPC-only operating systems) +Should be fully m68k JIT compatible, at least in indirect mode. +Dual core CPU or better required. If you don't have one, you are not allowed to report anything, sorry. +PowerUP kernel does not work (hardware is not fully emulated). WarpOS appears to work. +Do not use BlizzardPPC, it has (currently incompatible) PowerUP in flash and it runs at boot. +Make sure CPU speed is fastest possible. PPC IO access serialization will be slowed down if m68k is waiting for +chipset. + + Beta 8: - When loading old config which has both cycle-exact and fastest possible enabled: disable fastest possible. diff --git a/qemuvga/lsi53c895a.cpp b/qemuvga/lsi53c895a.cpp index 348fbd2d..3dad3737 100644 --- a/qemuvga/lsi53c895a.cpp +++ b/qemuvga/lsi53c895a.cpp @@ -279,6 +279,8 @@ typedef struct { uint32_t csbc; uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ uint8_t sbr; + uint8_t chip_rev; + int last_level; /* Script ram is stored as 32-bit words in host byteorder. */ uint32_t script_ram[2048]; @@ -410,7 +412,6 @@ static void lsi_update_irq(LSIState *s) { PCIDevice *d = PCI_DEVICE(s); int level; - static int last_level; lsi_request *p; /* It's unclear whether the DIP/SIP bits should be cleared when the @@ -435,10 +436,10 @@ static void lsi_update_irq(LSIState *s) if (s->istat0 & LSI_ISTAT0_INTF) level = 1; - if (level != last_level) { + if (level != s->last_level) { DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n", level, s->dstat, s->sist1, s->sist0); - last_level = level; + s->last_level = level; } pci_set_irq(d, level); @@ -1557,7 +1558,7 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) case 0x18: /* CTEST0 */ return 0xff; case 0x19: /* CTEST1 */ - return 0; + return 0xf0; // dma fifo empty case 0x1a: /* CTEST2 */ tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM; if (s->istat0 & LSI_ISTAT0_SIGP) { @@ -1566,7 +1567,7 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) } return tmp; case 0x1b: /* CTEST3 */ - return s->ctest3; + return (s->ctest3 & (0x08 | 0x02 | 0x01)) | s->chip_rev; CASE_GET_REG32(temp, 0x1c) case 0x20: /* DFIFO */ return 0; @@ -1606,7 +1607,7 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) lsi_update_irq(s); return tmp; case 0x46: /* MACNTL */ - return 0x0f; + return 0x0f | s->chip_rev; case 0x47: /* GPCNTL0 */ return 0x0f; case 0x48: /* STIME0 */ @@ -1753,6 +1754,10 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) lsi_execute_script(s); } if (val & LSI_ISTAT0_SRST) { + if (s->last_level) + pci_set_irq(PCI_DEVICE(s), 0); + s->last_level = 0; + lsi_soft_reset(s); ;//qdev_reset_all(DEVICE(s)); } break; @@ -1998,6 +2003,7 @@ void lsi_scsi_reset(DeviceState *dev, void *privdata) lsi_soft_reset(s); s->bus.privdata = privdata; + s->chip_rev = 0x20; } void lsi_scsi_init(DeviceState *dev) diff --git a/statusline.cpp b/statusline.cpp index e20dd2c3..3d00cccc 100644 --- a/statusline.cpp +++ b/statusline.cpp @@ -170,12 +170,12 @@ void draw_status_line_single (uae_u8 *buf, int bpp, int y, int totalwidth, uae_u on_rgb = 0xcc0000; off_rgb = 0x000000; if (gui_data.cpu_halted) { - on_rgb = 0xcccc00; + on_rgb = gui_data.cpu_halted < 0 ? 0x444444 : 0xcccc00; idle = 0; on = 1; num1 = -1; num2 = 11; - num3 = gui_data.cpu_halted; + num3 = gui_data.cpu_halted < 0 ? 15 : gui_data.cpu_halted; am = 2; } else { num1 = idle / 100;