From 02475c94b93d56d979538e5b04f6460d261d3396 Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Wed, 30 Oct 2019 17:39:35 +0200 Subject: [PATCH] Validate 68010+ exception vector number and offset in stack frame. --- cputest/asm.S | 188 ++++++++++++++++++++++++++++++++++++++++++++++--- cputest/main.c | 36 +++++++--- 2 files changed, 204 insertions(+), 20 deletions(-) diff --git a/cputest/asm.S b/cputest/asm.S index d1833eb6..164d8c44 100644 --- a/cputest/asm.S +++ b/cputest/asm.S @@ -5,10 +5,10 @@ .globl _execute_test010 .globl _execute_test020 .globl _execute_testfpu - .globl _exception010 - .globl _exception020 - .globl _exceptionfpu .globl _exceptiontable000 + .globl _exceptiontable010 + .globl _exceptiontable020 + .globl _exceptiontablefpu .globl _setvbr .globl _setcpu .globl _flushcache @@ -26,7 +26,8 @@ S_MSP = S_SSP+4 S_PC = S_MSP+4 S_SR = S_PC+4 S_EXC = S_SR+4 -S_EXCFRAME = S_EXC+4 +S_EXC010 = S_EXC+4 +S_EXCFRAME = S_EXC010+4 S_FPU = S_EXCFRAME+4 S_FPIAR = S_FPU+8*12 S_FPCR = S_FPIAR+4 @@ -294,20 +295,75 @@ exception: movem.l (sp)+,d1-d7/a0-a6 rts -_exception010: +_exceptiontable010: + bsr.s exception010 | 2 + bsr.s exception010 | 3 + bsr.s exception010 | 4 + bsr.s exception010 | 5 + bsr.s exception010 | 6 + bsr.s exception010 | 7 + bsr.s exception010 | 8 + bsr.s exception010 | 9 + bsr.s exception010 | 10 + bsr.s exception010 | 11 + bsr.s exception010 | 12 + bsr.s exception010 | 13 + bsr.s exception010 | 14 + bsr.s exception010 | 15 + bsr.s exception010 | 16 + bsr.s exception010 | 17 + bsr.s exception010 | 18 + bsr.s exception010 | 19 + bsr.s exception010 | 20 + bsr.s exception010 | 21 + bsr.s exception010 | 22 + bsr.s exception010 | 23 + bsr.s exception010 | 24 + bsr.s exception010 | 25 + bsr.s exception010 | 26 + bsr.s exception010 | 27 + bsr.s exception010 | 28 + bsr.s exception010 | 29 + bsr.s exception010 | 30 + bsr.s exception010 | 31 + bsr.s exception010 | 32 + bsr.s exception010 | 33 + bsr.s exception010 | 34 + bsr.s exception010 | 35 + bsr.s exception010 | 36 + bsr.s exception010 | 37 + bsr.s exception010 | 38 + bsr.s exception010 | 30 + bsr.s exception010 | 40 + bsr.s exception010 | 41 + bsr.s exception010 | 42 + bsr.s exception010 | 43 + bsr.s exception010 | 44 + bsr.s exception010 | 45 + bsr.s exception010 | 46 + bsr.s exception010 | 47 + nop +exception010: move.w #0,ACTIVITYREG move.l a0,-(sp) move.l datapointer(pc),a0 movem.l d0-d7/a0-a6,(a0) move.l (sp)+,8*4(a0) + move.l (sp)+,d0 + lea _exceptiontable010(pc),a1 + sub.l a1,d0 + lsr.w #1,d0 + addq.w #1,d0 + move.w d0,S_EXC+2(a0) + move.l sp,S_EXCFRAME(a0) move.w (sp)+,S_SR+2(a0) move.l (sp)+,S_PC(a0) move.w (sp),d0 and.w #0xfff,d0 lsr.w #2,d0 - move.w d0,S_EXC+2(a0) + move.w d0,S_EXC010+2(a0) move.l USP,a1 move.l a1,S_AREG+7*4(a0) @@ -317,21 +373,76 @@ _exception010: move.w (sp)+,sr movem.l (sp)+,d1-d7/a0-a6 rts - -_exception020: + +_exceptiontable020: + bsr.s exception020 | 2 + bsr.s exception020 | 3 + bsr.s exception020 | 4 + bsr.s exception020 | 5 + bsr.s exception020 | 6 + bsr.s exception020 | 7 + bsr.s exception020 | 8 + bsr.s exception020 | 9 + bsr.s exception020 | 10 + bsr.s exception020 | 11 + bsr.s exception020 | 12 + bsr.s exception020 | 13 + bsr.s exception020 | 14 + bsr.s exception020 | 15 + bsr.s exception020 | 16 + bsr.s exception020 | 17 + bsr.s exception020 | 18 + bsr.s exception020 | 19 + bsr.s exception020 | 20 + bsr.s exception020 | 21 + bsr.s exception020 | 22 + bsr.s exception020 | 23 + bsr.s exception020 | 24 + bsr.s exception020 | 25 + bsr.s exception020 | 26 + bsr.s exception020 | 27 + bsr.s exception020 | 28 + bsr.s exception020 | 29 + bsr.s exception020 | 30 + bsr.s exception020 | 31 + bsr.s exception020 | 32 + bsr.s exception020 | 33 + bsr.s exception020 | 34 + bsr.s exception020 | 35 + bsr.s exception020 | 36 + bsr.s exception020 | 37 + bsr.s exception020 | 38 + bsr.s exception020 | 30 + bsr.s exception020 | 40 + bsr.s exception020 | 41 + bsr.s exception020 | 42 + bsr.s exception020 | 43 + bsr.s exception020 | 44 + bsr.s exception020 | 45 + bsr.s exception020 | 46 + bsr.s exception020 | 47 + nop +exception020: move.w #0,ACTIVITYREG move.l a0,-(sp) move.l datapointer(pc),a0 movem.l d0-d7/a0-a6,(a0) move.l (sp)+,8*4(a0) + move.l (sp)+,d0 + lea _exceptiontable020(pc),a1 + sub.l a1,d0 + lsr.w #1,d0 + addq.w #1,d0 + move.w d0,S_EXC+2(a0) + move.l sp,S_EXCFRAME(a0) move.w (sp)+,S_SR+2(a0) move.l (sp)+,S_PC(a0) move.w (sp),d0 and.w #0xfff,d0 lsr.w #2,d0 - move.w d0,S_EXC+2(a0) + move.w d0,S_EXC010+2(a0) _msp_address3: movec MSP,a1 @@ -349,20 +460,75 @@ _msp_address3: movem.l (sp)+,d1-d7/a0-a6 rts -_exceptionfpu: +_exceptiontablefpu: + bsr.s exceptionfpu | 2 + bsr.s exceptionfpu | 3 + bsr.s exceptionfpu | 4 + bsr.s exceptionfpu | 5 + bsr.s exceptionfpu | 6 + bsr.s exceptionfpu | 7 + bsr.s exceptionfpu | 8 + bsr.s exceptionfpu | 9 + bsr.s exceptionfpu | 10 + bsr.s exceptionfpu | 11 + bsr.s exceptionfpu | 12 + bsr.s exceptionfpu | 13 + bsr.s exceptionfpu | 14 + bsr.s exceptionfpu | 15 + bsr.s exceptionfpu | 16 + bsr.s exceptionfpu | 17 + bsr.s exceptionfpu | 18 + bsr.s exceptionfpu | 19 + bsr.s exceptionfpu | 20 + bsr.s exceptionfpu | 21 + bsr.s exceptionfpu | 22 + bsr.s exceptionfpu | 23 + bsr.s exceptionfpu | 24 + bsr.s exceptionfpu | 25 + bsr.s exceptionfpu | 26 + bsr.s exceptionfpu | 27 + bsr.s exceptionfpu | 28 + bsr.s exceptionfpu | 29 + bsr.s exceptionfpu | 30 + bsr.s exceptionfpu | 31 + bsr.s exceptionfpu | 32 + bsr.s exceptionfpu | 33 + bsr.s exceptionfpu | 34 + bsr.s exceptionfpu | 35 + bsr.s exceptionfpu | 36 + bsr.s exceptionfpu | 37 + bsr.s exceptionfpu | 38 + bsr.s exceptionfpu | 30 + bsr.s exceptionfpu | 40 + bsr.s exceptionfpu | 41 + bsr.s exceptionfpu | 42 + bsr.s exceptionfpu | 43 + bsr.s exceptionfpu | 44 + bsr.s exceptionfpu | 45 + bsr.s exceptionfpu | 46 + bsr.s exceptionfpu | 47 + nop +exceptionfpu: move.w #0,ACTIVITYREG move.l a0,-(sp) move.l datapointer(pc),a0 movem.l d0-d7/a0-a6,(a0) move.l (sp)+,8*4(a0) + move.l (sp)+,d0 + lea _exceptiontable020(pc),a1 + sub.l a1,d0 + lsr.w #1,d0 + addq.w #1,d0 + move.w d0,S_EXC+2(a0) + move.l sp,S_EXCFRAME(a0) move.w (sp)+,S_SR+2(a0) move.l (sp)+,S_PC(a0) move.w (sp),d0 and.w #0xfff,d0 lsr.w #2,d0 - move.w d0,S_EXC+2(a0) + move.w d0,S_EXC010+2(a0) _msp_address4: movec MSP,a1 diff --git a/cputest/main.c b/cputest/main.c index 075a4715..41a5f82a 100644 --- a/cputest/main.c +++ b/cputest/main.c @@ -41,7 +41,7 @@ struct registers uae_u32 msp; uae_u32 pc; uae_u32 sr; - uae_u32 exc; + uae_u32 exc, exc010; uae_u32 excframe; struct fpureg fpuregs[8]; uae_u32 fpiar, fpcr, fpsr; @@ -145,7 +145,7 @@ static uae_u32 tosuper(uae_u32 v) static void touser(uae_u32 v) { } -static uae_u32 exceptiontable000, exception010, exception020, exceptionfpu; +static uae_u32 exceptiontable000, exceptiontable010, exceptiontable020, exceptiontablefpu; static uae_u32 testexit(void) { return 0; @@ -180,7 +180,7 @@ extern void execute_test020(struct registers *); extern void execute_testfpu(struct registers *); extern uae_u32 tosuper(uae_u32); extern void touser(uae_u32); -extern uae_u32 exceptiontable000, exception010, exception020, exceptionfpu; +extern uae_u32 exceptiontable000, exceptiontable010, exceptiontable020, exceptiontablefpu; extern uae_u32 testexit(void); extern uae_u32 setvbr(uae_u32); extern uae_u32 get_cpu_model(void); @@ -333,8 +333,14 @@ static void start_test(void) } } else { oldvbr = setvbr((uae_u32)vbr); - for (int i = 0; i < 256; i++) { - vbr[i] = fpu_model ? (uae_u32)(&exceptionfpu) : (cpu_lvl == 1 ? (uae_u32)(&exception010) : (uae_u32)(&exception020)); + for (int i = 2; i < 48; i++) { + if (fpu_model) { + vbr[i] = (uae_u32)(((uae_u32)&exceptiontablefpu) + (i - 2) * 2); + } else if (cpu_lvl == 1) { + vbr[i] = (uae_u32)(((uae_u32)&exceptiontable010) + (i - 2) * 2); + } else { + vbr[i] = (uae_u32)(((uae_u32)&exceptiontable020) + (i - 2) * 2); + } if (i >= 2 && i < 12) { error_vectors[i - 2] = vbr[i]; } @@ -1242,6 +1248,7 @@ static uae_u8 *validate_test(uae_u8 *p, int ignore_errors, int ignore_sr) if (v & CT_END) { exc = v & CT_EXCEPTION_MASK; int cpuexc = test_regs.exc & 65535; + int cpuexc010 = test_regs.exc010 & 65535; p++; if ((v & CT_END_INIT) == CT_END_INIT) { end_test(); @@ -1251,10 +1258,21 @@ static uae_u8 *validate_test(uae_u8 *p, int ignore_errors, int ignore_sr) } if (exc == 1) { end_test(); - printf("Invalid exception ID %02x\n", exc); + printf("Invalid exception %02x\n", exc); endinfo(); exit(0); } + if (cpu_lvl > 0 && exc > 0 && cpuexc010 != cpuexc) { + addinfo(); + if (dooutput) { + sprintf(outbp, "Exception: vector number does not match vector offset! (%d <> %d)\n", exc, cpuexc010); + experr = 1; + outbp += strlen(outbp); + errors++; + } + break; + } + if (ignore_errors) { if (exc) { p = validate_exception(&test_regs, p, exc, exc == cpuexc, &experr); @@ -1277,11 +1295,11 @@ static uae_u8 *validate_test(uae_u8 *p, int ignore_errors, int ignore_sr) addinfo(); if (dooutput) { if (cpuexc == 4 && last_registers.pc == test_regs.pc) { - sprintf(outbp, "Exception ID: expected %d but got no exception.\n", exc); + sprintf(outbp, "Exception: expected %d but got no exception.\n", exc); } else if (cpuexc == 4) { - sprintf(outbp, "Exception ID: expected %d but got %d (or no exception)\n", exc, cpuexc); + sprintf(outbp, "Exception: expected %d but got %d (or no exception)\n", exc, cpuexc); } else { - sprintf(outbp, "Exception ID: expected %d but got %d\n", exc, cpuexc); + sprintf(outbp, "Exception: expected %d but got %d\n", exc, cpuexc); } experr = 1; } -- 2.47.3