From 0782c297dba5dcba6c0260d68b8a2d8430ac3f37 Mon Sep 17 00:00:00 2001 From: Aleksey Demakov Date: Sun, 2 Jul 2006 23:01:24 +0000 Subject: [PATCH] more native x86 instruction selection rules --- ChangeLog | 10 ++++ jit/jit-rules-x86.c | 6 ++ jit/jit-rules-x86.ins | 135 +++++++++++++++++++++++++++++++++++------- 3 files changed, 131 insertions(+), 20 deletions(-) diff --git a/ChangeLog b/ChangeLog index 2302e70..21e1bfc 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,13 @@ +2006-07-03 Aleksey Demakov + + * jit/jit-rules-x86.ins: add JIT_OP_LOW_WORD, JIT_OP_EXPAND_INT, + JIT_OP_EXPAND_UINT, JIT_OP_INT_TO_NFLOAT, JIT_OP_UINT_TO_NFLOAT, + JIT_OP_LONG_TO_NFLOAT, JIT_OP_ULONG_TO_NFLOAT and rewrite + JIT_OP_TRUNC_SBYTE, JIT_OP_TRUNC_UBYTE, JIT_OP_LOAD_PC rules. + + * jit/jit-rules-x86.c (_jit_opcode_is_supported): include .inc file + instead of .slc if USE_NEW_REG_ALLOC is defined. + 2006-06-28 Aleksey Demakov * tools/gen-rules-parser.y (gensel_output_code): diff --git a/jit/jit-rules-x86.c b/jit/jit-rules-x86.c index 5cc9631..65bfea3 100644 --- a/jit/jit-rules-x86.c +++ b/jit/jit-rules-x86.c @@ -187,7 +187,11 @@ int _jit_opcode_is_supported(int opcode) switch(opcode) { #define JIT_INCLUDE_SUPPORTED +#if USE_NEW_REG_ALLOC + #include "jit-rules-x86.inc" +#else #include "jit-rules-x86.slc" +#endif #undef JIT_INCLUDE_SUPPORTED } return 0; @@ -1247,6 +1251,7 @@ void _jit_gen_fix_value(jit_value_t value) } } +#if !USE_NEW_REG_ALLOC /* * Widen a byte register. */ @@ -1265,6 +1270,7 @@ static unsigned char *widen_byte(unsigned char *inst, int reg, int isSigned) } return inst; } +#endif /* * Shift the contents of a register. diff --git a/jit/jit-rules-x86.ins b/jit/jit-rules-x86.ins index bf98fdc..d6d73cb 100644 --- a/jit/jit-rules-x86.ins +++ b/jit/jit-rules-x86.ins @@ -23,13 +23,13 @@ */ JIT_OP_TRUNC_SBYTE: unary - [reg] -> { - inst = widen_byte(inst, $1, 1); + [reg("eax"|"ecx"|"edx"|"ebx")] -> { + x86_widen_reg(inst, $1, $1, 1, 0); } JIT_OP_TRUNC_UBYTE: unary - [reg] -> { - inst = widen_byte(inst, $1, 0); + [reg("eax"|"ecx"|"edx"|"ebx")] -> { + x86_widen_reg(inst, $1, $1, 0, 0); } JIT_OP_TRUNC_SHORT: unary @@ -101,17 +101,121 @@ JIT_OP_CHECK_INT, JIT_OP_CHECK_UINT: unary, more_space inst = throw_builtin(inst, func, JIT_RESULT_OVERFLOW); x86_patch(patch1, inst); } + +JIT_OP_LOW_WORD: + [=reg, imm] -> { + jit_uint value = ((jit_uint *)($2))[0]; + x86_mov_reg_imm(inst, $1, value); + } + [=reg, local] -> { + x86_mov_reg_membase(inst, $1, X86_EBP, $2, 4); + } + [=reg, lreg] -> { + if($1 != $2) + { + x86_mov_reg_reg(inst, $1, $2, 4); + } + } + +JIT_OP_EXPAND_INT: + [=lreg, imm] -> { + x86_mov_reg_imm(inst, $1, $2); + x86_mov_reg_reg(inst, %1, $1, 4); + x86_shift_reg_imm(inst, X86_SAR, %1, 31); + } + [=lreg, local] -> { + x86_mov_reg_membase(inst, $1, X86_EBP, $2, 4); + x86_mov_reg_reg(inst, %1, $1, 4); + x86_shift_reg_imm(inst, X86_SAR, %1, 31); + } + [=lreg, reg] -> { + if($1 != $2) + { + x86_mov_reg_reg(inst, $1, $2, 4); + } + x86_mov_reg_reg(inst, %1, $1, 4); + x86_shift_reg_imm(inst, X86_SAR, %1, 31); + } -JIT_OP_NFLOAT_TO_FLOAT32: unary, stack - [freg] -> { +JIT_OP_EXPAND_UINT: + [=lreg, imm] -> { + x86_mov_reg_imm(inst, $1, $2); + x86_clear_reg(inst, %1); + } + [=lreg, local] -> { + x86_mov_reg_membase(inst, $1, X86_EBP, $2, 4); + x86_clear_reg(inst, %1); + } + [=lreg, reg] -> { + if($1 != $2) + { + x86_mov_reg_reg(inst, $1, $2, 4); + } + x86_clear_reg(inst, %1); + } + +JIT_OP_INT_TO_NFLOAT: + [=freg, local] -> { + x86_fild_membase(inst, X86_EBP, $2, 0); + } + [=freg, reg] -> { + x86_push_reg(inst, $2); + x86_fild_membase(inst, X86_ESP, 0, 0); + x86_alu_reg_imm(inst, X86_ADD, X86_ESP, sizeof(jit_nint)); + } + +JIT_OP_UINT_TO_NFLOAT: + [=freg, reg, scratch("?")] -> { + x86_clear_reg(inst, $3); + x86_push_reg(inst, $3); + x86_push_reg(inst, $2); + x86_fild_membase(inst, X86_ESP, 0, 1); + x86_alu_reg_imm(inst, X86_ADD, X86_ESP, sizeof(jit_long)); + } + +JIT_OP_LONG_TO_NFLOAT: + [=freg, local] -> { + x86_fild_membase(inst, X86_EBP, $2, 1); + } + [=freg, lreg] -> { + x86_push_reg(inst, %2); + x86_push_reg(inst, $2); + x86_fild_membase(inst, X86_ESP, 0, 1); + x86_alu_reg_imm(inst, X86_ADD, X86_ESP, sizeof(jit_long)); + } + +JIT_OP_ULONG_TO_NFLOAT: more_space + [=freg, lreg] -> { + /* TODO: review wrt relocation for elf pre-compilation */ + static float f2pow64; + static int inited; + if(!inited) + { + f2pow64 = jit_float32_pow(2.0, 64); + inited = 1; + } + unsigned char *patch; + x86_push_reg(inst, %2); + x86_push_reg(inst, $2); + x86_fild_membase(inst, X86_ESP, 0, 1); + x86_alu_reg_imm(inst, X86_ADD, X86_ESP, sizeof(jit_long)); + x86_test_reg_reg(inst, %2, %2); + patch = inst; + x86_branch8(inst, X86_CC_NS, 0, 1); + x86_fp_op_mem(inst, X86_FADD, &f2pow64, 0); + x86_patch(patch, inst); + } + +JIT_OP_NFLOAT_TO_FLOAT32: stack + [=freg, freg] -> { x86_alu_reg_imm(inst, X86_SUB, X86_ESP, sizeof(void *)); x86_fst_membase(inst, X86_ESP, 0, 0, 1); x86_fld_membase(inst, X86_ESP, 0, 0); x86_alu_reg_imm(inst, X86_ADD, X86_ESP, sizeof(void *)); } -JIT_OP_NFLOAT_TO_FLOAT64: unary, stack - [freg] -> { +JIT_OP_NFLOAT_TO_FLOAT64: stack + [=freg, freg] -> { x86_alu_reg_imm(inst, X86_SUB, X86_ESP, sizeof(jit_float64)); x86_fst_membase(inst, X86_ESP, 0, 1, 1); x86_fld_membase(inst, X86_ESP, 0, 1); @@ -1399,19 +1503,10 @@ JIT_OP_THROW: unary_branch JIT_OP_RETHROW: manual [] -> { /* Not used in native code back ends */ } -JIT_OP_LOAD_PC: manual - [] -> { - unsigned char *inst; - int reg = _jit_regs_dest_value(gen, insn->dest); - inst = gen->posn.ptr; - if(!jit_cache_check_for_n(&(gen->posn), 32)) - { - jit_cache_mark_full(&(gen->posn)); - return; - } +JIT_OP_LOAD_PC: + [=reg] -> { x86_call_imm(inst, 0); - x86_pop_reg(inst, _jit_reg_info[reg].cpu_reg); - gen->posn.ptr = inst; + x86_pop_reg(inst, $1); } JIT_OP_LOAD_EXCEPTION_PC: manual -- 2.47.3