From 181d9265a168ef8ba4e8753b778d397371c16543 Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Sun, 18 Sep 2022 16:50:32 +0300 Subject: [PATCH] Power up chipram and slow ram memory pattern is now configurable. Updated to match different chipsets. --- cfgfile.cpp | 3 ++ custom.cpp | 4 ++ include/options.h | 1 + memory.cpp | 95 +++++++++++++++++------------------ od-win32/resources/resource.h | 1 + od-win32/resources/winuae.rc | 1 + od-win32/win32gui.cpp | 3 ++ 7 files changed, 60 insertions(+), 48 deletions(-) diff --git a/cfgfile.cpp b/cfgfile.cpp index a7b69a8d..b3b58bed 100644 --- a/cfgfile.cpp +++ b/cfgfile.cpp @@ -2555,6 +2555,7 @@ void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type) cfgfile_dwrite_str(f, _T("ciaa_type"), ciatype[p->cs_ciatype[0]]); cfgfile_dwrite_str(f, _T("ciab_type"), ciatype[p->cs_ciatype[1]]); cfgfile_dwrite_str(f, _T("unmapped_address_space"), unmapped[p->cs_unmapped_space]); + cfgfile_dwrite_bool(f, _T("memory_pattern"), p->cs_memorypatternfill); cfgfile_dwrite(f, _T("keyboard_handshake"), _T("%d"), currprefs.cs_kbhandshake); cfgfile_dwrite(f, _T("chipset_hacks"), _T("0x%x"), p->cs_hacks); cfgfile_dwrite(f, _T("eclockphase"), _T("%d"), p->cs_eclockphase); @@ -5687,6 +5688,7 @@ static int cfgfile_parse_hardware (struct uae_prefs *p, const TCHAR *option, TCH || cfgfile_strval (option, value, _T("serial_translate"), &p->serial_crlf, serialcrlf, 0) || cfgfile_strval(option, value, _T("hvcsync"), &p->cs_hvcsync, hvcsync, 0) || cfgfile_strval(option, value, _T("unmapped_address_space"), &p->cs_unmapped_space, unmapped, 0) + || cfgfile_yesno(option, value, _T("memory_pattern"), &p->cs_memorypatternfill) || cfgfile_strval(option, value, _T("ciaa_type"), &p->cs_ciatype[0], ciatype, 0) || cfgfile_strval(option, value, _T("ciab_type"), &p->cs_ciatype[1], ciatype, 0) || cfgfile_strboolval (option, value, _T("comp_flushmode"), &p->comp_hardflush, flushmode, 0) @@ -8079,6 +8081,7 @@ void default_prefs (struct uae_prefs *p, bool reset, int type) p->cs_hvcsync = false; p->cs_ciatype[0] = 0; p->cs_ciatype[1] = 0; + p->cs_memorypatternfill = true; for (int i = APMODE_NATIVE; i <= APMODE_RTG; i++) { struct gfx_filterdata *f = &p->gf[i]; diff --git a/custom.cpp b/custom.cpp index de21e723..3867181a 100644 --- a/custom.cpp +++ b/custom.cpp @@ -14582,6 +14582,8 @@ uae_u8 *restore_custom_extra(uae_u8 *src) currprefs.cs_ciatype[0] = changed_prefs.cs_ciatype[0] = RBB; currprefs.cs_ciatype[1] = changed_prefs.cs_ciatype[1] = RBB; + currprefs.cs_memorypatternfill = changed_prefs.cs_memorypatternfill = RBB; + return src; } @@ -14641,6 +14643,7 @@ uae_u8 *save_custom_extra(size_t *len, uae_u8 *dstptr) SB(currprefs.cs_romisslow ? 1 : 0); SB(currprefs.cs_ciatype[0]); SB(currprefs.cs_ciatype[1]); + SB(currprefs.cs_memorypatternfill); *len = dst - dstbak; return dstbak; @@ -14782,6 +14785,7 @@ void check_prefs_changed_custom(void) currprefs.cs_eclocksync = changed_prefs.cs_eclocksync; currprefs.cs_ciatype[0] = changed_prefs.cs_ciatype[0]; currprefs.cs_ciatype[1] = changed_prefs.cs_ciatype[1]; + currprefs.cs_memorypatternfill = changed_prefs.cs_memorypatternfill; if (currprefs.chipset_mask != changed_prefs.chipset_mask || currprefs.cs_dipagnus != changed_prefs.cs_dipagnus || diff --git a/include/options.h b/include/options.h index 5cad8d6c..ac5b2d55 100644 --- a/include/options.h +++ b/include/options.h @@ -697,6 +697,7 @@ struct uae_prefs { int cs_hvcsync; int cs_eclockphase; int cs_eclocksync; + bool cs_memorypatternfill; struct boardromconfig expansionboard[MAX_EXPANSION_BOARDS]; diff --git a/memory.cpp b/memory.cpp index 601cb88a..9bec083b 100644 --- a/memory.cpp +++ b/memory.cpp @@ -2596,64 +2596,63 @@ void map_overlay (int chip) m68k_setpc_normal (m68k_getpc ()); } -void memory_clear (void) -{ - mem_hardreset = 0; - if (savestate_state == STATE_RESTORE) - return; - - // Set a default pattern for uninitialized memory after hard reset. - // 0:even 1:odd on columns for even rows, - // 1:even 0:odd on columns for odd rows. - if (chipmem_bank.baseaddr) { - if (aga_mode) { - uae_u32 fillval = 0; - for (int fillbank = 0; fillbank < chipmem_bank.allocated_size / 2048; fillbank++) { - for (int fillrow = fillbank * 2048; fillrow < (fillbank + 1) * 2048; fillrow += 4) { - // Chip emulated: NEC PD42S4260 (A1200 R1). Spec says 512x512x16. - *((uae_u32*)(chipmem_bank.baseaddr + fillrow)) = fillval; +// Set a default pattern for uninitialized memory after hard reset. +// 0:even 1:odd on columns for even rows, +// 1:even 0:odd on columns for odd rows. +static void fillpattern(addrbank *ab) +{ + if (currprefs.cs_memorypatternfill && aga_mode) { + uae_u32 fillval = 0; + for (int fillbank = 0; fillbank < ab->allocated_size / 2048; fillbank++) { + fillval = ~fillval; + for (int fillrow = fillbank * 2048; fillrow < (fillbank + 1) * 2048; fillrow += 4) { + // Chip emulated: NEC PD42S4260 (A1200 R1). Spec says 512x512x16. + *((uae_u32 *)(ab->baseaddr + fillrow)) = fillval; + if ((fillrow & 7) == 4) { fillval = ~fillval; } - fillval = ~fillval; } - } else { - uae_u16 fillval = 0; - for (int fillbank = 0; fillbank < chipmem_bank.allocated_size / 1024; fillbank++) { - for (int fillrow = fillbank * 1024; fillrow < (fillbank + 1) * 1024; fillrow += 2) { - // Chip emulated: Generic 4256. Should apply to both 512x512x1 and 512x512x4. - *((uae_u16*)(chipmem_bank.baseaddr + fillrow)) = fillval; + } + } else if (currprefs.cs_memorypatternfill && (currprefs.chipset_mask & CSMASK_ECS_AGNUS)) { + uae_u32 fillval = 0; + for (int fillbank = 0; fillbank < ab->allocated_size / 1024; fillbank++) { + fillval = ~fillval; + for (int fillrow = fillbank * 1024; fillrow < (fillbank + 1) * 1024; fillrow += 4) { + // Chip emulated: Generic 4256. 4 * 512x4. + *((uae_u32 *)(ab->baseaddr + fillrow)) = fillval; + if ((fillrow & 7) == 0) { fillval = ~fillval; } - fillval = ~fillval; } } + } else if (currprefs.cs_memorypatternfill) { + // OCS Agnus has swapped row and column compared to ECS and AGA. + uae_u16 fillval = 0; + for (int fillbank = 0; fillbank < ab->allocated_size / 256; fillbank++) { + fillval = ~fillval; + for (int fillrow = 0; fillrow < 256; fillrow += 2) { + // Chip emulated: Generic 4256. 16 * 512x1. + *((uae_u16 *)(ab->baseaddr + fillbank * 256 + fillrow)) = fillval; + } + } + } else { + memset(ab->baseaddr, 0, ab->allocated_size); + } +} + +void memory_clear (void) +{ + mem_hardreset = 0; + if (savestate_state == STATE_RESTORE) + return; + + if (chipmem_bank.baseaddr) { + fillpattern(&chipmem_bank); } if (bogomem_bank.baseaddr) { - // NOTE: At reset, WinUAE maps "slow" memory to fast before later re-assigning to chip. - if (ce_banktype[0xC0] == CE_MEMBANK_FAST32) { - uae_u32 fillval = 0; - for (int fillbank = 0; fillbank < bogomem_bank.allocated_size / 2048; fillbank++) { - for (int fillrow = fillbank * 2048; fillrow < (fillbank + 1) * 2048; fillrow += 4) { - // Chip emulated: 512x512x16 (A1200 R1) - *((uae_u32*)(bogomem_bank.baseaddr + fillrow)) = fillval; - fillval = ~fillval; - } - fillval = ~fillval; - } - } else if (ce_banktype[0xC0] == CE_MEMBANK_FAST16) { - uae_u16 fillval = 0; - for (int fillbank = 0; fillbank < bogomem_bank.allocated_size / 1024; fillbank++) { - for (int fillrow = fillbank * 1024; fillrow < (fillbank + 1) * 1024; fillrow += 2) { - // Chip emulated: Generic 4256 - *((uae_u16*)(bogomem_bank.baseaddr + fillrow)) = fillval; - fillval = ~fillval; - } - fillval = ~fillval; - } - } else { - memset(bogomem_bank.baseaddr, 0, bogomem_bank.allocated_size); - } + // TODO: slow RAM can have 16x chips even if Agnus is ECS. + fillpattern(&bogomem_bank); } if (mem25bit_bank.baseaddr) diff --git a/od-win32/resources/resource.h b/od-win32/resources/resource.h index 9f0697f0..68204bb0 100644 --- a/od-win32/resources/resource.h +++ b/od-win32/resources/resource.h @@ -1156,6 +1156,7 @@ #define IDC_DBG_MEMUPFAST 1760 #define IDC_CS_CIA 1760 #define IDC_DA_RESET 1761 +#define IDC_CS_MEMORYPATTERN 1761 #define IDC_DBG_STATUS 1762 #define IDC_DBG_BRKPTS 1763 #define IDC_DBG_MCUSTOM 1764 diff --git a/od-win32/resources/winuae.rc b/od-win32/resources/winuae.rc index c036861d..8e1cf7d1 100644 --- a/od-win32/resources/winuae.rc +++ b/od-win32/resources/winuae.rc @@ -855,6 +855,7 @@ BEGIN EDITTEXT IDC_CS_DENISEREV,311,298,45,13,ES_AUTOHSCROLL COMBOBOX IDC_CS_CIASYNC,313,212,71,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP RTEXT "CIA E-Clock Sync",IDC_STATIC,206,215,101,9 + CONTROL "Power up memory pattern",IDC_CS_MEMORYPATTERN,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,197,125,12 END IDD_AVIOUTPUT DIALOGEX 0, 0, 396, 316 diff --git a/od-win32/win32gui.cpp b/od-win32/win32gui.cpp index 680a05e5..4c06e15a 100644 --- a/od-win32/win32gui.cpp +++ b/od-win32/win32gui.cpp @@ -9331,6 +9331,7 @@ static void values_to_chipsetdlg2 (HWND hDlg) CheckDlgButton(hDlg, IDC_CS_TOSHIBAGARY, workprefs.cs_toshibagary); CheckDlgButton(hDlg, IDC_CS_ROMISSLOW, workprefs.cs_romisslow); CheckDlgButton(hDlg, IDC_CS_CIA, workprefs.cs_ciatype[0]); + CheckDlgButton(hDlg, IDC_CS_MEMORYPATTERN, workprefs.cs_memorypatternfill); xSendDlgItemMessage(hDlg, IDC_CS_UNMAPPED, CB_SETCURSEL, workprefs.cs_unmapped_space, 0); xSendDlgItemMessage(hDlg, IDC_CS_CIASYNC, CB_SETCURSEL, workprefs.cs_eclocksync, 0); txt[0] = 0; @@ -9424,6 +9425,7 @@ static void values_from_chipsetdlg2 (HWND hDlg, UINT msg, WPARAM wParam, LPARAM workprefs.cs_toshibagary = ischecked(hDlg, IDC_CS_TOSHIBAGARY); workprefs.cs_romisslow = ischecked(hDlg, IDC_CS_ROMISSLOW); workprefs.cs_ciatype[0] = workprefs.cs_ciatype[1] = ischecked(hDlg, IDC_CS_CIA); + workprefs.cs_memorypatternfill = ischecked(hDlg, IDC_CS_MEMORYPATTERN); int val = xSendDlgItemMessage(hDlg, IDC_CS_UNMAPPED, CB_GETCURSEL, 0, 0L); if (val != CB_ERR) @@ -9521,6 +9523,7 @@ static void enable_for_chipsetdlg2 (HWND hDlg) ew(hDlg, IDC_CS_UNMAPPED, e); ew(hDlg, IDC_CS_CIASYNC, e); ew(hDlg, IDC_CS_CIA, e); + ew(hDlg, IDC_CS_MEMORYPATTERN, e); } static INT_PTR CALLBACK ChipsetDlgProc2 (HWND hDlg, UINT msg, WPARAM wParam, LPARAM lParam) -- 2.47.3