From 2dfd5691a7c206b97e49332cdf10e734336c583e Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Thu, 18 Aug 2022 21:23:51 +0300 Subject: [PATCH] Save also MSM6242B RTC model control registers to RTC file. --- cia.cpp | 28 ++++++++++++++-------------- rtc.cpp | 42 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 50 insertions(+), 20 deletions(-) diff --git a/cia.cpp b/cia.cpp index d7efa40e..9854e6ec 100644 --- a/cia.cpp +++ b/cia.cpp @@ -2656,20 +2656,20 @@ void rtc_hardreset(void) cfgfile_resolve_path_out_load(currprefs.rtcfile, path, MAX_DPATH, PATH_ROM); struct zfile *f = zfile_fopen(path, _T("rb")); if (f) { - uae_u8 empty[13]; - zfile_fread(empty, 13, 1, f); - uae_u8 v; - zfile_fread(&v, 1, 1, f); - rtc_ricoh.clock_control_d = v; - rtc_msm.clock_control_d = v; - zfile_fread(&v, 1, 1, f); - rtc_ricoh.clock_control_e = v; - rtc_msm.clock_control_d = v; - zfile_fread(&v, 1, 1, f); - rtc_ricoh.clock_control_f = v; - rtc_msm.clock_control_d = v; - zfile_fread(rtc_ricoh.rtc_alarm, RF5C01A_RAM_SIZE, 1, f); - zfile_fread(rtc_ricoh.rtc_memory, RF5C01A_RAM_SIZE, 1, f); + int size = zfile_size32(f); + uae_u8 empty[16]; + zfile_fread(empty, sizeof(empty), 1, f); + if (size > 16) { + rtc_ricoh.clock_control_d = empty[13]; + rtc_ricoh.clock_control_e = empty[14]; + rtc_ricoh.clock_control_f = empty[15]; + zfile_fread(rtc_ricoh.rtc_alarm, RF5C01A_RAM_SIZE, 1, f); + zfile_fread(rtc_ricoh.rtc_memory, RF5C01A_RAM_SIZE, 1, f); + } else if (size == 16) { + rtc_msm.clock_control_d = empty[13]; + rtc_msm.clock_control_e = empty[14]; + rtc_msm.clock_control_f = empty[15]; + } zfile_fclose(f); } } diff --git a/rtc.cpp b/rtc.cpp index 64d53113..59cc3438 100644 --- a/rtc.cpp +++ b/rtc.cpp @@ -58,9 +58,24 @@ bool put_clock_msm(struct rtc_msm_data *data, int addr, uae_u8 v) { switch (addr) { - case 0xD: data->clock_control_d = v & (1|8); break; - case 0xE: data->clock_control_e = v; break; - case 0xF: data->clock_control_f = v; break; + case 0xD: + if (data->clock_control_d != (v & (1 | 8))) { + data->clock_control_d = v & (1 | 8); + data->delayed_write = -1; + } + break; + case 0xE: + if (data->clock_control_e != v) { + data->clock_control_e = v; + data->delayed_write = -1; + } + break; + case 0xF: + if (data->clock_control_f != v) { + data->clock_control_f = v; + data->delayed_write = -1; + } + break; } return false; } @@ -149,8 +164,23 @@ void put_clock_ricoh(struct rtc_ricoh_data *data, int addr, uae_u8 v) #endif switch (addr) { - case 0xD: data->clock_control_d = v; break; - case 0xE: data->clock_control_e = v; break; - case 0xF: data->clock_control_f = v; break; + case 0xD: + if (data->clock_control_d != v) { + data->clock_control_d = v; + data->delayed_write = -1; + } + break; + case 0xE: + if (data->clock_control_e != v) { + data->clock_control_e = v; + data->delayed_write = -1; + } + break; + case 0xF: + if (data->clock_control_f != v) { + data->clock_control_f = v; + data->delayed_write = -1; + } + break; } } -- 2.47.3