From 3da2ed8232cd7cd11e00775df427d175d700d56e Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Sat, 16 Feb 2019 13:11:28 +0200 Subject: [PATCH] Debugger updates. --- blitter.cpp | 14 +- cia.cpp | 39 +++ custom.cpp | 41 +++- debug.cpp | 221 +++++++++++++++-- identify.cpp | 534 ++++++++++++++++++++---------------------- include/debug.h | 9 +- include/identify.h | 20 +- include/inputdevice.h | 1 + inputdevice.cpp | 22 ++ memory.cpp | 2 +- 10 files changed, 576 insertions(+), 327 deletions(-) diff --git a/blitter.cpp b/blitter.cpp index 56d881d1..133e6025 100644 --- a/blitter.cpp +++ b/blitter.cpp @@ -305,13 +305,13 @@ STATIC_INLINE void record_dma_blit (uae_u16 reg, uae_u16 dat, uae_u32 addr, int mask = MW_MASK_BLITTER_D_F; if (blitline) mask = MW_MASK_BLITTER_D_L; - debug_wputpeekdma_chipram(addr, dat, mask, reg); + debug_wputpeekdma_chipram(addr, dat, mask, reg, 0x054); } else if (reg == 0x70) { - debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_C, reg); + debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_C, reg, 0x48); } else if (reg == 0x72) { - debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_B, reg); + debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_B, reg, 0x4c); } else if (reg == 0x74) { - debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_A, reg); + debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_A, reg, 0x52); } } #endif @@ -504,7 +504,7 @@ STATIC_INLINE void chipmem_agnus_wput2 (uaecptr addr, uae_u32 w) //last_custom_value1 = w; blitter writes are not stored if (!(log_blitter & 4)) { chipmem_wput_indirect (addr, w); - debug_wputpeekdma_chipram (addr, w, MW_MASK_BLITTER_D_N, 0x000); + debug_wputpeekdma_chipram (addr, w, MW_MASK_BLITTER_D_N, 0x000, 0x054); } } @@ -711,7 +711,7 @@ STATIC_INLINE void blitter_read (void) if (!dmaen (DMA_BLITTER)) return; blt_info.bltcdat = chipmem_wget_indirect (bltcpt); - debug_wgetpeekdma_chipram (bltcpt, blt_info.bltcdat, MW_MASK_BLITTER_C, 0x070); + debug_wgetpeekdma_chipram (bltcpt, blt_info.bltcdat, MW_MASK_BLITTER_C, 0x070, 0x048); last_custom_value1 = blt_info.bltcdat; } bltstate = BLT_work; @@ -727,7 +727,7 @@ STATIC_INLINE void blitter_write (void) return; //last_custom_value1 = blt_info.bltddat; blitter writes are not stored chipmem_wput_indirect (bltdpt, blt_info.bltddat); - debug_wputpeekdma_chipram (bltdpt, blt_info.bltddat, MW_MASK_BLITTER_D_N, 0x000); + debug_wputpeekdma_chipram (bltdpt, blt_info.bltddat, MW_MASK_BLITTER_D_N, 0x000, 0x054); } bltstate = BLT_next; } diff --git a/cia.cpp b/cia.cpp index d5442e9c..db02b937 100644 --- a/cia.cpp +++ b/cia.cpp @@ -1900,6 +1900,29 @@ static void cia_wait_post (int cianummask, uae_u32 value) } } +static void validate_cia(uaecptr addr, int write, uae_u8 val) +{ + bool err = false; + if (((addr >> 12) & 3) == 0 || ((addr >> 12) & 3) == 3) + err = true; + if (((addr & 0xf00) >> 8) == 11) + err = true; + int mask = addr & 0xf000; + if (mask != 0xe000 && mask != 0xd000) + err = true; + if (mask == 0xe000 && (addr & 1) == 0) + err = true; + if (mask == 0xd000 && (addr & 1) != 0) + err = true; + if (err) { + if (write) { + write_log(_T("Invalid CIA write %08x = %02x PC=%08x\n"), addr, val, M68K_GETPC); + } else { + write_log(_T("Invalid CIA read %08x PC=%08x\n"), addr, M68K_GETPC); + } + } +} + // Gayle or Fat Gary does not enable CIA /CS lines if both CIAs are selected // Old Gary based Amigas enable both CIAs in this situation @@ -1959,6 +1982,10 @@ static uae_u32 REGPARAM2 cia_bget (uaecptr addr) if (!isgaylenocia (addr)) return dummy_get(addr, 1, false, 0); + if (memwatch_access_validator) { + validate_cia(addr, 0, 0); + } + switch (cia_chipselect(addr)) { case 0: @@ -2017,6 +2044,10 @@ static uae_u32 REGPARAM2 cia_wget (uaecptr addr) if (!isgaylenocia (addr)) return dummy_get_safe(addr, 2, false, 0); + if (memwatch_access_validator) { + write_log(_T("CIA word read %08x PC=%08x\n"), addr, M68K_GETPC); + } + switch (cia_chipselect(addr)) { case 0: @@ -2090,6 +2121,10 @@ static void REGPARAM2 cia_bput (uaecptr addr, uae_u32 value) if (!isgaylenocia (addr)) return; + if (memwatch_access_validator) { + validate_cia(addr, 1, value); + } + int cs = cia_chipselect(addr); if (!issinglecia () || (cs & 3) != 0) { @@ -2124,6 +2159,10 @@ static void REGPARAM2 cia_wput (uaecptr addr, uae_u32 value) if (!isgaylenocia (addr)) return; + if (memwatch_access_validator) { + write_log(_T("CIA word write %08x = %04x PC=%08x\n"), addr, value & 0xffff, M68K_GETPC); + } + int cs = cia_chipselect(addr); if (!issinglecia () || (cs & 3) != 0) { diff --git a/custom.cpp b/custom.cpp index 5d5bbe8b..28b1c794 100644 --- a/custom.cpp +++ b/custom.cpp @@ -360,6 +360,7 @@ struct copper { int vcmp, hcmp; int strobe; /* COPJMP1 / COPJMP2 accessed */ + int last_strobe; int moveaddr, movedata, movedelay; }; @@ -1442,7 +1443,7 @@ static void fetch (int nr, int fm, bool modulo, int hpos) if (debug_dma) record_dma (0x110 + nr * 2, chipmem_wget_indirect (p), p, hpos, vpos, DMARECORD_BITPLANE, nr); if (memwatch_enabled) - debug_wgetpeekdma_chipram(p, chipmem_wget_indirect (p), MW_MASK_BPL_0 << nr, 0x110 + nr * 2); + debug_wgetpeekdma_chipram(p, chipmem_wget_indirect (p), MW_MASK_BPL_0 << nr, 0x110 + nr * 2, 0xe0 + nr * 4); #endif switch (fm) { @@ -5545,6 +5546,7 @@ static void COPJMP (int num, int vblank) cop_state.hpos = current_hpos () & ~1; copper_enabled_thisline = 0; cop_state.strobe = num; + cop_state.last_strobe = num; if (nocustom ()) { immediate_copper (num); @@ -7124,7 +7126,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (0x8c, chipmem_wget_indirect (cop_state.ip), cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x8c); + debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80); #endif if (old_hpos == maxhpos - 2) { // if COP_strobe_delay2 would cross scanlines (positioned immediately @@ -7150,7 +7152,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (0x1fe, chipmem_wget_indirect (cop_state.ip), cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x1fe); + debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x1fe, 0x1fe); #endif } cop_state.state = COP_read1; @@ -7179,7 +7181,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (0x1fe, chipmem_wget_indirect (cop_state.ip), cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x1fe); + debug_wgetpeekdma_chipram(cop_state.ip, chipmem_wget_indirect (cop_state.ip), MW_MASK_COPPER, 0x1fe, 0x1fe); #endif cop_state.state = COP_read1; // Next cycle finally reads from new pointer @@ -7202,7 +7204,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (0x1fe, cop_state.i1, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 2); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip, cop_state.i1, MW_MASK_COPPER, 0x1fe); + debug_wgetpeekdma_chipram(cop_state.ip, cop_state.i1, MW_MASK_COPPER, 0x1fe, 0x1fe); #endif cop_state.ip = cop1lc; break; @@ -7216,7 +7218,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (0x8c, cop_state.i1, cop_state.ip, old_hpos, vpos, DMARECORD_COPPER, 0); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip, cop_state.i1, MW_MASK_COPPER, 0x8c); + debug_wgetpeekdma_chipram(cop_state.ip, cop_state.i1, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80); #endif cop_state.ip += 2; cop_state.state = COP_read2; @@ -7242,7 +7244,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (0x8c, cop_state.i2, cop_state.ip - 2, old_hpos, vpos, DMARECORD_COPPER, (cop_state.i1 & 1) ? 1 : 0); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip - 2, cop_state.i2, MW_MASK_COPPER, 0x8c); + debug_wgetpeekdma_chipram(cop_state.ip - 2, cop_state.i2, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80); #endif } else { // MOVE #ifdef DEBUGGER @@ -7255,7 +7257,7 @@ static void update_copper (int until_hpos) if (debug_dma) record_dma (reg, data, cop_state.ip - 2, old_hpos, vpos, DMARECORD_COPPER, 0); if (memwatch_enabled) - debug_wgetpeekdma_chipram(cop_state.ip - 2, data, MW_MASK_COPPER, reg); + debug_wgetpeekdma_chipram(cop_state.ip - 2, data, MW_MASK_COPPER, 0x8c, cop_state.last_strobe == 2 ? 0x84 : 0x80); #endif test_copper_dangerous (reg); if (! copper_enabled_thisline) @@ -7266,9 +7268,11 @@ static void update_copper (int until_hpos) if (reg == 0x88) { cop_state.strobe = 1; + cop_state.last_strobe = 1; cop_state.state = COP_strobe_delay1; } else if (reg == 0x8a) { cop_state.strobe = 2; + cop_state.last_strobe = 2; cop_state.state = COP_strobe_delay1; } else { #if 0 @@ -7540,7 +7544,7 @@ static uae_u16 sprite_fetch(struct sprite *s, uaecptr pt, bool dma, int hpos, in if (debug_dma) record_dma (num * 8 + 0x140 + mode * 4 + cycle * 2, data, pt, hpos, vpos, DMARECORD_SPRITE, num); if (memwatch_enabled) - debug_wgetpeekdma_chipram(pt, data, MW_MASK_SPR_0 << num, num * 8 + 0x140 + mode * 4 + cycle * 2); + debug_wgetpeekdma_chipram(pt, data, MW_MASK_SPR_0 << num, num * 8 + 0x140 + mode * 4 + cycle * 2, num * 4 + 0x120); #endif } return data; @@ -8551,7 +8555,7 @@ static void dmal_emu (uae_u32 v) if (debug_dma) record_dma (0xaa + nr * 16, dat, pt, hpos, vpos, DMARECORD_AUDIO, nr); if (memwatch_enabled) - debug_wgetpeekdma_chipram(pt, dat, MW_MASK_AUDIO_0 << nr, 0xaa + nr * 16); + debug_wgetpeekdma_chipram(pt, dat, MW_MASK_AUDIO_0 << nr, 0xaa + nr * 16, 0xa0 + nr * 16); #endif last_custom_value1 = last_custom_value2 = dat; AUDxDAT (nr, dat, pt); @@ -8578,7 +8582,7 @@ static void dmal_emu (uae_u32 v) if (debug_dma) record_dma (w ? 0x26 : 0x08, dat, pt, hpos, vpos, DMARECORD_DISK, v / 2); if (memwatch_enabled) - debug_wgetpeekdma_chipram(pt, dat, MW_MASK_DISK, w ? 0x26 : 0x08); + debug_wgetpeekdma_chipram(pt, dat, MW_MASK_DISK, w ? 0x26 : 0x08, 0x20); #endif } } @@ -10238,10 +10242,14 @@ static uae_u32 REGPARAM2 custom_wget_1(int hpos, uaecptr addr, int noput, bool i { uae_u16 v; int missing; - addr &= 0xfff; #if CUSTOM_DEBUG > 2 write_log (_T("%d:%d:wget: %04X=%04X pc=%p\n"), current_hpos(), vpos, addr, addr & 0x1fe, m68k_getpc ()); #endif + if (memwatch_access_validator) + debug_check_reg(addr, 0, 0); + + addr &= 0xfff; + switch (addr & 0x1fe) { case 0x002: v = DMACONR (hpos); break; case 0x004: v = VPOSR (); break; @@ -10372,6 +10380,7 @@ static uae_u32 REGPARAM2 custom_wget (uaecptr addr) if ((addr & 0xffff) < 0x8000 && currprefs.cs_fatgaryrev >= 0) return dummy_get(addr, 2, false, 0); if (addr & 1) { + debug_invalid_reg(addr, 2, 0); /* think about move.w $dff005,d0.. (68020+ only) */ addr &= ~1; v = custom_wget2 (addr, false) << 8; @@ -10386,6 +10395,7 @@ static uae_u32 REGPARAM2 custom_bget (uaecptr addr) uae_u32 v; if ((addr & 0xffff) < 0x8000 && currprefs.cs_fatgaryrev >= 0) return dummy_get(addr, 1, false, 0); + debug_invalid_reg(addr, 1, 0); v = custom_wget2 (addr & ~1, true); v >>= (addr & 1 ? 0 : 8); return v; @@ -10399,6 +10409,7 @@ static uae_u32 REGPARAM2 custom_lget (uaecptr addr) } static int REGPARAM2 custom_wput_1 (int hpos, uaecptr addr, uae_u32 value, int noget) { + uaecptr oaddr = addr; addr &= 0x1FE; value &= 0xffff; custom_storage[addr >> 1].value = (uae_u16)value; @@ -10409,6 +10420,8 @@ static int REGPARAM2 custom_wput_1 (int hpos, uaecptr addr, uae_u32 value, int n ar_custom[addr + 1]=(uae_u8)(value); #endif #endif + if (memwatch_access_validator) + debug_check_reg(oaddr, 1, value); switch (addr) { case 0x00E: CLXDAT (); break; @@ -10472,7 +10485,7 @@ static int REGPARAM2 custom_wput_1 (int hpos, uaecptr addr, uae_u32 value, int n case 0x09C: INTREQ (value); break; case 0x09E: ADKCON (hpos, value); break; - case 0x0A0: AUDxLCH (0, value); break; + case 0x0A0: AUDxLCH(0, value); break; case 0x0A2: AUDxLCL (0, value); break; case 0x0A4: AUDxLEN (0, value); break; case 0x0A6: AUDxPER (0, value); break; @@ -10625,6 +10638,7 @@ static void REGPARAM2 custom_wput (uaecptr addr, uae_u32 value) #endif sync_copper_with_cpu (hpos, 1); if (addr & 1) { + debug_invalid_reg(addr, -2, value); addr &= ~1; custom_wput_1 (hpos, addr, (value >> 8) | (value & 0xff00), 0); custom_wput_1 (hpos, addr + 2, (value << 8) | (value & 0x00ff), 0); @@ -10641,6 +10655,7 @@ static void REGPARAM2 custom_bput (uaecptr addr, uae_u32 value) dummy_put(addr, 1, value); return; } + debug_invalid_reg(addr, -1, value); if (currprefs.chipset_mask & CSMASK_AGA) { if (addr & 1) { rval = value & 0xff; diff --git a/debug.cpp b/debug.cpp index 822f718e..0c1b6b2e 100644 --- a/debug.cpp +++ b/debug.cpp @@ -65,6 +65,7 @@ static uae_u32 trace_param2; int debugger_active; static int debug_rewind; static int memwatch_triggered; +int memwatch_access_validator; int memwatch_enabled; int debugging; int exception_debugging; @@ -1249,17 +1250,29 @@ static void dump_custom_regs(bool aga, bool ext) p4[11] = p3[11]; free (p3); } - end = 0; - while (custd[end].name) - end++; - end++; - end /= 2; - for (int i = 0; i < end; i++) { + int total = 0; + int i = 0; + while (custd[i].name) { + if (!(custd[i].special & CD_NONE)) + total++; + i++; + } + int cnt1 = 0; + int cnt2 = 0; + i = 0; + while (i < total / 2 + 1) { + for (;;) { + cnt2++; + if (!(custd[cnt2].special & CD_NONE)) + break; + } + i++; + } + for (int i = 0; i < total / 2 + 1; i++) { uae_u16 v1, v2; int addr1, addr2; - int j = end + i; - addr1 = custd[i].adr & 0x1ff; - addr2 = custd[j].adr & 0x1ff; + addr1 = custd[cnt1].adr & 0x1ff; + addr2 = custd[cnt2].adr & 0x1ff; v1 = (p1[addr1 + 0] << 8) | p1[addr1 + 1]; v2 = (p1[addr2 + 0] << 8) | p1[addr2 + 1]; if (ext) { @@ -1270,8 +1283,18 @@ static void dump_custom_regs(bool aga, bool ext) _stprintf(extra2, _T("\t%04X %08X %s"), cs->value, cs->pc & ~1, (cs->pc & 1) ? _T("COP") : _T("CPU")); } console_out_f (_T("%03X %s\t%04X%s\t%03X %s\t%04X%s\n"), - addr1, custd[i].name, v1, extra1, - addr2, custd[j].name, v2, extra2); + addr1, custd[cnt1].name, v1, extra1, + addr2, custd[cnt2].name, v2, extra2); + for (;;) { + cnt1++; + if (!(custd[cnt1].special & CD_NONE)) + break; + } + for (;;) { + cnt2++; + if (!(custd[cnt2].special & CD_NONE)) + break; + } } xfree(p2); } @@ -1889,6 +1912,7 @@ struct dma_rec *record_dma (uae_u16 reg, uae_u16 dat, uae_u32 addr, int hpos, in dma_record_frame[0] = -1; dma_record_frame[1] = -1; } + if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS) return NULL; @@ -2605,7 +2629,7 @@ static void illg_init (void) i = 0; while (custd[i].name) { - int rw = custd[i].rw; + int rw = (custd[i].special & CD_WO) ? 2 : 1; illgdebug[custd[i].adr] = rw; illgdebug[custd[i].adr + 1] = rw; i++; @@ -2884,6 +2908,105 @@ void restore_debug_memwatch_finish (void) } } +void debug_check_reg(uae_u32 addr, int write, uae_u16 v) +{ + if (!memwatch_access_validator) + return; + int reg = addr & 0x1ff; + const struct customData *cd = &custd[reg >> 1]; + + if (((addr & 0xfe00) != 0xf000 && (addr & 0xffff0000) != 0) || ((addr & 0xffff0000) != 0 && (addr & 0xffff0000) != 0x00df0000) || (addr & 0x0600)) { + write_log(_T("Mirror custom register %08x (%s) %s access. PC=%08x\n"), addr, cd->name, write ? _T("write") : _T("read"), M68K_GETPC); + } + + int spc = cd->special; + if ((spc & CD_AGA) && !(currprefs.chipset_mask & CSMASK_AGA)) + spc |= CD_NONE; + if ((spc & CD_ECS_DENISE) && !(currprefs.chipset_mask & CSMASK_ECS_DENISE)) + spc |= CD_NONE; + if ((spc & CD_ECS_AGNUS) && !(currprefs.chipset_mask & CSMASK_ECS_AGNUS)) + spc |= CD_NONE; + if (spc & CD_NONE) { + write_log(_T("Non-existing custom register %04x (%s) %s access. PC=%08x\n"), reg, cd->name, write ? _T("write") : _T("read"), M68K_GETPC); + return; + } + + if (spc & CD_COLOR) { + if (currprefs.chipset_mask & CSMASK_AGA) + return; + } + + if (write & !(spc & CD_WO)) { + write_log(_T("Write access to read-only custom register %04x (%s). PC=%08x\n"), reg, cd->name, M68K_GETPC); + return; + } else if (!write && (spc & CD_WO)) { + write_log(_T("Read access from write-only custom register %04x (%s). PC=%08x\n"), reg, cd->name, M68K_GETPC); + return; + } + + if (write && cd->mask[2]) { + int idx = (currprefs.chipset_mask & CSMASK_AGA) ? 2 : (currprefs.chipset_mask & CSMASK_ECS_AGNUS) ? 1 : 0; + uae_u16 mask = cd->mask[idx]; + if (v & ~mask) { + write_log(_T("Unuset bits set %04x when writing custom register %04x (%s) PC=%08x\n"), v & ~mask, reg, cd->name, M68K_GETPC); + } + } + + if (spc & CD_DMA_PTR) { + uae_u32 addr = (custom_storage[((reg & ~2) >> 1)].value << 16) | custom_storage[((reg | 2) >> 1)].value; + if (currprefs.z3chipmem_size) { + if (addr >= currprefs.z3chipmem_start && addr < currprefs.z3chipmem_start + currprefs.z3chipmem_size) + return; + } + if(addr >= currprefs.chipmem_size) + write_log(_T("DMA pointer %04x (%s) set to invalid value %08x %s=%08x\n"), reg, cd->name, addr, + custom_storage[reg >> 1].pc & 1 ? _T("COP") : _T("PC"), custom_storage[reg >> 1].pc); + } +} + +void debug_invalid_reg(int reg, int size, uae_u16 v) +{ + if (!memwatch_access_validator) + return; + reg &= 0x1ff; + if (size == 1) { + if (reg == 2) // DMACONR low byte + return; + if (reg == 6) // VPOS + return; + } + const struct customData *cd = &custd[reg >> 1]; + if (size == -2 && (reg & 1)) { + write_log(_T("Unaligned word write to register %04x (%s) val %04x PC=%08x\n"), reg, cd->name, v, M68K_GETPC); + } else if (size == -1) { + write_log(_T("Byte write to register %04x (%s) val %02x PC=%08x\n"), reg, cd->name, v & 0xff, M68K_GETPC); + } else if (size == 2 && (reg & 1)) { + write_log(_T("Unaligned word read from register %04x (%s) PC=%08x\n"), reg, cd->name, M68K_GETPC); + } else if (size == 1) { + write_log(_T("Byte read from register %04x (%s) PC=%08x\n"), reg, cd->name, M68K_GETPC); + } +} + +static void is_valid_dma(int reg, int ptrreg, uaecptr addr) +{ + if (!memwatch_access_validator) + return; + if (reg == 0x1fe) // refresh + return; + if (currprefs.z3chipmem_size) { + if (addr >= currprefs.z3chipmem_start && addr < currprefs.z3chipmem_start + currprefs.z3chipmem_size) + return; + } + if (!(addr & ~(currprefs.chipmem_size - 1))) + return; + const struct customData *cdreg = &custd[reg >> 1]; + const struct customData *cdptr = &custd[ptrreg >> 1]; + write_log(_T("DMA DAT %04x (%s), PT %04x (%s) accessed invalid memory %08x. Init: %08x, PC/COP=%08x\n"), + reg, cdreg->name, ptrreg, cdptr->name, addr, + (custom_storage[ptrreg >> 1].value << 16) | (custom_storage[(ptrreg >> 1) + 1].value), + custom_storage[ptrreg >> 1].pc); +} + static void mungwall_memwatch(uaecptr addr, int rwi, int size, uae_u32 valp) { struct mungwall_data *mwd = mungwall[addr >> 16]; @@ -3210,10 +3333,11 @@ uae_u16 debug_wputpeekdma_chipset (uaecptr addr, uae_u32 v, uae_u32 mask, int re memwatch_func (addr, 2, 2, &v, mask, reg); return v; } -uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg) +uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg) { if (!memwatch_enabled) return v; + is_valid_dma(reg, ptrreg, addr); if (debug_mem_banks[addr >> 16] == NULL) return v; if (!currprefs.z3chipmem_size) @@ -3221,11 +3345,12 @@ uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int re memwatch_func (addr & chipmem_bank.mask, 2, 2, &v, mask, reg); return v; } -uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg) +uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg) { uae_u32 vv = v; if (!memwatch_enabled) return v; + is_valid_dma(reg, ptrreg, addr); if (debug_mem_banks[addr >> 16] == NULL) return v; if (!currprefs.z3chipmem_size) @@ -3561,6 +3686,7 @@ static void memwatch (TCHAR **c) if (!memwatch_enabled) { initialize_memwatch (0); console_out (_T("Memwatch breakpoints enabled\n")); + memwatch_access_validator = 0; } cp = *c; @@ -3575,6 +3701,12 @@ static void memwatch (TCHAR **c) console_out (_T("Memwatch breakpoints disabled\n")); return; } + if (nc == 'l') { + memwatch_access_validator = !memwatch_access_validator; + console_out_f(_T("Memwatch DMA validator %s\n"), memwatch_access_validator ? _T("enabled") : _T("disabled")); + return; + } + if (nc == 'd') { if (illgdebug) { ignore_ws (c); @@ -6587,6 +6719,7 @@ After [patch] section must come at least one patch descriptor. [patch] name=name enable=true/false +event=KEY_F1 ; patch descriptor data=200e46802d400026200cxx02 ; this is comment @@ -6607,6 +6740,7 @@ replaceoffset=4 name: name of the option (appears in GUI in the future) enable: true = automatically enabled at startup. (false=manually activated using key shortcut etc.., will be implemented later) +event: inputevents.def event name data: match data, when emulated CPU executes first opcode of this data and following words also match: match is detected. x = anything. offset: word offset from beginning of "data" that points to memory read/write instruction that you want to "patch". Default=0. @@ -6667,6 +6801,8 @@ struct trainerpatch uae_u32 oldval; int patchtype; int setvalue; + int *events; + int eventcount; int memwatchindex; bool enabledatstart; bool enabled; @@ -7011,6 +7147,44 @@ void debug_init_trainer(const TCHAR *file) xfree(data); } + if (ini_getstring(ini, section, _T("event"), &data)) { + TCHAR *s = data; + _tcscat(s, _T(",")); + while (*s) { + bool end = false; + while (*s == ' ') + s++; + TCHAR *se = _tcschr(s, ','); + if (se) { + *se = 0; + } else { + end = true; + } + TCHAR *se2 = se - 1; + while (se2 > s) { + if (*se2 != ' ') + break; + *se2 = 0; + se2--; + } + int evt = inputdevice_geteventid(s); + if (evt > 0) { + if (tp->events) { + tp->events = xrealloc(int, tp->events, tp->eventcount + 1); + } else { + tp->events = xmalloc(int, 1); + } + tp->events[tp->eventcount++] = evt; + } else { + write_log(_T("Unknown event '%s'\n"), s); + } + if (end) + break; + s = se + 1; + } + xfree(data); + } + tp->first = tp->data[tp->offset]; tp->name = name; @@ -7037,3 +7211,22 @@ end: ini_free(ini); } + +bool debug_trainer_event(int evt, int state) +{ + for (int i = 0; i < tpptrcnt; i++) { + struct trainerpatch *tp = tpptr[i]; + for (int j = 0; j < tp->eventcount; j++) { + if (tp->events[j] <= 0) + continue; + if (tp->events[j] == evt) { + if (!state) + return true; + write_log(_T("Trainer %d ('%s') -> %s\n"), i, tp->name, tp->enabled ? _T("off") : _T("on")); + debug_trainer_enable(tp, !tp->enabled); + return true; + } + } + } + return false; +} diff --git a/identify.cpp b/identify.cpp index 543f3558..eee9af67 100644 --- a/identify.cpp +++ b/identify.cpp @@ -117,286 +117,262 @@ const struct mem_labels mem_labels[] = const struct customData custd[] = { -#if 0 - { _T("BLTDDAT"), 0xdff000 }, /* Blitter dest. early read (dummy address) */ -#endif - { _T("DMACONR"), 0xdff002, 1 }, /* Dma control (and blitter status) read */ - { _T("VPOSR"), 0xdff004, 1 }, /* Read vert most sig. bits (and frame flop */ - { _T("VHPOSR"), 0xdff006, 1 }, /* Read vert and horiz position of beam */ -#if 0 - { _T("DSKDATR"), 0xdff008 }, /* Disk data early read (dummy address) */ -#endif - { _T("JOY0DAT"), 0xdff00A, 1 }, /* Joystick-mouse 0 data (vert,horiz) */ - { _T("JOT1DAT"), 0xdff00C, 1 }, /* Joystick-mouse 1 data (vert,horiz) */ - { _T("CLXDAT"), 0xdff00E, 1 }, /* Collision data reg. (read and clear) */ - { _T("ADKCONR"), 0xdff010, 1 }, /* Audio,disk control register read */ - { _T("POT0DAT"), 0xdff012, 1 }, /* Pot counter pair 0 data (vert,horiz) */ - { _T("POT1DAT"), 0xdff014, 1 }, /* Pot counter pair 1 data (vert,horiz) */ - { _T("POTGOR"), 0xdff016, 1 }, /* Pot pin data read */ - { _T("SERDATR"), 0xdff018, 1 }, /* Serial port data and status read */ - { _T("DSKBYTR"), 0xdff01A, 1 }, /* Disk data byte and status read */ - { _T("INTENAR"), 0xdff01C, 1 }, /* Interrupt enable bits read */ - { _T("INTREQR"), 0xdff01E, 1 }, /* Interrupt request bits read */ - { _T("DSKPTH"), 0xdff020, 2, 1 }, /* Disk pointer (high 5 bits) */ - { _T("DSKPTL"), 0xdff022, 2, 2 }, /* Disk pointer (low 15 bits) */ - { _T("DSKLEN"), 0xdff024, 2, 0 }, /* Disk lentgh */ -#if 0 - { _T("DSKDAT"), 0xdff026 }, /* Disk DMA data write */ - { _T("REFPTR"), 0xdff028 }, /* Refresh pointer */ -#endif - { _T("VPOSW"), 0xdff02A, 2, 0 }, /* Write vert most sig. bits(and frame flop) */ - { _T("VHPOSW"), 0xdff02C, 2, 0 }, /* Write vert and horiz pos of beam */ - { _T("COPCON"), 0xdff02e, 2, 0 }, /* Coprocessor control reg (CDANG) */ - { _T("SERDAT"), 0xdff030, 2, 0 }, /* Serial port data and stop bits write */ - { _T("SERPER"), 0xdff032, 2, 0 }, /* Serial port period and control */ - { _T("POTGO"), 0xdff034, 2, 0 }, /* Pot count start,pot pin drive enable data */ - { _T("JOYTEST"), 0xdff036, 2, 0 }, /* Write to all 4 joystick-mouse counters at once */ - { _T("STREQU"), 0xdff038, 2, 0 }, /* Strobe for horiz sync with VB and EQU */ - { _T("STRVBL"), 0xdff03A, 2, 0 }, /* Strobe for horiz sync with VB (vert blank) */ - { _T("STRHOR"), 0xdff03C, 2, 0 }, /* Strobe for horiz sync */ - { _T("STRLONG"), 0xdff03E, 2, 0 }, /* Strobe for identification of long horiz line */ - { _T("BLTCON0"), 0xdff040, 2, 0 }, /* Blitter control reg 0 */ - { _T("BLTCON1"), 0xdff042, 2, 0 }, /* Blitter control reg 1 */ - { _T("BLTAFWM"), 0xdff044, 2, 0 }, /* Blitter first word mask for source A */ - { _T("BLTALWM"), 0xdff046, 2, 0 }, /* Blitter last word mask for source A */ - { _T("BLTCPTH"), 0xdff048, 2, 1 }, /* Blitter pointer to source C (high 5 bits) */ - { _T("BLTCPTL"), 0xdff04A, 2, 2 }, /* Blitter pointer to source C (low 15 bits) */ - { _T("BLTBPTH"), 0xdff04C, 2, 1 }, /* Blitter pointer to source B (high 5 bits) */ - { _T("BLTBPTL"), 0xdff04E, 2, 2 }, /* Blitter pointer to source B (low 15 bits) */ - { _T("BLTAPTH"), 0xdff050, 2, 1 }, /* Blitter pointer to source A (high 5 bits) */ - { _T("BLTAPTL"), 0xdff052, 2, 2 }, /* Blitter pointer to source A (low 15 bits) */ - { _T("BPTDPTH"), 0xdff054, 2, 1 }, /* Blitter pointer to destn D (high 5 bits) */ - { _T("BLTDPTL"), 0xdff056, 2, 2 }, /* Blitter pointer to destn D (low 15 bits) */ - { _T("BLTSIZE"), 0xdff058, 2, 0 }, /* Blitter start and size (win/width,height) */ - { _T("BLTCON0L"), 0xdff05A, 2, 4 }, /* Blitter control 0 lower 8 bits (minterms) */ - { _T("BLTSIZV"), 0xdff05C, 2, 4 }, /* Blitter V size (for 15 bit vert size) */ - { _T("BLTSIZH"), 0xdff05E, 2, 4 }, /* Blitter H size & start (for 11 bit H size) */ - { _T("BLTCMOD"), 0xdff060, 2, 0 }, /* Blitter modulo for source C */ - { _T("BLTBMOD"), 0xdff062, 2, 0 }, /* Blitter modulo for source B */ - { _T("BLTAMOD"), 0xdff064, 2, 0 }, /* Blitter modulo for source A */ - { _T("BLTDMOD"), 0xdff066, 2, 0 }, /* Blitter modulo for destn D */ -#if 0 - { _T("Unknown"), 0xdff068 }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff06a }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff06c }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff06e }, /* Unknown or Unused */ -#endif - { _T("BLTCDAT"), 0xdff070, 2, 0 }, /* Blitter source C data reg */ - { _T("BLTBDAT"), 0xdff072, 2, 0 }, /* Blitter source B data reg */ - { _T("BLTADAT"), 0xdff074, 2, 0 }, /* Blitter source A data reg */ - { _T("BLTDDAT"), 0xdff076, 2, 0 }, /* Blitter destination reg */ -#if 0 - { _T("SPRHDAT"), 0xdff078 }, /* Ext logic UHRES sprite pointer and data identifier */ - { _T("BPLHDAT"), 0xdff07A }, /* Ext logic UHRES bit plane identifier */ -#endif - { _T("LISAID"), 0xdff07C, 1, 8 }, /* Chip revision level for Denise/Lisa */ - { _T("DSKSYNC"), 0xdff07E, 2 }, /* Disk sync pattern reg for disk read */ - { _T("COP1LCH"), 0xdff080, 2, 1 }, /* Coprocessor first location reg (high 5 bits) */ - { _T("COP1LCL"), 0xdff082, 2, 2 }, /* Coprocessor first location reg (low 15 bits) */ - { _T("COP2LCH"), 0xdff084, 2, 1 }, /* Coprocessor second reg (high 5 bits) */ - { _T("COP2LCL"), 0xdff086, 2, 2 }, /* Coprocessor second reg (low 15 bits) */ - { _T("COPJMP1"), 0xdff088, 2 }, /* Coprocessor restart at first location */ - { _T("COPJMP2"), 0xdff08A, 2 }, /* Coprocessor restart at second location */ -#if 0 + { _T("BLTDDAT"), 0xdff000, CD_NONE }, /* Blitter dest. early read (dummy address) */ + { _T("DMACONR"), 0xdff002, 0 }, /* Dma control (and blitter status) read */ + { _T("VPOSR"), 0xdff004, 0 }, /* Read vert most sig. bits (and frame flop */ + { _T("VHPOSR"), 0xdff006, 0 }, /* Read vert and horiz position of beam */ + { _T("DSKDATR"), 0xdff008, CD_NONE }, /* Disk data early read (dummy address) */ + { _T("JOY0DAT"), 0xdff00A, 0 }, /* Joystick-mouse 0 data (vert,horiz) */ + { _T("JOT1DAT"), 0xdff00C, 0 }, /* Joystick-mouse 1 data (vert,horiz) */ + { _T("CLXDAT"), 0xdff00E, 0 }, /* Collision data reg. (read and clear) */ + { _T("ADKCONR"), 0xdff010, 0 }, /* Audio,disk control register read */ + { _T("POT0DAT"), 0xdff012, 0 }, /* Pot counter pair 0 data (vert,horiz) */ + { _T("POT1DAT"), 0xdff014, 0 }, /* Pot counter pair 1 data (vert,horiz) */ + { _T("POTGOR"), 0xdff016, 0 }, /* Pot pin data read */ + { _T("SERDATR"), 0xdff018, 0 }, /* Serial port data and status read */ + { _T("DSKBYTR"), 0xdff01A, 0 }, /* Disk data byte and status read */ + { _T("INTENAR"), 0xdff01C, 0 }, /* Interrupt enable bits read */ + { _T("INTREQR"), 0xdff01E, 0 }, /* Interrupt request bits read */ + { _T("DSKPTH"), 0xdff020, CD_WO | CD_DMA_PTR }, /* Disk pointer (high 5 bits) */ + { _T("DSKPTL"), 0xdff022, CD_WO | CD_DMA_PTR }, /* Disk pointer (low 15 bits) */ + { _T("DSKLEN"), 0xdff024, CD_WO }, /* Disk lentgh */ + { _T("DSKDAT"), 0xdff026, CD_NONE }, /* Disk DMA data write */ + { _T("REFPTR"), 0xdff028, CD_NONE }, /* Refresh pointer */ + { _T("VPOSW"), 0xdff02A, CD_WO }, /* Write vert most sig. bits(and frame flop) */ + { _T("VHPOSW"), 0xdff02C, CD_WO }, /* Write vert and horiz pos of beam */ + { _T("COPCON"), 0xdff02e, CD_WO }, /* Coprocessor control reg (CDANG) */ + { _T("SERDAT"), 0xdff030, CD_WO }, /* Serial port data and stop bits write */ + { _T("SERPER"), 0xdff032, CD_WO }, /* Serial port period and control */ + { _T("POTGO"), 0xdff034, CD_WO }, /* Pot count start,pot pin drive enable data */ + { _T("JOYTEST"), 0xdff036, CD_WO }, /* Write to all 4 joystick-mouse counters at once */ + { _T("STREQU"), 0xdff038, CD_WO }, /* Strobe for horiz sync with VB and EQU */ + { _T("STRVBL"), 0xdff03A, CD_WO }, /* Strobe for horiz sync with VB (vert blank) */ + { _T("STRHOR"), 0xdff03C, CD_WO }, /* Strobe for horiz sync */ + { _T("STRLONG"), 0xdff03E, CD_WO }, /* Strobe for identification of long horiz line */ + { _T("BLTCON0"), 0xdff040, CD_WO }, /* Blitter control reg 0 */ + { _T("BLTCON1"), 0xdff042, CD_WO }, /* Blitter control reg 1 */ + { _T("BLTAFWM"), 0xdff044, CD_WO }, /* Blitter first word mask for source A */ + { _T("BLTALWM"), 0xdff046, CD_WO }, /* Blitter last word mask for source A */ + { _T("BLTCPTH"), 0xdff048, CD_WO | CD_DMA_PTR }, /* Blitter pointer to source C (high 5 bits) */ + { _T("BLTCPTL"), 0xdff04A, CD_WO | CD_DMA_PTR }, /* Blitter pointer to source C (low 15 bits) */ + { _T("BLTBPTH"), 0xdff04C, CD_WO | CD_DMA_PTR }, /* Blitter pointer to source B (high 5 bits) */ + { _T("BLTBPTL"), 0xdff04E, CD_WO | CD_DMA_PTR }, /* Blitter pointer to source B (low 15 bits) */ + { _T("BLTAPTH"), 0xdff050, CD_WO | CD_DMA_PTR }, /* Blitter pointer to source A (high 5 bits) */ + { _T("BLTAPTL"), 0xdff052, CD_WO | CD_DMA_PTR }, /* Blitter pointer to source A (low 15 bits) */ + { _T("BPTDPTH"), 0xdff054, CD_WO | CD_DMA_PTR }, /* Blitter pointer to destn D (high 5 bits) */ + { _T("BLTDPTL"), 0xdff056, CD_WO | CD_DMA_PTR }, /* Blitter pointer to destn D (low 15 bits) */ + { _T("BLTSIZE"), 0xdff058, CD_WO }, /* Blitter start and size (win/width,height) */ + { _T("BLTCON0L"), 0xdff05A, CD_WO | CD_ECS_AGNUS }, /* Blitter control 0 lower 8 bits (minterms) */ + { _T("BLTSIZV"), 0xdff05C, CD_WO | CD_ECS_AGNUS, { 0, 0x07ff, 0x07ff } }, /* Blitter V size (for 15 bit vert size) */ + { _T("BLTSIZH"), 0xdff05E, CD_WO | CD_ECS_AGNUS, { 0, 0x7fff, 0x7fff } }, /* Blitter H size & start (for 11 bit H size) */ + { _T("BLTCMOD"), 0xdff060, CD_WO }, /* Blitter modulo for source C */ + { _T("BLTBMOD"), 0xdff062, CD_WO }, /* Blitter modulo for source B */ + { _T("BLTAMOD"), 0xdff064, CD_WO }, /* Blitter modulo for source A */ + { _T("BLTDMOD"), 0xdff066, CD_WO }, /* Blitter modulo for destn D */ + { _T("-"), 0xdff068, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff06a, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff06c, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff06e, CD_NONE }, /* Unknown or Unused */ + { _T("BLTCDAT"), 0xdff070, CD_WO }, /* Blitter source C data reg */ + { _T("BLTBDAT"), 0xdff072, CD_WO }, /* Blitter source B data reg */ + { _T("BLTADAT"), 0xdff074, CD_WO }, /* Blitter source A data reg */ + { _T("BLTDDAT"), 0xdff076, CD_WO }, /* Blitter destination reg */ + { _T("-"), 0xdff078, CD_NONE }, /* Ext logic UHRES sprite pointer and data identifier */ + { _T("-"), 0xdff07A, CD_NONE }, /* Ext logic UHRES bit plane identifier */ + { _T("LISAID"), 0xdff07C, CD_ECS_DENISE }, /* Chip revision level for Denise/Lisa */ + { _T("DSKSYNC"), 0xdff07E, CD_WO }, /* Disk sync pattern reg for disk read */ + { _T("COP1LCH"), 0xdff080, CD_WO | CD_DMA_PTR }, /* Coprocessor first location reg (high 5 bits) */ + { _T("COP1LCL"), 0xdff082, CD_WO | CD_DMA_PTR }, /* Coprocessor first location reg (low 15 bits) */ + { _T("COP2LCH"), 0xdff084, CD_WO | CD_DMA_PTR }, /* Coprocessor second reg (high 5 bits) */ + { _T("COP2LCL"), 0xdff086, CD_WO | CD_DMA_PTR }, /* Coprocessor second reg (low 15 bits) */ + { _T("COPJMP1"), 0xdff088, CD_WO }, /* Coprocessor restart at first location */ + { _T("COPJMP2"), 0xdff08A, CD_WO }, /* Coprocessor restart at second location */ { _T("COPINS"), 0xdff08C }, /* Coprocessor inst fetch identify */ -#endif - { _T("DIWSTRT"), 0xdff08E, 2 }, /* Display window start (upper left vert-hor pos) */ - { _T("DIWSTOP"), 0xdff090, 2 }, /* Display window stop (lower right vert-hor pos) */ - { _T("DDFSTRT"), 0xdff092, 2 }, /* Display bit plane data fetch start.hor pos */ - { _T("DDFSTOP"), 0xdff094, 2 }, /* Display bit plane data fetch stop.hor pos */ - { _T("DMACON"), 0xdff096, 2 }, /* DMA control write (clear or set) */ - { _T("CLXCON"), 0xdff098, 2 }, /* Collision control */ - { _T("INTENA"), 0xdff09A, 2 }, /* Interrupt enable bits (clear or set bits) */ - { _T("INTREQ"), 0xdff09C, 2 }, /* Interrupt request bits (clear or set bits) */ - { _T("ADKCON"), 0xdff09E, 2 }, /* Audio,disk,UART,control */ - { _T("AUD0LCH"), 0xdff0A0, 2, 1 }, /* Audio channel 0 location (high 5 bits) */ - { _T("AUD0LCL"), 0xdff0A2, 2, 2 }, /* Audio channel 0 location (low 15 bits) */ - { _T("AUD0LEN"), 0xdff0A4, 2 }, /* Audio channel 0 lentgh */ - { _T("AUD0PER"), 0xdff0A6, 2 }, /* Audio channel 0 period */ - { _T("AUD0VOL"), 0xdff0A8, 2 }, /* Audio channel 0 volume */ - { _T("AUD0DAT"), 0xdff0AA, 2 }, /* Audio channel 0 data */ -#if 0 - { _T("Unknown"), 0xdff0AC }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff0AE }, /* Unknown or Unused */ -#endif - { _T("AUD1LCH"), 0xdff0B0, 2, 1 }, /* Audio channel 1 location (high 5 bits) */ - { _T("AUD1LCL"), 0xdff0B2, 2, 2 }, /* Audio channel 1 location (low 15 bits) */ - { _T("AUD1LEN"), 0xdff0B4, 2 }, /* Audio channel 1 lentgh */ - { _T("AUD1PER"), 0xdff0B6, 2 }, /* Audio channel 1 period */ - { _T("AUD1VOL"), 0xdff0B8, 2 }, /* Audio channel 1 volume */ - { _T("AUD1DAT"), 0xdff0BA, 2 }, /* Audio channel 1 data */ -#if 0 - { _T("Unknown"), 0xdff0BC }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff0BE }, /* Unknown or Unused */ -#endif - { _T("AUD2LCH"), 0xdff0C0, 2, 1 }, /* Audio channel 2 location (high 5 bits) */ - { _T("AUD2LCL"), 0xdff0C2, 2, 2 }, /* Audio channel 2 location (low 15 bits) */ - { _T("AUD2LEN"), 0xdff0C4, 2 }, /* Audio channel 2 lentgh */ - { _T("AUD2PER"), 0xdff0C6, 2 }, /* Audio channel 2 period */ - { _T("AUD2VOL"), 0xdff0C8, 2 }, /* Audio channel 2 volume */ - { _T("AUD2DAT"), 0xdff0CA, 2 }, /* Audio channel 2 data */ -#if 0 - { _T("Unknown"), 0xdff0CC }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff0CE }, /* Unknown or Unused */ -#endif - { _T("AUD3LCH"), 0xdff0D0, 2, 1 }, /* Audio channel 3 location (high 5 bits) */ - { _T("AUD3LCL"), 0xdff0D2, 2, 2 }, /* Audio channel 3 location (low 15 bits) */ - { _T("AUD3LEN"), 0xdff0D4, 2 }, /* Audio channel 3 lentgh */ - { _T("AUD3PER"), 0xdff0D6, 2 }, /* Audio channel 3 period */ - { _T("AUD3VOL"), 0xdff0D8, 2 }, /* Audio channel 3 volume */ - { _T("AUD3DAT"), 0xdff0DA, 2 }, /* Audio channel 3 data */ -#if 0 - { _T("Unknown"), 0xdff0DC }, /* Unknown or Unused */ - { _T("Unknown"), 0xdff0DE }, /* Unknown or Unused */ -#endif - { _T("BPL1PTH"), 0xdff0E0, 2, 1 }, /* Bit plane pointer 1 (high 5 bits) */ - { _T("BPL1PTL"), 0xdff0E2, 2, 2 }, /* Bit plane pointer 1 (low 15 bits) */ - { _T("BPL2PTH"), 0xdff0E4, 2, 1 }, /* Bit plane pointer 2 (high 5 bits) */ - { _T("BPL2PTL"), 0xdff0E6, 2, 2 }, /* Bit plane pointer 2 (low 15 bits) */ - { _T("BPL3PTH"), 0xdff0E8, 2, 1 }, /* Bit plane pointer 3 (high 5 bits) */ - { _T("BPL3PTL"), 0xdff0EA, 2, 2 }, /* Bit plane pointer 3 (low 15 bits) */ - { _T("BPL4PTH"), 0xdff0EC, 2, 1 }, /* Bit plane pointer 4 (high 5 bits) */ - { _T("BPL4PTL"), 0xdff0EE, 2, 2 }, /* Bit plane pointer 4 (low 15 bits) */ - { _T("BPL5PTH"), 0xdff0F0, 2, 1 }, /* Bit plane pointer 5 (high 5 bits) */ - { _T("BPL5PTL"), 0xdff0F2, 2, 2 }, /* Bit plane pointer 5 (low 15 bits) */ - { _T("BPL6PTH"), 0xdff0F4, 2, 1|8 }, /* Bit plane pointer 6 (high 5 bits) */ - { _T("BPL6PTL"), 0xdff0F6, 2, 2|8 }, /* Bit plane pointer 6 (low 15 bits) */ - { _T("BPL7PTH"), 0xdff0F8, 2, 1|8 }, /* Bit plane pointer 7 (high 5 bits) */ - { _T("BPL7PTL"), 0xdff0FA, 2, 2|8 }, /* Bit plane pointer 7 (low 15 bits) */ - { _T("BPL8PTH"), 0xdff0FC, 2, 1|8 }, /* Bit plane pointer 8 (high 5 bits) */ - { _T("BPL8PTL"), 0xdff0FE, 2, 2|8 }, /* Bit plane pointer 8 (low 15 bits) */ - { _T("BPLCON0"), 0xdff100, 2 }, /* Bit plane control reg (misc control bits) */ - { _T("BPLCON1"), 0xdff102, 2 }, /* Bit plane control reg (scroll val PF1,PF2) */ - { _T("BPLCON2"), 0xdff104, 2 }, /* Bit plane control reg (priority control) */ - { _T("BPLCON3"), 0xdff106, 2|8 }, /* Bit plane control reg (enhanced features) */ - { _T("BPL1MOD"), 0xdff108, 2 }, /* Bit plane modulo (odd planes,or active- fetch lines if bitplane scan-doubling is enabled */ - { _T("BPL2MOD"), 0xdff10A, 2 }, /* Bit plane modulo (even planes or inactive- fetch lines if bitplane scan-doubling is enabled */ - { _T("BPLCON4"), 0xdff10C, 2|8 }, /* Bit plane control reg (bitplane and sprite masks) */ - { _T("CLXCON2"), 0xdff10e, 2|8 }, /* Extended collision control reg */ - { _T("BPL1DAT"), 0xdff110, 2 }, /* Bit plane 1 data (parallel to serial con- vert) */ - { _T("BPL2DAT"), 0xdff112, 2 }, /* Bit plane 2 data (parallel to serial con- vert) */ - { _T("BPL3DAT"), 0xdff114, 2 }, /* Bit plane 3 data (parallel to serial con- vert) */ - { _T("BPL4DAT"), 0xdff116, 2 }, /* Bit plane 4 data (parallel to serial con- vert) */ - { _T("BPL5DAT"), 0xdff118, 2 }, /* Bit plane 5 data (parallel to serial con- vert) */ - { _T("BPL6DAT"), 0xdff11a, 2 }, /* Bit plane 6 data (parallel to serial con- vert) */ - { _T("BPL7DAT"), 0xdff11c, 2|8 }, /* Bit plane 7 data (parallel to serial con- vert) */ - { _T("BPL8DAT"), 0xdff11e, 2|8 }, /* Bit plane 8 data (parallel to serial con- vert) */ - { _T("SPR0PTH"), 0xdff120, 2, 1 }, /* Sprite 0 pointer (high 5 bits) */ - { _T("SPR0PTL"), 0xdff122, 2, 2 }, /* Sprite 0 pointer (low 15 bits) */ - { _T("SPR1PTH"), 0xdff124, 2, 1 }, /* Sprite 1 pointer (high 5 bits) */ - { _T("SPR1PTL"), 0xdff126, 2, 2 }, /* Sprite 1 pointer (low 15 bits) */ - { _T("SPR2PTH"), 0xdff128, 2, 1 }, /* Sprite 2 pointer (high 5 bits) */ - { _T("SPR2PTL"), 0xdff12A, 2, 2 }, /* Sprite 2 pointer (low 15 bits) */ - { _T("SPR3PTH"), 0xdff12C, 2, 1 }, /* Sprite 3 pointer (high 5 bits) */ - { _T("SPR3PTL"), 0xdff12E, 2, 2 }, /* Sprite 3 pointer (low 15 bits) */ - { _T("SPR4PTH"), 0xdff130, 2, 1 }, /* Sprite 4 pointer (high 5 bits) */ - { _T("SPR4PTL"), 0xdff132, 2, 2 }, /* Sprite 4 pointer (low 15 bits) */ - { _T("SPR5PTH"), 0xdff134, 2, 1 }, /* Sprite 5 pointer (high 5 bits) */ - { _T("SPR5PTL"), 0xdff136, 2, 2 }, /* Sprite 5 pointer (low 15 bits) */ - { _T("SPR6PTH"), 0xdff138, 2, 1 }, /* Sprite 6 pointer (high 5 bits) */ - { _T("SPR6PTL"), 0xdff13A, 2, 2 }, /* Sprite 6 pointer (low 15 bits) */ - { _T("SPR7PTH"), 0xdff13C, 2, 1 }, /* Sprite 7 pointer (high 5 bits) */ - { _T("SPR7PTL"), 0xdff13E, 2, 2 }, /* Sprite 7 pointer (low 15 bits) */ - { _T("SPR0POS"), 0xdff140, 2 }, /* Sprite 0 vert-horiz start pos data */ - { _T("SPR0CTL"), 0xdff142, 2 }, /* Sprite 0 position and control data */ - { _T("SPR0DATA"), 0xdff144, 2 }, /* Sprite 0 image data register A */ - { _T("SPR0DATB"), 0xdff146, 2 }, /* Sprite 0 image data register B */ - { _T("SPR1POS"), 0xdff148, 2 }, /* Sprite 1 vert-horiz start pos data */ - { _T("SPR1CTL"), 0xdff14A, 2 }, /* Sprite 1 position and control data */ - { _T("SPR1DATA"), 0xdff14C, 2 }, /* Sprite 1 image data register A */ - { _T("SPR1DATB"), 0xdff14E, 2 }, /* Sprite 1 image data register B */ - { _T("SPR2POS"), 0xdff150, 2 }, /* Sprite 2 vert-horiz start pos data */ - { _T("SPR2CTL"), 0xdff152, 2 }, /* Sprite 2 position and control data */ - { _T("SPR2DATA"), 0xdff154, 2 }, /* Sprite 2 image data register A */ - { _T("SPR2DATB"), 0xdff156, 2 }, /* Sprite 2 image data register B */ - { _T("SPR3POS"), 0xdff158, 2 }, /* Sprite 3 vert-horiz start pos data */ - { _T("SPR3CTL"), 0xdff15A, 2 }, /* Sprite 3 position and control data */ - { _T("SPR3DATA"), 0xdff15C, 2 }, /* Sprite 3 image data register A */ - { _T("SPR3DATB"), 0xdff15E, 2 }, /* Sprite 3 image data register B */ - { _T("SPR4POS"), 0xdff160, 2 }, /* Sprite 4 vert-horiz start pos data */ - { _T("SPR4CTL"), 0xdff162, 2 }, /* Sprite 4 position and control data */ - { _T("SPR4DATA"), 0xdff164, 2 }, /* Sprite 4 image data register A */ - { _T("SPR4DATB"), 0xdff166, 2 }, /* Sprite 4 image data register B */ - { _T("SPR5POS"), 0xdff168, 2 }, /* Sprite 5 vert-horiz start pos data */ - { _T("SPR5CTL"), 0xdff16A, 2 }, /* Sprite 5 position and control data */ - { _T("SPR5DATA"), 0xdff16C, 2 }, /* Sprite 5 image data register A */ - { _T("SPR5DATB"), 0xdff16E, 2 }, /* Sprite 5 image data register B */ - { _T("SPR6POS"), 0xdff170, 2 }, /* Sprite 6 vert-horiz start pos data */ - { _T("SPR6CTL"), 0xdff172, 2 }, /* Sprite 6 position and control data */ - { _T("SPR6DATA"), 0xdff174, 2 }, /* Sprite 6 image data register A */ - { _T("SPR6DATB"), 0xdff176, 2 }, /* Sprite 6 image data register B */ - { _T("SPR7POS"), 0xdff178, 2 }, /* Sprite 7 vert-horiz start pos data */ - { _T("SPR7CTL"), 0xdff17A, 2 }, /* Sprite 7 position and control data */ - { _T("SPR7DATA"), 0xdff17C, 2 }, /* Sprite 7 image data register A */ - { _T("SPR7DATB"), 0xdff17E, 2 }, /* Sprite 7 image data register B */ - { _T("COLOR00"), 0xdff180, 2 }, /* Color table 00 */ - { _T("COLOR01"), 0xdff182, 2 }, /* Color table 01 */ - { _T("COLOR02"), 0xdff184, 2 }, /* Color table 02 */ - { _T("COLOR03"), 0xdff186, 2 }, /* Color table 03 */ - { _T("COLOR04"), 0xdff188, 2 }, /* Color table 04 */ - { _T("COLOR05"), 0xdff18A, 2 }, /* Color table 05 */ - { _T("COLOR06"), 0xdff18C, 2 }, /* Color table 06 */ - { _T("COLOR07"), 0xdff18E, 2 }, /* Color table 07 */ - { _T("COLOR08"), 0xdff190, 2 }, /* Color table 08 */ - { _T("COLOR09"), 0xdff192, 2 }, /* Color table 09 */ - { _T("COLOR10"), 0xdff194, 2 }, /* Color table 10 */ - { _T("COLOR11"), 0xdff196, 2 }, /* Color table 11 */ - { _T("COLOR12"), 0xdff198, 2 }, /* Color table 12 */ - { _T("COLOR13"), 0xdff19A, 2 }, /* Color table 13 */ - { _T("COLOR14"), 0xdff19C, 2 }, /* Color table 14 */ - { _T("COLOR15"), 0xdff19E, 2 }, /* Color table 15 */ - { _T("COLOR16"), 0xdff1A0, 2 }, /* Color table 16 */ - { _T("COLOR17"), 0xdff1A2, 2 }, /* Color table 17 */ - { _T("COLOR18"), 0xdff1A4, 2 }, /* Color table 18 */ - { _T("COLOR19"), 0xdff1A6, 2 }, /* Color table 19 */ - { _T("COLOR20"), 0xdff1A8, 2 }, /* Color table 20 */ - { _T("COLOR21"), 0xdff1AA, 2 }, /* Color table 21 */ - { _T("COLOR22"), 0xdff1AC, 2 }, /* Color table 22 */ - { _T("COLOR23"), 0xdff1AE, 2 }, /* Color table 23 */ - { _T("COLOR24"), 0xdff1B0, 2 }, /* Color table 24 */ - { _T("COLOR25"), 0xdff1B2, 2 }, /* Color table 25 */ - { _T("COLOR26"), 0xdff1B4, 2 }, /* Color table 26 */ - { _T("COLOR27"), 0xdff1B6, 2 }, /* Color table 27 */ - { _T("COLOR28"), 0xdff1B8, 2 }, /* Color table 28 */ - { _T("COLOR29"), 0xdff1BA, 2 }, /* Color table 29 */ - { _T("COLOR30"), 0xdff1BC, 2 }, /* Color table 30 */ - { _T("COLOR31"), 0xdff1BE, 2 }, /* Color table 31 */ - { _T("HTOTAL"), 0xdff1C0, 2|4 }, /* Highest number count in horiz line (VARBEAMEN = 1) */ - { _T("HSSTOP"), 0xdff1C2, 2|4 }, /* Horiz line pos for HSYNC stop */ - { _T("HBSTRT"), 0xdff1C4, 2|4 }, /* Horiz line pos for HBLANK start */ - { _T("HBSTOP"), 0xdff1C6, 2|4 }, /* Horiz line pos for HBLANK stop */ - { _T("VTOTAL"), 0xdff1C8, 2|4 }, /* Highest numbered vertical line (VARBEAMEN = 1) */ - { _T("VSSTOP"), 0xdff1CA, 2|4 }, /* Vert line for VBLANK start */ - { _T("VBSTRT"), 0xdff1CC, 2|4 }, /* Vert line for VBLANK start */ - { _T("VBSTOP"), 0xdff1CE, 2|4 }, /* Vert line for VBLANK stop */ -#if 0 - { _T("SPRHSTRT"), 0xdff1D0 }, /* UHRES sprite vertical start */ - { _T("SPRHSTOP"), 0xdff1D2 }, /* UHRES sprite vertical stop */ - { _T("BPLHSTRT"), 0xdff1D4 }, /* UHRES bit plane vertical stop */ - { _T("BPLHSTOP"), 0xdff1D6 }, /* UHRES bit plane vertical stop */ - { _T("HHPOSW"), 0xdff1D8 }, /* DUAL mode hires H beam counter write */ - { _T("HHPOSR"), 0xdff1DA }, /* DUAL mode hires H beam counter read */ -#endif - { _T("BEAMCON0"), 0xdff1DC, 2|4 }, /* Beam counter control register (SHRES,UHRES,PAL) */ - { _T("HSSTRT"), 0xdff1DE, 2|4 }, /* Horizontal sync start (VARHSY) */ - { _T("VSSTRT"), 0xdff1E0, 2|4 }, /* Vertical sync start (VARVSY) */ - { _T("HCENTER"), 0xdff1E2, 2|4 }, /* Horizontal pos for vsync on interlace */ - { _T("DIWHIGH"), 0xdff1E4, 2|4 }, /* Display window upper bits for start/stop */ -#if 0 - { _T("BPLHMOD"), 0xdff1E6 }, /* UHRES bit plane modulo */ - { _T("SPRHPTH"), 0xdff1E8 }, /* UHRES sprite pointer (high 5 bits) */ - { _T("SPRHPTL"), 0xdff1EA }, /* UHRES sprite pointer (low 15 bits) */ - { _T("BPLHPTH"), 0xdff1EC }, /* VRam (UHRES) bitplane pointer (hi 5 bits) */ - { _T("BPLHPTL"), 0xdff1EE }, /* VRam (UHRES) bitplane pointer (lo 15 bits) */ - { _T("RESERVED"), 0xdff1F0 }, /* Reserved (forever i guess!) */ - { _T("RESERVED"), 0xdff1F2 }, /* Reserved (forever i guess!) */ - { _T("RESERVED"), 0xdff1F4 }, /* Reserved (forever i guess!) */ - { _T("RESERVED"), 0xdff1F6 }, /* Reserved (forever i guess!) */ - { _T("RESERVED"), 0xdff1F8 }, /* Reserved (forever i guess!) */ - { _T("RESERVED"), 0xdff1Fa }, /* Reserved (forever i guess!) */ -#endif - { _T("FMODE"), 0xdff1FC, 2|8 }, /* Fetch mode register */ - { _T("NO-OP(NULL)"), 0xdff1FE }, /* Can also indicate last 2 or 3 refresh + { _T("DIWSTRT"), 0xdff08E, CD_WO }, /* Display window start (upper left vert-hor pos) */ + { _T("DIWSTOP"), 0xdff090, CD_WO }, /* Display window stop (lower right vert-hor pos) */ + { _T("DDFSTRT"), 0xdff092, CD_WO, { 0x00fc, 0x00fe, 0x00fe } }, /* Display bit plane data fetch start.hor pos */ + { _T("DDFSTOP"), 0xdff094, CD_WO, { 0x00fc, 0x00fe, 0x00fe } }, /* Display bit plane data fetch stop.hor pos */ + { _T("DMACON"), 0xdff096, CD_WO, { 0x87ff, 0x87ff, 0x87ff } }, /* DMA control write (clear or set) */ + { _T("CLXCON"), 0xdff098, CD_WO }, /* Collision control */ + { _T("INTENA"), 0xdff09A, CD_WO }, /* Interrupt enable bits (clear or set bits) */ + { _T("INTREQ"), 0xdff09C, CD_WO }, /* Interrupt request bits (clear or set bits) */ + { _T("ADKCON"), 0xdff09E, CD_WO }, /* Audio,disk,UART,control */ + { _T("AUD0LCH"), 0xdff0A0, CD_WO | CD_DMA_PTR }, /* Audio channel 0 location (high 5 bits) */ + { _T("AUD0LCL"), 0xdff0A2, CD_WO | CD_DMA_PTR }, /* Audio channel 0 location (low 15 bits) */ + { _T("AUD0LEN"), 0xdff0A4, CD_WO }, /* Audio channel 0 lentgh */ + { _T("AUD0PER"), 0xdff0A6, CD_WO }, /* Audio channel 0 period */ + { _T("AUD0VOL"), 0xdff0A8, CD_WO }, /* Audio channel 0 volume */ + { _T("AUD0DAT"), 0xdff0AA, CD_WO }, /* Audio channel 0 data */ + { _T("-"), 0xdff0AC, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff0AE, CD_NONE }, /* Unknown or Unused */ + { _T("AUD1LCH"), 0xdff0B0, CD_WO | CD_DMA_PTR }, /* Audio channel 1 location (high 5 bits) */ + { _T("AUD1LCL"), 0xdff0B2, CD_WO | CD_DMA_PTR }, /* Audio channel 1 location (low 15 bits) */ + { _T("AUD1LEN"), 0xdff0B4, CD_WO }, /* Audio channel 1 lentgh */ + { _T("AUD1PER"), 0xdff0B6, CD_WO }, /* Audio channel 1 period */ + { _T("AUD1VOL"), 0xdff0B8, CD_WO }, /* Audio channel 1 volume */ + { _T("AUD1DAT"), 0xdff0BA, CD_WO }, /* Audio channel 1 data */ + { _T("-"), 0xdff0BC, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff0BE, CD_NONE }, /* Unknown or Unused */ + { _T("AUD2LCH"), 0xdff0C0, CD_WO | CD_DMA_PTR }, /* Audio channel 2 location (high 5 bits) */ + { _T("AUD2LCL"), 0xdff0C2, CD_WO | CD_DMA_PTR }, /* Audio channel 2 location (low 15 bits) */ + { _T("AUD2LEN"), 0xdff0C4, CD_WO }, /* Audio channel 2 lentgh */ + { _T("AUD2PER"), 0xdff0C6, CD_WO }, /* Audio channel 2 period */ + { _T("AUD2VOL"), 0xdff0C8, CD_WO }, /* Audio channel 2 volume */ + { _T("AUD2DAT"), 0xdff0CA, CD_WO }, /* Audio channel 2 data */ + { _T("-"), 0xdff0CC, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff0CE, CD_NONE }, /* Unknown or Unused */ + { _T("AUD3LCH"), 0xdff0D0, CD_WO | CD_DMA_PTR }, /* Audio channel 3 location (high 5 bits) */ + { _T("AUD3LCL"), 0xdff0D2, CD_WO | CD_DMA_PTR }, /* Audio channel 3 location (low 15 bits) */ + { _T("AUD3LEN"), 0xdff0D4, CD_WO }, /* Audio channel 3 lentgh */ + { _T("AUD3PER"), 0xdff0D6, CD_WO }, /* Audio channel 3 period */ + { _T("AUD3VOL"), 0xdff0D8, CD_WO }, /* Audio channel 3 volume */ + { _T("AUD3DAT"), 0xdff0DA, CD_WO }, /* Audio channel 3 data */ + { _T("-"), 0xdff0DC, CD_NONE }, /* Unknown or Unused */ + { _T("-"), 0xdff0DE, CD_NONE }, /* Unknown or Unused */ + { _T("BPL1PTH"), 0xdff0E0, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 1 (high 5 bits) */ + { _T("BPL1PTL"), 0xdff0E2, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 1 (low 15 bits) */ + { _T("BPL2PTH"), 0xdff0E4, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 2 (high 5 bits) */ + { _T("BPL2PTL"), 0xdff0E6, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 2 (low 15 bits) */ + { _T("BPL3PTH"), 0xdff0E8, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 3 (high 5 bits) */ + { _T("BPL3PTL"), 0xdff0EA, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 3 (low 15 bits) */ + { _T("BPL4PTH"), 0xdff0EC, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 4 (high 5 bits) */ + { _T("BPL4PTL"), 0xdff0EE, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 4 (low 15 bits) */ + { _T("BPL5PTH"), 0xdff0F0, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 5 (high 5 bits) */ + { _T("BPL5PTL"), 0xdff0F2, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 5 (low 15 bits) */ + { _T("BPL6PTH"), 0xdff0F4, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 6 (high 5 bits) */ + { _T("BPL6PTL"), 0xdff0F6, CD_WO | CD_DMA_PTR }, /* Bit plane pointer 6 (low 15 bits) */ + { _T("BPL7PTH"), 0xdff0F8, CD_WO | CD_AGA | CD_DMA_PTR }, /* Bit plane pointer 7 (high 5 bits) */ + { _T("BPL7PTL"), 0xdff0FA, CD_WO | CD_AGA | CD_DMA_PTR }, /* Bit plane pointer 7 (low 15 bits) */ + { _T("BPL8PTH"), 0xdff0FC, CD_WO | CD_AGA | CD_DMA_PTR }, /* Bit plane pointer 8 (high 5 bits) */ + { _T("BPL8PTL"), 0xdff0FE, CD_WO | CD_AGA | CD_DMA_PTR }, /* Bit plane pointer 8 (low 15 bits) */ + { _T("BPLCON0"), 0xdff100, CD_WO, { ~0x00f1, ~0x00b0, ~0x0080 } }, /* Bit plane control reg (misc control bits) */ + { _T("BPLCON1"), 0xdff102, CD_WO }, /* Bit plane control reg (scroll val PF1,PF2) */ + { _T("BPLCON2"), 0xdff104, CD_WO, { 0x007f, 0x01ff, 0x7fff } }, /* Bit plane control reg (priority control) */ + { _T("BPLCON3"), 0xdff106, CD_WO | CD_ECS_DENISE, { 0x003f, 0x003f, 0xffff } }, /* Bit plane control reg (enhanced features) */ + { _T("BPL1MOD"), 0xdff108, CD_WO }, /* Bit plane modulo (odd planes,or active- fetch lines if bitplane scan-doubling is enabled */ + { _T("BPL2MOD"), 0xdff10A, CD_WO }, /* Bit plane modulo (even planes or inactive- fetch lines if bitplane scan-doubling is enabled */ + { _T("BPLCON4"), 0xdff10C, CD_WO | CD_AGA }, /* Bit plane control reg (bitplane and sprite masks) */ + { _T("CLXCON2"), 0xdff10e, CD_WO | CD_AGA }, /* Extended collision control reg */ + { _T("BPL1DAT"), 0xdff110, CD_WO }, /* Bit plane 1 data (parallel to serial con- vert) */ + { _T("BPL2DAT"), 0xdff112, CD_WO }, /* Bit plane 2 data (parallel to serial con- vert) */ + { _T("BPL3DAT"), 0xdff114, CD_WO }, /* Bit plane 3 data (parallel to serial con- vert) */ + { _T("BPL4DAT"), 0xdff116, CD_WO }, /* Bit plane 4 data (parallel to serial con- vert) */ + { _T("BPL5DAT"), 0xdff118, CD_WO }, /* Bit plane 5 data (parallel to serial con- vert) */ + { _T("BPL6DAT"), 0xdff11a, CD_WO }, /* Bit plane 6 data (parallel to serial con- vert) */ + { _T("BPL7DAT"), 0xdff11c, CD_WO | CD_AGA }, /* Bit plane 7 data (parallel to serial con- vert) */ + { _T("BPL8DAT"), 0xdff11e, CD_WO | CD_AGA }, /* Bit plane 8 data (parallel to serial con- vert) */ + { _T("SPR0PTH"), 0xdff120, CD_WO | CD_DMA_PTR }, /* Sprite 0 pointer (high 5 bits) */ + { _T("SPR0PTL"), 0xdff122, CD_WO | CD_DMA_PTR }, /* Sprite 0 pointer (low 15 bits) */ + { _T("SPR1PTH"), 0xdff124, CD_WO | CD_DMA_PTR }, /* Sprite 1 pointer (high 5 bits) */ + { _T("SPR1PTL"), 0xdff126, CD_WO | CD_DMA_PTR }, /* Sprite 1 pointer (low 15 bits) */ + { _T("SPR2PTH"), 0xdff128, CD_WO | CD_DMA_PTR }, /* Sprite 2 pointer (high 5 bits) */ + { _T("SPR2PTL"), 0xdff12A, CD_WO | CD_DMA_PTR }, /* Sprite 2 pointer (low 15 bits) */ + { _T("SPR3PTH"), 0xdff12C, CD_WO | CD_DMA_PTR }, /* Sprite 3 pointer (high 5 bits) */ + { _T("SPR3PTL"), 0xdff12E, CD_WO | CD_DMA_PTR }, /* Sprite 3 pointer (low 15 bits) */ + { _T("SPR4PTH"), 0xdff130, CD_WO | CD_DMA_PTR }, /* Sprite 4 pointer (high 5 bits) */ + { _T("SPR4PTL"), 0xdff132, CD_WO | CD_DMA_PTR }, /* Sprite 4 pointer (low 15 bits) */ + { _T("SPR5PTH"), 0xdff134, CD_WO | CD_DMA_PTR }, /* Sprite 5 pointer (high 5 bits) */ + { _T("SPR5PTL"), 0xdff136, CD_WO | CD_DMA_PTR }, /* Sprite 5 pointer (low 15 bits) */ + { _T("SPR6PTH"), 0xdff138, CD_WO | CD_DMA_PTR }, /* Sprite 6 pointer (high 5 bits) */ + { _T("SPR6PTL"), 0xdff13A, CD_WO | CD_DMA_PTR }, /* Sprite 6 pointer (low 15 bits) */ + { _T("SPR7PTH"), 0xdff13C, CD_WO | CD_DMA_PTR }, /* Sprite 7 pointer (high 5 bits) */ + { _T("SPR7PTL"), 0xdff13E, CD_WO | CD_DMA_PTR }, /* Sprite 7 pointer (low 15 bits) */ + { _T("SPR0POS"), 0xdff140, CD_WO }, /* Sprite 0 vert-horiz start pos data */ + { _T("SPR0CTL"), 0xdff142, CD_WO }, /* Sprite 0 position and control data */ + { _T("SPR0DATA"), 0xdff144, CD_WO }, /* Sprite 0 image data register A */ + { _T("SPR0DATB"), 0xdff146, CD_WO }, /* Sprite 0 image data register B */ + { _T("SPR1POS"), 0xdff148, CD_WO }, /* Sprite 1 vert-horiz start pos data */ + { _T("SPR1CTL"), 0xdff14A, CD_WO }, /* Sprite 1 position and control data */ + { _T("SPR1DATA"), 0xdff14C, CD_WO }, /* Sprite 1 image data register A */ + { _T("SPR1DATB"), 0xdff14E, CD_WO }, /* Sprite 1 image data register B */ + { _T("SPR2POS"), 0xdff150, CD_WO }, /* Sprite 2 vert-horiz start pos data */ + { _T("SPR2CTL"), 0xdff152, CD_WO }, /* Sprite 2 position and control data */ + { _T("SPR2DATA"), 0xdff154, CD_WO }, /* Sprite 2 image data register A */ + { _T("SPR2DATB"), 0xdff156, CD_WO }, /* Sprite 2 image data register B */ + { _T("SPR3POS"), 0xdff158, CD_WO }, /* Sprite 3 vert-horiz start pos data */ + { _T("SPR3CTL"), 0xdff15A, CD_WO }, /* Sprite 3 position and control data */ + { _T("SPR3DATA"), 0xdff15C, CD_WO }, /* Sprite 3 image data register A */ + { _T("SPR3DATB"), 0xdff15E, CD_WO }, /* Sprite 3 image data register B */ + { _T("SPR4POS"), 0xdff160, CD_WO }, /* Sprite 4 vert-horiz start pos data */ + { _T("SPR4CTL"), 0xdff162, CD_WO }, /* Sprite 4 position and control data */ + { _T("SPR4DATA"), 0xdff164, CD_WO }, /* Sprite 4 image data register A */ + { _T("SPR4DATB"), 0xdff166, CD_WO }, /* Sprite 4 image data register B */ + { _T("SPR5POS"), 0xdff168, CD_WO }, /* Sprite 5 vert-horiz start pos data */ + { _T("SPR5CTL"), 0xdff16A, CD_WO }, /* Sprite 5 position and control data */ + { _T("SPR5DATA"), 0xdff16C, CD_WO }, /* Sprite 5 image data register A */ + { _T("SPR5DATB"), 0xdff16E, CD_WO }, /* Sprite 5 image data register B */ + { _T("SPR6POS"), 0xdff170, CD_WO }, /* Sprite 6 vert-horiz start pos data */ + { _T("SPR6CTL"), 0xdff172, CD_WO }, /* Sprite 6 position and control data */ + { _T("SPR6DATA"), 0xdff174, CD_WO }, /* Sprite 6 image data register A */ + { _T("SPR6DATB"), 0xdff176, CD_WO }, /* Sprite 6 image data register B */ + { _T("SPR7POS"), 0xdff178, CD_WO }, /* Sprite 7 vert-horiz start pos data */ + { _T("SPR7CTL"), 0xdff17A, CD_WO }, /* Sprite 7 position and control data */ + { _T("SPR7DATA"), 0xdff17C, CD_WO }, /* Sprite 7 image data register A */ + { _T("SPR7DATB"), 0xdff17E, CD_WO }, /* Sprite 7 image data register B */ + { _T("COLOR00"), 0xdff180, CD_WO | CD_COLOR }, /* Color table 00 */ + { _T("COLOR01"), 0xdff182, CD_WO | CD_COLOR }, /* Color table 01 */ + { _T("COLOR02"), 0xdff184, CD_WO | CD_COLOR }, /* Color table 02 */ + { _T("COLOR03"), 0xdff186, CD_WO | CD_COLOR }, /* Color table 03 */ + { _T("COLOR04"), 0xdff188, CD_WO | CD_COLOR }, /* Color table 04 */ + { _T("COLOR05"), 0xdff18A, CD_WO | CD_COLOR }, /* Color table 05 */ + { _T("COLOR06"), 0xdff18C, CD_WO | CD_COLOR }, /* Color table 06 */ + { _T("COLOR07"), 0xdff18E, CD_WO | CD_COLOR }, /* Color table 07 */ + { _T("COLOR08"), 0xdff190, CD_WO | CD_COLOR }, /* Color table 08 */ + { _T("COLOR09"), 0xdff192, CD_WO | CD_COLOR }, /* Color table 09 */ + { _T("COLOR10"), 0xdff194, CD_WO | CD_COLOR }, /* Color table 10 */ + { _T("COLOR11"), 0xdff196, CD_WO | CD_COLOR }, /* Color table 11 */ + { _T("COLOR12"), 0xdff198, CD_WO | CD_COLOR }, /* Color table 12 */ + { _T("COLOR13"), 0xdff19A, CD_WO | CD_COLOR }, /* Color table 13 */ + { _T("COLOR14"), 0xdff19C, CD_WO | CD_COLOR }, /* Color table 14 */ + { _T("COLOR15"), 0xdff19E, CD_WO | CD_COLOR }, /* Color table 15 */ + { _T("COLOR16"), 0xdff1A0, CD_WO | CD_COLOR }, /* Color table 16 */ + { _T("COLOR17"), 0xdff1A2, CD_WO | CD_COLOR }, /* Color table 17 */ + { _T("COLOR18"), 0xdff1A4, CD_WO | CD_COLOR }, /* Color table 18 */ + { _T("COLOR19"), 0xdff1A6, CD_WO | CD_COLOR }, /* Color table 19 */ + { _T("COLOR20"), 0xdff1A8, CD_WO | CD_COLOR }, /* Color table 20 */ + { _T("COLOR21"), 0xdff1AA, CD_WO | CD_COLOR }, /* Color table 21 */ + { _T("COLOR22"), 0xdff1AC, CD_WO | CD_COLOR }, /* Color table 22 */ + { _T("COLOR23"), 0xdff1AE, CD_WO | CD_COLOR }, /* Color table 23 */ + { _T("COLOR24"), 0xdff1B0, CD_WO | CD_COLOR }, /* Color table 24 */ + { _T("COLOR25"), 0xdff1B2, CD_WO | CD_COLOR }, /* Color table 25 */ + { _T("COLOR26"), 0xdff1B4, CD_WO | CD_COLOR }, /* Color table 26 */ + { _T("COLOR27"), 0xdff1B6, CD_WO | CD_COLOR }, /* Color table 27 */ + { _T("COLOR28"), 0xdff1B8, CD_WO | CD_COLOR }, /* Color table 28 */ + { _T("COLOR29"), 0xdff1BA, CD_WO | CD_COLOR }, /* Color table 29 */ + { _T("COLOR30"), 0xdff1BC, CD_WO | CD_COLOR }, /* Color table 30 */ + { _T("COLOR31"), 0xdff1BE, CD_WO | CD_COLOR }, /* Color table 31 */ + { _T("HTOTAL"), 0xdff1C0, CD_WO | CD_ECS_AGNUS }, /* Highest number count in horiz line (VARBEAMEN = 1) */ + { _T("HSSTOP"), 0xdff1C2, CD_WO | CD_ECS_DENISE }, /* Horiz line pos for HSYNC stop */ + { _T("HBSTRT"), 0xdff1C4, CD_WO | CD_ECS_DENISE }, /* Horiz line pos for HBLANK start */ + { _T("HBSTOP"), 0xdff1C6, CD_WO | CD_ECS_DENISE }, /* Horiz line pos for HBLANK stop */ + { _T("VTOTAL"), 0xdff1C8, CD_WO | CD_ECS_AGNUS }, /* Highest numbered vertical line (VARBEAMEN = 1) */ + { _T("VSSTOP"), 0xdff1CA, CD_WO | CD_ECS_AGNUS }, /* Vert line for VBLANK start */ + { _T("VBSTRT"), 0xdff1CC, CD_WO | CD_ECS_AGNUS }, /* Vert line for VBLANK start */ + { _T("VBSTOP"), 0xdff1CE, CD_WO | CD_ECS_AGNUS }, /* Vert line for VBLANK stop */ + { _T("-"), 0xdff1D0, CD_NONE }, /* UHRES sprite vertical start */ + { _T("-"), 0xdff1D2, CD_NONE }, /* UHRES sprite vertical stop */ + { _T("-"), 0xdff1D4, CD_NONE }, /* UHRES bit plane vertical stop */ + { _T("-"), 0xdff1D6, CD_NONE }, /* UHRES bit plane vertical stop */ + { _T("-"), 0xdff1D8, CD_NONE }, /* DUAL mode hires H beam counter write */ + { _T("-"), 0xdff1DA, CD_NONE }, /* DUAL mode hires H beam counter read */ + { _T("BEAMCON0"), 0xdff1DC, CD_WO | CD_ECS_AGNUS }, /* Beam counter control register (SHRES,UHRES,PAL) */ + { _T("HSSTRT"), 0xdff1DE, CD_WO | CD_ECS_DENISE }, /* Horizontal sync start (VARHSY) */ + { _T("VSSTRT"), 0xdff1E0, CD_WO | CD_ECS_DENISE }, /* Vertical sync start (VARVSY) */ + { _T("HCENTER"), 0xdff1E2, CD_WO | CD_ECS_DENISE }, /* Horizontal pos for vsync on interlace */ + { _T("DIWHIGH"), 0xdff1E4, CD_WO | CD_ECS_AGNUS | CD_ECS_DENISE }, /* Display window upper bits for start/stop */ + { _T("-"), 0xdff1E6, CD_NONE }, /* UHRES bit plane modulo */ + { _T("-"), 0xdff1E8, CD_NONE }, /* UHRES sprite pointer (high 5 bits) */ + { _T("-"), 0xdff1EA, CD_NONE }, /* UHRES sprite pointer (low 15 bits) */ + { _T("-"), 0xdff1EC, CD_NONE }, /* VRam (UHRES) bitplane pointer (hi 5 bits) */ + { _T("-"), 0xdff1EE, CD_NONE }, /* VRam (UHRES) bitplane pointer (lo 15 bits) */ + { _T("-"), 0xdff1F0, CD_NONE }, /* Reserved (forever i guess!) */ + { _T("-"), 0xdff1F2, CD_NONE }, /* Reserved (forever i guess!) */ + { _T("-"), 0xdff1F4, CD_NONE }, /* Reserved (forever i guess!) */ + { _T("-"), 0xdff1F6, CD_NONE }, /* Reserved (forever i guess!) */ + { _T("-"), 0xdff1F8, CD_NONE }, /* Reserved (forever i guess!) */ + { _T("-"), 0xdff1Fa, CD_NONE }, /* Reserved (forever i guess!) */ + { _T("FMODE"), 0xdff1FC, CD_WO | CD_AGA }, /* Fetch mode register */ + { _T("NULL"), 0xdff1FE, CD_WO }, /* Can also indicate last 2 or 3 refresh cycles or the restart of the COPPER after lockup.*/ { NULL } }; diff --git a/include/debug.h b/include/debug.h index 93d83e4e..73e9dbf1 100644 --- a/include/debug.h +++ b/include/debug.h @@ -54,15 +54,18 @@ extern void mmu_disasm (uaecptr pc, int lines); extern int debug_read_memory_16 (uaecptr addr); extern int debug_peek_memory_16 (uaecptr addr); extern int debug_read_memory_8 (uaecptr addr); -extern int debug_peek_memory_8 (uaecptr addr); extern int debug_write_memory_16 (uaecptr addr, uae_u16 v); extern int debug_write_memory_8 (uaecptr addr, uae_u8 v); extern bool debug_enforcer(void); extern int debug_safe_addr(uaecptr addr, int size); +extern void debug_invalid_reg(int reg, int size, uae_u16 val); +extern void debug_check_reg(uae_u32 addr, int write, uae_u16 v); +extern int memwatch_access_validator; extern void debug_init_trainer(const TCHAR*); extern void debug_trainer_match(void); extern bool debug_opcode_watch; +extern bool debug_trainer_event(int evt, int state); #define BREAKPOINT_TOTAL 20 #define BREAKPOINT_REG_Dx 0 @@ -160,8 +163,8 @@ extern struct memwatch_node mwnodes[MEMWATCH_TOTAL]; extern void memwatch_dump2 (TCHAR *buf, int bufsize, int num); -uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg); -uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg); +uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg); +uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg, int ptrreg); uae_u16 debug_wputpeekdma_chipset (uaecptr addr, uae_u32 v, uae_u32 mask, int reg); void debug_lgetpeek (uaecptr addr, uae_u32 v); void debug_wgetpeek (uaecptr addr, uae_u32 v); diff --git a/include/identify.h b/include/identify.h index ff027706..ea465bd2 100644 --- a/include/identify.h +++ b/include/identify.h @@ -16,22 +16,22 @@ struct mem_labels uae_u32 adr; }; +#define CD_WO 1 +#define CD_ECS_AGNUS 2 +#define CD_ECS_DENISE 4 +#define CD_AGA 8 +#define CD_NONE 16 +#define CD_DMA_PTR 32 +#define CD_COLOR 64 + struct customData { const TCHAR *name; uae_u32 adr; - uae_u8 rw, special; + int special; + uae_u16 mask[3]; }; -/* - special: - - 1: DMA pointer high word - 2: DMA pointer low word - 4: ECS/AGA only - 8: AGA only -*/ - extern const struct mem_labels mem_labels[]; extern const struct mem_labels int_labels[]; extern const struct mem_labels trap_labels[]; diff --git a/include/inputdevice.h b/include/inputdevice.h index 9ffccd6d..81f257a6 100644 --- a/include/inputdevice.h +++ b/include/inputdevice.h @@ -358,6 +358,7 @@ extern int jsem_iskbdjoy (int port, const struct uae_prefs *p); extern int inputdevice_uaelib (const TCHAR *, const TCHAR *); extern int inputdevice_uaelib(const TCHAR *s, int parm, int max, bool autofire); extern int handle_custom_event (const TCHAR *custom, int append); +extern int inputdevice_geteventid(const TCHAR *s); extern int inputdevice_testread (int*, int*, int*, bool); extern int inputdevice_istest (void); diff --git a/inputdevice.cpp b/inputdevice.cpp index a3904ec7..9bfec3fe 100644 --- a/inputdevice.cpp +++ b/inputdevice.cpp @@ -206,6 +206,20 @@ static int isdevice (struct uae_input_device *id) static void check_enable(int ei); +int inputdevice_geteventid(const TCHAR *s) +{ + for (int i = 1; events[i].name; i++) { + const struct inputevent *ie = &events[i]; + if (!_tcscmp(ie->confname, s)) + return i; + } + for (int i = 0; akss[i].name; i++) { + if (!_tcscmp(s, akss[i].name)) + return i + AKS_FIRST; + } + return 0; +} + int inputdevice_uaelib (const TCHAR *s, const TCHAR *parm) { //write_log(_T("%s: %s\n"), s, parm); @@ -4685,6 +4699,14 @@ static int handle_input_event2(int nr, int state, int max, int flags, int extra) isaks = true; } + if (isaks) { + if (debug_trainer_event(ie->data, state)) + return 0; + } else { + if (debug_trainer_event(nr, state)) + return 0; + } + if (!isaks) { if (input_record && input_record != INPREC_RECORD_PLAYING) inprec_recordevent (nr, state, max, autofire); diff --git a/memory.cpp b/memory.cpp index 3494cb7f..7e75d23b 100644 --- a/memory.cpp +++ b/memory.cpp @@ -240,7 +240,7 @@ static void dummylog (int rw, uaecptr addr, int size, uae_u32 val, int ins) return; if (debugmem_extinvalidmem(addr, val, rw ? size : -size)) return; - if (illegal_count >= MAX_ILG && MAX_ILG > 0) + if ((illegal_count >= MAX_ILG && MAX_ILG > 0) && !memwatch_access_validator) return; if (MAX_ILG >= 0) illegal_count++; -- 2.47.3