From 5068c1a5f186ea66b73427c98755783d86b0ddcb Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Sat, 11 Jan 2025 19:54:08 +0200 Subject: [PATCH] Fix undefined shifts --- cpuemu_0.cpp | 24 ++++++++++++------------ cpuemu_20.cpp | 24 ++++++++++++------------ cpuemu_21.cpp | 24 ++++++++++++------------ cpuemu_22.cpp | 24 ++++++++++++------------ cpuemu_23.cpp | 24 ++++++++++++------------ cpuemu_24.cpp | 24 ++++++++++++------------ cpuemu_31.cpp | 24 ++++++++++++------------ cpuemu_32.cpp | 24 ++++++++++++------------ cpuemu_33.cpp | 24 ++++++++++++------------ cpuemu_34.cpp | 24 ++++++++++++------------ cpuemu_35.cpp | 24 ++++++++++++------------ cpuemu_40.cpp | 24 ++++++++++++------------ cpuemu_50.cpp | 24 ++++++++++++------------ 13 files changed, 156 insertions(+), 156 deletions(-) diff --git a/cpuemu_0.cpp b/cpuemu_0.cpp index a1f821b7..5ebbbf7f 100644 --- a/cpuemu_0.cpp +++ b/cpuemu_0.cpp @@ -37636,7 +37636,7 @@ uae_u32 REGPARAM2 op_e8c0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37831,7 +37831,7 @@ uae_u32 REGPARAM2 op_e9c0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -38034,14 +38034,14 @@ uae_u32 REGPARAM2 op_eac0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16); } @@ -38192,7 +38192,7 @@ uae_u32 REGPARAM2 op_ebc0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -38395,14 +38395,14 @@ uae_u32 REGPARAM2 op_ecc0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16); } @@ -38554,7 +38554,7 @@ uae_u32 REGPARAM2 op_edc0_0_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -38780,14 +38780,14 @@ uae_u32 REGPARAM2 op_eec0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16); } @@ -38938,7 +38938,7 @@ uae_u32 REGPARAM2 op_efc0_0_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -38948,7 +38948,7 @@ uae_u32 REGPARAM2 op_efc0_0_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16); } diff --git a/cpuemu_20.cpp b/cpuemu_20.cpp index 6e6aaa6d..e6fc1305 100644 --- a/cpuemu_20.cpp +++ b/cpuemu_20.cpp @@ -39377,7 +39377,7 @@ uae_u32 REGPARAM2 op_e8c0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -39580,7 +39580,7 @@ uae_u32 REGPARAM2 op_e9c0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -39791,14 +39791,14 @@ uae_u32 REGPARAM2 op_eac0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_020_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -39955,7 +39955,7 @@ uae_u32 REGPARAM2 op_ebc0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -40166,14 +40166,14 @@ uae_u32 REGPARAM2 op_ecc0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_020_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -40331,7 +40331,7 @@ uae_u32 REGPARAM2 op_edc0_20_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40565,14 +40565,14 @@ uae_u32 REGPARAM2 op_eec0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_020_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -40729,7 +40729,7 @@ uae_u32 REGPARAM2 op_efc0_20_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40739,7 +40739,7 @@ uae_u32 REGPARAM2 op_efc0_20_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_020_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; diff --git a/cpuemu_21.cpp b/cpuemu_21.cpp index ca97a670..85b7900c 100644 --- a/cpuemu_21.cpp +++ b/cpuemu_21.cpp @@ -42622,7 +42622,7 @@ void REGPARAM2 op_e8c0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -42841,7 +42841,7 @@ void REGPARAM2 op_e9c0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -43068,14 +43068,14 @@ void REGPARAM2 op_eac0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce020_prefetch_opcode(4); m68k_incpci(4); return; @@ -43244,7 +43244,7 @@ void REGPARAM2 op_ebc0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -43471,14 +43471,14 @@ void REGPARAM2 op_ecc0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce020_prefetch_opcode(4); m68k_incpci(4); return; @@ -43648,7 +43648,7 @@ void REGPARAM2 op_edc0_21_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -43898,14 +43898,14 @@ void REGPARAM2 op_eec0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce020_prefetch_opcode(4); m68k_incpci(4); return; @@ -44074,7 +44074,7 @@ void REGPARAM2 op_efc0_21_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -44084,7 +44084,7 @@ void REGPARAM2 op_efc0_21_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce020_prefetch_opcode(4); m68k_incpci(4); return; diff --git a/cpuemu_22.cpp b/cpuemu_22.cpp index a5b3f117..ce9603fe 100644 --- a/cpuemu_22.cpp +++ b/cpuemu_22.cpp @@ -39378,7 +39378,7 @@ uae_u32 REGPARAM2 op_e8c0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -39581,7 +39581,7 @@ uae_u32 REGPARAM2 op_e9c0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -39792,14 +39792,14 @@ uae_u32 REGPARAM2 op_eac0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_030_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -39956,7 +39956,7 @@ uae_u32 REGPARAM2 op_ebc0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -40167,14 +40167,14 @@ uae_u32 REGPARAM2 op_ecc0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_030_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -40332,7 +40332,7 @@ uae_u32 REGPARAM2 op_edc0_22_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40566,14 +40566,14 @@ uae_u32 REGPARAM2 op_eec0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_030_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -40730,7 +40730,7 @@ uae_u32 REGPARAM2 op_efc0_22_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40740,7 +40740,7 @@ uae_u32 REGPARAM2 op_efc0_22_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_030_prefetch(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; diff --git a/cpuemu_23.cpp b/cpuemu_23.cpp index 75fafb4d..8a1fed69 100644 --- a/cpuemu_23.cpp +++ b/cpuemu_23.cpp @@ -42623,7 +42623,7 @@ void REGPARAM2 op_e8c0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -42842,7 +42842,7 @@ void REGPARAM2 op_e9c0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -43069,14 +43069,14 @@ void REGPARAM2 op_eac0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce030_prefetch_opcode(4); m68k_incpci(4); return; @@ -43245,7 +43245,7 @@ void REGPARAM2 op_ebc0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -43472,14 +43472,14 @@ void REGPARAM2 op_ecc0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce030_prefetch_opcode(4); m68k_incpci(4); return; @@ -43649,7 +43649,7 @@ void REGPARAM2 op_edc0_23_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -43899,14 +43899,14 @@ void REGPARAM2 op_eec0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce030_prefetch_opcode(4); m68k_incpci(4); return; @@ -44075,7 +44075,7 @@ void REGPARAM2 op_efc0_23_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -44085,7 +44085,7 @@ void REGPARAM2 op_efc0_23_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_word_ce030_prefetch_opcode(4); m68k_incpci(4); return; diff --git a/cpuemu_24.cpp b/cpuemu_24.cpp index eb179dec..8eb306d7 100644 --- a/cpuemu_24.cpp +++ b/cpuemu_24.cpp @@ -37545,7 +37545,7 @@ void REGPARAM2 op_e8c0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37740,7 +37740,7 @@ void REGPARAM2 op_e9c0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37943,14 +37943,14 @@ void REGPARAM2 op_eac0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return; } @@ -38101,7 +38101,7 @@ void REGPARAM2 op_ebc0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -38304,14 +38304,14 @@ void REGPARAM2 op_ecc0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return; } @@ -38463,7 +38463,7 @@ void REGPARAM2 op_edc0_24_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -38689,14 +38689,14 @@ void REGPARAM2 op_eec0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return; } @@ -38847,7 +38847,7 @@ void REGPARAM2 op_efc0_24_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -38857,7 +38857,7 @@ void REGPARAM2 op_efc0_24_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return; } diff --git a/cpuemu_31.cpp b/cpuemu_31.cpp index 4256ff0d..4fee5a36 100644 --- a/cpuemu_31.cpp +++ b/cpuemu_31.cpp @@ -40604,7 +40604,7 @@ uae_u32 REGPARAM2 op_e8c0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40799,7 +40799,7 @@ uae_u32 REGPARAM2 op_e9c0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -41002,14 +41002,14 @@ uae_u32 REGPARAM2 op_eac0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -41160,7 +41160,7 @@ uae_u32 REGPARAM2 op_ebc0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -41363,14 +41363,14 @@ uae_u32 REGPARAM2 op_ecc0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -41522,7 +41522,7 @@ uae_u32 REGPARAM2 op_edc0_31_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -41748,14 +41748,14 @@ uae_u32 REGPARAM2 op_eec0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -41906,7 +41906,7 @@ uae_u32 REGPARAM2 op_efc0_31_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -41916,7 +41916,7 @@ uae_u32 REGPARAM2 op_efc0_31_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } diff --git a/cpuemu_32.cpp b/cpuemu_32.cpp index 28d19a56..432f370f 100644 --- a/cpuemu_32.cpp +++ b/cpuemu_32.cpp @@ -41364,7 +41364,7 @@ uae_u32 REGPARAM2 op_e8c0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -41559,7 +41559,7 @@ uae_u32 REGPARAM2 op_e9c0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -41762,14 +41762,14 @@ uae_u32 REGPARAM2 op_eac0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -41920,7 +41920,7 @@ uae_u32 REGPARAM2 op_ebc0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -42123,14 +42123,14 @@ uae_u32 REGPARAM2 op_ecc0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -42282,7 +42282,7 @@ uae_u32 REGPARAM2 op_edc0_32_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -42508,14 +42508,14 @@ uae_u32 REGPARAM2 op_eec0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -42666,7 +42666,7 @@ uae_u32 REGPARAM2 op_efc0_32_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -42676,7 +42676,7 @@ uae_u32 REGPARAM2 op_efc0_32_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } diff --git a/cpuemu_33.cpp b/cpuemu_33.cpp index 2d0a1663..069fb662 100644 --- a/cpuemu_33.cpp +++ b/cpuemu_33.cpp @@ -38944,7 +38944,7 @@ uae_u32 REGPARAM2 op_e8c0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -39139,7 +39139,7 @@ uae_u32 REGPARAM2 op_e9c0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -39342,14 +39342,14 @@ uae_u32 REGPARAM2 op_eac0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -39500,7 +39500,7 @@ uae_u32 REGPARAM2 op_ebc0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -39703,14 +39703,14 @@ uae_u32 REGPARAM2 op_ecc0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -39862,7 +39862,7 @@ uae_u32 REGPARAM2 op_edc0_33_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40088,14 +40088,14 @@ uae_u32 REGPARAM2 op_eec0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } @@ -40246,7 +40246,7 @@ uae_u32 REGPARAM2 op_efc0_33_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -40256,7 +40256,7 @@ uae_u32 REGPARAM2 op_efc0_33_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; } diff --git a/cpuemu_34.cpp b/cpuemu_34.cpp index bd48c322..dd66fab7 100644 --- a/cpuemu_34.cpp +++ b/cpuemu_34.cpp @@ -43173,7 +43173,7 @@ uae_u32 REGPARAM2 op_e8c0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -43376,7 +43376,7 @@ uae_u32 REGPARAM2 op_e9c0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -43587,14 +43587,14 @@ uae_u32 REGPARAM2 op_eac0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -43751,7 +43751,7 @@ uae_u32 REGPARAM2 op_ebc0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -43962,14 +43962,14 @@ uae_u32 REGPARAM2 op_ecc0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -44127,7 +44127,7 @@ uae_u32 REGPARAM2 op_edc0_34_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -44361,14 +44361,14 @@ uae_u32 REGPARAM2 op_eec0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; @@ -44525,7 +44525,7 @@ uae_u32 REGPARAM2 op_efc0_34_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -44535,7 +44535,7 @@ uae_u32 REGPARAM2 op_efc0_34_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4; diff --git a/cpuemu_35.cpp b/cpuemu_35.cpp index f39c2d13..608925e6 100644 --- a/cpuemu_35.cpp +++ b/cpuemu_35.cpp @@ -46416,7 +46416,7 @@ void REGPARAM2 op_e8c0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -46635,7 +46635,7 @@ void REGPARAM2 op_e9c0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -46862,14 +46862,14 @@ void REGPARAM2 op_eac0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return; @@ -47038,7 +47038,7 @@ void REGPARAM2 op_ebc0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -47265,14 +47265,14 @@ void REGPARAM2 op_ecc0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return; @@ -47442,7 +47442,7 @@ void REGPARAM2 op_edc0_35_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -47692,14 +47692,14 @@ void REGPARAM2 op_eec0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return; @@ -47868,7 +47868,7 @@ void REGPARAM2 op_efc0_35_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -47878,7 +47878,7 @@ void REGPARAM2 op_efc0_35_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; regs.irc = get_iword_mmu030c_opcode_state(4); m68k_incpci(4); return; diff --git a/cpuemu_40.cpp b/cpuemu_40.cpp index f42c86a6..ee691796 100644 --- a/cpuemu_40.cpp +++ b/cpuemu_40.cpp @@ -35926,7 +35926,7 @@ uae_u32 REGPARAM2 op_e8c0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -36113,7 +36113,7 @@ uae_u32 REGPARAM2 op_e9c0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -36308,14 +36308,14 @@ uae_u32 REGPARAM2 op_eac0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } @@ -36460,7 +36460,7 @@ uae_u32 REGPARAM2 op_ebc0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -36655,14 +36655,14 @@ uae_u32 REGPARAM2 op_ecc0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } @@ -36808,7 +36808,7 @@ uae_u32 REGPARAM2 op_edc0_40_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37026,14 +37026,14 @@ uae_u32 REGPARAM2 op_eec0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } @@ -37178,7 +37178,7 @@ uae_u32 REGPARAM2 op_efc0_40_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37188,7 +37188,7 @@ uae_u32 REGPARAM2 op_efc0_40_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } diff --git a/cpuemu_50.cpp b/cpuemu_50.cpp index 895b10e4..8f3b7453 100644 --- a/cpuemu_50.cpp +++ b/cpuemu_50.cpp @@ -35980,7 +35980,7 @@ uae_u32 REGPARAM2 op_e8c0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -36167,7 +36167,7 @@ uae_u32 REGPARAM2 op_e9c0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -36362,14 +36362,14 @@ uae_u32 REGPARAM2 op_eac0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = tmp ^ (0xffffffffu >> (32 - width)); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } @@ -36514,7 +36514,7 @@ uae_u32 REGPARAM2 op_ebc0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp = (uae_s32)tmp >> (32 - width); @@ -36709,14 +36709,14 @@ uae_u32 REGPARAM2 op_ecc0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0; tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } @@ -36862,7 +36862,7 @@ uae_u32 REGPARAM2 op_edc0_50_ff(uae_u32 opcode) uae_u32 offset2 = offset; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37080,14 +37080,14 @@ uae_u32 REGPARAM2 op_eec0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0); tmp = 0xffffffffu >> (32 - width); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } @@ -37232,7 +37232,7 @@ uae_u32 REGPARAM2 op_efc0_50_ff(uae_u32 opcode) int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1; uae_u32 tmp = m68k_dreg(regs, dstreg); offset &= 0x1f; - tmp = (tmp << offset) | (tmp >> (32 - offset)); + if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset)); bdata[0] = tmp & ((1 << (32 - width)) - 1); SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0); tmp >>= (32 - width); @@ -37242,7 +37242,7 @@ uae_u32 REGPARAM2 op_efc0_50_ff(uae_u32 opcode) SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0); SET_ZFLG(tmp == 0); tmp = bdata[0] | (tmp << (32 - width)); - m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset)); + m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp; m68k_incpc(4); return 0; } -- 2.47.3