From 681110628414f4c90be7bb1c6b48d630b246666f Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Mon, 22 Oct 2018 21:27:25 +0300 Subject: [PATCH] 68030 MMU datacache mode LRMW support. --- cpummu30.cpp | 52 ++++++++++++++++++++++++++++-------------------- include/newcpu.h | 2 ++ newcpu.cpp | 24 ++++++++++++++-------- 3 files changed, 48 insertions(+), 30 deletions(-) diff --git a/cpummu30.cpp b/cpummu30.cpp index 7f0cf982..77f0dde6 100644 --- a/cpummu30.cpp +++ b/cpummu30.cpp @@ -3001,17 +3001,21 @@ void m68k_do_rte_mmu030c (uaecptr a7) if (read) { uae_u32 val = 0; - switch (size) - { - case sz_byte: - val = read_dcache030_bget(addr, fc); - break; - case sz_word: - val = read_dcache030_wget(addr, fc); - break; - case sz_long: - val = read_dcache030_lget(addr, fc); - break; + if (ssw & MMU030_SSW_RM) { + val = read_dcache030_lrmw_mmu_fcx(addr, size, fc); + } else { + switch (size) + { + case sz_byte: + val = read_dcache030_bget(addr, fc); + break; + case sz_word: + val = read_dcache030_wget(addr, fc); + break; + case sz_long: + val = read_dcache030_lget(addr, fc); + break; + } } if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) { mmu030_data_buffer = val; @@ -3027,17 +3031,21 @@ void m68k_do_rte_mmu030c (uaecptr a7) val = mdata; else val = mmu030_ad[idxsize].val; - switch (size) - { - case sz_byte: - write_dcache030_bput(addr, val, fc); - break; - case sz_word: - write_dcache030_wput(addr, val, fc); - break; - case sz_long: - write_dcache030_lput(addr, val, fc); - break; + if (ssw & MMU030_SSW_RM) { + write_dcache030_lrmw_mmu_fcx(addr, val, size, fc); + } else { + switch (size) + { + case sz_byte: + write_dcache030_bput(addr, val, fc); + break; + case sz_word: + write_dcache030_wput(addr, val, fc); + break; + case sz_long: + write_dcache030_lput(addr, val, fc); + break; + } } if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) { mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM2; diff --git a/include/newcpu.h b/include/newcpu.h index 572f41bb..f139275d 100644 --- a/include/newcpu.h +++ b/include/newcpu.h @@ -595,7 +595,9 @@ extern uae_u32 read_dcache030_mmu_bget(uaecptr); extern uae_u32 read_dcache030_mmu_wget(uaecptr); extern uae_u32 read_dcache030_mmu_lget(uaecptr); extern void write_dcache030_lrmw_mmu(uaecptr, uae_u32, uae_u32); +extern void write_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, uae_u32, int); extern uae_u32 read_dcache030_lrmw_mmu(uaecptr, uae_u32); +extern uae_u32 read_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, int); extern void check_t0_trace(void); extern uae_u32 get_word_icache030(uaecptr addr); diff --git a/newcpu.cpp b/newcpu.cpp index eadf1018..63ff67d1 100644 --- a/newcpu.cpp +++ b/newcpu.cpp @@ -9994,15 +9994,15 @@ void write_dcache030_mmu_lput(uaecptr addr, uae_u32 val) write_dcache030_lput(addr, val, (regs.s ? 4 : 0) | 1); } -uae_u32 read_dcache030_lrmw_mmu(uaecptr addr, uae_u32 size) +uae_u32 read_dcache030_lrmw_mmu_fcx(uaecptr addr, uae_u32 size, int fc) { if (currprefs.cpu_data_cache) { mmu030_cache_state = CACHE_DISABLE_MMU; if (size == 0) - return read_dcache030_bget(addr, (regs.s ? 4 : 0) | 1); + return read_dcache030_bget(addr, fc); if (size == 1) - return read_dcache030_wget(addr, (regs.s ? 4 : 0) | 1); - return read_dcache030_lget(addr, (regs.s ? 4 : 0) | 1); + return read_dcache030_wget(addr, fc); + return read_dcache030_lget(addr, fc); } else { if (size == 0) return read_data_030_bget(addr); @@ -10011,16 +10011,20 @@ uae_u32 read_dcache030_lrmw_mmu(uaecptr addr, uae_u32 size) return read_data_030_lget(addr); } } -void write_dcache030_lrmw_mmu(uaecptr addr, uae_u32 val, uae_u32 size) +uae_u32 read_dcache030_lrmw_mmu(uaecptr addr, uae_u32 size) +{ + return read_dcache030_lrmw_mmu_fcx(addr, size, (regs.s ? 4 : 0) | 1); +} +void write_dcache030_lrmw_mmu_fcx(uaecptr addr, uae_u32 val, uae_u32 size, int fc) { if (currprefs.cpu_data_cache) { mmu030_cache_state = CACHE_DISABLE_MMU; if (size == 0) - write_dcache030_bput(addr, val, (regs.s ? 4 : 0) | 1); + write_dcache030_bput(addr, val, fc); else if (size == 1) - write_dcache030_wput(addr, val, (regs.s ? 4 : 0) | 1); + write_dcache030_wput(addr, val, fc); else - write_dcache030_lput(addr, val, (regs.s ? 4 : 0) | 1); + write_dcache030_lput(addr, val, fc); } else { if (size == 0) write_data_030_bput(addr, val); @@ -10030,6 +10034,10 @@ void write_dcache030_lrmw_mmu(uaecptr addr, uae_u32 val, uae_u32 size) write_data_030_lput(addr, val); } } +void write_dcache030_lrmw_mmu(uaecptr addr, uae_u32 val, uae_u32 size) +{ + write_dcache030_lrmw_mmu_fcx(addr, val, size, (regs.s ? 4 : 0) | 1); +} static void do_access_or_bus_error(uaecptr pc, uaecptr pcnow) { -- 2.47.3