From 7ce12876aec5db91d45ba50ebae5fe177eff8cc2 Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Mon, 6 Jul 2015 20:23:29 +0300 Subject: [PATCH] Preliminary A2410 emulation. TMS34010 core from MAME. --- mame/a2410.cpp | 805 ++++++++++++ mame/mameglue.h | 98 ++ mame/tm34010/34010dsm.c | 1761 ++++++++++++++++++++++++++ mame/tm34010/34010fld.c | 681 ++++++++++ mame/tm34010/34010gfx.c | 1979 +++++++++++++++++++++++++++++ mame/tm34010/34010ops.c | 2463 +++++++++++++++++++++++++++++++++++++ mame/tm34010/34010ops.h | 154 +++ mame/tm34010/34010tbl.c | 782 ++++++++++++ mame/tm34010/dis34010.c | 115 ++ mame/tm34010/tms34010.cpp | 1714 ++++++++++++++++++++++++++ mame/tm34010/tms34010.h | 1049 ++++++++++++++++ 11 files changed, 11601 insertions(+) create mode 100644 mame/a2410.cpp create mode 100644 mame/mameglue.h create mode 100644 mame/tm34010/34010dsm.c create mode 100644 mame/tm34010/34010fld.c create mode 100644 mame/tm34010/34010gfx.c create mode 100644 mame/tm34010/34010ops.c create mode 100644 mame/tm34010/34010ops.h create mode 100644 mame/tm34010/34010tbl.c create mode 100644 mame/tm34010/dis34010.c create mode 100644 mame/tm34010/tms34010.cpp create mode 100644 mame/tm34010/tms34010.h diff --git a/mame/a2410.cpp b/mame/a2410.cpp new file mode 100644 index 00000000..c0a82c75 --- /dev/null +++ b/mame/a2410.cpp @@ -0,0 +1,805 @@ +/* +* UAE - The Un*x Amiga Emulator +* +* A2410 +* +*/ +#include "sysconfig.h" +#include "sysdeps.h" + +#include "debug.h" +#include "mameglue.h" +#include "tm34010/tms34010.h" + +#include "options.h" +#include "memory.h" +#include "custom.h" +#include "picasso96.h" +#include "statusline.h" +#include "newcpu.h" + +static int tms_vp, tms_hp; +rectangle tms_rectangle; +static mscreen tms_screen; +static tms340x0_device tms_device; +static address_space tms_space; +mscreen *m_screen; + +#define OVERLAY_WIDTH 512 + +static uae_u8 *program_ram; +static int a2410_palette_index; +static uae_u8 a2410_palette[4 * (256 + 4)]; +static uae_u32 a2410_palette_32[256 + 4]; +static uae_u8 a2410_palette_control[4]; +static uae_u16 a2410_control; +static bool a2410_modified[1024]; +static int a2410_displaywidth; +static int a2410_displayend; +static int a2410_vertical_start; +static bool a2410_isactive; +static uae_u8 a2410_overlay_mask[2]; +static int a2410_overlay_blink_rate_on; +static int a2410_overlay_blink_rate_off; +static int a2410_overlay_blink_cnt; + +int mscreen::hpos() +{ + if (a2410_displayend) { + tms_hp++; + tms_hp %= a2410_displayend; + } else { + tms_hp = 0; + } + return tms_hp; +} +int mscreen::vpos() +{ + return tms_vp; +} + +static void tms_execute_single(void) +{ + tms_device.m_icount = 0; + tms_device.execute_run(); +} + +#define A2410_BANK_FRAMEBUFFER 1 +#define A2410_BANK_PROGRAM 2 +#define A2410_BANK_RAMDAC 3 +#define A2410_BANK_CONTROL 4 +#define A2410_BANK_TMSIO 5 + +static uaecptr makeaddr(UINT32 a, int *bank) +{ + uaecptr addr = 0; + UINT32 aa = a << 3; + if ((aa & 0xfff00000) == 0xc0000000) { + *bank = A2410_BANK_TMSIO; + addr = (a & 0xff) >> 1; + } else if ((aa & 0xff900000) == 0xfe800000) { + *bank = A2410_BANK_RAMDAC; + addr = (a >> 1) & 3; + } else if ((aa & 0xff900000) == 0xfe900000) { + *bank = A2410_BANK_CONTROL; + } else if ((aa & 0xff800000) == 0xff800000) { + addr = (a & 0xfffff); + *bank = A2410_BANK_PROGRAM; + } else if ((aa & 0xff800000) == 0xfe000000) { + addr = a & 0xfffff; + *bank = A2410_BANK_FRAMEBUFFER; + } else { + *bank = 0; + write_log(_T("Unknown BANK %08x PC=%08x\n"), aa, M68K_GETPC); + } + return addr; +} + +void m_to_shiftreg_cb(address_space space, offs_t offset, UINT16 *shiftreg) +{ + memcpy(shiftreg, &gfxmem_bank.baseaddr[TOWORD(offset)], 256 * sizeof(UINT16)); +} +void m_from_shiftreg_cb(address_space space, offs_t offset, UINT16* shiftreg) +{ + memcpy(&gfxmem_bank.baseaddr[TOWORD(offset)], shiftreg, 256 * sizeof(UINT16)); +} + +UINT16 direct_read_data::read_decrypted_word(UINT32 pc) +{ + uae_u16 v = 0; + int bank; + uaecptr addr = makeaddr(pc, &bank); + v = program_ram[addr] << 8; + v |= program_ram[addr + 1]; + //write_log(_T("TMS instruction word read RAM %08x (%08x) =%04x\n"), pc, addr, v); + return v; +} +UINT16 direct_read_data::read_raw_word(UINT32 pc) +{ + uae_u16 v = 0; + int bank; + uaecptr addr = makeaddr(pc, &bank); + v = program_ram[addr] << 8; + v |= program_ram[addr + 1]; + //write_log(_T("TMS instruction word read RAM %08x (%08x) =%04x\n"), pc, addr, v); + return v; +} + +static void mark_overlay(int addr) +{ + if (!a2410_isactive) + return; + addr &= 0x1ffff; + addr /= OVERLAY_WIDTH / 4; + a2410_modified[addr] = true; +} + +static void a2410_create_palette32(int offset) +{ + int idx = a2410_palette_index / 4 + offset; + a2410_palette_32[idx] = + (a2410_palette[idx * 4 + 0] << 16) | + (a2410_palette[idx * 4 + 1] << 8) | + (a2410_palette[idx * 4 + 2] << 0); +} + +static void write_ramdac(int addr, uae_u8 v) +{ + switch (addr) + { + case 0: + a2410_palette_index = v * 4; + break; + case 1: + a2410_palette[a2410_palette_index] = v; + a2410_create_palette32(0); + a2410_palette_index++; + if ((a2410_palette_index & 3) == 3) + a2410_palette_index++; + if (a2410_palette_index >= 256 * 4) + a2410_palette_index = 0; + break; + case 2: + if (a2410_palette_index >= 4 * 4 && a2410_palette_index < 8 * 4) { + a2410_palette_control[a2410_palette_index / 4 - 4] = v; + } + a2410_overlay_mask[0] = 0xff; + a2410_overlay_mask[1] = 0xff; + if (!(a2410_palette_control[6 - 4] & 1)) + a2410_overlay_mask[0] = 0; + if (!(a2410_palette_control[6 - 4] & 2)) + a2410_overlay_mask[1] = 0; + switch((a2410_palette_control[6 - 4] >> 4) & 3) + { + case 0: + a2410_overlay_blink_rate_on = 16; + a2410_overlay_blink_rate_off = 48; + break; + case 1: + a2410_overlay_blink_rate_on = 16; + a2410_overlay_blink_rate_off = 16; + break; + case 2: + a2410_overlay_blink_rate_on = 32; + a2410_overlay_blink_rate_off = 32; + break; + case 3: + a2410_overlay_blink_rate_on = 64; + a2410_overlay_blink_rate_off = 64; + break; + } + break; + case 3: + if (a2410_palette_index < 4 * 4) { + a2410_palette[a2410_palette_index + 256 * 4] = v; + a2410_create_palette32(256); + a2410_palette_index++; + if ((a2410_palette_index & 3) == 3) + a2410_palette_index++; + if (a2410_palette_index >= 4 * 4) + a2410_palette_index = 0; + } + break; + default: + write_log(_T("Unknown write RAMDAC address %08x PC=%08x\n"), addr, M68K_GETPC); + break; + } +} +static uae_u8 read_ramdac(int addr) +{ + uae_u8 v = 0; + switch (addr) + { + case 0: + v = a2410_palette_index / 4; + break; + case 1: + v = a2410_palette[a2410_palette_index]; + a2410_palette_index++; + if ((a2410_palette_index & 3) == 3) + a2410_palette_index++; + if (a2410_palette_index >= 256 * 4) + a2410_palette_index = 0; + break; + case 2: + if (a2410_palette_index >= 4 * 4 && a2410_palette_index < 8 * 4) { + v = a2410_palette_control[a2410_palette_index / 4 - 4]; + } + break; + case 3: + if (a2410_palette_index < 4 * 4) { + v = a2410_palette[a2410_palette_index + 256 * 4]; + a2410_palette_index++; + if ((a2410_palette_index & 3) == 3) + a2410_palette_index = 0; + if (a2410_palette_index >= 4 * 4) + a2410_palette_index = 0; + } + break; + default: + write_log(_T("Unknown read RAMDAC address %08x PC=%08x\n"), addr, M68K_GETPC); + break; + } + return v; +} + +static uae_u8 get_a2410_control(void) +{ + uae_u8 v = a2410_control; + v &= ~(0x08 | 0x10 | 0x20 | 0x40); + return v; +} + +UINT8 address_space::read_byte(UINT32 a) +{ + int bank; + uae_u8 v = 0; + UINT32 aa = a << 3; + uaecptr addr = makeaddr(a, &bank); + switch (bank) + { + case A2410_BANK_PROGRAM: + v = program_ram[addr]; + //write_log(_T("TMS byte read RAM %08x (%08x) =%02x PC=%08x\n"), aa, addr, v, M68K_GETPC); + break; + case A2410_BANK_FRAMEBUFFER: + v = gfxmem_bank.baseaddr[addr]; + write_log(_T("TMS byte read framebuffer %08x (%08x) = %02x PC=%08x\n"), aa, addr, v, M68K_GETPC); + break; + case A2410_BANK_RAMDAC: + v = read_ramdac(addr); + write_log(_T("RAMDAC READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC); + break; + case A2410_BANK_CONTROL: + v = get_a2410_control(); + write_log(_T("CONTROL READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC); + break; + default: + write_log(_T("UNKNOWN READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC); + break; + + } + return v; +} +UINT16 address_space::read_word(UINT32 a) +{ + int bank; + uae_u16 v = 0; + UINT32 aa = a << 3; + uaecptr addr = makeaddr(a, &bank); + switch (bank) + { + case A2410_BANK_TMSIO: + v = tms_device.io_register_r(*this, addr); + write_log(_T("TMS IO word read %08x (%08x) = %04x PC=%08x PC=%08x\n"), aa, addr, v, M68K_GETPC); + break; + case A2410_BANK_PROGRAM: + v = program_ram[addr] << 8; + v |= program_ram[addr + 1]; + //write_log(_T("TMS program word read RAM %08x (%08x) = %04x PC=%08x\n"), aa, addr, v, M68K_GETPC); + break; + case A2410_BANK_FRAMEBUFFER: + v = gfxmem_bank.baseaddr[addr] << 8; + v |= gfxmem_bank.baseaddr[addr + 1]; + //write_log(_T("TMS gfx word read %08x (%08x) = %04x PC=%08x\n"), aa, addr, v, M68K_GETPC); + break; + case A2410_BANK_RAMDAC: + v = read_ramdac(addr); + write_log(_T("RAMDAC READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC); + break; + case A2410_BANK_CONTROL: + v = get_a2410_control(); + write_log(_T("CONTROL READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC); + break; + default: + write_log(_T("UNKNOWN READ %08x = %04x PC=%08x\n"), aa, v, M68K_GETPC); + break; + } + return v; +} +void address_space::write_byte(UINT32 a, UINT8 b) +{ + int bank; + UINT32 aa = a << 3; + uaecptr addr = makeaddr(a, &bank); + switch (bank) + { + case A2410_BANK_PROGRAM: + program_ram[addr] = b; + if (addr < 0x40000) + mark_overlay(addr); + //write_log(_T("TMS program byte write %08x (%08x) = %02x PC=%08x\n"), aa, addr, b, M68K_GETPC); + break; + case A2410_BANK_FRAMEBUFFER: + gfxmem_bank.baseaddr[addr] = b; + write_log(_T("TMS gfx byte write %08x (%08x) = %02x PC=%08x\n"), aa, addr, b, M68K_GETPC); + break; + case A2410_BANK_RAMDAC: + //write_log(_T("RAMDAC WRITE %08x = %02x PC=%08x\n"), aa, b, M68K_GETPC); + write_ramdac(addr, b); + break; + case A2410_BANK_CONTROL: + write_log(_T("CONTROL WRITE %08x = %02x PC=%08x\n"), aa, b, M68K_GETPC); + a2410_control = b; + break; + default: + write_log(_T("UNKNOWN WRITE %08x = %02x PC=%08x\n"), aa, b, M68K_GETPC); + break; + } +} +void address_space::write_word(UINT32 a, UINT16 b) +{ + int bank; + UINT32 aa = a << 3; + uaecptr addr = makeaddr(a, &bank); + switch (bank) + { + case A2410_BANK_TMSIO: + tms_device.io_register_w(*this, addr, b); + write_log(_T("TMS IO word write %08x (%08x) = %04x PC=%08x\n"), aa, addr, b, M68K_GETPC); + break; + case A2410_BANK_PROGRAM: + program_ram[addr] = b >> 8; + program_ram[addr + 1] = b & 0xff; + if (addr < 0x40000) + mark_overlay(addr); + //write_log(_T("TMS program word write RAM %08x (%08x) = %04x PC=%08x\n"), aa, addr, b, M68K_GETPC); + break; + case A2410_BANK_FRAMEBUFFER: + gfxmem_bank.baseaddr[addr] = b >> 8; + gfxmem_bank.baseaddr[addr + 1] = b & 0xff; + //write_log(_T("TMS gfx word write %08x (%08x) = %04x PC=%08x\n"), aa, addr, b, M68K_GETPC); + break; + case A2410_BANK_RAMDAC: + //write_log(_T("RAMDAC WRITE %08x = %04x PC=%08x\n"), aa, b, M68K_GETPC); + write_ramdac(addr, b); + break; + case A2410_BANK_CONTROL: + write_log(_T("CONTROL WRITE %08x = %04x PC=%08x\n"), aa, b, M68K_GETPC); + a2410_control = b; + break; + default: + write_log(_T("UNKNOWN WRITE %08x = %04x PC=%08x\n"), aa, b, M68K_GETPC); + break; + } +} + +static int tms_configured; +static uae_u8 tms_config[128]; +extern addrbank tms_bank; + +static uae_u32 REGPARAM2 tms_bget(uaecptr addr) +{ + uae_u32 v = 0xff; +#ifdef JIT + special_mem |= S_READ; +#endif + addr &= 65535; + if (!tms_configured) { + v = tms_config[addr]; + } else { + uae_u16 vv = tms_device.host_r(tms_space, addr >> 1); + if (!(addr & 1)) + vv >>= 8; + v = (uae_u8)vv; + tms_execute_single(); + } + return v; +} +static uae_u32 REGPARAM2 tms_wget(uaecptr addr) +{ + uae_u16 v; +#ifdef JIT + special_mem |= S_READ; +#endif + addr &= 65535; + if (tms_configured) { + v = tms_device.host_r(tms_space, addr >> 1); + //write_log(_T("TMS read %08x = %04x\n"), addr, v & 0xffff); + tms_execute_single(); + } else { + v = tms_bget(addr) << 8; + v |= tms_bget(addr + 1); + } + return v; +} +static uae_u32 REGPARAM2 tms_lget(uaecptr addr) +{ + uae_u32 v; +#ifdef JIT + special_mem |= S_READ; +#endif + addr &= 65535; + v = tms_wget(addr) << 16; + v |= tms_wget(addr + 2); + return v; +} + + +static void REGPARAM2 tms_wput(uaecptr addr, uae_u32 w) +{ +#ifdef JIT + special_mem |= S_WRITE; +#endif + addr &= 65535; + if (tms_configured) { + //write_log(_T("TMS write %08x = %04x\n"), addr, w & 0xffff); + tms_device.host_w(tms_space, addr >> 1, w); + tms_execute_single(); + } +} + +static void REGPARAM2 tms_lput(uaecptr addr, uae_u32 l) +{ +#ifdef JIT + special_mem |= S_WRITE; +#endif + addr &= 65535; + tms_wput(addr, l >> 16); + tms_wput(addr + 2, l); +} + +static void REGPARAM2 tms_bput(uaecptr addr, uae_u32 b) +{ +#ifdef JIT + special_mem |= S_WRITE; +#endif + b &= 0xff; + addr &= 65535; + if (!tms_configured) { + if (addr == 0x48 && !tms_configured) { + map_banks_z2(&tms_bank, b, 0x10000 >> 16); + tms_configured = b; + expamem_next(&tms_bank, NULL); + return; + } + if (addr == 0x4c && !tms_configured) { + tms_configured = 0xff; + expamem_shutup(&tms_bank); + return; + } + return; + } + tms_device.host_w(tms_space, addr >> 1, (b << 8) | b); + tms_execute_single(); +} + +addrbank tms_bank = { + tms_lget, tms_wget, tms_bget, + tms_lput, tms_wput, tms_bput, + default_xlate, default_check, NULL, NULL, _T("A2410"), + tms_lget, tms_wget, ABFLAG_IO +}; + +void tms_reset(void) +{ + tms_device.device_reset(); + tms_configured = 0; +} + +static void ew(int addr, uae_u32 value) +{ + addr &= 0xffff; + if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) { + tms_config[addr] = (value & 0xf0); + tms_config[addr + 2] = (value & 0x0f) << 4; + } else { + tms_config[addr] = ~(value & 0xf0); + tms_config[addr + 2] = ~((value & 0x0f) << 4); + } +} + +void tms_free(void) +{ + mapped_free(&gfxmem_bank); + xfree(program_ram); +} + +addrbank *tms_init(int devnum) +{ + memset(tms_config, 0xff, sizeof tms_config); + ew(0x00, 0xc0 | 0x01); + // product id + ew(0x04, 0x00); + // manufacturer id + ew(0x10, 1030 >> 8); + ew(0x14, 1030 & 0xff); + + mapped_free(&gfxmem_bank); + xfree(program_ram); + + gfxmem_bank.label = _T("x_a0"); + gfxmem_bank.allocated = 1 * 1024 * 1024; + mapped_malloc(&gfxmem_bank); + picasso_allocatewritewatch(gfxmem_bank.allocated); + gfxmem_bank.start = 0xa00000; + + program_ram = xcalloc(uae_u8, 1 * 1024 * 1024); + + m_screen = &tms_screen; + tms_device.device_start(); + tms_reset(); + + return &tms_bank; +} + +static bool a2410_modechanged; +static int a2410_gotmode; +static int a2410_width, a2410_height; +static int fullrefresh; +static int a2410_vram_start_offset; +static uae_u8 *a2410_surface; +static int a2410_interlace; + +void mscreen::configure(int width, int height, rectangle vis) +{ + a2410_width = vis.max_x - vis.min_x + 1; + a2410_height = vis.max_y - vis.min_y + 1; + a2410_interlace = vis.interlace ? 1 : 0; + if (a2410_interlace) + a2410_height *= 2; + a2410_modechanged = true; + a2410_gotmode = true; + m_screen->height_v = height; + m_screen->width_v = width; + tms_rectangle = vis; +} + +static void get_a2410_surface(void) +{ + bool gotsurf = false; + if (picasso_on) { + if (a2410_surface == NULL) { + a2410_surface = gfx_lock_picasso(false, false); + gotsurf = true; + } + if (a2410_surface && gotsurf) { + if (!(currprefs.leds_on_screen & STATUSLINE_TARGET)) + picasso_statusline(a2410_surface); + } + } +} + +bool tms_toggle(int mode) +{ + if (!tms_configured) + return false; + + if (a2410_isactive) { + a2410_isactive = false; + a2410_modechanged = false; + picasso_requested_on = 0; + a2410_gotmode = -1; + return true; + } else { + if (!a2410_gotmode) + return false; + a2410_gotmode = 1; + a2410_modechanged = true; + return true; + } + return false; +} + +void tms_vsync_handler(void) +{ + if (!tms_configured) + return; + + tms34010_display_params parms; + tms_device.get_display_params(&parms); + bool enabled = parms.enabled != 0 && a2410_gotmode > 0; + + if (enabled && a2410_modechanged) { + + if (a2410_surface) + gfx_unlock_picasso(false); + a2410_surface = NULL; + + picasso96_state.Width = a2410_width; + picasso96_state.Height = a2410_height; + picasso96_state.BytesPerPixel = 1; + picasso96_state.RGBFormat = RGBFB_CLUT; + write_log(_T("A2410 %dx%d\n"), a2410_width, a2410_height); + gfx_set_picasso_modeinfo(a2410_width, a2410_height, 1, RGBFB_NONE); + fullrefresh = 2; + init_hz_p96(); + picasso_requested_on = 1; + a2410_modechanged = false; + return; + } + + if (enabled != a2410_isactive) { + if (!enabled) + picasso_requested_on = 0; + a2410_isactive = enabled; + write_log(_T("A2410 ACTIVE=%d\n"), a2410_isactive); + } + + if (picasso_on) { + if (currprefs.leds_on_screen & STATUSLINE_RTG) { + get_a2410_surface(); + } + if (fullrefresh > 0) + fullrefresh--; + } + + if (a2410_surface) + gfx_unlock_picasso(true); + a2410_surface = NULL; + + a2410_interlace = -a2410_interlace; + + a2410_overlay_blink_cnt++; + if (a2410_overlay_blink_cnt == 0 || a2410_overlay_blink_cnt == a2410_overlay_blink_rate_on) { + // any blink mode enabled? + if (a2410_palette_control[5 - 4] != 0 || (a2410_palette_control[6 - 4] & (4 | 8))) + fullrefresh++; + } + if (a2410_overlay_blink_cnt > a2410_overlay_blink_rate_off + a2410_overlay_blink_rate_on) { + a2410_overlay_blink_cnt = 0; + } +} + +void tms_hsync_handler(void) +{ + int a2410_vpos = tms_vp; + if (!tms_configured) + return; + + if (a2410_vpos == 0 && a2410_isactive) { + picasso_getwritewatch(a2410_vram_start_offset); + } + + tms_device.m_icount = 50; + tms_device.execute_run(); + tms_vp = tms_device.scanline_callback(NULL, tms_vp); + + if (!a2410_isactive) + return; + + tms34010_display_params parms; + tms_device.get_display_params(&parms); + + if (a2410_interlace) { + a2410_vpos = tms_vp * 2; + if (a2410_interlace < 0) + a2410_vpos++; + } + + a2410_displaywidth = parms.hsblnk - parms.heblnk; + a2410_displayend = parms.heblnk; + a2410_vertical_start = parms.veblnk; + + if (a2410_vpos >= a2410_height || a2410_vpos >= picasso_vidinfo.height) + return; + + int coladdr = parms.coladdr; + int vramoffset = ((parms.rowaddr << 8) & 0x7ffff); + uae_u16 *vram = (uae_u16*)gfxmem_bank.baseaddr + vramoffset; + + int overlayoffset = a2410_vpos - parms.veblnk; + uae_u8 *overlay0 = program_ram + overlayoffset * OVERLAY_WIDTH / 4; + uae_u8 *overlay1 = overlay0 + 0x20000; + + if (!fullrefresh && !a2410_modified[a2410_vpos]) { + if (!picasso_is_vram_dirty(gfxmem_bank.start + (vramoffset << 1), a2410_displaywidth)) { + if (!picasso_is_vram_dirty(gfxmem_bank.start + ((vramoffset + 0x200) << 1), a2410_displaywidth)) { + return; + } + } + } + a2410_modified[a2410_vpos] = false; + + get_a2410_surface(); + uae_u8 *dst = a2410_surface; + if (!dst) + return; + dst += a2410_vpos * picasso_vidinfo.rowbytes; + + bool overlay0color = !(a2410_palette_control[6 - 4] & 0x40); + uae_u16 bitmap_mask = a2410_palette_control[4 - 4]; + + uae_u8 overlay_mask[2] = { a2410_overlay_mask[0], a2410_overlay_mask[1] }; + if (a2410_overlay_blink_cnt >= a2410_overlay_blink_rate_on) { + if (a2410_palette_control[6 - 4] & 4) + overlay_mask[0] = 0; + if (a2410_palette_control[6 - 4] & 8) + overlay_mask[1] = 0; + uae_u16 blink_mask = a2410_palette_control[5 - 4]; + blink_mask |= blink_mask << 8; + bitmap_mask &= ~blink_mask; + } + + int xx = 0; + int overlay_offset = 0; + int overlay_bitcount = 0; + uae_u8 opix0 = 0, opix1 = 0; + + for (int x = parms.heblnk; x < parms.hsblnk && xx < picasso_vidinfo.width; x += 2, xx += 2) { + uae_u16 pix; + + if (!overlay_bitcount && overlayoffset >= 0) { + opix0 = overlay0[overlay_offset ^ 1] & a2410_overlay_mask[0]; + opix1 = overlay1[overlay_offset ^ 1] & a2410_overlay_mask[1]; + overlay_offset++; + } + + if (overlay0color || opix0 || opix1) { + + int pal; + uae_u8 ov; + + pix = vram[coladdr & 0x1ff]; + + pal = (pix >> 8) & bitmap_mask; + ov = opix0 & 1; + ov |= (opix1 & 1) << 1; + if (ov || overlay0color) + pal = 256 + ov; + ((uae_u32*)dst)[0] = a2410_palette_32[pal]; + opix0 >>= 1; + opix1 >>= 1; + + pal = pix & bitmap_mask; + ov = opix0 & 1; + ov |= (opix1 & 1) << 1; + if (ov || overlay0color) + pal = 256 + ov; + ((uae_u32*)dst)[1] = a2410_palette_32[pal]; + opix0 >>= 1; + opix1 >>= 1; + + dst += 8; + coladdr++; + + } else { + + pix = vram[coladdr & 0x1ff]; + + ((uae_u32*)dst)[0] = a2410_palette_32[pix >> 8]; + ((uae_u32*)dst)[1] = a2410_palette_32[pix & 0xff]; + + dst += 8; + coladdr++; + + opix0 >>= 2; + opix1 >>= 2; + + } + + overlay_bitcount += 2; + overlay_bitcount &= 7; + } + while (xx < picasso_vidinfo.width) { + ((uae_u32*)dst)[0] = 0; + dst += 4; + xx++; + } + +} + +void standard_irq_callback(int v) +{ + INTREQ_0(0x8000 | 0x0008); +} diff --git a/mame/mameglue.h b/mame/mameglue.h new file mode 100644 index 00000000..6b9479ae --- /dev/null +++ b/mame/mameglue.h @@ -0,0 +1,98 @@ + + +#include "sysconfig.h" +#include "sysdeps.h" + +extern void write_log(const char *, ...); +extern void activate_debugger(void); + +#define MIN(a, b) ((a) > (b) ? (a) : (b)) + +#define osd_printf_debug write_log +#define fatalerror write_log +#define logerror write_log +#define tag() "X" +#define DEBUG_FLAG_ENABLED 0 + +#define STATE_GENPC 0 +#define STATE_GENSP 1 +#define STATE_GENPCBASE 2 + +#define CLEAR_LINE 1 + +typedef unsigned long offs_t; + +#define FALSE 0 +#define TRUE 1 + +#define TIMER_CALLBACK_MEMBER(x) int x(void *p, int param) +extern void standard_irq_callback(int); + +#define CONCAT_64(hi,lo) (((UINT64)(hi) << 32) | (UINT32)(lo)) +#define EXTRACT_64HI(val) ((UINT32)((val) >> 32)) +#define EXTRACT_64LO(val) ((UINT32)(val)) +inline INT64 mul_32x32(INT32 a, INT32 b) +{ + return (INT64)a * (INT64)b; +} +inline UINT64 mulu_32x32(UINT32 a, UINT32 b) +{ + return (UINT64)a * (UINT64)b; +} +#define NULL 0 + +class direct_read_data +{ +public: + UINT16 read_decrypted_word(UINT32 pc); + UINT16 read_raw_word(UINT32 pc); +}; + +class rectangle +{ +public: + int min_x, min_y; + int max_x, max_y; + bool interlace; +}; +extern rectangle tms_rectangle; +class mscreen +{ +public: + int width_v; + int height_v; + rectangle visible_area() { return tms_rectangle; } + void configure(int width, int height, rectangle visarea); + int vpos(); + int hpos(); + int width() { return width_v; } + int height() { return height_v; } +}; + +extern mscreen *m_screen; + +class address_space +{ +public: + UINT8 read_byte(UINT32 a); + UINT16 read_word(UINT32 a); + void write_word(UINT32 a, UINT16 v); + void write_byte(UINT32 a, UINT8 v); +}; + +#define DECLARE_READ16_MEMBER(name) UINT16 name(address_space &space, offs_t offset, UINT16 mem_mask = 0xffff) +#define DECLARE_WRITE16_MEMBER(name) void name(address_space &space, offs_t offset, UINT16 data, UINT16 mem_mask = 0xffff) +#define READ16_MEMBER(name) UINT16 name(address_space &space, offs_t offset, UINT16 mem_mask) +#define WRITE16_MEMBER(name) void name(address_space &space, offs_t offset, UINT16 data, UINT16 mem_mask) + +typedef UINT32 device_state_entry; + +typedef UINT32 address_spacenum; +typedef UINT32 address_space_config; +typedef UINT32 screen_device; +typedef UINT32 bitmap_ind16; +#define AS_0 0 +#define AS_PROGRAM 1 + +extern void m_to_shiftreg_cb(address_space, offs_t, UINT16*); +extern void m_from_shiftreg_cb(address_space, offs_t, UINT16*); diff --git a/mame/tm34010/34010dsm.c b/mame/tm34010/34010dsm.c new file mode 100644 index 00000000..15136885 --- /dev/null +++ b/mame/tm34010/34010dsm.c @@ -0,0 +1,1761 @@ +// license:BSD-3-Clause +// copyright-holders:Zsolt Vasvari +/* + * A TMS34010 disassembler + * + * This code written by Zsolt Vasvari for the MAME project + * + */ + +#include "emu.h" + +#ifdef STANDALONE +#define PC __pc + (offset << 3) +#define OP_WORD(v) { v = filebuf[_pc>>3]; _pc += 8; v = v | (filebuf[_pc>>3] << 8); _pc += 8;} +#define PARAM_WORD(v) { v = filebuf[_pc>>3]; _pc += 8; v = v | (filebuf[_pc>>3] << 8); _pc += 8;} +#define PARAM_LONG(v) { int v1, v2; PARAM_WORD(v1); PARAM_WORD(v2); v = v1 | (v2 << 16); } +#else +#define PC __pc +#define OP_WORD(v) { v = rombase[(__pc - pcbase) >> 3] | (rombase[(__pc + 8 - pcbase) >> 3] << 8); _pc += 16; } +#define PARAM_WORD(v) { v = rambase[(__pc + 16 - pcbase) >> 3] | (rambase[(__pc + 24 - pcbase) >> 3] << 8); _pc += 16; } +#define PARAM_LONG(v) { v = rambase[(__pc + 16 - pcbase) >> 3] | (rambase[(__pc + 24 - pcbase) >> 3] << 8) | (rambase[(__pc + 32 - pcbase) >> 3] << 16) | (rambase[(__pc + 40 - pcbase) >> 3] << 24); _pc += 32; } +#endif + +static UINT8 rf; +static UINT32 __pc, _pc; +static UINT16 op,rs,rd; + +static char *buffer; +static char temp[20]; + +static const UINT8 *rombase; +static const UINT8 *rambase; +static offs_t pcbase; + + +static void print_reg(UINT8 reg) +{ + if (reg != 0x0f) + { + sprintf(temp, "%c%d", rf, reg); + strcat(buffer, temp); + } + else + { + strcat(buffer, "SP"); + } +} + +static void print_src_reg(void) +{ + print_reg(rs); +} + +static void print_des_reg(void) +{ + print_reg(rd); +} + +static void print_src_des_reg(void) +{ + print_src_reg(); + strcat(buffer, ","); + print_des_reg(); +} + +static void print_word_parm(void) +{ + UINT16 w; + + PARAM_WORD(w); + + sprintf(temp, "%Xh", w); + strcat(buffer, temp); +} + +static void print_word_parm_1s_comp(void) +{ + UINT16 w; + + PARAM_WORD(w); + w = ~w; + sprintf(temp, "%Xh", w); + strcat(buffer, temp); +} + +static void print_long_parm(void) +{ + UINT32 l; + + PARAM_LONG(l); + sprintf(temp, "%Xh", l); + strcat(buffer, temp); +} + +static void print_long_parm_1s_comp(void) +{ + UINT32 l; + + PARAM_LONG(l); + sprintf(temp, "%Xh", ~l); + strcat(buffer, temp); +} + +static void print_constant(void) +{ + UINT8 constant = (op >> 5) & 0x1f; + + sprintf(temp, "%Xh", constant); + strcat(buffer, temp); +} + +static void print_constant_1_32(void) +{ + UINT8 constant = (op >> 5) & 0x1f; + if (!constant) constant = 0x20; + + sprintf(temp, "%Xh", constant); + strcat(buffer, temp); +} + +static void print_constant_1s_comp(void) +{ + UINT8 constant = (~op >> 5) & 0x1f; + + sprintf(temp, "%Xh", constant); + strcat(buffer, temp); +} + +static void print_constant_2s_comp(void) +{ + UINT8 constant = 32 - ((op >> 5) & 0x1f); + + sprintf(temp, "%Xh", constant); + strcat(buffer, temp); +} + +static void print_relative(void) +{ + UINT16 l; + INT16 ls; + + PARAM_WORD(l); + ls = (INT16)l; + + sprintf(temp, "%Xh", PC + 32 + (ls << 4)); + strcat(buffer, temp); +} + +static void print_relative_8bit(void) +{ + INT8 ls = (INT8)op; + + sprintf(temp, "%Xh", PC + 16 + (ls << 4)); + strcat(buffer, temp); +} + +static void print_relative_5bit(void) +{ + INT8 ls = (INT8)((op >> 5) & 0x1f); + if (op & 0x0400) ls = -ls; + + sprintf(temp, "%Xh", PC + 16 + (ls << 4)); + strcat(buffer, temp); +} + +static void print_field(void) +{ + sprintf(temp, "%c", (op & 0x200) ? '1' : '0'); + strcat(buffer, temp); +} + +static void print_condition_code(void) +{ + switch (op & 0x0f00) + { + case 0x0000: strcat(buffer, " "); break; /* This is really UC (Unconditional) */ + case 0x0100: strcat(buffer, "P "); break; + case 0x0200: strcat(buffer, "LS"); break; + case 0x0300: strcat(buffer, "HI"); break; + case 0x0400: strcat(buffer, "LT"); break; + case 0x0500: strcat(buffer, "GE"); break; + case 0x0600: strcat(buffer, "LE"); break; + case 0x0700: strcat(buffer, "GT"); break; + case 0x0800: strcat(buffer, "C "); break; + case 0x0900: strcat(buffer, "NC"); break; + case 0x0a00: strcat(buffer, "EQ"); break; + case 0x0b00: strcat(buffer, "NE"); break; + case 0x0c00: strcat(buffer, "V "); break; + case 0x0d00: strcat(buffer, "NV"); break; + case 0x0e00: strcat(buffer, "N "); break; + case 0x0f00: strcat(buffer, "NN"); break; + } +} + +static void print_reg_list_range(INT8 first, INT8 last) +{ + if ((first != -1 ) && (first != last)) + { + if ((last - first) == 1) + strcat(buffer, ","); + else + strcat(buffer, "-"); + print_reg(last); + } +} + +static void print_reg_list(UINT16 rev) +{ + UINT16 l; + UINT8 i; + INT8 first = -1, last = 0; + + PARAM_WORD(l); + + for (i = 0; i < 16; i++) + { + int moved; + + if (rev) + { + moved = l & 0x8000; + l <<= 1; + } + else + { + moved = l & 0x01; + l >>= 1; + } + + if (moved) + { + if (first == -1) + { + strcat(buffer, ","); + print_reg(i); + first = i; + } + last = i; + } + else + { + print_reg_list_range(first, last); + first = -1; + } + } + + print_reg_list_range(first, last); +} + + +static unsigned Dasm340x0(char *buff, UINT32 pc, int is_34020) +{ + int flags = 0; + UINT8 bad = 0; + UINT16 subop; + + __pc = _pc = pc; + buffer = buff; + + OP_WORD(op); + + subop = (op & 0x01e0); + rs = (op >> 5) & 0x0f; /* Source register */ + rd = op & 0x0f; /* Destination register */ + rf = ((op & 0x10) ? 'B' : 'A'); /* Register file */ + + switch (op & 0xfe00) + { + case 0x0000: + switch (subop) + { + case 0x0020: + sprintf (buffer, "REV "); + print_des_reg(); + break; + + case 0x0040: + if (is_34020) + sprintf (buffer, "IDLE "); + else + bad = 1; + break; + + case 0x0080: + if (is_34020) + sprintf (buffer, "MWAIT "); + else + bad = 1; + break; + + case 0x00e0: + if (is_34020) + sprintf (buffer, "BLMOVE %d,%d", (op >> 1) & 1, op & 1); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "EMU "); + break; + + case 0x0120: + sprintf (buffer, "EXGPC "); + print_des_reg(); + break; + + case 0x0140: + sprintf (buffer, "GETPC "); + print_des_reg(); + break; + + case 0x0160: + sprintf (buffer, "JUMP "); + print_des_reg(); + break; + + case 0x0180: + sprintf (buffer, "GETST "); + print_des_reg(); + break; + + case 0x01a0: + sprintf (buffer, "PUTST "); + print_des_reg(); + break; + + case 0x01c0: + sprintf (buffer, "POPST "); + break; + + case 0x01e0: + sprintf (buffer, "PUSHST "); + break; + + default: + bad = 1; + } + break; + + + case 0x0200: + switch (subop) + { + case 0x0040: + if (is_34020) + sprintf (buffer, "SETCSP "); + else + bad = 1; + break; + + case 0x0060: + if (is_34020) + sprintf (buffer, "SETCDP "); + else + bad = 1; + break; + + case 0x0080: + if (is_34020) + { + sprintf (buffer, "RPIX "); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x00a0: + if (is_34020) + { + sprintf (buffer, "EXGPS "); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x00c0: + if (is_34020) + { + sprintf (buffer, "GETPS "); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x00e0: + if (is_34020) + sprintf (buffer, "SETCMP "); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "NOP "); + break; + + case 0x0120: + sprintf (buffer, "CLRC "); + break; + + case 0x0140: + sprintf (buffer, "MOVB @"); + print_long_parm(); + strcat(buffer, ",@"); + print_long_parm(); + break; + + case 0x0160: + sprintf (buffer, "DINT "); + break; + + case 0x0180: + sprintf (buffer, "ABS "); + print_des_reg(); + break; + + case 0x01a0: + sprintf (buffer, "NEG "); + print_des_reg(); + break; + + case 0x01c0: + sprintf (buffer, "NEGB "); + print_des_reg(); + break; + + case 0x01e0: + sprintf (buffer, "NOT "); + print_des_reg(); + break; + + default: + bad = 1; + } + break; + + + case 0x0400: + case 0x0600: + switch (subop) + { + case 0x0000: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CEXEC %d,%06X,%d", (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + } + else + bad = 1; + break; + + case 0x0020: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVGC "); + print_des_reg(); + sprintf(temp, ",%06X,%d", (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x0040: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVGC "); + print_des_reg(); + strcat(buffer, ","); + rf = (x & 0x10) ? 'B' : 'A'; + print_reg(x & 0x0f); + sprintf(temp, ",%d,%06X,%d", (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x0060: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + + if (op == 0x0660 && (x & 0xff) == 0x01) + { + sprintf(buffer, "CMOVCS "); + sprintf(temp, ",%06X,%d", (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + { + sprintf(buffer, "CMOVCG "); + print_des_reg(); + strcat(buffer, ","); + rf = (x & 0x10) ? 'B' : 'A'; + print_reg(x & 0x0f); + sprintf(temp, ",%d,%06X,%d", (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + } + else + bad = 1; + break; + + case 0x0080: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVMC *"); + rf = (x & 0x10) ? 'B' : 'A'; + print_reg(x & 0x0f); + sprintf(temp, "+,%d,%d,%06X,%d", op & 0x1f, (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x00a0: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVCM *"); + print_des_reg(); + sprintf(temp, "+,%d,%d,%06X,%d", x & 0x1f, (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x00c0: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVCM *-"); + print_des_reg(); + sprintf(temp, ",%d,%d,%06X,%d", x & 0x1f, (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x00e0: + if (is_34020 && (op & 0xfe00) == 0x0600) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVMC *"); + rf = (x & 0x10) ? 'B' : 'A'; + print_reg(x & 0x0f); + strcat(buffer, "+,"); + rf = (op & 0x10) ? 'B' : 'A'; + print_reg(op & 0x0f); + sprintf(temp, ",%d,%06X,%d", (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "SEXT "); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + case 0x0120: + sprintf (buffer, "ZEXT "); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + case 0x0140: + case 0x0160: + sprintf (buffer, "SETF %Xh,%X,", + (op & 0x1f) ? op & 0x1f : 0x20, + (op >> 5) & 1); + print_field(); + break; + + case 0x0180: + sprintf (buffer, "MOVE "); + print_des_reg(); + strcat(buffer, ",@"); + print_long_parm(); + strcat(buffer, ","); + print_field(); + break; + + case 0x01a0: + sprintf (buffer, "MOVE @"); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + case 0x01c0: + sprintf (buffer, "MOVE @"); + print_long_parm(); + strcat(buffer, ",@"); + print_long_parm(); + strcat(buffer, ","); + print_field(); + break; + + case 0x01e0: + if (op & 0x200) + { + sprintf (buffer, "MOVE @"); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + } + else + { + sprintf (buffer, "MOVB "); + print_des_reg(); + strcat(buffer, ",@"); + print_long_parm(); + } + break; + + default: + bad = 1; + } + break; + + + case 0x0800: + switch (subop) + { + case 0x0000: + if (is_34020) + { + sprintf (buffer, "TRAPL "); + flags = DASMFLAG_STEP_OVER; + } + else + bad = 1; + break; + + case 0x0020: + if (is_34020) + { + UINT32 x; + PARAM_LONG(x); + sprintf(buffer, "CMOVMC *-"); + rf = (x & 0x10) ? 'B' : 'A'; + print_reg(x & 0x0f); + sprintf(temp, ",%d,%d,%06X,%d", op & 0x1f, (x >> 7) & 1, (x >> 8) & 0x1fffff, (x >> 29) & 7); + strcat(buffer, temp); + } + else + bad = 1; + break; + + case 0x0040: + if (is_34020) + sprintf (buffer, "VBLT B,L"); + else + bad = 1; + break; + + case 0x0060: + if (is_34020) + { + sprintf(buffer, "RETM "); + flags = DASMFLAG_STEP_OUT; + } + else + bad = 1; + break; + + case 0x00e0: + if (is_34020) + sprintf (buffer, "CLIP "); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "TRAP %Xh", op & 0x1f); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x0120: + sprintf (buffer, "CALL "); + print_des_reg(); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x0140: + sprintf (buffer, "RETI "); + flags = DASMFLAG_STEP_OUT; + break; + + case 0x0160: + sprintf (buffer, "RETS "); + flags = DASMFLAG_STEP_OUT; + if (op & 0x1f) + { + sprintf(temp, "%Xh", op & 0x1f); + strcat(buffer, temp); + } + break; + + case 0x0180: + sprintf (buffer, "MMTM "); + print_des_reg(); + print_reg_list(1); + break; + + case 0x01a0: + sprintf (buffer, "MMFM "); + print_des_reg(); + print_reg_list(0); + break; + + case 0x01c0: + sprintf (buffer, "MOVI "); + print_word_parm(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x01e0: + sprintf (buffer, "MOVI "); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + break; + + default: + bad = 1; + } + break; + + + case 0x0a00: + switch (subop) + { + case 0x0000: + if (is_34020) + sprintf (buffer, "VLCOL "); + else + bad = 1; + break; + + case 0x0020: + if (is_34020) + sprintf (buffer, "PFILL XY"); + else + bad = 1; + break; + + case 0x0040: + if (is_34020) + sprintf (buffer, "VFILL L"); + else + bad = 1; + break; + + case 0x0060: + if (is_34020) + { + sprintf (buffer, "CVMXYL "); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x0080: + if (is_34020) + { + sprintf (buffer, "CVDXYL "); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x00a0: + if (is_34020) + sprintf (buffer, "FPIXEQ "); + else + bad = 1; + break; + + case 0x00c0: + if (is_34020) + sprintf (buffer, "FPIXNE "); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "ADDI "); + print_word_parm(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x0120: + sprintf (buffer, "ADDI "); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x0140: + sprintf (buffer, "CMPI "); + print_word_parm_1s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x0160: + sprintf (buffer, "CMPI "); + print_long_parm_1s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x0180: + sprintf (buffer, "ANDI "); + print_long_parm_1s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x01a0: + sprintf (buffer, "ORI "); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x01c0: + sprintf (buffer, "XORI "); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x01e0: + sprintf (buffer, "SUBI "); + print_word_parm_1s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + default: + bad = 1; + } + break; + + + case 0x0c00: + switch (subop) + { + case 0x0000: + if (is_34020) + { + sprintf (buffer, "ADDXYI "); + print_long_parm(); + strcat(buffer, ","); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x0040: + if (is_34020) + sprintf (buffer, "LINIT "); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "SUBI "); + print_long_parm_1s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x0120: + sprintf (buffer, "CALLR "); + print_relative(); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x0140: + sprintf (buffer, "CALLA "); + print_long_parm(); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x0160: + sprintf (buffer, "EINT "); + break; + + case 0x0180: + sprintf (buffer, "DSJ "); + print_des_reg(); + strcat(buffer, ","); + print_relative(); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x01a0: + sprintf (buffer, "DSJEQ "); + print_des_reg(); + strcat(buffer, ","); + print_relative(); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x01c0: + sprintf (buffer, "DSJNE "); + print_des_reg(); + strcat(buffer, ","); + print_relative(); + flags = DASMFLAG_STEP_OVER; + break; + + case 0x01e0: + sprintf (buffer, "SETC "); + break; + + default: + bad = 1; + } + break; + + + case 0x0e00: + flags = DASMFLAG_STEP_OVER; + switch (subop) + { + case 0x0000: + if (is_34020) + sprintf (buffer, "PIXBLT L,M,L"); + else + bad = 1; + break; + + case 0x00e0: + if (is_34020) + sprintf (buffer, "TFILL XY"); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "PIXBLT L,L"); + break; + + case 0x0120: + sprintf (buffer, "PIXBLT L,XY"); + break; + + case 0x0140: + sprintf (buffer, "PIXBLT XY,L"); + break; + + case 0x0160: + sprintf (buffer, "PIXBLT XY,XY"); + break; + + case 0x0180: + sprintf (buffer, "PIXBLT B,L"); + break; + + case 0x01a0: + sprintf (buffer, "PIXBLT B,XY"); + break; + + case 0x01c0: + sprintf (buffer, "FILL L"); + break; + + case 0x01e0: + sprintf (buffer, "FILL XY"); + break; + + default: + bad = 1; + } + break; + + + case 0x1000: + case 0x1200: + if ((op & 0x03e0) != 0x0020) + { + sprintf (buffer, "ADDK "); + print_constant_1_32(); + strcat(buffer, ","); + } + else + { + sprintf (buffer, "INC "); + } + print_des_reg(); + + break; + + + case 0x1400: + case 0x1600: + if ((op & 0x03e0) != 0x0020) + { + sprintf (buffer, "SUBK "); + print_constant_1_32(); + strcat(buffer, ","); + } + else + { + sprintf (buffer, "DEC "); + } + print_des_reg(); + + break; + + + case 0x1800: + case 0x1a00: + sprintf (buffer, "MOVK "); + print_constant_1_32(); + strcat(buffer, ","); + print_des_reg(); + break; + + + case 0x1c00: + case 0x1e00: + sprintf (buffer, "BTST "); + print_constant_1s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + + case 0x2000: + case 0x2200: + sprintf (buffer, "SLA "); + print_constant(); + strcat(buffer, ","); + print_des_reg(); + break; + + + case 0x2400: + case 0x2600: + sprintf (buffer, "SLL "); + print_constant(); + strcat(buffer, ","); + print_des_reg(); + break; + + + case 0x2800: + case 0x2a00: + sprintf (buffer, "SRA "); + print_constant_2s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + + case 0x2c00: + case 0x2e00: + sprintf (buffer, "SRL "); + print_constant_2s_comp(); + strcat(buffer, ","); + print_des_reg(); + break; + + + case 0x3000: + case 0x3200: + sprintf (buffer, "RL "); + print_constant(); + strcat(buffer, ","); + print_des_reg(); + break; + + case 0x3400: + case 0x3600: + if (is_34020) + { + sprintf (buffer, "CMPK "); + print_constant_1_32(); + strcat(buffer, ","); + print_des_reg(); + } + else + bad = 1; + break; + + case 0x3800: + case 0x3a00: + case 0x3c00: + case 0x3e00: + sprintf (buffer, "DSJS "); + print_des_reg(); + strcat(buffer, ","); + print_relative_5bit(); + flags = DASMFLAG_STEP_OVER; + break; + + + case 0x4000: + sprintf (buffer, "ADD "); + print_src_des_reg(); + break; + + + case 0x4200: + sprintf (buffer, "ADDC "); + print_src_des_reg(); + break; + + + case 0x4400: + sprintf (buffer, "SUB "); + print_src_des_reg(); + break; + + + case 0x4600: + sprintf (buffer, "SUBB "); + print_src_des_reg(); + break; + + + case 0x4800: + sprintf (buffer, "CMP "); + print_src_des_reg(); + break; + + + case 0x4a00: + sprintf (buffer, "BTST "); + print_src_des_reg(); + break; + + + case 0x4c00: + case 0x4e00: + sprintf (buffer, "MOVE "); + + if (!(op & 0x0200)) + { + print_src_des_reg(); + } + else + { + print_src_reg(); + strcat(buffer, ","); + + if (rf == 'A') + { + rf = 'B'; + } + else + { + rf = 'A'; + } + + print_des_reg(); + } + break; + + + case 0x5000: + sprintf (buffer, "AND "); + print_src_des_reg(); + break; + + + case 0x5200: + sprintf (buffer, "ANDN "); + print_src_des_reg(); + break; + + + case 0x5400: + sprintf (buffer, "OR "); + print_src_des_reg(); + break; + + + case 0x5600: + if (rs != rd) + { + sprintf (buffer, "XOR "); + print_src_des_reg(); + } + else + { + sprintf (buffer, "CLR "); + print_des_reg(); + } + break; + + + case 0x5800: + sprintf (buffer, "DIVS "); + print_src_des_reg(); + break; + + + case 0x5a00: + sprintf (buffer, "DIVU "); + print_src_des_reg(); + break; + + + case 0x5c00: + sprintf (buffer, "MPYS "); + print_src_des_reg(); + break; + + + case 0x5e00: + sprintf (buffer, "MPYU "); + print_src_des_reg(); + break; + + + case 0x6000: + sprintf (buffer, "SLA "); + print_src_des_reg(); + break; + + + case 0x6200: + sprintf (buffer, "SLL "); + print_src_des_reg(); + break; + + + case 0x6400: + sprintf (buffer, "SRA "); + print_src_des_reg(); + break; + + + case 0x6600: + sprintf (buffer, "SRL "); + print_src_des_reg(); + break; + + + case 0x6800: + sprintf (buffer, "RL "); + print_src_des_reg(); + break; + + + case 0x6a00: + sprintf (buffer, "LMO "); + print_src_des_reg(); + break; + + + case 0x6c00: + sprintf (buffer, "MODS "); + print_src_des_reg(); + break; + + + case 0x6e00: + sprintf (buffer, "MODU "); + print_src_des_reg(); + break; + + + case 0x7a00: + if (is_34020) + { + sprintf (buffer, "RMO "); + print_src_des_reg(); + } + else + bad = 1; + break; + + case 0x7e00: + if (is_34020) + { + sprintf (buffer, "SWAPF *"); + print_src_des_reg(); + strcat(buffer, ",0"); + } + else + bad = 1; + break; + + + case 0x8000: + case 0x8200: + sprintf (buffer, "MOVE "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0x8400: + case 0x8600: + sprintf (buffer, "MOVE *"); + print_src_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0x8800: + case 0x8a00: + sprintf (buffer, "MOVE *"); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0x8c00: + sprintf (buffer, "MOVB "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + break; + + + case 0x8e00: + sprintf (buffer, "MOVB *"); + print_src_des_reg(); + break; + + + case 0x9000: + case 0x9200: + sprintf (buffer, "MOVE "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, "+,"); + print_field(); + break; + + + case 0x9400: + case 0x9600: + sprintf (buffer, "MOVE *"); + print_src_reg(); + strcat(buffer, "+,"); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0x9800: + case 0x9a00: + sprintf (buffer, "MOVE *"); + print_src_reg(); + strcat(buffer, "+,*"); + print_des_reg(); + strcat(buffer, "+,"); + print_field(); + break; + + + case 0x9c00: + sprintf (buffer, "MOVB *"); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + break; + + + case 0xa000: + case 0xa200: + sprintf (buffer, "MOVE "); + print_src_reg(); + strcat(buffer, ",-*"); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0xa400: + case 0xa600: + sprintf (buffer, "MOVE -*"); + print_src_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0xa800: + case 0xaa00: + sprintf (buffer, "MOVE -*"); + print_src_reg(); + strcat(buffer, ",-*"); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0xac00: + sprintf (buffer, "MOVB "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, ")"); + break; + + + case 0xae00: + sprintf (buffer, "MOVB *"); + print_src_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),"); + print_des_reg(); + break; + + + case 0xb000: + case 0xb200: + sprintf (buffer, "MOVE "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),"); + print_field(); + break; + + + case 0xb400: + case 0xb600: + sprintf (buffer, "MOVE *"); + print_src_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),"); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + + case 0xb800: + case 0xba00: + sprintf (buffer, "MOVE *"); + print_src_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),*"); + print_des_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),"); + print_field(); + break; + + + case 0xbc00: + sprintf (buffer, "MOVB *"); + print_src_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),*"); + print_des_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, ")"); + break; + + + case 0xc000: + case 0xc200: + case 0xc400: + case 0xc600: + case 0xc800: + case 0xca00: + case 0xcc00: + case 0xce00: + if ((op & 0x00ff) == 0x80) + { + sprintf (buffer, "JA"); + } + else + { + sprintf (buffer, "JR"); + } + + print_condition_code(); + strcat (buffer, " "); + + switch (op & 0x00ff) + { + case 0x00: + print_relative(); + break; + + case 0x80: + print_long_parm(); + break; + + default: + print_relative_8bit(); + } + break; + + + case 0xd000: + case 0xd200: + sprintf (buffer, "MOVE *"); + print_src_reg(); + strcat(buffer, "("); + print_word_parm(); + strcat(buffer, "),*"); + print_des_reg(); + strcat(buffer, "+,"); + print_field(); + break; + + + case 0xd400: + case 0xd600: + switch (subop) + { + case 0x0000: + sprintf (buffer, "MOVE @"); + print_long_parm(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, "+,"); + print_field(); + break; + + case 0x0100: + sprintf (buffer, "EXGF "); + print_des_reg(); + strcat(buffer, ","); + print_field(); + break; + + default: + bad = 1; + } + break; + + case 0xd800: + if (is_34020) + { + UINT32 x; + PARAM_WORD(x); + sprintf(buffer, "CEXEC %d,%06X,%d", op & 1, ((x << 5) & 0x1fffe0) | ((op >> 1) & 0x1f), (x >> 13) & 7); + } + else + bad = 1; + break; + + + case 0xde00: + switch (subop) + { + case 0x0000: + if (is_34020) + sprintf (buffer, "FLINE 0"); + else + bad = 1; + break; + + case 0x0080: + if (is_34020) + sprintf (buffer, "FLINE 1"); + else + bad = 1; + break; + + case 0x0100: + sprintf (buffer, "LINE 0"); + break; + + case 0x0180: + sprintf (buffer, "LINE 1"); + break; + + default: + bad = 1; + } + break; + + case 0xe000: + sprintf (buffer, "ADDXY "); + print_src_des_reg(); + break; + + + case 0xe200: + sprintf (buffer, "SUBXY "); + print_src_des_reg(); + break; + + + case 0xe400: + sprintf (buffer, "CMPXY "); + print_src_des_reg(); + break; + + + case 0xe600: + sprintf (buffer, "CPW "); + print_src_des_reg(); + break; + + + case 0xe800: + sprintf (buffer, "CVXYL "); + print_src_des_reg(); + break; + + + case 0xea00: + if (is_34020) + { + sprintf (buffer, "CVSXYL "); + print_src_des_reg(); + } + else + bad = 1; + break; + + + case 0xec00: + sprintf (buffer, "MOVX "); + print_src_des_reg(); + break; + + + case 0xee00: + sprintf (buffer, "MOVY "); + print_src_des_reg(); + break; + + + case 0xf000: + sprintf (buffer, "PIXT "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + strcat(buffer, ",XY"); + break; + + + case 0xf200: + sprintf (buffer, "PIXT *"); + print_src_reg(); + strcat(buffer, ",XY,"); + print_des_reg(); + break; + + + case 0xf400: + sprintf (buffer, "PIXT *"); + print_src_reg(); + strcat(buffer, ",XY,*"); + print_des_reg(); + strcat(buffer, ",XY"); + break; + + + case 0xf600: + sprintf (buffer, "DRAV "); + print_src_des_reg(); + break; + + + case 0xf800: + sprintf (buffer, "PIXT "); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + break; + + + case 0xfa00: + sprintf (buffer, "PIXT *"); + print_src_des_reg(); + break; + + + case 0xfc00: + sprintf (buffer, "PIXT *"); + print_src_reg(); + strcat(buffer, ",*"); + print_des_reg(); + break; + + default: + bad = 1; + } + + if (bad) + { + sprintf (buffer, "DW %04Xh", op & 0xffff); + } + + return (_pc - __pc) | flags | DASMFLAG_SUPPORTED; +} + +CPU_DISASSEMBLE( tms34010 ) +{ + rombase = oprom; + rambase = opram; + pcbase = pc; + return Dasm340x0(buffer, pc, 0); +} + +CPU_DISASSEMBLE( tms34020 ) +{ + rombase = oprom; + rambase = opram; + pcbase = pc; + return Dasm340x0(buffer, pc, 1); +} diff --git a/mame/tm34010/34010fld.c b/mame/tm34010/34010fld.c new file mode 100644 index 00000000..ca05039d --- /dev/null +++ b/mame/tm34010/34010fld.c @@ -0,0 +1,681 @@ +// license:BSD-3-Clause +// copyright-holders:Alex Pasadyn,Zsolt Vasvari +/*************************************************************************** + + TMS34010: Portable Texas Instruments TMS34010 emulator + + Copyright Alex Pasadyn/Zsolt Vasvari + Parts based on code by Aaron Giles + +***************************************************************************/ + + + +/*************************************************************************** + FIELD WRITE FUNCTIONS +***************************************************************************/ + +void tms340x0_device::wfield_01(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x01,16); +} + +void tms340x0_device::wfield_02(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x03,15); +} + +void tms340x0_device::wfield_03(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x07,14); +} + +void tms340x0_device::wfield_04(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x0f,13); +} + +void tms340x0_device::wfield_05(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x1f,12); +} + +void tms340x0_device::wfield_06(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x3f,11); +} + +void tms340x0_device::wfield_07(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x7f,10); +} + +void tms340x0_device::wfield_08(offs_t offset, UINT32 data) +{ + WFIELDMAC_8(); +} + +void tms340x0_device::wfield_09(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x1ff,8); +} + +void tms340x0_device::wfield_10(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x3ff,7); +} + +void tms340x0_device::wfield_11(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x7ff,6); +} + +void tms340x0_device::wfield_12(offs_t offset, UINT32 data) +{ + WFIELDMAC(0xfff,5); +} + +void tms340x0_device::wfield_13(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x1fff,4); +} + +void tms340x0_device::wfield_14(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x3fff,3); +} + +void tms340x0_device::wfield_15(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x7fff,2); +} + +void tms340x0_device::wfield_16(offs_t offset, UINT32 data) +{ + if (offset & 0x0f) + { + WFIELDMAC(0xffff,1); + } + else + { + TMS34010_WRMEM_WORD(TOBYTE(offset),data); + } +} + +void tms340x0_device::wfield_17(offs_t offset, UINT32 data) +{ + WFIELDMAC(0x1ffff,0); +} + +void tms340x0_device::wfield_18(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x3ffff,15); +} + +void tms340x0_device::wfield_19(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x7ffff,14); +} + +void tms340x0_device::wfield_20(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0xfffff,13); +} + +void tms340x0_device::wfield_21(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x1fffff,12); +} + +void tms340x0_device::wfield_22(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x3fffff,11); +} + +void tms340x0_device::wfield_23(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x7fffff,10); +} + +void tms340x0_device::wfield_24(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0xffffff,9); +} + +void tms340x0_device::wfield_25(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x1ffffff,8); +} + +void tms340x0_device::wfield_26(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x3ffffff,7); +} + +void tms340x0_device::wfield_27(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x7ffffff,6); +} + +void tms340x0_device::wfield_28(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0xfffffff,5); +} + +void tms340x0_device::wfield_29(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x1fffffff,4); +} + +void tms340x0_device::wfield_30(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x3fffffff,3); +} + +void tms340x0_device::wfield_31(offs_t offset, UINT32 data) +{ + WFIELDMAC_BIG(0x7fffffff,2); +} + +void tms340x0_device::wfield_32(offs_t offset, UINT32 data) +{ + WFIELDMAC_32(); +} + + +const tms340x0_device::wfield_func tms340x0_device::s_wfield_functions[32] = +{ + &tms340x0_device::wfield_32, &tms340x0_device::wfield_01, &tms340x0_device::wfield_02, &tms340x0_device::wfield_03, &tms340x0_device::wfield_04, &tms340x0_device::wfield_05, + &tms340x0_device::wfield_06, &tms340x0_device::wfield_07, &tms340x0_device::wfield_08, &tms340x0_device::wfield_09, &tms340x0_device::wfield_10, &tms340x0_device::wfield_11, + &tms340x0_device::wfield_12, &tms340x0_device::wfield_13, &tms340x0_device::wfield_14, &tms340x0_device::wfield_15, &tms340x0_device::wfield_16, &tms340x0_device::wfield_17, + &tms340x0_device::wfield_18, &tms340x0_device::wfield_19, &tms340x0_device::wfield_20, &tms340x0_device::wfield_21, &tms340x0_device::wfield_22, &tms340x0_device::wfield_23, + &tms340x0_device::wfield_24, &tms340x0_device::wfield_25, &tms340x0_device::wfield_26, &tms340x0_device::wfield_27, &tms340x0_device::wfield_28, &tms340x0_device::wfield_29, + &tms340x0_device::wfield_30, &tms340x0_device::wfield_31 +}; + + + +/*************************************************************************** + FIELD READ FUNCTIONS (ZERO-EXTEND) +***************************************************************************/ + +UINT32 tms340x0_device::rfield_z_01(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x01,16); + return ret; +} + +UINT32 tms340x0_device::rfield_z_02(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x03,15); + return ret; +} + +UINT32 tms340x0_device::rfield_z_03(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x07,14); + return ret; +} + +UINT32 tms340x0_device::rfield_z_04(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x0f,13); + return ret; +} + +UINT32 tms340x0_device::rfield_z_05(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1f,12); + return ret; +} + +UINT32 tms340x0_device::rfield_z_06(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x3f,11); + return ret; +} + +UINT32 tms340x0_device::rfield_z_07(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x7f,10); + return ret; +} + +UINT32 tms340x0_device::rfield_z_08(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_8(); + return ret; +} + +UINT32 tms340x0_device::rfield_z_09(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1ff,8); + return ret; +} + +UINT32 tms340x0_device::rfield_z_10(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x3ff,7); + return ret; +} + +UINT32 tms340x0_device::rfield_z_11(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x7ff,6); + return ret; +} + +UINT32 tms340x0_device::rfield_z_12(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0xfff,5); + return ret; +} + +UINT32 tms340x0_device::rfield_z_13(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1fff,4); + return ret; +} + +UINT32 tms340x0_device::rfield_z_14(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x3fff,3); + return ret; +} + +UINT32 tms340x0_device::rfield_z_15(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x7fff,2); + return ret; +} + +UINT32 tms340x0_device::rfield_z_16(offs_t offset) +{ + UINT32 ret; + if (offset & 0x0f) + { + RFIELDMAC(0xffff,1); + } + + else + ret = TMS34010_RDMEM_WORD(TOBYTE(offset)); + return ret; +} + +UINT32 tms340x0_device::rfield_z_17(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1ffff,0); + return ret; +} + +UINT32 tms340x0_device::rfield_z_18(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3ffff,15); + return ret; +} + +UINT32 tms340x0_device::rfield_z_19(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7ffff,14); + return ret; +} + +UINT32 tms340x0_device::rfield_z_20(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0xfffff,13); + return ret; +} + +UINT32 tms340x0_device::rfield_z_21(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x1fffff,12); + return ret; +} + +UINT32 tms340x0_device::rfield_z_22(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3fffff,11); + return ret; +} + +UINT32 tms340x0_device::rfield_z_23(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7fffff,10); + return ret; +} + +UINT32 tms340x0_device::rfield_z_24(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0xffffff,9); + return ret; +} + +UINT32 tms340x0_device::rfield_z_25(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x1ffffff,8); + return ret; +} + +UINT32 tms340x0_device::rfield_z_26(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3ffffff,7); + return ret; +} + +UINT32 tms340x0_device::rfield_z_27(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7ffffff,6); + return ret; +} + +UINT32 tms340x0_device::rfield_z_28(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0xfffffff,5); + return ret; +} + +UINT32 tms340x0_device::rfield_z_29(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x1fffffff,4); + return ret; +} + +UINT32 tms340x0_device::rfield_z_30(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3fffffff,3); + return ret; +} + +UINT32 tms340x0_device::rfield_z_31(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7fffffff,2); + return ret; +} + +UINT32 tms340x0_device::rfield_32(offs_t offset) +{ + RFIELDMAC_32(); +} + + +/*************************************************************************** + FIELD READ FUNCTIONS (SIGN-EXTEND) +***************************************************************************/ + +UINT32 tms340x0_device::rfield_s_01(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x01,16); + return ((INT32)(ret << 31)) >> 31; +} + +UINT32 tms340x0_device::rfield_s_02(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x03,15); + return ((INT32)(ret << 30)) >> 30; +} + +UINT32 tms340x0_device::rfield_s_03(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x07,14); + return ((INT32)(ret << 29)) >> 29; +} + +UINT32 tms340x0_device::rfield_s_04(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x0f,13); + return ((INT32)(ret << 28)) >> 28; +} + +UINT32 tms340x0_device::rfield_s_05(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1f,12); + return ((INT32)(ret << 27)) >> 27; +} + +UINT32 tms340x0_device::rfield_s_06(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x3f,11); + return ((INT32)(ret << 26)) >> 26; +} + +UINT32 tms340x0_device::rfield_s_07(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x7f,10); + return ((INT32)(ret << 25)) >> 25; +} + +UINT32 tms340x0_device::rfield_s_08(offs_t offset) +{ + UINT32 ret; + if (offset & 0x07) + { + RFIELDMAC(0xff,9); + } + + else + ret = TMS34010_RDMEM(TOBYTE(offset)); + return (INT32)(INT8)ret; +} + +UINT32 tms340x0_device::rfield_s_09(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1ff,8); + return ((INT32)(ret << 23)) >> 23; +} + +UINT32 tms340x0_device::rfield_s_10(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x3ff,7); + return ((INT32)(ret << 22)) >> 22; +} + +UINT32 tms340x0_device::rfield_s_11(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x7ff,6); + return ((INT32)(ret << 21)) >> 21; +} + +UINT32 tms340x0_device::rfield_s_12(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0xfff,5); + return ((INT32)(ret << 20)) >> 20; +} + +UINT32 tms340x0_device::rfield_s_13(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1fff,4); + return ((INT32)(ret << 19)) >> 19; +} + +UINT32 tms340x0_device::rfield_s_14(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x3fff,3); + return ((INT32)(ret << 18)) >> 18; +} + +UINT32 tms340x0_device::rfield_s_15(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x7fff,2); + return ((INT32)(ret << 17)) >> 17; +} + +UINT32 tms340x0_device::rfield_s_16(offs_t offset) +{ + UINT32 ret; + if (offset & 0x0f) + { + RFIELDMAC(0xffff,1); + } + + else + { + ret = TMS34010_RDMEM_WORD(TOBYTE(offset)); + } + + return (INT32)(INT16)ret; +} + +UINT32 tms340x0_device::rfield_s_17(offs_t offset) +{ + UINT32 ret; + RFIELDMAC(0x1ffff,0); + return ((INT32)(ret << 15)) >> 15; +} + +UINT32 tms340x0_device::rfield_s_18(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3ffff,15); + return ((INT32)(ret << 14)) >> 14; +} + +UINT32 tms340x0_device::rfield_s_19(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7ffff,14); + return ((INT32)(ret << 13)) >> 13; +} + +UINT32 tms340x0_device::rfield_s_20(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0xfffff,13); + return ((INT32)(ret << 12)) >> 12; +} + +UINT32 tms340x0_device::rfield_s_21(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x1fffff,12); + return ((INT32)(ret << 11)) >> 11; +} + +UINT32 tms340x0_device::rfield_s_22(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3fffff,11); + return ((INT32)(ret << 10)) >> 10; +} + +UINT32 tms340x0_device::rfield_s_23(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7fffff,10); + return ((INT32)(ret << 9)) >> 9; +} + +UINT32 tms340x0_device::rfield_s_24(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0xffffff,9); + return ((INT32)(ret << 8)) >> 8; +} + +UINT32 tms340x0_device::rfield_s_25(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x1ffffff,8); + return ((INT32)(ret << 7)) >> 7; +} + +UINT32 tms340x0_device::rfield_s_26(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3ffffff,7); + return ((INT32)(ret << 6)) >> 6; +} + +UINT32 tms340x0_device::rfield_s_27(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7ffffff,6); + return ((INT32)(ret << 5)) >> 5; +} + +UINT32 tms340x0_device::rfield_s_28(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0xfffffff,5); + return ((INT32)(ret << 4)) >> 4; +} + +UINT32 tms340x0_device::rfield_s_29(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x1fffffff,4); + return ((INT32)(ret << 3)) >> 3; +} + +UINT32 tms340x0_device::rfield_s_30(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x3fffffff,3); + return ((INT32)(ret << 2)) >> 2; +} + +UINT32 tms340x0_device::rfield_s_31(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_BIG(0x7fffffff,2); + return ((INT32)(ret << 1)) >> 1; +} + +const tms340x0_device::rfield_func tms340x0_device::s_rfield_functions[64] = +{ + &tms340x0_device::rfield_32 , &tms340x0_device::rfield_z_01, &tms340x0_device::rfield_z_02, &tms340x0_device::rfield_z_03, &tms340x0_device::rfield_z_04, &tms340x0_device::rfield_z_05, + &tms340x0_device::rfield_z_06, &tms340x0_device::rfield_z_07, &tms340x0_device::rfield_z_08, &tms340x0_device::rfield_z_09, &tms340x0_device::rfield_z_10, &tms340x0_device::rfield_z_11, + &tms340x0_device::rfield_z_12, &tms340x0_device::rfield_z_13, &tms340x0_device::rfield_z_14, &tms340x0_device::rfield_z_15, &tms340x0_device::rfield_z_16, &tms340x0_device::rfield_z_17, + &tms340x0_device::rfield_z_18, &tms340x0_device::rfield_z_19, &tms340x0_device::rfield_z_20, &tms340x0_device::rfield_z_21, &tms340x0_device::rfield_z_22, &tms340x0_device::rfield_z_23, + &tms340x0_device::rfield_z_24, &tms340x0_device::rfield_z_25, &tms340x0_device::rfield_z_26, &tms340x0_device::rfield_z_27, &tms340x0_device::rfield_z_28, &tms340x0_device::rfield_z_29, + &tms340x0_device::rfield_z_30, &tms340x0_device::rfield_z_31, + &tms340x0_device::rfield_32 , &tms340x0_device::rfield_s_01, &tms340x0_device::rfield_s_02, &tms340x0_device::rfield_s_03, &tms340x0_device::rfield_s_04, &tms340x0_device::rfield_s_05, + &tms340x0_device::rfield_s_06, &tms340x0_device::rfield_s_07, &tms340x0_device::rfield_s_08, &tms340x0_device::rfield_s_09, &tms340x0_device::rfield_s_10, &tms340x0_device::rfield_s_11, + &tms340x0_device::rfield_s_12, &tms340x0_device::rfield_s_13, &tms340x0_device::rfield_s_14, &tms340x0_device::rfield_s_15, &tms340x0_device::rfield_s_16, &tms340x0_device::rfield_s_17, + &tms340x0_device::rfield_s_18, &tms340x0_device::rfield_s_19, &tms340x0_device::rfield_s_20, &tms340x0_device::rfield_s_21, &tms340x0_device::rfield_s_22, &tms340x0_device::rfield_s_23, + &tms340x0_device::rfield_s_24, &tms340x0_device::rfield_s_25, &tms340x0_device::rfield_s_26, &tms340x0_device::rfield_s_27, &tms340x0_device::rfield_s_28, &tms340x0_device::rfield_s_29, + &tms340x0_device::rfield_s_30, &tms340x0_device::rfield_s_31 +}; diff --git a/mame/tm34010/34010gfx.c b/mame/tm34010/34010gfx.c new file mode 100644 index 00000000..01d5688f --- /dev/null +++ b/mame/tm34010/34010gfx.c @@ -0,0 +1,1979 @@ +// license:BSD-3-Clause +// copyright-holders:Alex Pasadyn,Zsolt Vasvari,Aaron Giles +/*************************************************************************** + + TMS34010: Portable Texas Instruments TMS34010 emulator + + Copyright Alex Pasadyn/Zsolt Vasvari + Parts based on code by Aaron Giles + +***************************************************************************/ + +#ifndef RECURSIVE_INCLUDE + + +#define LOG_GFX_OPS 0 +#define LOGGFX(x) do { logerror x; } while(0) +//#define LOGGFX(x) do { if (LOG_GFX_OPS && machine().input().code_pressed(KEYCODE_L)) logerror x; } while (0) + + +/* Graphics Instructions */ + +void tms340x0_device::line(UINT16 op) +{ + if (!P_FLAG()) + { + if (WINDOW_CHECKING() != 0 && WINDOW_CHECKING() != 3) + logerror("LINE XY %08X - Window Checking Mode %d not supported\n", m_pc, WINDOW_CHECKING()); + + m_st |= STBIT_P; + TEMP() = (op & 0x80) ? 1 : 0; /* boundary value depends on the algorithm */ + LOGGFX(("%08X(%3d):LINE (%d,%d)-(%d,%d)\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DADDR_X() + DYDX_X(), DADDR_Y() + DYDX_Y())); + } + + if (COUNT() > 0) + { + INT16 x1,y1; + + COUNT()--; + if (WINDOW_CHECKING() != 3 || + (DADDR_X() >= WSTART_X() && DADDR_X() <= WEND_X() && + DADDR_Y() >= WSTART_Y() && DADDR_Y() <= WEND_Y())) + WPIXEL(DXYTOL(DADDR_XY()),COLOR1()); + + if (SADDR() >= TEMP()) + { + SADDR() += DYDX_Y()*2 - DYDX_X()*2; + x1 = INC1_X(); + y1 = INC1_Y(); + } + else + { + SADDR() += DYDX_Y()*2; + x1 = INC2_X(); + y1 = INC2_Y(); + } + DADDR_X() += x1; + DADDR_Y() += y1; + + COUNT_UNKNOWN_CYCLES(2); + m_pc -= 0x10; /* not done yet, check for interrupts and restart instruction */ + return; + } + m_st &= ~STBIT_P; +} + + +/* +cases: +* window modes (0,1,2,3) +* boolean/arithmetic ops (16+6) +* transparency (on/off) +* plane masking +* directions (left->right/right->left, top->bottom/bottom->top) +*/ + +int tms340x0_device::apply_window(const char *inst_name,int srcbpp, UINT32 *srcaddr, XY *dst, int *dx, int *dy) +{ + /* apply the window */ + if (WINDOW_CHECKING() == 0) + return 0; + else + { + int sx = dst->x; + int sy = dst->y; + int ex = sx + *dx - 1; + int ey = sy + *dy - 1; + int diff, cycles = 3; + +#if 0 + if (WINDOW_CHECKING() == 2) + logerror("%08x: %s apply_window window mode %d not supported!\n", pc(), inst_name, WINDOW_CHECKING()); +#endif + CLR_V(); + if (WINDOW_CHECKING() == 1) + SET_V_LOG(1); + + /* clip X */ + diff = WSTART_X() - sx; + if (diff > 0) + { + if (srcaddr) + *srcaddr += diff * srcbpp; + sx += diff; + SET_V_LOG(1); + } + diff = ex - WEND_X(); + if (diff > 0) + { + ex -= diff; + SET_V_LOG(1); + } + + + /* clip Y */ + diff = WSTART_Y() - sy; + if (diff > 0) + { + if (srcaddr) + *srcaddr += diff * m_convsp; + + sy += diff; + SET_V_LOG(1); + } + diff = ey - WEND_Y(); + if (diff > 0) + { + ey -= diff; + SET_V_LOG(1); + } + + /* compute cycles */ + if (*dx != ex - sx + 1 || *dy != ey - sy + 1) + { + if (dst->x != sx || dst->y != sy) + cycles += 11; + else + cycles += 3; + } + else if (dst->x != sx || dst->y != sy) + cycles += 7; + + /* update the values */ + dst->x = sx; + dst->y = sy; + *dx = ex - sx + 1; + *dy = ey - sy + 1; + return cycles; + } +} + + +/******************************************************************* + + About the timing of gfx operations: + + The 34010 manual lists a fairly intricate and accurate way of + computing cycle timings for graphics ops. However, there are + enough typos and misleading statements to make the reliability + of the timing info questionable. + + So, to address this, here is a simplified approximate version + of the timing. + + timing = setup + (srcwords * 2 + dstwords * gfxop) * rows + + Each read access takes 2 cycles. Each gfx operation has + its own timing as specified in the 34010 manual. So, it's 2 + cycles per read plus gfxop cycles per operation. Pretty + simple, no? + +*******************************************************************/ + +int tms340x0_device::compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing) +{ + int dstwords; + + if (left_partials) full_words += 1; + if (right_partials) full_words += 1; + dstwords = full_words; + + return (dstwords * op_timing); +} + +int tms340x0_device::compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing) +{ + int srcwords, dstwords; + + if (left_partials) full_words += 1; + if (right_partials) full_words += 1; + srcwords = full_words; + dstwords = full_words; + + return (dstwords * op_timing + srcwords * 2) + 2; +} + +int tms340x0_device::compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp) +{ + int srcwords, dstwords; + + if (left_partials) full_words += 1; + if (right_partials) full_words += 1; + srcwords = full_words * bpp / 16; + dstwords = full_words; + + return (dstwords * op_timing + srcwords * 2) * rows + 2; +} + + +/* Shift register handling */ +void tms340x0_device::memory_w(address_space &space, offs_t offset,UINT16 data) +{ + space.write_word(offset, data); +} + +UINT16 tms340x0_device::memory_r(address_space &space, offs_t offset) +{ + return space.read_word(offset); +} + +void tms340x0_device::shiftreg_w(address_space &space, offs_t offset,UINT16 data) +{ +#if 0 + if (!m_from_shiftreg_cb.isnull()) + m_from_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]); + else + logerror("From ShiftReg function not set. PC = %08X\n", m_pc); +#endif +} + +UINT16 tms340x0_device::shiftreg_r(address_space &space, offs_t offset) +{ +#if 0 + if (!m_to_shiftreg_cb.isnull()) + m_to_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]); + else + logerror("To ShiftReg function not set. PC = %08X\n", m_pc); + return m_shiftreg[0]; +#endif + return 0; +} + +UINT16 tms340x0_device::dummy_shiftreg_r(address_space &space, offs_t offset) +{ + return m_shiftreg[0]; +} + + + +/* Pixel operations */ +UINT32 tms340x0_device::pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix; } +UINT32 tms340x0_device::pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & dstpix; } +UINT32 tms340x0_device::pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & ~dstpix; } +UINT32 tms340x0_device::pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return 0; } +UINT32 tms340x0_device::pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix | ~dstpix) & mask; } +UINT32 tms340x0_device::pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix ^ dstpix) & mask; } +UINT32 tms340x0_device::pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~dstpix & mask; } +UINT32 tms340x0_device::pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix | dstpix) & mask; } +UINT32 tms340x0_device::pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix | dstpix) & mask; } +UINT32 tms340x0_device::pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return dstpix & mask; } +UINT32 tms340x0_device::pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix ^ dstpix) & mask; } +UINT32 tms340x0_device::pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; } +UINT32 tms340x0_device::pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return mask; } +UINT32 tms340x0_device::pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; } +UINT32 tms340x0_device::pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix & dstpix) & mask; } +UINT32 tms340x0_device::pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix ^ mask; } +UINT32 tms340x0_device::pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix + dstpix) & mask; } +UINT32 tms340x0_device::pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix + (dstpix & mask); return (tmp > mask) ? mask : tmp; } +UINT32 tms340x0_device::pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (dstpix - srcpix) & mask; } +UINT32 tms340x0_device::pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix - (dstpix & mask); return (tmp < 0) ? 0 : tmp; } +UINT32 tms340x0_device::pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix > dstpix) ? srcpix : dstpix; } +UINT32 tms340x0_device::pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix < dstpix) ? srcpix : dstpix; } + +const tms340x0_device::pixel_op_func tms340x0_device::s_pixel_op_table[32] = +{ + &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op01, &tms340x0_device::pixel_op02, &tms340x0_device::pixel_op03, &tms340x0_device::pixel_op04, &tms340x0_device::pixel_op05, &tms340x0_device::pixel_op06, &tms340x0_device::pixel_op07, + &tms340x0_device::pixel_op08, &tms340x0_device::pixel_op09, &tms340x0_device::pixel_op10, &tms340x0_device::pixel_op11, &tms340x0_device::pixel_op12, &tms340x0_device::pixel_op13, &tms340x0_device::pixel_op14, &tms340x0_device::pixel_op15, + &tms340x0_device::pixel_op16, &tms340x0_device::pixel_op17, &tms340x0_device::pixel_op18, &tms340x0_device::pixel_op19, &tms340x0_device::pixel_op20, &tms340x0_device::pixel_op21, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, + &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00 +}; +const UINT8 tms340x0_device::s_pixel_op_timing_table[33] = +{ + 2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,6,5,5,2,2,2,2,2,2,2,2,2,2,2 +}; + + +/* tables */ +const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_op_table[] = +{ + &tms340x0_device::pixblt_1_op0, &tms340x0_device::pixblt_1_op0_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, + + &tms340x0_device::pixblt_2_op0, &tms340x0_device::pixblt_2_op0_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, + + &tms340x0_device::pixblt_4_op0, &tms340x0_device::pixblt_4_op0_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, + + &tms340x0_device::pixblt_8_op0, &tms340x0_device::pixblt_8_op0_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, + + &tms340x0_device::pixblt_16_op0, &tms340x0_device::pixblt_16_op0_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, + &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans +}; + +const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_r_op_table[] = +{ + &tms340x0_device::pixblt_r_1_op0, &tms340x0_device::pixblt_r_1_op0_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, + + &tms340x0_device::pixblt_r_2_op0, &tms340x0_device::pixblt_r_2_op0_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, + + &tms340x0_device::pixblt_r_4_op0, &tms340x0_device::pixblt_r_4_op0_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, + + &tms340x0_device::pixblt_r_8_op0, &tms340x0_device::pixblt_r_8_op0_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, + + &tms340x0_device::pixblt_r_16_op0,&tms340x0_device::pixblt_r_16_op0_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, + &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans +}; + +const tms340x0_device::pixblt_b_op_func tms340x0_device::s_pixblt_b_op_table[] = +{ + &tms340x0_device::pixblt_b_1_op0, &tms340x0_device::pixblt_b_1_op0_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, + + &tms340x0_device::pixblt_b_2_op0, &tms340x0_device::pixblt_b_2_op0_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, + + &tms340x0_device::pixblt_b_4_op0, &tms340x0_device::pixblt_b_4_op0_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, + + &tms340x0_device::pixblt_b_8_op0, &tms340x0_device::pixblt_b_8_op0_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, + + &tms340x0_device::pixblt_b_16_op0,&tms340x0_device::pixblt_b_16_op0_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, + &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans +}; + +const tms340x0_device::pixblt_b_op_func tms340x0_device::s_fill_op_table[] = +{ + &tms340x0_device::fill_1_op0, &tms340x0_device::fill_1_op0_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, + + &tms340x0_device::fill_2_op0, &tms340x0_device::fill_2_op0_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, + + &tms340x0_device::fill_4_op0, &tms340x0_device::fill_4_op0_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, + + &tms340x0_device::fill_8_op0, &tms340x0_device::fill_8_op0_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, + + &tms340x0_device::fill_16_op0, &tms340x0_device::fill_16_op0_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, + &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans +}; + + +#define RECURSIVE_INCLUDE + +/* non-transparent replace ops */ +#define PIXEL_OP(src, mask, pixel) pixel = pixel +#define PIXEL_OP_TIMING 2 +#define PIXEL_OP_REQUIRES_SOURCE 0 +#define TRANSPARENCY 0 + + /* 1bpp cases */ + #define BITS_PER_PIXEL 1 + #define FUNCTION_NAME(base) base##_1_op0 + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 2bpp cases */ + #define BITS_PER_PIXEL 2 + #define FUNCTION_NAME(base) base##_2_op0 + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 4bpp cases */ + #define BITS_PER_PIXEL 4 + #define FUNCTION_NAME(base) base##_4_op0 + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 8bpp cases */ + #define BITS_PER_PIXEL 8 + #define FUNCTION_NAME(base) base##_8_op0 + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 16bpp cases */ + #define BITS_PER_PIXEL 16 + #define FUNCTION_NAME(base) base##_16_op0 + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + +#undef TRANSPARENCY +#undef PIXEL_OP_REQUIRES_SOURCE +#undef PIXEL_OP_TIMING +#undef PIXEL_OP + + +#define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel) +#define PIXEL_OP_TIMING m_pixel_op_timing +#define PIXEL_OP_REQUIRES_SOURCE 1 +#define TRANSPARENCY 0 + + /* 1bpp cases */ + #define BITS_PER_PIXEL 1 + #define FUNCTION_NAME(base) base##_1_opx + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 2bpp cases */ + #define BITS_PER_PIXEL 2 + #define FUNCTION_NAME(base) base##_2_opx + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 4bpp cases */ + #define BITS_PER_PIXEL 4 + #define FUNCTION_NAME(base) base##_4_opx + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 8bpp cases */ + #define BITS_PER_PIXEL 8 + #define FUNCTION_NAME(base) base##_8_opx + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 16bpp cases */ + #define BITS_PER_PIXEL 16 + #define FUNCTION_NAME(base) base##_16_opx + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + +#undef TRANSPARENCY +#undef PIXEL_OP_REQUIRES_SOURCE +#undef PIXEL_OP_TIMING +#undef PIXEL_OP + + +/* transparent replace ops */ +#define PIXEL_OP(src, mask, pixel) pixel = pixel +#define PIXEL_OP_REQUIRES_SOURCE 0 +#define PIXEL_OP_TIMING 4 +#define TRANSPARENCY 1 + + /* 1bpp cases */ + #define BITS_PER_PIXEL 1 + #define FUNCTION_NAME(base) base##_1_op0_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 2bpp cases */ + #define BITS_PER_PIXEL 2 + #define FUNCTION_NAME(base) base##_2_op0_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 4bpp cases */ + #define BITS_PER_PIXEL 4 + #define FUNCTION_NAME(base) base##_4_op0_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 8bpp cases */ + #define BITS_PER_PIXEL 8 + #define FUNCTION_NAME(base) base##_8_op0_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 16bpp cases */ + #define BITS_PER_PIXEL 16 + #define FUNCTION_NAME(base) base##_16_op0_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + +#undef TRANSPARENCY +#undef PIXEL_OP_REQUIRES_SOURCE +#undef PIXEL_OP_TIMING +#undef PIXEL_OP + + +#define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel) +#define PIXEL_OP_REQUIRES_SOURCE 1 +#define PIXEL_OP_TIMING (2+m_pixel_op_timing) +#define TRANSPARENCY 1 + + /* 1bpp cases */ + #define BITS_PER_PIXEL 1 + #define FUNCTION_NAME(base) base##_1_opx_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 2bpp cases */ + #define BITS_PER_PIXEL 2 + #define FUNCTION_NAME(base) base##_2_opx_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 4bpp cases */ + #define BITS_PER_PIXEL 4 + #define FUNCTION_NAME(base) base##_4_opx_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 8bpp cases */ + #define BITS_PER_PIXEL 8 + #define FUNCTION_NAME(base) base##_8_opx_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + + /* 16bpp cases */ + #define BITS_PER_PIXEL 16 + #define FUNCTION_NAME(base) base##_16_opx_trans + #include "34010gfx.c" + #undef FUNCTION_NAME + #undef BITS_PER_PIXEL + +#undef TRANSPARENCY +#undef PIXEL_OP_REQUIRES_SOURCE +#undef PIXEL_OP_TIMING +#undef PIXEL_OP + +static const UINT8 pixelsize_lookup[32] = +{ + 0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 +}; + + +void tms340x0_device::pixblt_b_l(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + (this->*s_pixblt_b_op_table[ix])(1); +} + +void tms340x0_device::pixblt_b_xy(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + (this->*s_pixblt_b_op_table[ix])(0); +} + +void tms340x0_device::pixblt_l_l(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int pbh = (IOREG(REG_CONTROL) >> 8) & 1; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + if (!pbh) + (this->*s_pixblt_op_table[ix])(1, 1); + else + (this->*s_pixblt_r_op_table[ix])(1, 1); +} + +void tms340x0_device::pixblt_l_xy(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int pbh = (IOREG(REG_CONTROL) >> 8) & 1; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + if (!pbh) + (this->*s_pixblt_op_table[ix])(1, 0); + else + (this->*s_pixblt_r_op_table[ix])(1, 0); +} + +void tms340x0_device::pixblt_xy_l(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int pbh = (IOREG(REG_CONTROL) >> 8) & 1; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + if (!pbh) + (this->*s_pixblt_op_table[ix])(0, 1); + else + (this->*s_pixblt_r_op_table[ix])(0, 1); +} + +void tms340x0_device::pixblt_xy_xy(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int pbh = (IOREG(REG_CONTROL) >> 8) & 1; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,XY (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + if (!pbh) + (this->*s_pixblt_op_table[ix])(0, 0); + else + (this->*s_pixblt_r_op_table[ix])(0, 0); +} + +void tms340x0_device::fill_l(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + (this->*s_fill_op_table[ix])(1); +} + +void tms340x0_device::fill_xy(UINT16 op) +{ + int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; + int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; + int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; + int ix = trans | (rop << 1) | (psize << 6); + if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); + m_pixel_op = s_pixel_op_table[rop]; + m_pixel_op_timing = s_pixel_op_timing_table[rop]; + (this->*s_fill_op_table[ix])(0); +} + + +#else + + +#undef PIXELS_PER_WORD +#undef PIXEL_MASK + +#define PIXELS_PER_WORD (16 / BITS_PER_PIXEL) +#define PIXEL_MASK ((1 << BITS_PER_PIXEL) - 1) + +void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear) +{ + /* if this is the first time through, perform the operation */ + if (!P_FLAG()) + { + int dx, dy, x, y, /*words,*/ yreverse; + word_write_func word_write; + word_read_func word_read; + UINT32 readwrites = 0; + UINT32 saddr, daddr; + XY dstxy = { 0 }; + + /* determine read/write functions */ + if (IOREG(REG_DPYCTL) & 0x0800) + { + word_write = &tms340x0_device::shiftreg_w; + word_read = &tms340x0_device::shiftreg_r; + } + else + { + word_write = &tms340x0_device::memory_w; + word_read = &tms340x0_device::memory_r; + } + + /* compute the starting addresses */ + saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY()); + + /* compute the bounds of the operation */ + dx = (INT16)DYDX_X(); + dy = (INT16)DYDX_Y(); + + /* apply the window for non-linear destinations */ + m_gfxcycles = 7 + (src_is_linear ? 0 : 2); + if (!dst_is_linear) + { + dstxy = DADDR_XY(); + m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy); + daddr = DXYTOL(dstxy); + } + else + daddr = DADDR(); + daddr &= ~(BITS_PER_PIXEL - 1); + LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); + + /* bail if we're clipped */ + if (dx <= 0 || dy <= 0) + return; + + /* window mode 1: just return and interrupt if we are within the window */ + if (WINDOW_CHECKING() == 1 && !dst_is_linear) + { + CLR_V(); + DADDR_XY() = dstxy; + DYDX_X() = dx; + DYDX_Y() = dy; + IOREG(REG_INTPEND) |= TMS34010_WV; + check_interrupt(); + return; + } + + /* handle flipping the addresses */ + yreverse = (IOREG(REG_CONTROL) >> 9) & 1; + if (!src_is_linear || !dst_is_linear) + { + if (yreverse) + { + saddr += (dy - 1) * m_convsp; + daddr += (dy - 1) * m_convdp; + } + } + + m_st |= STBIT_P; + + /* loop over rows */ + for (y = 0; y < dy; y++) + { + UINT32 srcwordaddr = saddr >> 4; + UINT32 dstwordaddr = daddr >> 4; + UINT8 srcbit = saddr & 15; + UINT8 dstbit = daddr & 15; + UINT32 srcword, dstword = 0; + + /* fetch the initial source word */ + srcword = (this->*word_read)(*m_program, srcwordaddr++ << 1); + readwrites++; + + /* fetch the initial dest word */ + if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY || (daddr & 0x0f) != 0) + { + dstword = (this->*word_read)(*m_program, dstwordaddr << 1); + readwrites++; + } + + /* loop over pixels */ + for (x = 0; x < dx; x++) + { + UINT32 dstmask; + UINT32 pixel; + + /* fetch more words if necessary */ + if (srcbit + BITS_PER_PIXEL > 16) + { + srcword |= (this->*word_read)(*m_program, srcwordaddr++ << 1) << 16; + readwrites++; + } + + /* extract pixel from source */ + pixel = (srcword >> srcbit) & PIXEL_MASK; + srcbit += BITS_PER_PIXEL; + if (srcbit > 16) + { + srcbit -= 16; + srcword >>= 16; + } + + /* fetch additional destination word if necessary */ + if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) + if (dstbit + BITS_PER_PIXEL > 16) + { + dstword |= (this->*word_read)(*m_program, (dstwordaddr + 1) << 1) << 16; + readwrites++; + } + + /* apply pixel operations */ + pixel <<= dstbit; + dstmask = PIXEL_MASK << dstbit; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* flush destination words */ + dstbit += BITS_PER_PIXEL; + if (dstbit > 16) + { + (this->*word_write)(*m_program, dstwordaddr++ << 1, dstword); + readwrites++; + dstbit -= 16; + dstword >>= 16; + } + } + + /* flush any remaining words */ + if (dstbit > 0) + { + /* if we're right-partial, read and mask the remaining bits */ + if (dstbit != 16) + { + UINT16 origdst = (this->*word_read)(*m_program, dstwordaddr << 1); + UINT16 mask = 0xffff << dstbit; + dstword = (dstword & ~mask) | (origdst & mask); + readwrites++; + } + + (this->*word_write)(*m_program, dstwordaddr++ << 1, dstword); + readwrites++; + } + + + +#if 0 + int left_partials, right_partials, full_words, bitshift, bitshift_alt; + UINT16 srcword, srcmask, dstword, dstmask, pixel; + UINT32 swordaddr, dwordaddr; + + /* determine the bit shift to get from source to dest */ + bitshift = ((daddr & 15) - (saddr & 15)) & 15; + bitshift_alt = (16 - bitshift) & 15; + + /* how many left and right partial pixels do we have? */ + left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); + right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; + full_words = dx - left_partials - right_partials; + if (full_words < 0) + left_partials = dx, right_partials = full_words = 0; + else + full_words /= PIXELS_PER_WORD; + + /* compute cycles */ + m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); + + /* use word addresses each row */ + swordaddr = saddr >> 4; + dwordaddr = daddr >> 4; + + /* fetch the initial source word */ + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = PIXEL_MASK << (saddr & 15); + + /* handle the left partial word */ + if (left_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + dstmask = PIXEL_MASK << (daddr & 15); + + /* loop over partials */ + for (x = 0; x < left_partials; x++) + { + /* fetch another word if necessary */ + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = PIXEL_MASK; + } + + /* process the pixel */ + pixel = srcword & srcmask; + if (dstmask > srcmask) + pixel <<= bitshift; + else + pixel >>= bitshift_alt; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the source */ + srcmask <<= BITS_PER_PIXEL; + + /* update the destination */ + dstmask <<= BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* loop over full words */ + for (words = 0; words < full_words; words++) + { + /* fetch the destination word (if necessary) */ + if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + else + dstword = 0; + dstmask = PIXEL_MASK; + + /* loop over partials */ + for (x = 0; x < PIXELS_PER_WORD; x++) + { + /* fetch another word if necessary */ + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = PIXEL_MASK; + } + + /* process the pixel */ + pixel = srcword & srcmask; + if (dstmask > srcmask) + pixel <<= bitshift; + else + pixel >>= bitshift_alt; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the source */ + srcmask <<= BITS_PER_PIXEL; + + /* update the destination */ + dstmask <<= BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* handle the right partial word */ + if (right_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + dstmask = PIXEL_MASK; + + /* loop over partials */ + for (x = 0; x < right_partials; x++) + { + /* fetch another word if necessary */ + if (srcmask == 0) + { + LOGGFX((" right fetch @ %08x\n", swordaddr)); + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = PIXEL_MASK; + } + + /* process the pixel */ + pixel = srcword & srcmask; + if (dstmask > srcmask) + pixel <<= bitshift; + else + pixel >>= bitshift_alt; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the source */ + srcmask <<= BITS_PER_PIXEL; + + /* update the destination */ + dstmask <<= BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } +#endif + + /* update for next row */ + if (!yreverse) + { + saddr += SPTCH(); + daddr += DPTCH(); + } + else + { + saddr -= SPTCH(); + daddr -= DPTCH(); + } + } + + m_gfxcycles += readwrites * 2 + dx * dy * (PIXEL_OP_TIMING - 2); + + LOGGFX((" (%d cycles)\n", m_gfxcycles)); + } + + /* eat cycles */ + if (m_gfxcycles > m_icount) + { + m_gfxcycles -= m_icount; + m_icount = 0; + m_pc -= 0x10; + } + else + { + m_icount -= m_gfxcycles; + m_st &= ~STBIT_P; + if (src_is_linear && dst_is_linear) + SADDR() += DYDX_Y() * SPTCH(); + else if (src_is_linear) + SADDR() += DYDX_Y() * SPTCH(); + else + SADDR_Y() += DYDX_Y(); + if (dst_is_linear) + DADDR() += DYDX_Y() * DPTCH(); + else + DADDR_Y() += DYDX_Y(); + } +} + +void FUNCTION_NAME(tms340x0_device::pixblt_r)(int src_is_linear, int dst_is_linear) +{ + /* if this is the first time through, perform the operation */ + if (!P_FLAG()) + { + int dx, dy, x, y, words, yreverse; + word_write_func word_write; + word_read_func word_read; + UINT32 saddr, daddr; + XY dstxy = { 0 }; + + /* determine read/write functions */ + if (IOREG(REG_DPYCTL) & 0x0800) + { + word_write = &tms340x0_device::shiftreg_w; + word_read = &tms340x0_device::shiftreg_r; + } + else + { + word_write = &tms340x0_device::memory_w; + word_read = &tms340x0_device::memory_r; + } + + /* compute the starting addresses */ + saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY()); +if ((saddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd saddr\n", BITS_PER_PIXEL); + saddr &= ~(BITS_PER_PIXEL - 1); + + /* compute the bounds of the operation */ + dx = (INT16)DYDX_X(); + dy = (INT16)DYDX_Y(); + + /* apply the window for non-linear destinations */ + m_gfxcycles = 7 + (src_is_linear ? 0 : 2); + if (!dst_is_linear) + { + dstxy = DADDR_XY(); + m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT R", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy); + daddr = DXYTOL(dstxy); + } + else + daddr = DADDR(); +if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd daddr\n", BITS_PER_PIXEL); + daddr &= ~(BITS_PER_PIXEL - 1); + LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); + + /* bail if we're clipped */ + if (dx <= 0 || dy <= 0) + return; + + /* window mode 1: just return and interrupt if we are within the window */ + if (WINDOW_CHECKING() == 1 && !dst_is_linear) + { + CLR_V(); + DADDR_XY() = dstxy; + DYDX_X() = dx; + DYDX_Y() = dy; + IOREG(REG_INTPEND) |= TMS34010_WV; + check_interrupt(); + return; + } + + /* handle flipping the addresses */ + yreverse = (IOREG(REG_CONTROL) >> 9) & 1; + if (!src_is_linear || !dst_is_linear) + { + saddr += dx * BITS_PER_PIXEL; + daddr += dx * BITS_PER_PIXEL; + if (yreverse) + { + saddr += (dy - 1) * m_convsp; + daddr += (dy - 1) * m_convdp; + } + } + + m_st |= STBIT_P; + + /* loop over rows */ + for (y = 0; y < dy; y++) + { + int left_partials, right_partials, full_words, bitshift, bitshift_alt; + UINT16 srcword, srcmask, dstword, dstmask, pixel; + UINT32 swordaddr, dwordaddr; + + /* determine the bit shift to get from source to dest */ + bitshift = ((daddr & 15) - (saddr & 15)) & 15; + bitshift_alt = (16 - bitshift) & 15; + + /* how many left and right partial pixels do we have? */ + left_partials = (PIXELS_PER_WORD - (((daddr - dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); + right_partials = (daddr & 15) / BITS_PER_PIXEL; + full_words = dx - left_partials - right_partials; + if (full_words < 0) + right_partials = dx, left_partials = full_words = 0; + else + full_words /= PIXELS_PER_WORD; + + /* compute cycles */ + m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); + + /* use word addresses each row */ + swordaddr = (saddr + 15) >> 4; + dwordaddr = (daddr + 15) >> 4; + + /* fetch the initial source word */ + srcword = (this->*word_read)(*m_program, --swordaddr << 1); + srcmask = PIXEL_MASK << ((saddr - BITS_PER_PIXEL) & 15); + + /* handle the right partial word */ + if (right_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, --dwordaddr << 1); + dstmask = PIXEL_MASK << ((daddr - BITS_PER_PIXEL) & 15); + + /* loop over partials */ + for (x = 0; x < right_partials; x++) + { + /* fetch source pixel if necessary */ + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, --swordaddr << 1); + srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); + } + + /* process the pixel */ + pixel = srcword & srcmask; + if (dstmask > srcmask) + pixel <<= bitshift; + else + pixel >>= bitshift_alt; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + +#if (BITS_PER_PIXEL<16) + /* update the source */ + srcmask >>= BITS_PER_PIXEL; + + /* update the destination */ + dstmask >>= BITS_PER_PIXEL; +#else + srcmask = 0; + dstmask = 0; +#endif + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr << 1, dstword); + } + + /* loop over full words */ + for (words = 0; words < full_words; words++) + { + /* fetch the destination word (if necessary) */ + dwordaddr--; + if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + else + dstword = 0; + dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); + + /* loop over partials */ + for (x = 0; x < PIXELS_PER_WORD; x++) + { + /* fetch source pixel if necessary */ + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, --swordaddr << 1); + srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); + } + + /* process the pixel */ + pixel = srcword & srcmask; + if (dstmask > srcmask) + pixel <<= bitshift; + else + pixel >>= bitshift_alt; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + +#if (BITS_PER_PIXEL<16) + /* update the source */ + srcmask >>= BITS_PER_PIXEL; + + /* update the destination */ + dstmask >>= BITS_PER_PIXEL; +#else + srcmask = 0; + dstmask = 0; +#endif + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr << 1, dstword); + } + + /* handle the left partial word */ + if (left_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, --dwordaddr << 1); + dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); + + /* loop over partials */ + for (x = 0; x < left_partials; x++) + { + /* fetch the source pixel if necessary */ + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, --swordaddr << 1); + srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); + } + + /* process the pixel */ + pixel = srcword & srcmask; + if (dstmask > srcmask) + pixel <<= bitshift; + else + pixel >>= bitshift_alt; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + +#if (BITS_PER_PIXEL<16) + /* update the source */ + srcmask >>= BITS_PER_PIXEL; + + /* update the destination */ + dstmask >>= BITS_PER_PIXEL; +#else + srcmask = 0; + dstmask = 0; +#endif + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr << 1, dstword); + } + + /* update for next row */ + if (!yreverse) + { + saddr += SPTCH(); + daddr += DPTCH(); + } + else + { + saddr -= SPTCH(); + daddr -= DPTCH(); + } + } + LOGGFX((" (%d cycles)\n", m_gfxcycles)); + } + + /* eat cycles */ + if (m_gfxcycles > m_icount) + { + m_gfxcycles -= m_icount; + m_icount = 0; + m_pc -= 0x10; + } + else + { + m_icount -= m_gfxcycles; + m_st &= ~STBIT_P; + if (src_is_linear && dst_is_linear) + SADDR() += DYDX_Y() * SPTCH(); + else if (src_is_linear) + SADDR() += DYDX_Y() * SPTCH(); + else + SADDR_Y() += DYDX_Y(); + if (dst_is_linear) + DADDR() += DYDX_Y() * DPTCH(); + else + DADDR_Y() += DYDX_Y(); + } +} + +void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear) +{ + /* if this is the first time through, perform the operation */ + if (!P_FLAG()) + { + int dx, dy, x, y, words, left_partials, right_partials, full_words; + word_write_func word_write; + word_read_func word_read; + UINT32 saddr, daddr; + XY dstxy = { 0 }; + + /* determine read/write functions */ + if (IOREG(REG_DPYCTL) & 0x0800) + { + word_write = &tms340x0_device::shiftreg_w; + word_read = &tms340x0_device::shiftreg_r; + } + else + { + word_write = &tms340x0_device::memory_w; + word_read = &tms340x0_device::memory_r; + } + + /* compute the starting addresses */ + saddr = SADDR(); + + /* compute the bounds of the operation */ + dx = (INT16)DYDX_X(); + dy = (INT16)DYDX_Y(); + + /* apply the window for non-linear destinations */ + m_gfxcycles = 4; + if (!dst_is_linear) + { + dstxy = DADDR_XY(); + m_gfxcycles += 2 + apply_window("PIXBLT B", 1, &saddr, &dstxy, &dx, &dy); + daddr = DXYTOL(dstxy); + } + else + daddr = DADDR(); + daddr &= ~(BITS_PER_PIXEL - 1); + LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); + + /* bail if we're clipped */ + if (dx <= 0 || dy <= 0) + return; + + /* window mode 1: just return and interrupt if we are within the window */ + if (WINDOW_CHECKING() == 1 && !dst_is_linear) + { + CLR_V(); + DADDR_XY() = dstxy; + DYDX_X() = dx; + DYDX_Y() = dy; + IOREG(REG_INTPEND) |= TMS34010_WV; + check_interrupt(); + return; + } + + /* how many left and right partial pixels do we have? */ + left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); + right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; + full_words = dx - left_partials - right_partials; + if (full_words < 0) + left_partials = dx, right_partials = full_words = 0; + else + full_words /= PIXELS_PER_WORD; + + /* compute cycles */ + m_gfxcycles += compute_pixblt_b_cycles(left_partials, right_partials, full_words, dy, PIXEL_OP_TIMING, BITS_PER_PIXEL); + m_st |= STBIT_P; + + /* loop over rows */ + for (y = 0; y < dy; y++) + { + UINT16 srcword, srcmask, dstword, dstmask, pixel; + UINT32 swordaddr, dwordaddr; + + /* use byte addresses each row */ + swordaddr = saddr >> 4; + dwordaddr = daddr >> 4; + + /* fetch the initial source word */ + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = 1 << (saddr & 15); + + /* handle the left partial word */ + if (left_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + dstmask = PIXEL_MASK << (daddr & 15); + + /* loop over partials */ + for (x = 0; x < left_partials; x++) + { + /* process the pixel */ + pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); + pixel &= dstmask; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the source */ + srcmask <<= 1; + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = 0x0001; + } + + /* update the destination */ + dstmask = dstmask << BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* loop over full words */ + for (words = 0; words < full_words; words++) + { + /* fetch the destination word (if necessary) */ + if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + else + dstword = 0; + dstmask = PIXEL_MASK; + + /* loop over partials */ + for (x = 0; x < PIXELS_PER_WORD; x++) + { + /* process the pixel */ + pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); + pixel &= dstmask; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the source */ + srcmask <<= 1; + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = 0x0001; + } + + /* update the destination */ + dstmask = dstmask << BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* handle the right partial word */ + if (right_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + dstmask = PIXEL_MASK; + + /* loop over partials */ + for (x = 0; x < right_partials; x++) + { + /* process the pixel */ + pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); + pixel &= dstmask; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the source */ + srcmask <<= 1; + if (srcmask == 0) + { + srcword = (this->*word_read)(*m_program, swordaddr++ << 1); + srcmask = 0x0001; + } + + /* update the destination */ + dstmask = dstmask << BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* update for next row */ + saddr += SPTCH(); + daddr += DPTCH(); + } + LOGGFX((" (%d cycles)\n", m_gfxcycles)); + } + + /* eat cycles */ + if (m_gfxcycles > m_icount) + { + m_gfxcycles -= m_icount; + m_icount = 0; + m_pc -= 0x10; + } + else + { + m_icount -= m_gfxcycles; + m_st &= ~STBIT_P; + SADDR() += DYDX_Y() * SPTCH(); + if (dst_is_linear) + DADDR() += DYDX_Y() * DPTCH(); + else + DADDR_Y() += DYDX_Y(); + } +} + +void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear) +{ + /* if this is the first time through, perform the operation */ + if (!P_FLAG()) + { + int dx, dy, x, y, words, left_partials, right_partials, full_words; + word_write_func word_write; + word_read_func word_read; + UINT32 daddr; + XY dstxy = { 0 }; + + /* determine read/write functions */ + if (IOREG(REG_DPYCTL) & 0x0800) + { + word_write = &tms340x0_device::shiftreg_w; + word_read = &tms340x0_device::dummy_shiftreg_r; + } + else + { + word_write = &tms340x0_device::memory_w; + word_read = &tms340x0_device::memory_r; + } + + /* compute the bounds of the operation */ + dx = (INT16)DYDX_X(); + dy = (INT16)DYDX_Y(); + + /* apply the window for non-linear destinations */ + m_gfxcycles = 4; + if (!dst_is_linear) + { + dstxy = DADDR_XY(); + m_gfxcycles += 2 + apply_window("FILL", 0, NULL, &dstxy, &dx, &dy); + daddr = DXYTOL(dstxy); + } + else + daddr = DADDR(); + daddr &= ~(BITS_PER_PIXEL - 1); + LOGGFX((" daddr=%08X\n", daddr)); + + /* bail if we're clipped */ + if (dx <= 0 || dy <= 0) + return; + + /* window mode 1: just return and interrupt if we are within the window */ + if (WINDOW_CHECKING() == 1 && !dst_is_linear) + { + CLR_V(); + DADDR_XY() = dstxy; + DYDX_X() = dx; + DYDX_Y() = dy; + IOREG(REG_INTPEND) |= TMS34010_WV; + check_interrupt(); + return; + } + + /* how many left and right partial pixels do we have? */ + left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); + right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; + full_words = dx - left_partials - right_partials; + if (full_words < 0) + left_partials = dx, right_partials = full_words = 0; + else + full_words /= PIXELS_PER_WORD; + + /* compute cycles */ + m_gfxcycles += 2; + m_st |= STBIT_P; + + /* loop over rows */ + for (y = 0; y < dy; y++) + { + UINT16 dstword, dstmask, pixel; + UINT32 dwordaddr; + + /* use byte addresses each row */ + dwordaddr = daddr >> 4; + + /* compute cycles */ + m_gfxcycles += compute_fill_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); + + /* handle the left partial word */ + if (left_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + dstmask = PIXEL_MASK << (daddr & 15); + + /* loop over partials */ + for (x = 0; x < left_partials; x++) + { + /* process the pixel */ + pixel = COLOR1() & dstmask; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the destination */ + dstmask = dstmask << BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* loop over full words */ + for (words = 0; words < full_words; words++) + { + /* fetch the destination word (if necessary) */ + if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + else + dstword = 0; + dstmask = PIXEL_MASK; + + /* loop over partials */ + for (x = 0; x < PIXELS_PER_WORD; x++) + { + /* process the pixel */ + pixel = COLOR1() & dstmask; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the destination */ + dstmask = dstmask << BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* handle the right partial word */ + if (right_partials != 0) + { + /* fetch the destination word */ + dstword = (this->*word_read)(*m_program, dwordaddr << 1); + dstmask = PIXEL_MASK; + + /* loop over partials */ + for (x = 0; x < right_partials; x++) + { + /* process the pixel */ + pixel = COLOR1() & dstmask; + PIXEL_OP(dstword, dstmask, pixel); + if (!TRANSPARENCY || pixel != 0) + dstword = (dstword & ~dstmask) | pixel; + + /* update the destination */ + dstmask = dstmask << BITS_PER_PIXEL; + } + + /* write the result */ + (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); + } + + /* update for next row */ + daddr += DPTCH(); + } + + LOGGFX((" (%d cycles)\n", m_gfxcycles)); + } + + /* eat cycles */ + if (m_gfxcycles > m_icount) + { + m_gfxcycles -= m_icount; + m_icount = 0; + m_pc -= 0x10; + } + else + { + m_icount -= m_gfxcycles; + m_st &= ~STBIT_P; + if (dst_is_linear) + DADDR() += DYDX_Y() * DPTCH(); + else + DADDR_Y() += DYDX_Y(); + } +} + +#endif diff --git a/mame/tm34010/34010ops.c b/mame/tm34010/34010ops.c new file mode 100644 index 00000000..ab5a5671 --- /dev/null +++ b/mame/tm34010/34010ops.c @@ -0,0 +1,2463 @@ +// license:BSD-3-Clause +// copyright-holders:Alex Pasadyn,Zsolt Vasvari +/*************************************************************************** + + TMS34010: Portable Texas Instruments TMS34010 emulator + + Copyright Alex Pasadyn/Zsolt Vasvari + Parts based on code by Aaron Giles + +***************************************************************************/ + + + +/*************************************************************************** + MISC MACROS +***************************************************************************/ + +#define ZEXTEND(val,width) if (width) (val) &= ((UINT32)0xffffffff >> (32 - (width))) +#define SEXTEND(val,width) if (width) (val) = (INT32)((val) << (32 - (width))) >> (32 - (width)) + +#define SXYTOL(val) ((((INT16)(val).y * m_convsp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) +#define DXYTOL(val) ((((INT16)(val).y * m_convdp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) +#define MXYTOL(val) ((((INT16)(val).y * m_convmp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) + +#define COUNT_CYCLES(x) m_icount -= x +#define COUNT_UNKNOWN_CYCLES(x) COUNT_CYCLES(x) + +#define CORRECT_ODD_PC(x) do { if (m_pc & 0x0f) logerror("%s to PC=%08X\n", x, m_pc); m_pc &= ~0x0f; } while (0) + + + +/*************************************************************************** + FLAG HANDLING MACROS +***************************************************************************/ + +#define SIGN(val) ((val) & 0x80000000) + +#define CLR_Z() m_st &= ~STBIT_Z +#define CLR_V() m_st &= ~STBIT_V +#define CLR_C() m_st &= ~STBIT_C +#define CLR_N() m_st &= ~STBIT_N +#define CLR_NZ() m_st &= ~(STBIT_N | STBIT_Z) +#define CLR_CZ() m_st &= ~(STBIT_C | STBIT_Z) +#define CLR_ZV() m_st &= ~(STBIT_Z | STBIT_V) +#define CLR_NZV() m_st &= ~(STBIT_N | STBIT_Z | STBIT_V) +#define CLR_NCZ() m_st &= ~(STBIT_N | STBIT_C | STBIT_Z) +#define CLR_NCZV() m_st &= ~(STBIT_N | STBIT_C | STBIT_Z | STBIT_V) + +#define SET_V_BIT_LO(val,bit) m_st |= ((val) << (28 - (bit))) & STBIT_V +#define SET_V_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 28)) & STBIT_V +#define SET_V_LOG(val) m_st |= (val) << 28 +#define SET_Z_BIT_LO(val,bit) m_st |= ((val) << (29 - (bit))) & STBIT_Z +#define SET_Z_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 29)) & STBIT_Z +#define SET_Z_LOG(val) m_st |= (val) << 29 +#define SET_C_BIT_LO(val,bit) m_st |= ((val) << (30 - (bit))) & STBIT_C +#define SET_C_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 30)) & STBIT_C +#define SET_C_LOG(val) m_st |= (val) << 30 +#define SET_N_BIT(val,bit) m_st |= ((val) << (31 - (bit))) & STBIT_N +#define SET_N_LOG(val) m_st |= (val) << 31 + +#define SET_Z_VAL(val) SET_Z_LOG((val) == 0) +#define SET_N_VAL(val) SET_N_BIT(val, 31) +#define SET_NZ_VAL(val) SET_Z_VAL(val); SET_N_VAL(val) +#define SET_V_SUB(a,b,r) SET_V_BIT_HI(((a) ^ (b)) & ((a) ^ (r)), 31) +#define SET_V_ADD(a,b,r) SET_V_BIT_HI(~((a) ^ (b)) & ((a) ^ (r)), 31) +#define SET_C_SUB(a,b) SET_C_LOG((UINT32)(b) > (UINT32)(a)) +#define SET_C_ADD(a,b) SET_C_LOG((UINT32)~(a) < (UINT32)(b)) +#define SET_NZV_SUB(a,b,r) SET_NZ_VAL(r); SET_V_SUB(a,b,r) +#define SET_NZCV_SUB(a,b,r) SET_NZV_SUB(a,b,r); SET_C_SUB(a,b) +#define SET_NZCV_ADD(a,b,r) SET_NZ_VAL(r); SET_V_ADD(a,b,r); SET_C_ADD(a,b) + +static const UINT8 fw_inc[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; + + +/*************************************************************************** + UNIMPLEMENTED INSTRUCTION +***************************************************************************/ + +void tms340x0_device::unimpl(UINT16 op) +{ + /* kludge for Super High Impact -- this doesn't seem to cause */ + /* an illegal opcode exception */ + if (m_direct->read_decrypted_word(TOBYTE(m_pc - 0x10)) == 0x0007) + return; + + /* 9 Ball Shootout calls to FFDF7468, expecting it */ + /* to execute the next instruction from FFDF7470 */ + /* but the instruction at FFDF7460 is an 0x0001 */ + if (m_direct->read_decrypted_word(TOBYTE(m_pc - 0x10)) == 0x0001) + return; + + PUSH(m_pc); + PUSH(m_st); + RESET_ST(); + m_pc = RLONG(0xfffffc20); + COUNT_UNKNOWN_CYCLES(16); + + write_log("TMS UNIMPL!\n"); +#if 0 + /* extra check to prevent bad things */ + if (m_pc == 0 || s_opcode_table[m_direct->read_decrypted_word(TOBYTE(m_pc)) >> 4] == &tms34010_device::unimpl) + { + set_input_line(INPUT_LINE_HALT, ASSERT_LINE); + debugger_break(machine()); + } +#endif +} + + + +/*************************************************************************** + X/Y OPERATIONS +***************************************************************************/ + +#define ADD_XY(R) \ +{ \ + XY a = R##REG_XY(SRCREG(op)); \ + XY *b = &R##REG_XY(DSTREG(op)); \ + CLR_NCZV(); \ + b->x += a.x; \ + b->y += a.y; \ + SET_N_LOG(b->x == 0); \ + SET_C_BIT_LO(b->y, 15); \ + SET_Z_LOG(b->y == 0); \ + SET_V_BIT_LO(b->x, 15); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::add_xy_a(UINT16 op) { ADD_XY(A); } +void tms340x0_device::add_xy_b(UINT16 op) { ADD_XY(B); } + +#define SUB_XY(R) \ +{ \ + XY a = R##REG_XY(SRCREG(op)); \ + XY *b = &R##REG_XY(DSTREG(op)); \ + CLR_NCZV(); \ + SET_N_LOG(a.x == b->x); \ + SET_C_LOG(a.y > b->y); \ + SET_Z_LOG(a.y == b->y); \ + SET_V_LOG(a.x > b->x); \ + b->x -= a.x; \ + b->y -= a.y; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::sub_xy_a(UINT16 op) { SUB_XY(A); } +void tms340x0_device::sub_xy_b(UINT16 op) { SUB_XY(B); } + +#define CMP_XY(R) \ +{ \ + INT16 res; \ + XY a = R##REG_XY(DSTREG(op)); \ + XY b = R##REG_XY(SRCREG(op)); \ + CLR_NCZV(); \ + res = a.x-b.x; \ + SET_N_LOG(res == 0); \ + SET_V_BIT_LO(res, 15); \ + res = a.y-b.y; \ + SET_Z_LOG(res == 0); \ + SET_C_BIT_LO(res, 15); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::cmp_xy_a(UINT16 op) { CMP_XY(A); } +void tms340x0_device::cmp_xy_b(UINT16 op) { CMP_XY(B); } + +#define CPW(R) \ +{ \ + INT32 res = 0; \ + INT16 x = R##REG_X(SRCREG(op)); \ + INT16 y = R##REG_Y(SRCREG(op)); \ + \ + CLR_V(); \ + res |= ((WSTART_X() > x) ? 0x20 : 0); \ + res |= ((x > WEND_X()) ? 0x40 : 0); \ + res |= ((WSTART_Y() > y) ? 0x80 : 0); \ + res |= ((y > WEND_Y()) ? 0x100 : 0); \ + R##REG(DSTREG(op)) = res; \ + SET_V_LOG(res != 0); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::cpw_a(UINT16 op) { CPW(A); } +void tms340x0_device::cpw_b(UINT16 op) { CPW(B); } + +#define CVXYL(R) \ +{ \ + R##REG(DSTREG(op)) = DXYTOL(R##REG_XY(SRCREG(op))); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::cvxyl_a(UINT16 op) { CVXYL(A); } +void tms340x0_device::cvxyl_b(UINT16 op) { CVXYL(B); } + +#define MOVX(R) \ +{ \ + R##REG(DSTREG(op)) = (R##REG(DSTREG(op)) & 0xffff0000) | (UINT16)R##REG(SRCREG(op)); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::movx_a(UINT16 op) { MOVX(A); } +void tms340x0_device::movx_b(UINT16 op) { MOVX(B); } + +#define MOVY(R) \ +{ \ + R##REG(DSTREG(op)) = (R##REG(SRCREG(op)) & 0xffff0000) | (UINT16)R##REG(DSTREG(op)); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::movy_a(UINT16 op) { MOVY(A); } +void tms340x0_device::movy_b(UINT16 op) { MOVY(B); } + + + +/*************************************************************************** + PIXEL TRANSFER OPERATIONS +***************************************************************************/ + +#define PIXT_RI(R) \ +{ \ + WPIXEL(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ + COUNT_UNKNOWN_CYCLES(2); \ +} +void tms340x0_device::pixt_ri_a(UINT16 op) { PIXT_RI(A); } +void tms340x0_device::pixt_ri_b(UINT16 op) { PIXT_RI(B); } + +#define PIXT_RIXY(R) \ +{ \ + if (WINDOW_CHECKING() != 0) \ + { \ + CLR_V(); \ + if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ + R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ + { \ + SET_V_LOG(1); \ + goto skip; \ + } \ + if (WINDOW_CHECKING() == 1) goto skip; \ + } \ + WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),R##REG(SRCREG(op))); \ +skip: \ + COUNT_UNKNOWN_CYCLES(4); \ +} +void tms340x0_device::pixt_rixy_a(UINT16 op) { PIXT_RIXY(A); } +void tms340x0_device::pixt_rixy_b(UINT16 op) { PIXT_RIXY(B); } + +#define PIXT_IR(R) \ +{ \ + INT32 temp = RPIXEL(R##REG(SRCREG(op))); \ + CLR_V(); \ + R##REG(DSTREG(op)) = temp; \ + SET_V_LOG(temp != 0); \ + COUNT_CYCLES(4); \ +} +void tms340x0_device::pixt_ir_a(UINT16 op) { PIXT_IR(A); } +void tms340x0_device::pixt_ir_b(UINT16 op) { PIXT_IR(B); } + +#define PIXT_II(R) \ +{ \ + WPIXEL(R##REG(DSTREG(op)),RPIXEL(R##REG(SRCREG(op)))); \ + COUNT_UNKNOWN_CYCLES(4); \ +} +void tms340x0_device::pixt_ii_a(UINT16 op) { PIXT_II(A); } +void tms340x0_device::pixt_ii_b(UINT16 op) { PIXT_II(B); } + +#define PIXT_IXYR(R) \ +{ \ + INT32 temp = RPIXEL(SXYTOL(R##REG_XY(SRCREG(op)))); \ + CLR_V(); \ + R##REG(DSTREG(op)) = temp; \ + SET_V_LOG(temp != 0); \ + COUNT_CYCLES(6); \ +} +void tms340x0_device::pixt_ixyr_a(UINT16 op) { PIXT_IXYR(A); } +void tms340x0_device::pixt_ixyr_b(UINT16 op) { PIXT_IXYR(B); } + +#define PIXT_IXYIXY(R) \ +{ \ + if (WINDOW_CHECKING() != 0) \ + { \ + CLR_V(); \ + if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ + R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ + { \ + SET_V_LOG(1); \ + goto skip; \ + } \ + if (WINDOW_CHECKING() == 1) goto skip; \ + } \ + WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),RPIXEL(SXYTOL(R##REG_XY(SRCREG(op))))); \ +skip: \ + COUNT_UNKNOWN_CYCLES(7); \ +} +void tms340x0_device::pixt_ixyixy_a(UINT16 op) { PIXT_IXYIXY(A); } +void tms340x0_device::pixt_ixyixy_b(UINT16 op) { PIXT_IXYIXY(B); } + +#define DRAV(R) \ +{ \ + if (WINDOW_CHECKING() != 0) \ + { \ + CLR_V(); \ + if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ + R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ + { \ + SET_V_LOG(1); \ + goto skip; \ + } \ + if (WINDOW_CHECKING() == 1) goto skip; \ + } \ + WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),COLOR1()); \ +skip: \ + R##REG_X(DSTREG(op)) += R##REG_X(SRCREG(op)); \ + R##REG_Y(DSTREG(op)) += R##REG_Y(SRCREG(op)); \ + COUNT_UNKNOWN_CYCLES(4); \ +} +void tms340x0_device::drav_a(UINT16 op) { DRAV(A); } +void tms340x0_device::drav_b(UINT16 op) { DRAV(B); } + + + +/*************************************************************************** + ARITHMETIC OPERATIONS +***************************************************************************/ + +#define ABS(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 r = 0 - *rd; \ + CLR_NZV(); \ + if (r > 0) *rd = r; \ + SET_NZ_VAL(r); \ + SET_V_LOG(r == (INT32)0x80000000); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::abs_a(UINT16 op) { ABS(A); } +void tms340x0_device::abs_b(UINT16 op) { ABS(B); } + +#define ADD(R) \ +{ \ + INT32 a = R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 b = *rd; \ + INT32 r = a + b; \ + CLR_NCZV(); \ + *rd = r; \ + SET_NZCV_ADD(a,b,r); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::add_a(UINT16 op) { ADD(A); } +void tms340x0_device::add_b(UINT16 op) { ADD(B); } + +#define ADDC(R) \ +{ \ + /* I'm not sure to which side the carry is added to, should */ \ + /* verify it against the examples */ \ + INT32 a = R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 b = *rd; \ + INT32 r = a + b + (C_FLAG() ? 1 : 0); \ + CLR_NCZV(); \ + *rd = r; \ + SET_NZCV_ADD(a,b,r); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::addc_a(UINT16 op) { ADDC(A); } +void tms340x0_device::addc_b(UINT16 op) { ADDC(B); } + +#define ADDI_W(R) \ +{ \ + INT32 a = PARAM_WORD(); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 b = *rd; \ + INT32 r = a + b; \ + CLR_NCZV(); \ + *rd = r; \ + SET_NZCV_ADD(a,b,r); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::addi_w_a(UINT16 op) { ADDI_W(A); } +void tms340x0_device::addi_w_b(UINT16 op) { ADDI_W(B); } + +#define ADDI_L(R) \ +{ \ + INT32 a = PARAM_LONG(); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 b = *rd; \ + INT32 r = a + b; \ + CLR_NCZV(); \ + *rd = r; \ + SET_NZCV_ADD(a,b,r); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::addi_l_a(UINT16 op) { ADDI_L(A); } +void tms340x0_device::addi_l_b(UINT16 op) { ADDI_L(B); } + +#define ADDK(R) \ +{ \ + INT32 a = fw_inc[PARAM_K(op)]; \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 b = *rd; \ + INT32 r = a + b; \ + CLR_NCZV(); \ + *rd = r; \ + SET_NZCV_ADD(a,b,r); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::addk_a(UINT16 op) { ADDK(A); } +void tms340x0_device::addk_b(UINT16 op) { ADDK(B); } + +#define AND(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd &= R##REG(SRCREG(op)); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::and_a(UINT16 op) { AND(A); } +void tms340x0_device::and_b(UINT16 op) { AND(B); } + +#define ANDI(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd &= ~PARAM_LONG(); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::andi_a(UINT16 op) { ANDI(A); } +void tms340x0_device::andi_b(UINT16 op) { ANDI(B); } + +#define ANDN(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd &= ~R##REG(SRCREG(op)); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::andn_a(UINT16 op) { ANDN(A); } +void tms340x0_device::andn_b(UINT16 op) { ANDN(B); } + +#define BTST_K(R) \ +{ \ + int bit = 31 - PARAM_K(op); \ + CLR_Z(); \ + if (bit <= 29) \ + SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \ + else \ + SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::btst_k_a(UINT16 op) { BTST_K(A); } +void tms340x0_device::btst_k_b(UINT16 op) { BTST_K(B); } + +#define BTST_R(R) \ +{ \ + int bit = R##REG(SRCREG(op)) & 0x1f; \ + CLR_Z(); \ + if (bit <= 29) \ + SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \ + else \ + SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::btst_r_a(UINT16 op) { BTST_R(A); } +void tms340x0_device::btst_r_b(UINT16 op) { BTST_R(B); } + +void tms340x0_device::clrc(UINT16 op) +{ + CLR_C(); + COUNT_CYCLES(1); +} + +#define CMP(R) \ +{ \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 r = *rd - *rs; \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,*rs,r); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::cmp_a(UINT16 op) { CMP(A); } +void tms340x0_device::cmp_b(UINT16 op) { CMP(B); } + +#define CMPI_W(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = (INT16)~PARAM_WORD(); \ + INT32 r = *rd - t; \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,t,r); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::cmpi_w_a(UINT16 op) { CMPI_W(A); } +void tms340x0_device::cmpi_w_b(UINT16 op) { CMPI_W(B); } + +#define CMPI_L(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = ~PARAM_LONG(); \ + INT32 r = *rd - t; \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,t,r); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::cmpi_l_a(UINT16 op) { CMPI_L(A); } +void tms340x0_device::cmpi_l_b(UINT16 op) { CMPI_L(B); } + +void tms340x0_device::dint(UINT16 op) +{ + m_st &= ~STBIT_IE; + COUNT_CYCLES(3); +} + +#define DIVS(R) \ +{ \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 *rd1 = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + if (!(DSTREG(op) & 1)) \ + { \ + if (!*rs) \ + { \ + SET_V_LOG(1); \ + } \ + else \ + { \ + INT32 *rd2 = &R##REG(DSTREG(op)+1); \ + INT64 dividend = ((UINT64)*rd1 << 32) | (UINT32)*rd2; \ + INT64 quotient = dividend / *rs; \ + INT32 remainder = dividend % *rs; \ + UINT32 signbits = (INT32)quotient >> 31; \ + if (EXTRACT_64HI(quotient) != signbits) \ + { \ + SET_V_LOG(1); \ + } \ + else \ + { \ + *rd1 = quotient; \ + *rd2 = remainder; \ + SET_NZ_VAL(*rd1); \ + } \ + } \ + COUNT_CYCLES(40); \ + } \ + else \ + { \ + if (!*rs) \ + { \ + SET_V_LOG(1); \ + } \ + else \ + { \ + *rd1 /= *rs; \ + SET_NZ_VAL(*rd1); \ + } \ + COUNT_CYCLES(39); \ + } \ +} +void tms340x0_device::divs_a(UINT16 op) { DIVS(A); } +void tms340x0_device::divs_b(UINT16 op) { DIVS(B); } + +#define DIVU(R) \ +{ \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 *rd1 = &R##REG(DSTREG(op)); \ + CLR_ZV(); \ + if (!(DSTREG(op) & 1)) \ + { \ + if (!*rs) \ + { \ + SET_V_LOG(1); \ + } \ + else \ + { \ + INT32 *rd2 = &R##REG(DSTREG(op)+1); \ + UINT64 dividend = ((UINT64)*rd1 << 32) | (UINT32)*rd2; \ + UINT64 quotient = dividend / (UINT32)*rs; \ + UINT32 remainder = dividend % (UINT32)*rs; \ + if (EXTRACT_64HI(quotient) != 0) \ + { \ + SET_V_LOG(1); \ + } \ + else \ + { \ + *rd1 = quotient; \ + *rd2 = remainder; \ + SET_Z_VAL(*rd1); \ + } \ + } \ + } \ + else \ + { \ + if (!*rs) \ + { \ + SET_V_LOG(1); \ + } \ + else \ + { \ + *rd1 = (UINT32)*rd1 / (UINT32)*rs; \ + SET_Z_VAL(*rd1); \ + } \ + } \ + COUNT_CYCLES(37); \ +} +void tms340x0_device::divu_a(UINT16 op) { DIVU(A); } +void tms340x0_device::divu_b(UINT16 op) { DIVU(B); } + +void tms340x0_device::eint(UINT16 op) +{ + m_st |= STBIT_IE; + check_interrupt(); + COUNT_CYCLES(3); +} + +#define EXGF(F,R) \ +{ \ + UINT8 shift = F ? 6 : 0; \ + INT32 *rd = &R##REG(DSTREG(op)); \ + UINT32 temp = (m_st >> shift) & 0x3f; \ + m_st &= ~(0x3f << shift); \ + m_st |= (*rd & 0x3f) << shift; \ + *rd = temp; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::exgf0_a(UINT16 op) { EXGF(0,A); } +void tms340x0_device::exgf0_b(UINT16 op) { EXGF(0,B); } +void tms340x0_device::exgf1_a(UINT16 op) { EXGF(1,A); } +void tms340x0_device::exgf1_b(UINT16 op) { EXGF(1,B); } + +#define LMO(R) \ +{ \ + UINT32 res = 0; \ + UINT32 rs = R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + SET_Z_VAL(rs); \ + if (rs) \ + { \ + while (!(rs & 0x80000000)) \ + { \ + res++; \ + rs <<= 1; \ + } \ + } \ + *rd = res; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::lmo_a(UINT16 op) { LMO(A); } +void tms340x0_device::lmo_b(UINT16 op) { LMO(B); } + +#define MMFM(R) \ +{ \ + INT32 i; \ + UINT16 l = (UINT16) PARAM_WORD(); \ + COUNT_CYCLES(3); \ + { \ + INT32 rd = DSTREG(op); \ + for (i = 15; i >= 0 ; i--) \ + { \ + if (l & 0x8000) \ + { \ + R##REG(i) = RLONG(R##REG(rd)); \ + R##REG(rd) += 0x20; \ + COUNT_CYCLES(4); \ + } \ + l <<= 1; \ + } \ + } \ +} +void tms340x0_device::mmfm_a(UINT16 op) { MMFM(A); } +void tms340x0_device::mmfm_b(UINT16 op) { MMFM(B); } + +#define MMTM(R) \ +{ \ + UINT32 i; \ + UINT16 l = (UINT16) PARAM_WORD(); \ + COUNT_CYCLES(2); \ + { \ + INT32 rd = DSTREG(op); \ + if (m_is_34020) \ + { \ + CLR_N(); \ + SET_N_VAL(R##REG(rd) ^ 0x80000000); \ + } \ + for (i = 0; i < 16; i++) \ + { \ + if (l & 0x8000) \ + { \ + R##REG(rd) -= 0x20; \ + WLONG(R##REG(rd),R##REG(i)); \ + COUNT_CYCLES(4); \ + } \ + l <<= 1; \ + } \ + } \ +} +void tms340x0_device::mmtm_a(UINT16 op) { MMTM(A); } +void tms340x0_device::mmtm_b(UINT16 op) { MMTM(B); } + +#define MODS(R) \ +{ \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + if (*rs != 0) \ + { \ + *rd %= *rs; \ + SET_NZ_VAL(*rd); \ + } \ + else \ + SET_V_LOG(1); \ + COUNT_CYCLES(40); \ +} +void tms340x0_device::mods_a(UINT16 op) { MODS(A); } +void tms340x0_device::mods_b(UINT16 op) { MODS(B); } + +#define MODU(R) \ +{ \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_ZV(); \ + if (*rs != 0) \ + { \ + *rd = (UINT32)*rd % (UINT32)*rs; \ + SET_Z_VAL(*rd); \ + } \ + else \ + SET_V_LOG(1); \ + COUNT_CYCLES(35); \ +} +void tms340x0_device::modu_a(UINT16 op) { MODU(A); } +void tms340x0_device::modu_b(UINT16 op) { MODU(B); } + +#define MPYS(R) \ +{ \ + INT32 *rd1 = &R##REG(DSTREG(op)); \ + INT32 m1 = R##REG(SRCREG(op)); \ + INT64 product; \ + \ + SEXTEND(m1, FW(1)); \ + CLR_NZ(); \ + product = mul_32x32(m1, *rd1); \ + SET_Z_LOG(product == 0); \ + SET_N_BIT(product >> 32, 31); \ + \ + *rd1 = EXTRACT_64HI(product); \ + R##REG(DSTREG(op)|1) = EXTRACT_64LO(product); \ + \ + COUNT_CYCLES(20); \ +} +void tms340x0_device::mpys_a(UINT16 op) { MPYS(A); } +void tms340x0_device::mpys_b(UINT16 op) { MPYS(B); } + +#define MPYU(R) \ +{ \ + INT32 *rd1 = &R##REG(DSTREG(op)); \ + UINT32 m1 = R##REG(SRCREG(op)); \ + UINT64 product; \ + \ + ZEXTEND(m1, FW(1)); \ + CLR_Z(); \ + product = mulu_32x32(m1, *rd1); \ + SET_Z_LOG(product == 0); \ + \ + *rd1 = EXTRACT_64HI(product); \ + R##REG(DSTREG(op)|1) = EXTRACT_64LO(product); \ + \ + COUNT_CYCLES(21); \ +} +void tms340x0_device::mpyu_a(UINT16 op) { MPYU(A); } +void tms340x0_device::mpyu_b(UINT16 op) { MPYU(B); } + +#define NEG(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 r = 0 - *rd; \ + CLR_NCZV(); \ + SET_NZCV_SUB(0,*rd,r); \ + *rd = r; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::neg_a(UINT16 op) { NEG(A); } +void tms340x0_device::neg_b(UINT16 op) { NEG(B); } + +#define NEGB(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = *rd + (C_FLAG() ? 1 : 0); \ + INT32 r = 0 - t; \ + CLR_NCZV(); \ + SET_NZCV_SUB(0,t,r); \ + *rd = r; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::negb_a(UINT16 op) { NEGB(A); } +void tms340x0_device::negb_b(UINT16 op) { NEGB(B); } + +void tms340x0_device::nop(UINT16 op) +{ + COUNT_CYCLES(1); +} + +#define NOT(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd = ~(*rd); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::not_a(UINT16 op) { NOT(A); } +void tms340x0_device::not_b(UINT16 op) { NOT(B); } + +#define OR(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd |= R##REG(SRCREG(op)); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::or_a(UINT16 op) { OR(A); } +void tms340x0_device::or_b(UINT16 op) { OR(B); } + +#define ORI(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd |= PARAM_LONG(); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::ori_a(UINT16 op) { ORI(A); } +void tms340x0_device::ori_b(UINT16 op) { ORI(B); } + +void tms340x0_device::setc(UINT16 op) +{ + SET_C_LOG(1); + COUNT_CYCLES(1); +} + +#define SETF(F) \ +{ \ + UINT8 shift = F ? 6 : 0; \ + m_st &= ~(0x3f << shift); \ + m_st |= (op & 0x3f) << shift; \ + COUNT_CYCLES(1+F); \ +} +void tms340x0_device::setf0(UINT16 op) { SETF(0); } +void tms340x0_device::setf1(UINT16 op) { SETF(1); } + +#define SEXT(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZ(); \ + SEXTEND(*rd,FW(F)); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::sext0_a(UINT16 op) { SEXT(0,A); } +void tms340x0_device::sext0_b(UINT16 op) { SEXT(0,B); } +void tms340x0_device::sext1_a(UINT16 op) { SEXT(1,A); } +void tms340x0_device::sext1_b(UINT16 op) { SEXT(1,B); } + +#define RL(R,K) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 res = *rd; \ + INT32 k = (K); \ + CLR_CZ(); \ + if (k) \ + { \ + res<<=(k-1); \ + SET_C_BIT_HI(res, 31); \ + res<<=1; \ + res |= (((UINT32)*rd)>>((-k)&0x1f)); \ + *rd = res; \ + } \ + SET_Z_VAL(res); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::rl_k_a(UINT16 op) { RL(A,PARAM_K(op)); } +void tms340x0_device::rl_k_b(UINT16 op) { RL(B,PARAM_K(op)); } +void tms340x0_device::rl_r_a(UINT16 op) { RL(A,AREG(SRCREG(op))&0x1f); } +void tms340x0_device::rl_r_b(UINT16 op) { RL(B,BREG(SRCREG(op))&0x1f); } + +#define SLA(R,K) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + UINT32 res = *rd; \ + INT32 k = K; \ + CLR_NCZV(); \ + if (k) \ + { \ + UINT32 mask = (0xffffffff<<(31-k))&0x7fffffff; \ + UINT32 res2 = SIGN(res) ? res^mask : res; \ + SET_V_LOG((res2 & mask) != 0); \ + \ + res<<=(k-1); \ + SET_C_BIT_HI(res, 31); \ + res<<=1; \ + *rd = res; \ + } \ + SET_NZ_VAL(res); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::sla_k_a(UINT16 op) { SLA(A,PARAM_K(op)); } +void tms340x0_device::sla_k_b(UINT16 op) { SLA(B,PARAM_K(op)); } +void tms340x0_device::sla_r_a(UINT16 op) { SLA(A,AREG(SRCREG(op))&0x1f); } +void tms340x0_device::sla_r_b(UINT16 op) { SLA(B,BREG(SRCREG(op))&0x1f); } + +#define SLL(R,K) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + UINT32 res = *rd; \ + INT32 k = K; \ + CLR_CZ(); \ + if (k) \ + { \ + res<<=(k-1); \ + SET_C_BIT_HI(res, 31); \ + res<<=1; \ + *rd = res; \ + } \ + SET_Z_VAL(res); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::sll_k_a(UINT16 op) { SLL(A,PARAM_K(op)); } +void tms340x0_device::sll_k_b(UINT16 op) { SLL(B,PARAM_K(op)); } +void tms340x0_device::sll_r_a(UINT16 op) { SLL(A,AREG(SRCREG(op))&0x1f); } +void tms340x0_device::sll_r_b(UINT16 op) { SLL(B,BREG(SRCREG(op))&0x1f); } + +#define SRA(R,K) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 res = *rd; \ + INT32 k = (-(K)) & 0x1f; \ + CLR_NCZ(); \ + if (k) \ + { \ + res>>=(k-1); \ + SET_C_BIT_LO(res, 0); \ + res>>=1; \ + *rd = res; \ + } \ + SET_NZ_VAL(res); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::sra_k_a(UINT16 op) { SRA(A,PARAM_K(op)); } +void tms340x0_device::sra_k_b(UINT16 op) { SRA(B,PARAM_K(op)); } +void tms340x0_device::sra_r_a(UINT16 op) { SRA(A,AREG(SRCREG(op))); } +void tms340x0_device::sra_r_b(UINT16 op) { SRA(B,BREG(SRCREG(op))); } + +#define SRL(R,K) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + UINT32 res = *rd; \ + INT32 k = (-(K)) & 0x1f; \ + CLR_CZ(); \ + if (k) \ + { \ + res>>=(k-1); \ + SET_C_BIT_LO(res, 0); \ + res>>=1; \ + *rd = res; \ + } \ + SET_Z_VAL(res); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::srl_k_a(UINT16 op) { SRL(A,PARAM_K(op)); } +void tms340x0_device::srl_k_b(UINT16 op) { SRL(B,PARAM_K(op)); } +void tms340x0_device::srl_r_a(UINT16 op) { SRL(A,AREG(SRCREG(op))); } +void tms340x0_device::srl_r_b(UINT16 op) { SRL(B,BREG(SRCREG(op))); } + +#define SUB(R) \ +{ \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 r = *rd - *rs; \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,*rs,r); \ + *rd = r; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::sub_a(UINT16 op) { SUB(A); } +void tms340x0_device::sub_b(UINT16 op) { SUB(B); } + +#define SUBB(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = R##REG(SRCREG(op)); \ + INT32 r = *rd - t - (C_FLAG() ? 1 : 0); \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,t,r); \ + *rd = r; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::subb_a(UINT16 op) { SUBB(A); } +void tms340x0_device::subb_b(UINT16 op) { SUBB(B); } + +#define SUBI_W(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 r; \ + INT32 t = ~PARAM_WORD(); \ + CLR_NCZV(); \ + r = *rd - t; \ + SET_NZCV_SUB(*rd,t,r); \ + *rd = r; \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::subi_w_a(UINT16 op) { SUBI_W(A); } +void tms340x0_device::subi_w_b(UINT16 op) { SUBI_W(B); } + +#define SUBI_L(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = ~PARAM_LONG(); \ + INT32 r = *rd - t; \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,t,r); \ + *rd = r; \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::subi_l_a(UINT16 op) { SUBI_L(A); } +void tms340x0_device::subi_l_b(UINT16 op) { SUBI_L(B); } + +#define SUBK(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = fw_inc[PARAM_K(op)]; \ + INT32 r = *rd - t; \ + CLR_NCZV(); \ + SET_NZCV_SUB(*rd,t,r); \ + *rd = r; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::subk_a(UINT16 op) { SUBK(A); } +void tms340x0_device::subk_b(UINT16 op) { SUBK(B); } + +#define XOR(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd ^= R##REG(SRCREG(op)); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::xor_a(UINT16 op) { XOR(A); } +void tms340x0_device::xor_b(UINT16 op) { XOR(B); } + +#define XORI(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + *rd ^= PARAM_LONG(); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::xori_a(UINT16 op) { XORI(A); } +void tms340x0_device::xori_b(UINT16 op) { XORI(B); } + +#define ZEXT(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + ZEXTEND(*rd,FW(F)); \ + SET_Z_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::zext0_a(UINT16 op) { ZEXT(0,A); } +void tms340x0_device::zext0_b(UINT16 op) { ZEXT(0,B); } +void tms340x0_device::zext1_a(UINT16 op) { ZEXT(1,A); } +void tms340x0_device::zext1_b(UINT16 op) { ZEXT(1,B); } + + + +/*************************************************************************** + MOVE INSTRUCTIONS +***************************************************************************/ + +#define MOVI_W(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd=PARAM_WORD(); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::movi_w_a(UINT16 op) { MOVI_W(A); } +void tms340x0_device::movi_w_b(UINT16 op) { MOVI_W(B); } + +#define MOVI_L(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd=PARAM_LONG(); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::movi_l_a(UINT16 op) { MOVI_L(A); } +void tms340x0_device::movi_l_b(UINT16 op) { MOVI_L(B); } + +#define MOVK(R) \ +{ \ + INT32 k = PARAM_K(op); if (!k) k = 32; \ + R##REG(DSTREG(op)) = k; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::movk_a(UINT16 op) { MOVK(A); } +void tms340x0_device::movk_b(UINT16 op) { MOVK(B); } + +#define MOVB_RN(R) \ +{ \ + WBYTE(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::movb_rn_a(UINT16 op) { MOVB_RN(A); } +void tms340x0_device::movb_rn_b(UINT16 op) { MOVB_RN(B); } + +#define MOVB_NR(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd = (INT8)RBYTE(R##REG(SRCREG(op))); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::movb_nr_a(UINT16 op) { MOVB_NR(A); } +void tms340x0_device::movb_nr_b(UINT16 op) { MOVB_NR(B); } + +#define MOVB_NN(R) \ +{ \ + WBYTE(R##REG(DSTREG(op)),(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))));\ + COUNT_CYCLES(3); \ +} +void tms340x0_device::movb_nn_a(UINT16 op) { MOVB_NN(A); } +void tms340x0_device::movb_nn_b(UINT16 op) { MOVB_NN(B); } + +#define MOVB_R_NO(R) \ +{ \ + INT32 o = PARAM_WORD(); \ + WBYTE(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::movb_r_no_a(UINT16 op) { MOVB_R_NO(A); } +void tms340x0_device::movb_r_no_b(UINT16 op) { MOVB_R_NO(B); } + +#define MOVB_NO_R(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 o = PARAM_WORD(); \ + CLR_NZV(); \ + *rd = (INT8)RBYTE(R##REG(SRCREG(op))+o); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::movb_no_r_a(UINT16 op) { MOVB_NO_R(A); } +void tms340x0_device::movb_no_r_b(UINT16 op) { MOVB_NO_R(B); } + +#define MOVB_NO_NO(R) \ +{ \ + INT32 o1 = PARAM_WORD(); \ + INT32 o2 = PARAM_WORD(); \ + WBYTE(R##REG(DSTREG(op))+o2,(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))+o1)); \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::movb_no_no_a(UINT16 op) { MOVB_NO_NO(A); } +void tms340x0_device::movb_no_no_b(UINT16 op) { MOVB_NO_NO(B); } + +#define MOVB_RA(R) \ +{ \ + WBYTE(PARAM_LONG(),R##REG(DSTREG(op))); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::movb_ra_a(UINT16 op) { MOVB_RA(A); } +void tms340x0_device::movb_ra_b(UINT16 op) { MOVB_RA(B); } + +#define MOVB_AR(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd = (INT8)RBYTE(PARAM_LONG()); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::movb_ar_a(UINT16 op) { MOVB_AR(A); } +void tms340x0_device::movb_ar_b(UINT16 op) { MOVB_AR(B); } + +void tms340x0_device::movb_aa(UINT16 op) +{ + UINT32 bitaddrs=PARAM_LONG(); + WBYTE(PARAM_LONG(),(UINT32)(UINT8)RBYTE(bitaddrs)); + COUNT_CYCLES(6); +} + +#define MOVE_RR(RS,RD) \ +{ \ + INT32 *rd = &RD##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd = RS##REG(SRCREG(op)); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::move_rr_a (UINT16 op) { MOVE_RR(A,A); } +void tms340x0_device::move_rr_b (UINT16 op) { MOVE_RR(B,B); } +void tms340x0_device::move_rr_ax(UINT16 op) { MOVE_RR(A,B); } +void tms340x0_device::move_rr_bx(UINT16 op) { MOVE_RR(B,A); } + +#define MOVE_RN(F,R) \ +{ \ + WFIELD##F(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::move0_rn_a (UINT16 op) { MOVE_RN(0,A); } +void tms340x0_device::move0_rn_b (UINT16 op) { MOVE_RN(0,B); } +void tms340x0_device::move1_rn_a (UINT16 op) { MOVE_RN(1,A); } +void tms340x0_device::move1_rn_b (UINT16 op) { MOVE_RN(1,B); } + +#define MOVE_R_DN(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + *rd-=fw_inc[FW(F)]; \ + WFIELD##F(*rd,R##REG(SRCREG(op))); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::move0_r_dn_a (UINT16 op) { MOVE_R_DN(0,A); } +void tms340x0_device::move0_r_dn_b (UINT16 op) { MOVE_R_DN(0,B); } +void tms340x0_device::move1_r_dn_a (UINT16 op) { MOVE_R_DN(1,A); } +void tms340x0_device::move1_r_dn_b (UINT16 op) { MOVE_R_DN(1,B); } + +#define MOVE_R_NI(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + WFIELD##F(*rd,R##REG(SRCREG(op))); \ + *rd+=fw_inc[FW(F)]; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::move0_r_ni_a (UINT16 op) { MOVE_R_NI(0,A); } +void tms340x0_device::move0_r_ni_b (UINT16 op) { MOVE_R_NI(0,B); } +void tms340x0_device::move1_r_ni_a (UINT16 op) { MOVE_R_NI(1,A); } +void tms340x0_device::move1_r_ni_b (UINT16 op) { MOVE_R_NI(1,B); } + +#define MOVE_NR(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd = RFIELD##F(R##REG(SRCREG(op))); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::move0_nr_a (UINT16 op) { MOVE_NR(0,A); } +void tms340x0_device::move0_nr_b (UINT16 op) { MOVE_NR(0,B); } +void tms340x0_device::move1_nr_a (UINT16 op) { MOVE_NR(1,A); } +void tms340x0_device::move1_nr_b (UINT16 op) { MOVE_NR(1,B); } + +#define MOVE_DN_R(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 *rs = &R##REG(SRCREG(op)); \ + CLR_NZV(); \ + *rs-=fw_inc[FW(F)]; \ + *rd = RFIELD##F(*rs); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(4); \ +} +void tms340x0_device::move0_dn_r_a (UINT16 op) { MOVE_DN_R(0,A); } +void tms340x0_device::move0_dn_r_b (UINT16 op) { MOVE_DN_R(0,B); } +void tms340x0_device::move1_dn_r_a (UINT16 op) { MOVE_DN_R(1,A); } +void tms340x0_device::move1_dn_r_b (UINT16 op) { MOVE_DN_R(1,B); } + +#define MOVE_NI_R(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 data = RFIELD##F(*rs); \ + CLR_NZV(); \ + *rs+=fw_inc[FW(F)]; \ + *rd = data; \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::move0_ni_r_a (UINT16 op) { MOVE_NI_R(0,A); } +void tms340x0_device::move0_ni_r_b (UINT16 op) { MOVE_NI_R(0,B); } +void tms340x0_device::move1_ni_r_a (UINT16 op) { MOVE_NI_R(1,A); } +void tms340x0_device::move1_ni_r_b (UINT16 op) { MOVE_NI_R(1,B); } + +#define MOVE_NN(F,R) \ +{ \ + WFIELD##F(R##REG(DSTREG(op)),RFIELD##F(R##REG(SRCREG(op)))); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::move0_nn_a (UINT16 op) { MOVE_NN(0,A); } +void tms340x0_device::move0_nn_b (UINT16 op) { MOVE_NN(0,B); } +void tms340x0_device::move1_nn_a (UINT16 op) { MOVE_NN(1,A); } +void tms340x0_device::move1_nn_b (UINT16 op) { MOVE_NN(1,B); } + +#define MOVE_DN_DN(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 data; \ + *rs-=fw_inc[FW(F)]; \ + data = RFIELD##F(*rs); \ + *rd-=fw_inc[FW(F)]; \ + WFIELD##F(*rd,data); \ + COUNT_CYCLES(4); \ +} +void tms340x0_device::move0_dn_dn_a (UINT16 op) { MOVE_DN_DN(0,A); } +void tms340x0_device::move0_dn_dn_b (UINT16 op) { MOVE_DN_DN(0,B); } +void tms340x0_device::move1_dn_dn_a (UINT16 op) { MOVE_DN_DN(1,A); } +void tms340x0_device::move1_dn_dn_b (UINT16 op) { MOVE_DN_DN(1,B); } + +#define MOVE_NI_NI(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 *rs = &R##REG(SRCREG(op)); \ + INT32 data = RFIELD##F(*rs); \ + *rs+=fw_inc[FW(F)]; \ + WFIELD##F(*rd,data); \ + *rd+=fw_inc[FW(F)]; \ + COUNT_CYCLES(4); \ +} +void tms340x0_device::move0_ni_ni_a (UINT16 op) { MOVE_NI_NI(0,A); } +void tms340x0_device::move0_ni_ni_b (UINT16 op) { MOVE_NI_NI(0,B); } +void tms340x0_device::move1_ni_ni_a (UINT16 op) { MOVE_NI_NI(1,A); } +void tms340x0_device::move1_ni_ni_b (UINT16 op) { MOVE_NI_NI(1,B); } + +#define MOVE_R_NO(F,R) \ +{ \ + INT32 o = PARAM_WORD(); \ + WFIELD##F(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::move0_r_no_a (UINT16 op) { MOVE_R_NO(0,A); } +void tms340x0_device::move0_r_no_b (UINT16 op) { MOVE_R_NO(0,B); } +void tms340x0_device::move1_r_no_a (UINT16 op) { MOVE_R_NO(1,A); } +void tms340x0_device::move1_r_no_b (UINT16 op) { MOVE_R_NO(1,B); } + +#define MOVE_NO_R(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 o = PARAM_WORD(); \ + CLR_NZV(); \ + *rd = RFIELD##F(R##REG(SRCREG(op))+o); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::move0_no_r_a (UINT16 op) { MOVE_NO_R(0,A); } +void tms340x0_device::move0_no_r_b (UINT16 op) { MOVE_NO_R(0,B); } +void tms340x0_device::move1_no_r_a (UINT16 op) { MOVE_NO_R(1,A); } +void tms340x0_device::move1_no_r_b (UINT16 op) { MOVE_NO_R(1,B); } + +#define MOVE_NO_NI(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 o = PARAM_WORD(); \ + INT32 data = RFIELD##F(R##REG(SRCREG(op))+o); \ + WFIELD##F(*rd,data); \ + *rd+=fw_inc[FW(F)]; \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::move0_no_ni_a (UINT16 op) { MOVE_NO_NI(0,A); } +void tms340x0_device::move0_no_ni_b (UINT16 op) { MOVE_NO_NI(0,B); } +void tms340x0_device::move1_no_ni_a (UINT16 op) { MOVE_NO_NI(1,A); } +void tms340x0_device::move1_no_ni_b (UINT16 op) { MOVE_NO_NI(1,B); } + +#define MOVE_NO_NO(F,R) \ +{ \ + INT32 o1 = PARAM_WORD(); \ + INT32 o2 = PARAM_WORD(); \ + INT32 data = RFIELD##F(R##REG(SRCREG(op))+o1); \ + WFIELD##F(R##REG(DSTREG(op))+o2,data); \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::move0_no_no_a (UINT16 op) { MOVE_NO_NO(0,A); } +void tms340x0_device::move0_no_no_b (UINT16 op) { MOVE_NO_NO(0,B); } +void tms340x0_device::move1_no_no_a (UINT16 op) { MOVE_NO_NO(1,A); } +void tms340x0_device::move1_no_no_b (UINT16 op) { MOVE_NO_NO(1,B); } + +#define MOVE_RA(F,R) \ +{ \ + WFIELD##F(PARAM_LONG(),R##REG(DSTREG(op))); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::move0_ra_a (UINT16 op) { MOVE_RA(0,A); } +void tms340x0_device::move0_ra_b (UINT16 op) { MOVE_RA(0,B); } +void tms340x0_device::move1_ra_a (UINT16 op) { MOVE_RA(1,A); } +void tms340x0_device::move1_ra_b (UINT16 op) { MOVE_RA(1,B); } + +#define MOVE_AR(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_NZV(); \ + *rd = RFIELD##F(PARAM_LONG()); \ + SET_NZ_VAL(*rd); \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::move0_ar_a (UINT16 op) { MOVE_AR(0,A); } +void tms340x0_device::move0_ar_b (UINT16 op) { MOVE_AR(0,B); } +void tms340x0_device::move1_ar_a (UINT16 op) { MOVE_AR(1,A); } +void tms340x0_device::move1_ar_b (UINT16 op) { MOVE_AR(1,B); } + +#define MOVE_A_NI(F,R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + WFIELD##F(*rd,RFIELD##F(PARAM_LONG())); \ + *rd+=fw_inc[FW(F)]; \ + COUNT_CYCLES(5); \ +} +void tms340x0_device::move0_a_ni_a (UINT16 op) { MOVE_A_NI(0,A); } +void tms340x0_device::move0_a_ni_b (UINT16 op) { MOVE_A_NI(0,B); } +void tms340x0_device::move1_a_ni_a (UINT16 op) { MOVE_A_NI(1,A); } +void tms340x0_device::move1_a_ni_b (UINT16 op) { MOVE_A_NI(1,B); } + +#define MOVE_AA(F) \ +{ \ + UINT32 bitaddrs=PARAM_LONG(); \ + WFIELD##F(PARAM_LONG(),RFIELD##F(bitaddrs)); \ + COUNT_CYCLES(7); \ +} +void tms340x0_device::move0_aa (UINT16 op) { MOVE_AA(0); } +void tms340x0_device::move1_aa (UINT16 op) { MOVE_AA(1); } + + + +/*************************************************************************** + PROGRAM CONTROL INSTRUCTIONS +***************************************************************************/ + +#define CALL(R) \ +{ \ + PUSH(m_pc); \ + m_pc = R##REG(DSTREG(op)); \ + CORRECT_ODD_PC("CALL"); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::call_a (UINT16 op) { CALL(A); } +void tms340x0_device::call_b (UINT16 op) { CALL(B); } + +void tms340x0_device::callr(UINT16 op) +{ + PUSH(m_pc+0x10); + m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; + COUNT_CYCLES(3); +} + +void tms340x0_device::calla(UINT16 op) +{ + PUSH(m_pc+0x20); + m_pc = PARAM_LONG_NO_INC(); + CORRECT_ODD_PC("CALLA"); + COUNT_CYCLES(4); +} + +#define DSJ(R) \ +{ \ + if (--R##REG(DSTREG(op))) \ + { \ + m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ + COUNT_CYCLES(3); \ + } \ + else \ + { \ + SKIP_WORD(); \ + COUNT_CYCLES(2); \ + } \ +} +void tms340x0_device::dsj_a (UINT16 op) { DSJ(A); } +void tms340x0_device::dsj_b (UINT16 op) { DSJ(B); } + +#define DSJEQ(R) \ +{ \ + if (Z_FLAG()) \ + { \ + if (--R##REG(DSTREG(op))) \ + { \ + m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ + COUNT_CYCLES(3); \ + } \ + else \ + { \ + SKIP_WORD(); \ + COUNT_CYCLES(2); \ + } \ + } \ + else \ + { \ + SKIP_WORD(); \ + COUNT_CYCLES(2); \ + } \ +} +void tms340x0_device::dsjeq_a (UINT16 op) { DSJEQ(A); } +void tms340x0_device::dsjeq_b (UINT16 op) { DSJEQ(B); } + +#define DSJNE(R) \ +{ \ + if (!Z_FLAG()) \ + { \ + if (--R##REG(DSTREG(op))) \ + { \ + m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ + COUNT_CYCLES(3); \ + } \ + else \ + { \ + SKIP_WORD(); \ + COUNT_CYCLES(2); \ + } \ + } \ + else \ + { \ + SKIP_WORD(); \ + COUNT_CYCLES(2); \ + } \ +} +void tms340x0_device::dsjne_a (UINT16 op) { DSJNE(A); } +void tms340x0_device::dsjne_b (UINT16 op) { DSJNE(B); } + +#define DSJS(R) \ +{ \ + if (op & 0x0400) \ + { \ + if (--R##REG(DSTREG(op))) \ + { \ + m_pc -= ((PARAM_K(op))<<4); \ + COUNT_CYCLES(2); \ + } \ + else \ + COUNT_CYCLES(3); \ + } \ + else \ + { \ + if (--R##REG(DSTREG(op))) \ + { \ + m_pc += ((PARAM_K(op))<<4); \ + COUNT_CYCLES(2); \ + } \ + else \ + COUNT_CYCLES(3); \ + } \ +} +void tms340x0_device::dsjs_a (UINT16 op) { DSJS(A); } +void tms340x0_device::dsjs_b (UINT16 op) { DSJS(B); } + +void tms340x0_device::emu(UINT16 op) +{ + /* in RUN state, this instruction is a NOP */ + COUNT_CYCLES(6); +} + +#define EXGPC(R) \ +{ \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 temppc = *rd; \ + *rd = m_pc; \ + m_pc = temppc; \ + CORRECT_ODD_PC("EXGPC"); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::exgpc_a (UINT16 op) { EXGPC(A); } +void tms340x0_device::exgpc_b (UINT16 op) { EXGPC(B); } + +#define GETPC(R) \ +{ \ + R##REG(DSTREG(op)) = m_pc; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::getpc_a (UINT16 op) { GETPC(A); } +void tms340x0_device::getpc_b (UINT16 op) { GETPC(B); } + +#define GETST(R) \ +{ \ + R##REG(DSTREG(op)) = m_st; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::getst_a (UINT16 op) { GETST(A); } +void tms340x0_device::getst_b (UINT16 op) { GETST(B); } + +#define j_xx_8(TAKE) \ +{ \ + if (DSTREG(op)) \ + { \ + if (TAKE) \ + { \ + m_pc += (PARAM_REL8(op) << 4); \ + COUNT_CYCLES(2); \ + } \ + else \ + COUNT_CYCLES(1); \ + } \ + else \ + { \ + if (TAKE) \ + { \ + m_pc = PARAM_LONG_NO_INC(); \ + CORRECT_ODD_PC("J_XX_8"); \ + COUNT_CYCLES(3); \ + } \ + else \ + { \ + SKIP_LONG(); \ + COUNT_CYCLES(4); \ + } \ + } \ +} + +#define j_xx_0(TAKE) \ +{ \ + if (DSTREG(op)) \ + { \ + if (TAKE) \ + { \ + m_pc += (PARAM_REL8(op) << 4); \ + COUNT_CYCLES(2); \ + } \ + else \ + COUNT_CYCLES(1); \ + } \ + else \ + { \ + if (TAKE) \ + { \ + m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ + COUNT_CYCLES(3); \ + } \ + else \ + { \ + SKIP_WORD(); \ + COUNT_CYCLES(2); \ + } \ + } \ +} + +#define j_xx_x(TAKE) \ +{ \ + if (TAKE) \ + { \ + m_pc += (PARAM_REL8(op) << 4); \ + COUNT_CYCLES(2); \ + } \ + else \ + COUNT_CYCLES(1); \ +} + +void tms340x0_device::j_UC_0(UINT16 op) +{ + j_xx_0(1); +} +void tms340x0_device::j_UC_8(UINT16 op) +{ + j_xx_8(1); +} +void tms340x0_device::j_UC_x(UINT16 op) +{ + j_xx_x(1); +} +void tms340x0_device::j_P_0(UINT16 op) +{ + j_xx_0(!N_FLAG() && !Z_FLAG()); +} +void tms340x0_device::j_P_8(UINT16 op) +{ + j_xx_8(!N_FLAG() && !Z_FLAG()); +} +void tms340x0_device::j_P_x(UINT16 op) +{ + j_xx_x(!N_FLAG() && !Z_FLAG()); +} +void tms340x0_device::j_LS_0(UINT16 op) +{ + j_xx_0(C_FLAG() || Z_FLAG()); +} +void tms340x0_device::j_LS_8(UINT16 op) +{ + j_xx_8(C_FLAG() || Z_FLAG()); +} +void tms340x0_device::j_LS_x(UINT16 op) +{ + j_xx_x(C_FLAG() || Z_FLAG()); +} +void tms340x0_device::j_HI_0(UINT16 op) +{ + j_xx_0(!C_FLAG() && !Z_FLAG()); +} +void tms340x0_device::j_HI_8(UINT16 op) +{ + j_xx_8(!C_FLAG() && !Z_FLAG()); +} +void tms340x0_device::j_HI_x(UINT16 op) +{ + j_xx_x(!C_FLAG() && !Z_FLAG()); +} +void tms340x0_device::j_LT_0(UINT16 op) +{ + j_xx_0((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); +} +void tms340x0_device::j_LT_8(UINT16 op) +{ + j_xx_8((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); +} +void tms340x0_device::j_LT_x(UINT16 op) +{ + j_xx_x((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); +} +void tms340x0_device::j_GE_0(UINT16 op) +{ + j_xx_0((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); +} +void tms340x0_device::j_GE_8(UINT16 op) +{ + j_xx_8((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); +} +void tms340x0_device::j_GE_x(UINT16 op) +{ + j_xx_x((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); +} +void tms340x0_device::j_LE_0(UINT16 op) +{ + j_xx_0((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); +} +void tms340x0_device::j_LE_8(UINT16 op) +{ + j_xx_8((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); +} +void tms340x0_device::j_LE_x(UINT16 op) +{ + j_xx_x((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); +} +void tms340x0_device::j_GT_0(UINT16 op) +{ + j_xx_0((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); +} +void tms340x0_device::j_GT_8(UINT16 op) +{ + j_xx_8((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); +} +void tms340x0_device::j_GT_x(UINT16 op) +{ + j_xx_x((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); +} +void tms340x0_device::j_C_0(UINT16 op) +{ + j_xx_0(C_FLAG()); +} +void tms340x0_device::j_C_8(UINT16 op) +{ + j_xx_8(C_FLAG()); +} +void tms340x0_device::j_C_x(UINT16 op) +{ + j_xx_x(C_FLAG()); +} +void tms340x0_device::j_NC_0(UINT16 op) +{ + j_xx_0(!C_FLAG()); +} +void tms340x0_device::j_NC_8(UINT16 op) +{ + j_xx_8(!C_FLAG()); +} +void tms340x0_device::j_NC_x(UINT16 op) +{ + j_xx_x(!C_FLAG()); +} +void tms340x0_device::j_EQ_0(UINT16 op) +{ + j_xx_0(Z_FLAG()); +} +void tms340x0_device::j_EQ_8(UINT16 op) +{ + j_xx_8(Z_FLAG()); +} +void tms340x0_device::j_EQ_x(UINT16 op) +{ + j_xx_x(Z_FLAG()); +} +void tms340x0_device::j_NE_0(UINT16 op) +{ + j_xx_0(!Z_FLAG()); +} +void tms340x0_device::j_NE_8(UINT16 op) +{ + j_xx_8(!Z_FLAG()); +} +void tms340x0_device::j_NE_x(UINT16 op) +{ + j_xx_x(!Z_FLAG()); +} +void tms340x0_device::j_V_0(UINT16 op) +{ + j_xx_0(V_FLAG()); +} +void tms340x0_device::j_V_8(UINT16 op) +{ + j_xx_8(V_FLAG()); +} +void tms340x0_device::j_V_x(UINT16 op) +{ + j_xx_x(V_FLAG()); +} +void tms340x0_device::j_NV_0(UINT16 op) +{ + j_xx_0(!V_FLAG()); +} +void tms340x0_device::j_NV_8(UINT16 op) +{ + j_xx_8(!V_FLAG()); +} +void tms340x0_device::j_NV_x(UINT16 op) +{ + j_xx_x(!V_FLAG()); +} +void tms340x0_device::j_N_0(UINT16 op) +{ + j_xx_0(N_FLAG()); +} +void tms340x0_device::j_N_8(UINT16 op) +{ + j_xx_8(N_FLAG()); +} +void tms340x0_device::j_N_x(UINT16 op) +{ + j_xx_x(N_FLAG()); +} +void tms340x0_device::j_NN_0(UINT16 op) +{ + j_xx_0(!N_FLAG()); +} +void tms340x0_device::j_NN_8(UINT16 op) +{ + j_xx_8(!N_FLAG()); +} +void tms340x0_device::j_NN_x(UINT16 op) +{ + j_xx_x(!N_FLAG()); +} + +#define JUMP(R) \ +{ \ + m_pc = R##REG(DSTREG(op)); \ + CORRECT_ODD_PC("JUMP"); \ + COUNT_CYCLES(2); \ +} +void tms340x0_device::jump_a (UINT16 op) { JUMP(A); } +void tms340x0_device::jump_b (UINT16 op) { JUMP(B); } + +void tms340x0_device::popst(UINT16 op) +{ + SET_ST(POP()); + COUNT_CYCLES(8); +} + +void tms340x0_device::pushst(UINT16 op) +{ + PUSH(m_st); + COUNT_CYCLES(2); +} + +#define PUTST(R) \ +{ \ + SET_ST(R##REG(DSTREG(op))); \ + COUNT_CYCLES(3); \ +} +void tms340x0_device::putst_a (UINT16 op) { PUTST(A); } +void tms340x0_device::putst_b (UINT16 op) { PUTST(B); } + +void tms340x0_device::reti(UINT16 op) +{ + INT32 st = POP(); + m_pc = POP(); + CORRECT_ODD_PC("RETI"); + SET_ST(st); + COUNT_CYCLES(11); +} + +void tms340x0_device::rets(UINT16 op) +{ + UINT32 offs; + m_pc = POP(); + CORRECT_ODD_PC("RETS"); + offs = PARAM_N(op); + if (offs) + { + SP()+=(offs<<4); + } + COUNT_CYCLES(7); +} + +#define REV(R) \ +{ \ + R##REG(DSTREG(op)) = 0x0008; \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::rev_a (UINT16 op) { REV(A); } +void tms340x0_device::rev_b (UINT16 op) { REV(B); } + +void tms340x0_device::trap(UINT16 op) +{ + UINT32 t = PARAM_N(op); + if (t) + { + PUSH(m_pc); + PUSH(m_st); + } + RESET_ST(); + m_pc = RLONG(0xffffffe0-(t<<5)); + CORRECT_ODD_PC("TRAP"); + COUNT_CYCLES(16); +} + + + +/*************************************************************************** + 34020 INSTRUCTIONS +***************************************************************************/ + +/************************************ + +New 34020 ops: + + 0000 1100 000R dddd = ADDXYI IL,Rd + iiii iiii iiii iiii + iiii iiii iiii iiii + + 0000 0000 1111 00SD = BLMOVE S,D + + 0000 0110 0000 0000 = CEXEC S,c,ID,L + cccc cccc S000 0000 + iiic cccc cccc cccc + + 1101 1000 0ccc cccS = CEXEC S,c,ID + iiic cccc cccc cccc + + 0000 1000 1111 0010 = CLIP + + 0000 0110 011R dddd = CMOVCG Rd1,Rd2,S,c,ID + cccc cccc S00R dddd + iiic cccc cccc cccc + + 0000 0110 101R dddd = CMOVCM *Rd+,n,S,c,ID + cccc cccc S00n nnnn + iiic cccc cccc cccc + + 0000 0110 110R dddd = CMOVCM -*Rd,n,S,c,ID + cccc cccc S00n nnnn + iiic cccc cccc cccc + + 0000 0110 0110 0000 = CMOVCS c,ID + cccc cccc 0000 0001 + iiic cccc cccc cccc + + 0000 0110 001R ssss = CMOVGC Rs,c,ID + cccc cccc 0000 0000 + iiic cccc cccc cccc + + 0000 0110 010R ssss = CMOVGC Rs1,Rs2,S,c,ID + cccc cccc S00R ssss + iiic cccc cccc cccc + + 0000 0110 100n nnnn = CMOVMC *Rs+,n,S,c,ID + cccc cccc S00R ssss + iiic cccc cccc cccc + + 0000 1000 001n nnnn = CMOVMC -*Rs,n,S,c,ID + cccc cccc S00R ssss + iiic cccc cccc cccc + + 0000 0110 111R dddd = CMOVMC *Rs+,Rd,S,c,ID + cccc cccc S00R ssss + iiic cccc cccc cccc + + 0011 01kk kkkR dddd = CMPK k,Rd + + 0000 1010 100R dddd = CVDXYL Rd + + 0000 1010 011R dddd = CVMXYL Rd + + 1110 101s sssR dddd = CVSXYL Rs,Rd + + 0000 0010 101R dddd = EXGPS Rd + + 1101 1110 Z001 1010 = FLINE Z + + 0000 1010 1011 1011 = FPIXEQ + + 0000 1010 1101 1011 = FPIXNE + + 0000 0010 110R dddd = GETPS Rd + + 0000 0000 0100 0000 = IDLE + + 0000 1100 0101 0111 = LINIT + + 0000 0000 1000 0000 = MWAIT + + 0000 1010 0011 0111 = PFILL XY + + 0000 1110 0001 0111 = PIXBLT L,M,L + + 0000 1000 0110 0000 = RETM + + 0111 101s sssR dddd = RMO Rs,Rd + + 0000 0010 100R dddd = RPIX Rd + + 0000 0010 0111 0011 = SETCDP + + 0000 0010 1111 1011 = SETCMP + + 0000 0010 0101 0001 = SETCSP + + 0111 111s sssR dddd = SWAPF *Rs,Rd,0 + + 0000 1110 1111 1010 = TFILL XY + + 0000 1000 0000 1111 = TRAPL + + 0000 1000 0101 0111 = VBLT B,L + + 0000 1010 0101 0111 = VFILL L + + 0000 1010 0000 0000 = VLCOL + +************************************/ + + +#define ADD_XYI(R) \ +{ \ + UINT32 a = PARAM_LONG(); \ + XY *b = &R##REG_XY(DSTREG(op)); \ + CLR_NCZV(); \ + b->x += (INT16)(a & 0xffff); \ + b->y += ((INT32)a >> 16); \ + SET_N_LOG(b->x == 0); \ + SET_C_BIT_LO(b->y, 15); \ + SET_Z_LOG(b->y == 0); \ + SET_V_BIT_LO(b->x, 15); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::addxyi_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + ADD_XYI(A); +} +void tms340x0_device::addxyi_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + ADD_XYI(B); +} + +void tms340x0_device::blmove(UINT16 op) +{ + offs_t src = BREG(0); + offs_t dst = BREG(2); + offs_t bits = BREG(7); + + if (!m_is_34020) { unimpl(op); return; } + + /* src and dst are aligned */ + if (!(src & 0x0f) && !(dst & 0x0f)) + { + while (bits >= 16 && m_icount > 0) + { + TMS34010_WRMEM_WORD(TOBYTE(dst), TMS34010_RDMEM_WORD(TOBYTE(src))); + src += 0x10; + dst += 0x10; + bits -= 0x10; + m_icount -= 2; + } + if (bits != 0 && m_icount > 0) + { + (this->*s_wfield_functions[bits])(dst, (this->*s_rfield_functions[bits])(src)); + dst += bits; + src += bits; + bits = 0; + m_icount -= 2; + } + } + + /* src is aligned, dst is not */ + else if (!(src & 0x0f)) + { + logerror("020:BLMOVE with aligned src and unaligned dst\n"); + } + + /* dst is aligned, src is not */ + else if (!(dst & 0x0f)) + { + logerror("020:BLMOVE with unaligned src and aligned dst\n"); + } + + /* neither are aligned */ + else + { + logerror("020:BLMOVE with completely unaligned src and dst\n"); + } + + /* update the final results */ + BREG(0) = src; + BREG(2) = dst; + BREG(7) = bits; + + /* if we're not done yet, back up the PC */ + if (bits != 0) + m_pc -= 0x10; +} + +void tms340x0_device::cexec_l(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cexec_l\n"); +} + +void tms340x0_device::cexec_s(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cexec_s\n"); +} + +void tms340x0_device::clip(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:clip\n"); +} + +void tms340x0_device::cmovcg_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovcg_a\n"); +} + +void tms340x0_device::cmovcg_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovcg_b\n"); +} + +void tms340x0_device::cmovcm_f(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovcm_f\n"); +} + +void tms340x0_device::cmovcm_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovcm_b\n"); +} + +void tms340x0_device::cmovgc_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovgc_a\n"); +} + +void tms340x0_device::cmovgc_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovgc_b\n"); +} + +void tms340x0_device::cmovgc_a_s(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovgc_a_s\n"); +} + +void tms340x0_device::cmovgc_b_s(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovgc_b_s\n"); +} + +void tms340x0_device::cmovmc_f(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovmc_f\n"); +} + +void tms340x0_device::cmovmc_f_va(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovmc_f_va\n"); +} + +void tms340x0_device::cmovmc_f_vb(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovmc_f_vb\n"); +} + +void tms340x0_device::cmovmc_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cmovmc_b\n"); +} + +#define CMPK(R) \ +{ \ + INT32 r; \ + INT32 *rd = &R##REG(DSTREG(op)); \ + INT32 t = PARAM_K(op); if (!t) t = 32; \ + CLR_NCZV(); \ + r = *rd - t; \ + SET_NZCV_SUB(*rd,t,r); \ + COUNT_CYCLES(1); \ +} +void tms340x0_device::cmp_k_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + CMPK(A); +} +void tms340x0_device::cmp_k_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + CMPK(B); +} + +void tms340x0_device::cvdxyl_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cvdxyl_a\n"); +} + +void tms340x0_device::cvdxyl_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cvdxyl_b\n"); +} + +void tms340x0_device::cvmxyl_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cvmxyl_a\n"); +} + +void tms340x0_device::cvmxyl_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cvmxyl_b\n"); +} + +void tms340x0_device::cvsxyl_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cvsxyl_a\n"); +} + +void tms340x0_device::cvsxyl_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:cvsxyl_b\n"); +} + +void tms340x0_device::exgps_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:exgps_a\n"); +} + +void tms340x0_device::exgps_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:exgps_b\n"); +} + +void tms340x0_device::fline(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:fline\n"); +} + +void tms340x0_device::fpixeq(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:fpixeq\n"); +} + +void tms340x0_device::fpixne(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:fpixne\n"); +} + +void tms340x0_device::getps_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:getps_a\n"); +} + +void tms340x0_device::getps_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:getps_b\n"); +} + +void tms340x0_device::idle(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:idle\n"); +} + +void tms340x0_device::linit(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:linit\n"); +} + +void tms340x0_device::mwait(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } +} + +void tms340x0_device::pfill_xy(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:pfill_xy\n"); +} + +void tms340x0_device::pixblt_l_m_l(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:pixblt_l_m_l\n"); +} + +void tms340x0_device::retm(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:retm\n"); +} + +#define RMO(R) \ +{ \ + UINT32 res = 0; \ + UINT32 rs = R##REG(SRCREG(op)); \ + INT32 *rd = &R##REG(DSTREG(op)); \ + CLR_Z(); \ + SET_Z_VAL(rs); \ + if (rs) \ + { \ + while (!(rs & 0x00000001)) \ + { \ + res++; \ + rs >>= 1; \ + } \ + } \ + *rd = res; \ + COUNT_CYCLES(1); \ +} + +void tms340x0_device::rmo_a(UINT16 op) { RMO(A); } +void tms340x0_device::rmo_b(UINT16 op) { RMO(B); } + +#define RPIX(R) \ +{ \ + UINT32 v = R##REG(DSTREG(op)); \ + switch (m_pixelshift) \ + { \ + case 0: \ + v = (v & 1) ? 0xffffffff : 0x00000000;\ + COUNT_CYCLES(8); \ + break; \ + case 1: \ + v &= 3; \ + v |= v << 2; \ + v |= v << 4; \ + v |= v << 8; \ + v |= v << 16; \ + COUNT_CYCLES(7); \ + break; \ + case 2: \ + v &= 0x0f; \ + v |= v << 4; \ + v |= v << 8; \ + v |= v << 16; \ + COUNT_CYCLES(6); \ + break; \ + case 3: \ + v &= 0xff; \ + v |= v << 8; \ + v |= v << 16; \ + COUNT_CYCLES(5); \ + break; \ + case 4: \ + v &= 0xffff; \ + v |= v << 16; \ + COUNT_CYCLES(4); \ + break; \ + case 5: \ + COUNT_CYCLES(2); \ + break; \ + } \ + R##REG(DSTREG(op)) = v; \ +} + +void tms340x0_device::rpix_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + RPIX(A); +} + +void tms340x0_device::rpix_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + RPIX(B); +} + +void tms340x0_device::setcdp(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:setcdp\n"); +} + +void tms340x0_device::setcmp(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:setcmp\n"); +} + +void tms340x0_device::setcsp(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:setcsp\n"); +} + +void tms340x0_device::swapf_a(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:swapf_a\n"); +} + +void tms340x0_device::swapf_b(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:swapf_b\n"); +} + +void tms340x0_device::tfill_xy(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:tfill_xy\n"); +} + +void tms340x0_device::trapl(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:trapl\n"); +} + +void tms340x0_device::vblt_b_l(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:vblt_b_l\n"); +} + +void tms340x0_device::vfill_l(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:vfill_l\n"); +} + +void tms340x0_device::vlcol(UINT16 op) +{ + if (!m_is_34020) { unimpl(op); return; } + logerror("020:vlcol\n"); +} diff --git a/mame/tm34010/34010ops.h b/mame/tm34010/34010ops.h new file mode 100644 index 00000000..6dad233c --- /dev/null +++ b/mame/tm34010/34010ops.h @@ -0,0 +1,154 @@ +// license:BSD-3-Clause +// copyright-holders:Alex Pasadyn,Zsolt Vasvari +/*************************************************************************** + + TMS34010: Portable Texas Instruments TMS34010 emulator + + Copyright Alex Pasadyn/Zsolt Vasvari + Parts based on code by Aaron Giles + +***************************************************************************/ + +#pragma once + +#ifndef __34010OPS_H__ +#define __34010OPS_H__ + + + + +/*************************************************************************** + MEMORY I/O MACROS +***************************************************************************/ + +#define TMS34010_RDMEM(A) ((unsigned)m_program->read_byte (A)) +#define TMS34010_RDMEM_WORD(A) ((unsigned)m_program->read_word (A)) +inline UINT32 tms340x0_device::TMS34010_RDMEM_DWORD(offs_t A) +{ + UINT32 result = m_program->read_word(A); + return result | (m_program->read_word(A+2)<<16); +} + +#define TMS34010_WRMEM(A,V) (m_program->write_byte(A,V)) +#define TMS34010_WRMEM_WORD(A,V) (m_program->write_word(A,V)) +inline void tms340x0_device::TMS34010_WRMEM_DWORD(offs_t A, UINT32 V) +{ + m_program->write_word(A,V); + m_program->write_word(A+2,V>>16); +} + + + +/* IO registers accessor */ +#define IOREG(reg) (m_IOregs[reg]) +#define SMART_IOREG(reg) (m_IOregs[m_is_34020 ? (int)REG020_##reg : (int)REG_##reg]) +#define PBH() (IOREG(REG_CONTROL) & 0x0100) +#define PBV() (IOREG(REG_CONTROL) & 0x0200) + + + +/*************************************************************************** + FIELD WRITE MACROS +***************************************************************************/ + +#define WFIELDMAC(MASK,MAX) \ + UINT32 shift = offset & 0x0f; \ + UINT32 masked_data = data & (MASK); \ + UINT32 old; \ + \ + offset = TOBYTE(offset & 0xfffffff0); \ + \ + if (shift >= MAX) \ + { \ + old = (UINT32)TMS34010_RDMEM_DWORD(offset) & ~((MASK) << shift); \ + TMS34010_WRMEM_DWORD(offset, (masked_data << shift) | old); \ + } \ + else \ + { \ + old = (UINT32)TMS34010_RDMEM_WORD(offset) & ~((MASK) << shift); \ + TMS34010_WRMEM_WORD(offset, ((masked_data & (MASK)) << shift) | old); \ + } + +#define WFIELDMAC_BIG(MASK,MAX) \ + UINT32 shift = offset & 0x0f; \ + UINT32 masked_data = data & (MASK); \ + UINT32 old; \ + \ + offset = TOBYTE(offset & 0xfffffff0); \ + \ + old = (UINT32)TMS34010_RDMEM_DWORD(offset) & ~(UINT32)((MASK) << shift); \ + TMS34010_WRMEM_DWORD(offset, (UINT32)(masked_data << shift) | old); \ + if (shift >= MAX) \ + { \ + shift = 32 - shift; \ + old = (UINT32)TMS34010_RDMEM_WORD(offset + 4) & ~((MASK) >> shift); \ + TMS34010_WRMEM_WORD(offset, (masked_data >> shift) | old); \ + } + +#define WFIELDMAC_8() \ + if (offset & 0x07) \ + { \ + WFIELDMAC(0xff,9); \ + } \ + else \ + TMS34010_WRMEM(TOBYTE(offset), data); + +#define RFIELDMAC_8() \ + if (offset & 0x07) \ + { \ + RFIELDMAC(0xff,9); \ + } \ + else \ + return TMS34010_RDMEM(TOBYTE(offset)); + +#define WFIELDMAC_32() \ + if (offset & 0x0f) \ + { \ + UINT32 shift = offset&0x0f; \ + UINT32 old; \ + UINT32 hiword; \ + offset &= 0xfffffff0; \ + old = ((UINT32) TMS34010_RDMEM_DWORD (TOBYTE(offset ))&(0xffffffff>>(0x20-shift))); \ + hiword = ((UINT32) TMS34010_RDMEM_DWORD (TOBYTE(offset+0x20))&(0xffffffff<>(0x20-shift))|hiword); \ + } \ + else \ + TMS34010_WRMEM_DWORD(TOBYTE(offset),data); + + +/*************************************************************************** + FIELD READ MACROS +***************************************************************************/ + +#define RFIELDMAC(MASK,MAX) \ + UINT32 shift = offset & 0x0f; \ + offset = TOBYTE(offset & 0xfffffff0); \ + \ + if (shift >= MAX) \ + ret = (TMS34010_RDMEM_DWORD(offset) >> shift) & (MASK); \ + else \ + ret = (TMS34010_RDMEM_WORD(offset) >> shift) & (MASK); + +#define RFIELDMAC_BIG(MASK,MAX) \ + UINT32 shift = offset & 0x0f; \ + offset = TOBYTE(offset & 0xfffffff0); \ + \ + ret = (UINT32)TMS34010_RDMEM_DWORD(offset) >> shift; \ + if (shift >= MAX) \ + ret |= (TMS34010_RDMEM_WORD(offset + 4) << (32 - shift)); \ + ret &= MASK; + +#define RFIELDMAC_32() \ + if (offset&0x0f) \ + { \ + UINT32 shift = offset&0x0f; \ + offset &= 0xfffffff0; \ + return (((UINT32)TMS34010_RDMEM_DWORD (TOBYTE(offset ))>> shift) | \ + (TMS34010_RDMEM_DWORD (TOBYTE(offset+0x20))<<(0x20-shift)));\ + } \ + else \ + return TMS34010_RDMEM_DWORD(TOBYTE(offset)); + + +#endif /* __34010OPS_H__ */ diff --git a/mame/tm34010/34010tbl.c b/mame/tm34010/34010tbl.c new file mode 100644 index 00000000..2cef83dc --- /dev/null +++ b/mame/tm34010/34010tbl.c @@ -0,0 +1,782 @@ +// license:BSD-3-Clause +// copyright-holders:Alex Pasadyn,Zsolt Vasvari +/*** TMS34010: Portable TMS34010 emulator *********************************** + + Copyright Alex Pasadyn/Zsolt Vasvari + + Opcode Table + +*****************************************************************************/ + +/* Opcode Table */ +const tms340x0_device::opcode_func tms340x0_device::s_opcode_table[65536 >> 4] = +{ + /* 0x0000 0x0010 0x0020 0x0030 ... 0x00f0 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::rev_a, &tms340x0_device::rev_b, &tms340x0_device::idle, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::mwait, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::blmove, + /* 0x0100 */ + &tms340x0_device::emu, &tms340x0_device::unimpl, &tms340x0_device::exgpc_a, &tms340x0_device::exgpc_b, &tms340x0_device::getpc_a, &tms340x0_device::getpc_b, &tms340x0_device::jump_a, &tms340x0_device::jump_b, + &tms340x0_device::getst_a, &tms340x0_device::getst_b, &tms340x0_device::putst_a, &tms340x0_device::putst_b, &tms340x0_device::popst, &tms340x0_device::unimpl, &tms340x0_device::pushst, &tms340x0_device::unimpl, + /* 0x0200 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::setcsp, &tms340x0_device::unimpl, &tms340x0_device::setcdp, + &tms340x0_device::rpix_a, &tms340x0_device::rpix_b, &tms340x0_device::exgps_a, &tms340x0_device::exgps_b, &tms340x0_device::getps_a, &tms340x0_device::getps_b, &tms340x0_device::unimpl, &tms340x0_device::setcmp, + /* 0x0300 */ + &tms340x0_device::nop, &tms340x0_device::unimpl, &tms340x0_device::clrc, &tms340x0_device::unimpl, &tms340x0_device::movb_aa, &tms340x0_device::unimpl, &tms340x0_device::dint, &tms340x0_device::unimpl, + &tms340x0_device::abs_a, &tms340x0_device::abs_b, &tms340x0_device::neg_a, &tms340x0_device::neg_b, &tms340x0_device::negb_a, &tms340x0_device::negb_b, &tms340x0_device::not_a, &tms340x0_device::not_b, + /* 0x0400 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x0500 */ + &tms340x0_device::sext0_a, &tms340x0_device::sext0_b, &tms340x0_device::zext0_a, &tms340x0_device::zext0_b, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, + &tms340x0_device::move0_ra_a, &tms340x0_device::move0_ra_b, &tms340x0_device::move0_ar_a, &tms340x0_device::move0_ar_b, &tms340x0_device::move0_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ra_a, &tms340x0_device::movb_ra_b, + /* 0x0600 */ + &tms340x0_device::cexec_l, &tms340x0_device::unimpl, &tms340x0_device::cmovgc_a, &tms340x0_device::cmovgc_b, &tms340x0_device::cmovgc_a_s, &tms340x0_device::cmovgc_b_s, &tms340x0_device::cmovcg_a, &tms340x0_device::cmovcg_b, + &tms340x0_device::cmovmc_f, &tms340x0_device::cmovmc_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovmc_f_va,&tms340x0_device::cmovmc_f_vb, + /* 0x0700 */ + &tms340x0_device::sext1_a, &tms340x0_device::sext1_b, &tms340x0_device::zext1_a, &tms340x0_device::zext1_b, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, + &tms340x0_device::move1_ra_a, &tms340x0_device::move1_ra_b, &tms340x0_device::move1_ar_a, &tms340x0_device::move1_ar_b, &tms340x0_device::move1_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ar_a, &tms340x0_device::movb_ar_b, + /* 0x0800 */ + &tms340x0_device::trapl, &tms340x0_device::unimpl, &tms340x0_device::cmovmc_b, &tms340x0_device::cmovmc_b, &tms340x0_device::unimpl, &tms340x0_device::vblt_b_l, &tms340x0_device::retm, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::clip, + /* 0x0900 */ + &tms340x0_device::trap, &tms340x0_device::trap, &tms340x0_device::call_a, &tms340x0_device::call_b, &tms340x0_device::reti, &tms340x0_device::unimpl, &tms340x0_device::rets, &tms340x0_device::rets, + &tms340x0_device::mmtm_a, &tms340x0_device::mmtm_b, &tms340x0_device::mmfm_a, &tms340x0_device::mmfm_b, &tms340x0_device::movi_w_a, &tms340x0_device::movi_w_b, &tms340x0_device::movi_l_a, &tms340x0_device::movi_l_b, + /* 0x0a00 */ + &tms340x0_device::vlcol, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::pfill_xy, &tms340x0_device::unimpl, &tms340x0_device::vfill_l, &tms340x0_device::cvmxyl_a, &tms340x0_device::cvmxyl_b, + &tms340x0_device::cvdxyl_a, &tms340x0_device::cvdxyl_b, &tms340x0_device::unimpl, &tms340x0_device::fpixeq, &tms340x0_device::unimpl, &tms340x0_device::fpixne, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x0b00 */ + &tms340x0_device::addi_w_a, &tms340x0_device::addi_w_b, &tms340x0_device::addi_l_a, &tms340x0_device::addi_l_b, &tms340x0_device::cmpi_w_a, &tms340x0_device::cmpi_w_b, &tms340x0_device::cmpi_l_a, &tms340x0_device::cmpi_l_b, + &tms340x0_device::andi_a, &tms340x0_device::andi_b, &tms340x0_device::ori_a, &tms340x0_device::ori_b, &tms340x0_device::xori_a, &tms340x0_device::xori_b, &tms340x0_device::subi_w_a, &tms340x0_device::subi_w_b, + /* 0x0c00 */ + &tms340x0_device::addxyi_a, &tms340x0_device::addxyi_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::linit, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x0d00 */ + &tms340x0_device::subi_l_a, &tms340x0_device::subi_l_b, &tms340x0_device::unimpl, &tms340x0_device::callr, &tms340x0_device::unimpl, &tms340x0_device::calla, &tms340x0_device::eint, &tms340x0_device::unimpl, + &tms340x0_device::dsj_a, &tms340x0_device::dsj_b, &tms340x0_device::dsjeq_a, &tms340x0_device::dsjeq_b, &tms340x0_device::dsjne_a, &tms340x0_device::dsjne_b, &tms340x0_device::setc, &tms340x0_device::unimpl, + /* 0x0e00 */ + &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_m_l,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::tfill_xy, + /* 0x0f00 */ + &tms340x0_device::pixblt_l_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_xy,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_l,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_xy,&tms340x0_device::unimpl, + &tms340x0_device::pixblt_b_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_b_xy,&tms340x0_device::unimpl, &tms340x0_device::fill_l, &tms340x0_device::unimpl, &tms340x0_device::fill_xy, &tms340x0_device::unimpl, + /* 0x1000 */ + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + /* 0x1100 */ + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + /* 0x1200 */ + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + /* 0x1300 */ + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, + /* 0x1400 */ + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + /* 0x1500 */ + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + /* 0x1600 */ + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + /* 0x1700 */ + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, + /* 0x1800 */ + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + /* 0x1900 */ + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + /* 0x1a00 */ + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + /* 0x1b00 */ + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, + /* 0x1c00 */ + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + /* 0x1d00 */ + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + /* 0x1e00 */ + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + /* 0x1f00 */ + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, + /* 0x2000 */ + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + /* 0x2100 */ + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + /* 0x2200 */ + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + /* 0x2300 */ + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, + /* 0x2400 */ + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + /* 0x2500 */ + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + /* 0x2600 */ + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + /* 0x2700 */ + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, + /* 0x2800 */ + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + /* 0x2900 */ + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + /* 0x2a00 */ + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + /* 0x2b00 */ + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, + /* 0x2c00 */ + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + /* 0x2d00 */ + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + /* 0x2e00 */ + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + /* 0x2f00 */ + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, + /* 0x3000 */ + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + /* 0x3100 */ + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + /* 0x3200 */ + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + /* 0x3300 */ + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, + /* 0x3400 */ + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + /* 0x3500 */ + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + /* 0x3600 */ + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + /* 0x3700 */ + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, + /* 0x3800 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3900 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3a00 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3b00 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3c00 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3d00 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3e00 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x3f00 */ + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, + /* 0x4000 */ + &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, + &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, + /* 0x4100 */ + &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, + &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, + /* 0x4200 */ + &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, + &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, + /* 0x4300 */ + &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, + &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, + /* 0x4400 */ + &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, + &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, + /* 0x4500 */ + &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, + &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, + /* 0x4600 */ + &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, + &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, + /* 0x4700 */ + &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, + &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, + /* 0x4800 */ + &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, + &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, + /* 0x4900 */ + &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, + &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, + /* 0x4a00 */ + &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, + &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, + /* 0x4b00 */ + &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, + &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, + /* 0x4c00 */ + &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, + &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, + /* 0x4d00 */ + &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, + &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, + /* 0x4e00 */ + &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, + &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, + /* 0x4f00 */ + &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, + &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, + /* 0x5000 */ + &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, + &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, + /* 0x5100 */ + &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, + &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, + /* 0x5200 */ + &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, + &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, + /* 0x5300 */ + &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, + &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, + /* 0x5400 */ + &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, + &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, + /* 0x5500 */ + &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, + &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, + /* 0x5600 */ + &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, + &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, + /* 0x5700 */ + &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, + &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, + /* 0x5800 */ + &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, + &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, + /* 0x5900 */ + &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, + &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, + /* 0x5a00 */ + &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, + &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, + /* 0x5b00 */ + &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, + &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, + /* 0x5c00 */ + &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, + &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, + /* 0x5d00 */ + &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, + &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, + /* 0x5e00 */ + &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, + &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, + /* 0x5f00 */ + &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, + &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, + /* 0x6000 */ + &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, + &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, + /* 0x6100 */ + &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, + &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, + /* 0x6200 */ + &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, + &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, + /* 0x6300 */ + &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, + &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, + /* 0x6400 */ + &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, + &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, + /* 0x6500 */ + &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, + &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, + /* 0x6600 */ + &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, + &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, + /* 0x6700 */ + &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, + &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, + /* 0x6800 */ + &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, + &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, + /* 0x6900 */ + &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, + &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, + /* 0x6a00 */ + &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, + &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, + /* 0x6b00 */ + &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, + &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, + /* 0x6c00 */ + &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, + &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, + /* 0x6d00 */ + &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, + &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, + /* 0x6e00 */ + &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, + &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, + /* 0x6f00 */ + &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, + &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, + /* 0x7000 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7100 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7200 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7300 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7400 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7500 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7600 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7700 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7800 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7900 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7a00 */ + &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, + &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, + /* 0x7b00 */ + &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, + &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, + /* 0x7c00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7d00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x7e00 */ + &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, + &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, + /* 0x7f00 */ + &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, + &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, + /* 0x8000 */ + &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, + &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, + /* 0x8100 */ + &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, + &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, + /* 0x8200 */ + &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, + &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, + /* 0x8300 */ + &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, + &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, + /* 0x8400 */ + &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, + &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, + /* 0x8500 */ + &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, + &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, + /* 0x8600 */ + &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, + &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, + /* 0x8700 */ + &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, + &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, + /* 0x8800 */ + &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, + &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, + /* 0x8900 */ + &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, + &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, + /* 0x8a00 */ + &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, + &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, + /* 0x8b00 */ + &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, + &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, + /* 0x8c00 */ + &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, + &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, + /* 0x8d00 */ + &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, + &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, + /* 0x8e00 */ + &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, + &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, + /* 0x8f00 */ + &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, + &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, + /* 0x9000 */ + &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, + &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, + /* 0x9100 */ + &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, + &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, + /* 0x9200 */ + &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, + &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, + /* 0x9300 */ + &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, + &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, + /* 0x9400 */ + &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, + &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, + /* 0x9500 */ + &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, + &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, + /* 0x9600 */ + &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, + &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, + /* 0x9700 */ + &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, + &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, + /* 0x9800 */ + &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, + &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, + /* 0x9900 */ + &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, + &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, + /* 0x9a00 */ + &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, + &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, + /* 0x9b00 */ + &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, + &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, + /* 0x9c00 */ + &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, + &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, + /* 0x9d00 */ + &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, + &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, + /* 0x9e00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0x9f00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xa000 */ + &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, + &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, + /* 0xa100 */ + &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, + &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, + /* 0xa200 */ + &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, + &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, + /* 0xa300 */ + &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, + &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, + /* 0xa400 */ + &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, + &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, + /* 0xa500 */ + &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, + &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, + /* 0xa600 */ + &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, + &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, + /* 0xa700 */ + &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, + &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, + /* 0xa800 */ + &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, + &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, + /* 0xa900 */ + &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, + &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, + /* 0xaa00 */ + &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, + &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, + /* 0xab00 */ + &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, + &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, + /* 0xac00 */ + &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, + &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, + /* 0xad00 */ + &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, + &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, + /* 0xae00 */ + &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, + &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, + /* 0xaf00 */ + &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, + &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, + /* 0xb000 */ + &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, + &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, + /* 0xb100 */ + &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, + &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, + /* 0xb200 */ + &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, + &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, + /* 0xb300 */ + &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, + &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, + /* 0xb400 */ + &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, + &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, + /* 0xb500 */ + &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, + &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, + /* 0xb600 */ + &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, + &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, + /* 0xb700 */ + &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, + &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, + /* 0xb800 */ + &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, + &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, + /* 0xb900 */ + &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, + &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, + /* 0xba00 */ + &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, + &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, + /* 0xbb00 */ + &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, + &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, + /* 0xbc00 */ + &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, + &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, + /* 0xbd00 */ + &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, + &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, + /* 0xbe00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xbf00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xc000 */ + &tms340x0_device::j_UC_0, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, + &tms340x0_device::j_UC_8, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, + /* 0xc100 */ + &tms340x0_device::j_P_0, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, + &tms340x0_device::j_P_8, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, + /* 0xc200 */ + &tms340x0_device::j_LS_0, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, + &tms340x0_device::j_LS_8, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, + /* 0xc300 */ + &tms340x0_device::j_HI_0, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, + &tms340x0_device::j_HI_8, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, + /* 0xc400 */ + &tms340x0_device::j_LT_0, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, + &tms340x0_device::j_LT_8, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, + /* 0xc500 */ + &tms340x0_device::j_GE_0, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, + &tms340x0_device::j_GE_8, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, + /* 0xc600 */ + &tms340x0_device::j_LE_0, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, + &tms340x0_device::j_LE_8, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, + /* 0xc700 */ + &tms340x0_device::j_GT_0, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, + &tms340x0_device::j_GT_8, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, + /* 0xc800 */ + &tms340x0_device::j_C_0, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, + &tms340x0_device::j_C_8, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, + /* 0xc900 */ + &tms340x0_device::j_NC_0, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, + &tms340x0_device::j_NC_8, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, + /* 0xca00 */ + &tms340x0_device::j_EQ_0, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, + &tms340x0_device::j_EQ_8, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, + /* 0xcb00 */ + &tms340x0_device::j_NE_0, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, + &tms340x0_device::j_NE_8, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, + /* 0xcc00 */ + &tms340x0_device::j_V_0, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, + &tms340x0_device::j_V_8, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, + /* 0xcd00 */ + &tms340x0_device::j_NV_0, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, + &tms340x0_device::j_NV_8, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, + /* 0xce00 */ + &tms340x0_device::j_N_0, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, + &tms340x0_device::j_N_8, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, + /* 0xcf00 */ + &tms340x0_device::j_NN_0, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, + &tms340x0_device::j_NN_8, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, + /* 0xd000 */ + &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, + &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, + /* 0xd100 */ + &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, + &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, + /* 0xd200 */ + &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, + &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, + /* 0xd300 */ + &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, + &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, + /* 0xd400 */ + &tms340x0_device::move0_a_ni_a,&tms340x0_device::move0_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xd500 */ + &tms340x0_device::exgf0_a, &tms340x0_device::exgf0_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xd600 */ + &tms340x0_device::move1_a_ni_a,&tms340x0_device::move1_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xd700 */ + &tms340x0_device::exgf1_a, &tms340x0_device::exgf1_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xd800 */ + &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xd900 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xda00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xdb00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xdc00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xdd00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xde00 */ + &tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xdf00 */ + &tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xe000 */ + &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, + &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, + /* 0xe100 */ + &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, + &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, + /* 0xe200 */ + &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, + &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, + /* 0xe300 */ + &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, + &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, + /* 0xe400 */ + &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, + &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, + /* 0xe500 */ + &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, + &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, + /* 0xe600 */ + &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, + &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, + /* 0xe700 */ + &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, + &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, + /* 0xe800 */ + &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, + &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, + /* 0xe900 */ + &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, + &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, + /* 0xea00 */ + &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, + &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, + /* 0xeb00 */ + &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, + &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, + /* 0xec00 */ + &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, + &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, + /* 0xed00 */ + &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, + &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, + /* 0xee00 */ + &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, + &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, + /* 0xef00 */ + &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, + &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, + /* 0xf000 */ + &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, + &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, + /* 0xf100 */ + &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, + &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, + /* 0xf200 */ + &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, + &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, + /* 0xf300 */ + &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, + &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, + /* 0xf400 */ + &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, + &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, + /* 0xf500 */ + &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, + &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, + /* 0xf600 */ + &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, + &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, + /* 0xf700 */ + &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, + &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, + /* 0xf800 */ + &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, + &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, + /* 0xf900 */ + &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, + &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, + /* 0xfa00 */ + &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, + &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, + /* 0xfb00 */ + &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, + &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, + /* 0xfc00 */ + &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, + &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, + /* 0xfd00 */ + &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, + &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, + /* 0xfe00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + /* 0xff00 */ + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, + &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl +}; diff --git a/mame/tm34010/dis34010.c b/mame/tm34010/dis34010.c new file mode 100644 index 00000000..19e3338a --- /dev/null +++ b/mame/tm34010/dis34010.c @@ -0,0 +1,115 @@ +// license:BSD-3-Clause +// copyright-holders:Zsolt Vasvari +/* This program is based on DIS68k by Aaron Giles */ + +#include "emu.h" + +static UINT8 *filebuf; +static UINT32 offset; + +#define STANDALONE +#include "34010dsm.c" + + +static const char *const Options[]= +{ + "begin","end","offset",0 +}; + +static void usage (void) +{ + printf ("Usage: DIS34010 [options] \n" + "Available options are:\n" + " -begin - Specify begin offset in file to disassemble in bits [0]\n" + " -end - Specify end offset in file to disassemble in bits [none]\n" + " -offset - Specify address to load program in bits [0]\n" + "All values should be entered in hexadecimal\n"); + exit (1); +} + +int main (int argc,char *argv[]) +{ + UINT8 i,j,n; + char *filename=0,buf[80]; + FILE *f; + UINT32 begin=0,end=(UINT32)-1,filelen,len,pc; + printf ("DIS34010\n" + "Copyright Zsolt Vasvari/Aaron Giles\n"); + + for (i=1,n=0;iargc) usage(); + begin=strtoul(argv[i],0,16) >> 3; + break; + case 1: ++i; if (i>argc) usage(); + end=strtoul(argv[i],0,16) >> 3; + break; + case 2: ++i; if (i>argc) usage(); + offset=strtoul(argv[i],0,16) >> 3; + break; + default: usage(); + } + } + } + + if (!filename) + { + usage(); + return 1; + } + f=fopen (filename,"rb"); + if (!f) + { + printf ("Unable to open %s\n",filename); + return 2; + } + fseek (f,0,SEEK_END); + filelen=ftell (f); + fseek (f,begin,SEEK_SET); + len=(filelen>end)? (end-begin+1):(filelen-begin); + filebuf=malloc(len+16); + if (!filebuf) + { + printf ("Memory allocation error\n"); + fclose (f); + return 3; + } + memset (filebuf,0,len+16); + if (fread(filebuf,1,len,f)!=len) + { + printf ("Read error\n"); + fclose (f); + free (filebuf); + return 4; + } + fclose (f); + pc=0; + while (pc>3; + + printf ("%08X: ",(pc+offset) << 3); + for (j=0;j; +const device_type TMS34020 = &device_creator; +#endif + +/*************************************************************************** + GLOBAL VARIABLES +***************************************************************************/ + +#if 0 +tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__) + , device_video_interface(mconfig, *this) + , m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3) + , m_halt_on_reset(FALSE) + , m_pixclock(0) + , m_pixperclock(0) + , m_output_int_cb(*this) +{ +} + + +tms34010_device::tms34010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : tms340x0_device(mconfig, TMS34010, "TMS34010", tag, owner, clock, "tms34010") +{ + m_is_34020 = 0; +} + + +tms34020_device::tms34020_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : tms340x0_device(mconfig, TMS34020, "TMS34020", tag, owner, clock, "tms34020") +{ + m_is_34020 = 1; +} +#endif + +#include "34010ops.h" + + +/*************************************************************************** + MACROS +***************************************************************************/ + +/* status register definitions */ +#define STBIT_N (1 << 31) +#define STBIT_C (1 << 30) +#define STBIT_Z (1 << 29) +#define STBIT_V (1 << 28) +#define STBIT_P (1 << 25) +#define STBIT_IE (1 << 21) +#define STBIT_FE1 (1 << 11) +#define STBITS_F1 (0x1f << 6) +#define STBIT_FE0 (1 << 5) +#define STBITS_F0 (0x1f << 0) + +/* register definitions and shortcuts */ +#define N_FLAG() (m_st & STBIT_N) +#define Z_FLAG() (m_st & STBIT_Z) +#define C_FLAG() (m_st & STBIT_C) +#define V_FLAG() (m_st & STBIT_V) +#define P_FLAG() (m_st & STBIT_P) +#define IE_FLAG() (m_st & STBIT_IE) +#define FE0_FLAG() (m_st & STBIT_FE0) +#define FE1_FLAG() (m_st & STBIT_FE1) + +/* register file access */ +#define AREG(i) (m_regs[i].reg) +#define AREG_XY(i) (m_regs[i].xy) +#define AREG_X(i) (m_regs[i].xy.x) +#define AREG_Y(i) (m_regs[i].xy.y) +#define BREG(i) (m_regs[30 - (i)].reg) +#define BREG_XY(i) (m_regs[30 - (i)].xy) +#define BREG_X(i) (m_regs[30 - (i)].xy.x) +#define BREG_Y(i) (m_regs[30 - (i)].xy.y) +#define SP() AREG(15) +#define FW(i) ((m_st >> (i ? 6 : 0)) & 0x1f) +#define FWEX(i) ((m_st >> (i ? 6 : 0)) & 0x3f) + +/* opcode decode helpers */ +#define SRCREG(O) (((O) >> 5) & 0x0f) +#define DSTREG(O) ((O) & 0x0f) +#define SKIP_WORD() (m_pc += (2 << 3)) +#define SKIP_LONG() (m_pc += (4 << 3)) +#define PARAM_K(O) (((O) >> 5) & 0x1f) +#define PARAM_N(O) ((O) & 0x1f) +#define PARAM_REL8(O) ((INT8)(O)) + +/* memory I/O */ +#define WFIELD0(a,b) (this->*s_wfield_functions[FW(0)])(a,b) +#define WFIELD1(a,b) (this->*s_wfield_functions[FW(1)])(a,b) +#define RFIELD0(a) (this->*s_rfield_functions[FWEX(0)])(a) +#define RFIELD1(a) (this->*s_rfield_functions[FWEX(1)])(a) +#define WPIXEL(a,b) (this->*m_pixel_write)(a,b) +#define RPIXEL(a) (this->*m_pixel_read)(a) + +/* Implied Operands */ +#define SADDR() BREG(0) +#define SADDR_X() BREG_X(0) +#define SADDR_Y() BREG_Y(0) +#define SADDR_XY() BREG_XY(0) +#define SPTCH() BREG(1) +#define DADDR() BREG(2) +#define DADDR_X() BREG_X(2) +#define DADDR_Y() BREG_Y(2) +#define DADDR_XY() BREG_XY(2) +#define DPTCH() BREG(3) +#define OFFSET() BREG(4) +#define WSTART_X() BREG_X(5) +#define WSTART_Y() BREG_Y(5) +#define WEND_X() BREG_X(6) +#define WEND_Y() BREG_Y(6) +#define DYDX_X() BREG_X(7) +#define DYDX_Y() BREG_Y(7) +#define COLOR0() BREG(8) +#define COLOR1() BREG(9) +#define COUNT() BREG(10) +#define INC1_X() BREG_X(11) +#define INC1_Y() BREG_Y(11) +#define INC2_X() BREG_X(12) +#define INC2_Y() BREG_Y(12) +#define PATTRN() BREG(13) +#define TEMP() BREG(14) + +/* I/O registers */ +#define WINDOW_CHECKING() ((IOREG(REG_CONTROL) >> 6) & 0x03) + + + +/*************************************************************************** + INLINE SHORTCUTS +***************************************************************************/ + +/* Break up Status Register into indiviual flags */ +inline void tms340x0_device::SET_ST(UINT32 st) +{ + m_st = st; + /* interrupts might have been enabled, check it */ + check_interrupt(); +} + +/* Intialize Status to 0x0010 */ +inline void tms340x0_device::RESET_ST() +{ + SET_ST(0x00000010); +} + +/* shortcuts for reading opcodes */ +inline UINT32 tms340x0_device::ROPCODE() +{ + UINT32 pc = TOBYTE(m_pc); + m_pc += 2 << 3; + return m_direct->read_decrypted_word(pc); +} + +inline INT16 tms340x0_device::PARAM_WORD() +{ + UINT32 pc = TOBYTE(m_pc); + m_pc += 2 << 3; + return m_direct->read_raw_word(pc); +} + +inline INT32 tms340x0_device::PARAM_LONG() +{ + UINT32 pc = TOBYTE(m_pc); + m_pc += 4 << 3; + return (UINT16)m_direct->read_raw_word(pc) | (m_direct->read_raw_word(pc + 2) << 16); +} + +inline INT16 tms340x0_device::PARAM_WORD_NO_INC() +{ + return m_direct->read_raw_word(TOBYTE(m_pc)); +} + +inline INT32 tms340x0_device::PARAM_LONG_NO_INC() +{ + UINT32 pc = TOBYTE(m_pc); + return (UINT16)m_direct->read_raw_word(pc) | (m_direct->read_raw_word(pc + 2) << 16); +} + +/* read memory byte */ +inline UINT32 tms340x0_device::RBYTE(offs_t offset) +{ + UINT32 ret; + RFIELDMAC_8(); + return ret; +} + +/* write memory byte */ +inline void tms340x0_device::WBYTE(offs_t offset, UINT32 data) +{ + WFIELDMAC_8(); +} + +/* read memory long */ +inline UINT32 tms340x0_device::RLONG(offs_t offset) +{ + RFIELDMAC_32(); +} + +/* write memory long */ +inline void tms340x0_device::WLONG(offs_t offset, UINT32 data) +{ + WFIELDMAC_32(); +} + +/* pushes/pops a value from the stack */ +inline void tms340x0_device::PUSH(UINT32 data) +{ + SP() -= 0x20; + WLONG(SP(), data); +} + +inline INT32 tms340x0_device::POP() +{ + INT32 ret = RLONG(SP()); + SP() += 0x20; + return ret; +} + + + +/*************************************************************************** + PIXEL READS +***************************************************************************/ + +#define RP(m1,m2) \ + /* TODO: Plane masking */ \ + return (TMS34010_RDMEM_WORD(TOBYTE(offset & 0xfffffff0)) >> (offset & m1)) & m2; + +UINT32 tms340x0_device::read_pixel_1(offs_t offset) { RP(0x0f,0x01) } +UINT32 tms340x0_device::read_pixel_2(offs_t offset) { RP(0x0e,0x03) } +UINT32 tms340x0_device::read_pixel_4(offs_t offset) { RP(0x0c,0x0f) } +UINT32 tms340x0_device::read_pixel_8(offs_t offset) { RP(0x08,0xff) } +UINT32 tms340x0_device::read_pixel_16(offs_t offset) +{ + /* TODO: Plane masking */ + return TMS34010_RDMEM_WORD(TOBYTE(offset & 0xfffffff0)); +} +UINT32 tms340x0_device::read_pixel_32(offs_t offset) +{ + /* TODO: Plane masking */ + return TMS34010_RDMEM_DWORD(TOBYTE(offset & 0xffffffe0)); +} + +/* Shift register read */ +UINT32 tms340x0_device::read_pixel_shiftreg(offs_t offset) +{ + m_to_shiftreg_cb(*m_program, offset, &m_shiftreg[0]); +#if 0 + if (!m_to_shiftreg_cb.isnull()) + m_to_shiftreg_cb(*m_program, offset, &m_shiftreg[0]); + else + fatalerror("To ShiftReg function not set. PC = %08X\n", m_pc); +#endif + return m_shiftreg[0]; +} + + + +/*************************************************************************** + PIXEL WRITES +***************************************************************************/ + +/* No Raster Op + No Transparency */ +#define WP(m1,m2) \ + UINT32 a = TOBYTE(offset & 0xfffffff0); \ + UINT32 pix = TMS34010_RDMEM_WORD(a); \ + UINT32 shiftcount = offset & m1; \ + \ + /* TODO: plane masking */ \ + data &= m2; \ + pix = (pix & ~(m2 << shiftcount)) | (data << shiftcount); \ + TMS34010_WRMEM_WORD(a, pix); + +/* No Raster Op + Transparency */ +#define WP_T(m1,m2) \ + /* TODO: plane masking */ \ + data &= m2; \ + if (data) \ + { \ + UINT32 a = TOBYTE(offset & 0xfffffff0); \ + UINT32 pix = TMS34010_RDMEM_WORD(a); \ + UINT32 shiftcount = offset & m1; \ + \ + /* TODO: plane masking */ \ + pix = (pix & ~(m2 << shiftcount)) | (data << shiftcount); \ + TMS34010_WRMEM_WORD(a, pix); \ + } +/* Raster Op + No Transparency */ +#define WP_R(m1,m2) \ + UINT32 a = TOBYTE(offset & 0xfffffff0); \ + UINT32 pix = TMS34010_RDMEM_WORD(a); \ + UINT32 shiftcount = offset & m1; \ + \ + /* TODO: plane masking */ \ + data = (this->*m_raster_op)(data & m2, (pix >> shiftcount) & m2) & m2; \ + pix = (pix & ~(m2 << shiftcount)) | (data << shiftcount); \ + TMS34010_WRMEM_WORD(a, pix); + +/* Raster Op + Transparency */ +#define WP_R_T(m1,m2) \ + UINT32 a = TOBYTE(offset & 0xfffffff0); \ + UINT32 pix = TMS34010_RDMEM_WORD(a); \ + UINT32 shiftcount = offset & m1; \ + \ + /* TODO: plane masking */ \ + data = (this->*m_raster_op)(data & m2, (pix >> shiftcount) & m2) & m2; \ + if (data) \ + { \ + pix = (pix & ~(m2 << shiftcount)) | (data << shiftcount); \ + TMS34010_WRMEM_WORD(a, pix); \ + } + +/* No Raster Op + No Transparency */ +void tms340x0_device::write_pixel_1(offs_t offset, UINT32 data) { WP(0x0f, 0x01); } +void tms340x0_device::write_pixel_2(offs_t offset, UINT32 data) { WP(0x0e, 0x03); } +void tms340x0_device::write_pixel_4(offs_t offset, UINT32 data) { WP(0x0c, 0x0f); } +void tms340x0_device::write_pixel_8(offs_t offset, UINT32 data) { WP(0x08, 0xff); } +void tms340x0_device::write_pixel_16(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + TMS34010_WRMEM_WORD(TOBYTE(offset & 0xfffffff0), data); +} +void tms340x0_device::write_pixel_32(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + TMS34010_WRMEM_WORD(TOBYTE(offset & 0xffffffe0), data); +} + +/* No Raster Op + Transparency */ +void tms340x0_device::write_pixel_t_1(offs_t offset, UINT32 data) { WP_T(0x0f, 0x01); } +void tms340x0_device::write_pixel_t_2(offs_t offset, UINT32 data) { WP_T(0x0e, 0x03); } +void tms340x0_device::write_pixel_t_4(offs_t offset, UINT32 data) { WP_T(0x0c, 0x0f); } +void tms340x0_device::write_pixel_t_8(offs_t offset, UINT32 data) { WP_T(0x08, 0xff); } +void tms340x0_device::write_pixel_t_16(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + if (data) + TMS34010_WRMEM_WORD(TOBYTE(offset & 0xfffffff0), data); +} +void tms340x0_device::write_pixel_t_32(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + if (data) + TMS34010_WRMEM_DWORD(TOBYTE(offset & 0xffffffe0), data); +} + +/* Raster Op + No Transparency */ +void tms340x0_device::write_pixel_r_1(offs_t offset, UINT32 data) { WP_R(0x0f, 0x01); } +void tms340x0_device::write_pixel_r_2(offs_t offset, UINT32 data) { WP_R(0x0e, 0x03); } +void tms340x0_device::write_pixel_r_4(offs_t offset, UINT32 data) { WP_R(0x0c, 0x0f); } +void tms340x0_device::write_pixel_r_8(offs_t offset, UINT32 data) { WP_R(0x08, 0xff); } +void tms340x0_device::write_pixel_r_16(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + UINT32 a = TOBYTE(offset & 0xfffffff0); + TMS34010_WRMEM_WORD(a, (this->*m_raster_op)(data, TMS34010_RDMEM_WORD(a))); +} +void tms340x0_device::write_pixel_r_32(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + UINT32 a = TOBYTE(offset & 0xffffffe0); + TMS34010_WRMEM_DWORD(a, (this->*m_raster_op)(data, TMS34010_RDMEM_DWORD(a))); +} + +/* Raster Op + Transparency */ +void tms340x0_device::write_pixel_r_t_1(offs_t offset, UINT32 data) { WP_R_T(0x0f,0x01); } +void tms340x0_device::write_pixel_r_t_2(offs_t offset, UINT32 data) { WP_R_T(0x0e,0x03); } +void tms340x0_device::write_pixel_r_t_4(offs_t offset, UINT32 data) { WP_R_T(0x0c,0x0f); } +void tms340x0_device::write_pixel_r_t_8(offs_t offset, UINT32 data) { WP_R_T(0x08,0xff); } +void tms340x0_device::write_pixel_r_t_16(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + UINT32 a = TOBYTE(offset & 0xfffffff0); + data = (this->*m_raster_op)(data, TMS34010_RDMEM_WORD(a)); + + if (data) + TMS34010_WRMEM_WORD(a, data); +} +void tms340x0_device::write_pixel_r_t_32(offs_t offset, UINT32 data) +{ + /* TODO: plane masking */ + UINT32 a = TOBYTE(offset & 0xffffffe0); + data = (this->*m_raster_op)(data, TMS34010_RDMEM_DWORD(a)); + + if (data) + TMS34010_WRMEM_DWORD(a, data); +} + +/* Shift register write */ +void tms340x0_device::write_pixel_shiftreg(offs_t offset, UINT32 data) +{ + m_from_shiftreg_cb(*m_program, offset, &m_shiftreg[0]); +#if 0 + if (!m_from_shiftreg_cb.isnull()) + m_from_shiftreg_cb(*m_program, offset, &m_shiftreg[0]); + else + fatalerror("From ShiftReg function not set. PC = %08X\n", m_pc); +#endif +} + + + +/*************************************************************************** + RASTER OPS +***************************************************************************/ + +/* Raster operations */ +UINT32 tms340x0_device::raster_op_1(UINT32 newpix, UINT32 oldpix) { return newpix & oldpix; } +UINT32 tms340x0_device::raster_op_2(UINT32 newpix, UINT32 oldpix) { return newpix & ~oldpix; } +UINT32 tms340x0_device::raster_op_3(UINT32 newpix, UINT32 oldpix) { return 0; } +UINT32 tms340x0_device::raster_op_4(UINT32 newpix, UINT32 oldpix) { return newpix | ~oldpix; } +UINT32 tms340x0_device::raster_op_5(UINT32 newpix, UINT32 oldpix) { return ~(newpix ^ oldpix); } +UINT32 tms340x0_device::raster_op_6(UINT32 newpix, UINT32 oldpix) { return ~oldpix; } +UINT32 tms340x0_device::raster_op_7(UINT32 newpix, UINT32 oldpix) { return ~(newpix | oldpix); } +UINT32 tms340x0_device::raster_op_8(UINT32 newpix, UINT32 oldpix) { return newpix | oldpix; } +UINT32 tms340x0_device::raster_op_9(UINT32 newpix, UINT32 oldpix) { return oldpix; } +UINT32 tms340x0_device::raster_op_10(UINT32 newpix, UINT32 oldpix) { return newpix ^ oldpix; } +UINT32 tms340x0_device::raster_op_11(UINT32 newpix, UINT32 oldpix) { return ~newpix & oldpix; } +UINT32 tms340x0_device::raster_op_12(UINT32 newpix, UINT32 oldpix) { return 0xffff; } +UINT32 tms340x0_device::raster_op_13(UINT32 newpix, UINT32 oldpix) { return ~newpix | oldpix; } +UINT32 tms340x0_device::raster_op_14(UINT32 newpix, UINT32 oldpix) { return ~(newpix & oldpix); } +UINT32 tms340x0_device::raster_op_15(UINT32 newpix, UINT32 oldpix) { return ~newpix; } +UINT32 tms340x0_device::raster_op_16(UINT32 newpix, UINT32 oldpix) { return newpix + oldpix; } +UINT32 tms340x0_device::raster_op_17(UINT32 newpix, UINT32 oldpix) +{ + UINT32 max = (UINT32)0xffffffff >> (32 - IOREG(REG_PSIZE)); + UINT32 res = newpix + oldpix; + return (res > max) ? max : res; +} +UINT32 tms340x0_device::raster_op_18(UINT32 newpix, UINT32 oldpix) { return oldpix - newpix; } +UINT32 tms340x0_device::raster_op_19(UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? oldpix - newpix : 0; } +UINT32 tms340x0_device::raster_op_20(UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? oldpix : newpix; } +UINT32 tms340x0_device::raster_op_21(UINT32 newpix, UINT32 oldpix) { return (oldpix > newpix) ? newpix : oldpix; } + + + +/*************************************************************************** + OPCODE TABLE & IMPLEMENTATIONS +***************************************************************************/ + +#include "34010fld.c" + +/* includes the static function prototypes and the master opcode table */ +#include "34010tbl.c" + +/* includes the actual opcode implementations */ +#include "34010ops.c" +#include "34010gfx.c" + + + +/*************************************************************************** + Internal interrupt check +****************************************************************************/ + +/* Generate pending interrupts. */ +void tms340x0_device::check_interrupt() +{ + int vector = 0; + int irqline = -1; + int irq; + + /* if we're not actively executing, skip it */ + if (!m_executing) + return; + + /* check for NMI first */ + if (IOREG(REG_HSTCTLH) & 0x0100) + { + LOG(("TMS34010 '%s' takes NMI\n", tag())); + + /* ack the NMI */ + IOREG(REG_HSTCTLH) &= ~0x0100; + + /* handle NMI mode bit */ + if (!(IOREG(REG_HSTCTLH) & 0x0200)) + { + PUSH(m_pc); + PUSH(m_st); + } + + /* leap to the vector */ + RESET_ST(); + m_pc = RLONG(0xfffffee0); + COUNT_CYCLES(16); + return; + } + + /* early out if everything else is disabled */ + irq = IOREG(REG_INTPEND) & IOREG(REG_INTENB); + if (!IE_FLAG() || !irq) + return; + + /* host interrupt */ + if (irq & TMS34010_HI) + { + LOG(("TMS34010 '%s' takes HI\n", tag())); + vector = 0xfffffec0; + } + + /* display interrupt */ + else if (irq & TMS34010_DI) + { + LOG(("TMS34010 '%s' takes DI\n", tag())); + vector = 0xfffffea0; + } + + /* window violation interrupt */ + else if (irq & TMS34010_WV) + { + LOG(("TMS34010 '%s' takes WV\n", tag())); + vector = 0xfffffe80; + } + + /* external 1 interrupt */ + else if (irq & TMS34010_INT1) + { + LOG(("TMS34010 '%s' takes INT1\n", tag())); + vector = 0xffffffc0; + irqline = 0; + } + + /* external 2 interrupt */ + else if (irq & TMS34010_INT2) + { + LOG(("TMS34010 '%s' takes INT2\n", tag())); + vector = 0xffffffa0; + irqline = 1; + } + + /* if we took something, generate it */ + if (vector) + { + PUSH(m_pc); + PUSH(m_st); + RESET_ST(); + m_pc = RLONG(vector); + COUNT_CYCLES(16); + + /* call the callback for externals */ + if (irqline >= 0) { + write_log("tms interrupt\n"); + standard_irq_callback(irqline); + } + } +} + + + +/*************************************************************************** + Reset the CPU emulation +***************************************************************************/ + +void tms340x0_device::device_start() +{ +#if 0 + m_scanline_ind16_cb.bind_relative_to(*owner()); + m_scanline_rgb32_cb.bind_relative_to(*owner()); + m_output_int_cb.resolve(); + m_to_shiftreg_cb.bind_relative_to(*owner()); + m_from_shiftreg_cb.bind_relative_to(*owner()); +#endif + + m_external_host_access = FALSE; + +#if 0 + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + + /* set up the state table */ + { + state_add(TMS34010_PC, "PC", m_pc); + state_add(STATE_GENPC, "GENPC", m_pc).noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow(); + state_add(TMS34010_SP, "SP", m_regs[15].reg); + state_add(STATE_GENSP, "GENSP", m_regs[15].reg).noshow(); + state_add(TMS34010_ST, "ST", m_st); + state_add(STATE_GENFLAGS, "GENFLAGS", m_st).noshow().formatstr("%18s"); + + std::string tempstr; + for (int regnum = 0; regnum < 15; regnum++) + { + state_add(TMS34010_A0 + regnum, strformat(tempstr, "A%d", regnum).c_str(), m_regs[regnum].reg); + } + for (int regnum = 0; regnum < 15; regnum++) + { + state_add(TMS34010_B0 + regnum, strformat(tempstr, "B%d", regnum).c_str(), m_regs[30 - regnum].reg); + } + } + + /* allocate a scanline timer and set it to go off at the start */ + m_scantimer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tms340x0_device::scanline_callback), this)); + m_scantimer->adjust(attotime::zero); + + save_item(NAME(m_pc)); + save_item(NAME(m_st)); + save_item(NAME(m_reset_deferred)); + save_item(NAME(m_shiftreg)); + save_item(NAME(m_IOregs)); + save_item(NAME(m_convsp)); + save_item(NAME(m_convdp)); + save_item(NAME(m_convmp)); + save_item(NAME(m_pixelshift)); + save_item(NAME(m_gfxcycles)); + save_pointer(NAME(&m_regs[0].reg), ARRAY_LENGTH(m_regs)); + machine().save().register_postload(save_prepost_delegate(FUNC(tms340x0_device::tms34010_state_postload), this)); + + m_icountptr = &m_icount; +#endif +} + +void tms340x0_device::device_reset() +{ + m_ppc = 0; + m_st = 0; + m_pixel_write = NULL; + m_pixel_read = NULL; + m_raster_op = NULL; + m_pixel_op = NULL; + m_pixel_op_timing = 0; + m_convsp = 0; + m_convdp = 0; + m_convmp = 0; + m_gfxcycles = 0; + m_pixelshift = 0; + m_hblank_stable = 0; + m_external_host_access = 0; + m_executing = 0; + memset(m_regs, 0, sizeof(m_regs)); + memset(m_IOregs, 0, sizeof(m_IOregs)); + memset(m_shiftreg, 0, sizeof(m_shiftreg)); + + /* fetch the initial PC and reset the state */ + m_pc = RLONG(0xffffffe0) & 0xfffffff0; + RESET_ST(); + m_halt_on_reset = true; + m_pixperclock = 16; + + /* HALT the CPU if requested, and remember to re-read the starting PC */ + /* the first time we are run */ + m_reset_deferred = m_halt_on_reset; + + if (m_reset_deferred) + { + io_register_w(*m_program, REG_HSTCTLH, 0x8000, 0xffff); + } +} + +/*************************************************************************** + Set IRQ line state +***************************************************************************/ + +void tms340x0_device::execute_set_input(int inputnum, int state) +{ + LOG(("TMS34010 '%s' set irq line %d state %d\n", tag(), inputnum, state)); + + /* set the pending interrupt */ + switch (inputnum) + { + case 0: + if (state != CLEAR_LINE) + IOREG(REG_INTPEND) |= TMS34010_INT1; + else + IOREG(REG_INTPEND) &= ~TMS34010_INT1; + break; + + case 1: + if (state != CLEAR_LINE) + IOREG(REG_INTPEND) |= TMS34010_INT2; + else + IOREG(REG_INTPEND) &= ~TMS34010_INT2; + break; + } +} + + + +/*************************************************************************** + Generate internal interrupt +***************************************************************************/ + +TIMER_CALLBACK_MEMBER( tms340x0_device::internal_interrupt_callback ) +{ + int type = param; + + /* call through to the CPU to generate the int */ + IOREG(REG_INTPEND) |= type; + LOG(("TMS34010 '%s' set internal interrupt $%04x\n", tag(), type)); + + check_interrupt(); + + /* generate triggers so that spin loops can key off them */ +// signal_interrupt_trigger(); + return 0; +} + + + +/*************************************************************************** + Execute +***************************************************************************/ + +void tms340x0_device::execute_run() +{ + /* Get out if CPU is halted. Absolutely no interrupts must be taken!!! */ + if (IOREG(REG_HSTCTLH) & 0x8000) + { + m_icount = 0; + return; + } + /* if the CPU's reset was deferred, do it now */ + if (m_reset_deferred) + { + m_reset_deferred = FALSE; + m_pc = RLONG(0xffffffe0); + write_log("TMS started, PC=%08x\n", m_pc); + } + + /* check interrupts first */ + m_executing = TRUE; + check_interrupt(); +#if 0 + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) +#endif + { + do + { + UINT16 op; + m_ppc = m_pc; + op = ROPCODE(); + (this->*s_opcode_table[op >> 4])(op); + } while (m_icount > 0); + } +#if 0 + else + { + do + { + UINT16 op; + debugger_instruction_hook(this, m_pc); + m_ppc = m_pc; + op = ROPCODE(); + (this->*s_opcode_table[op >> 4])(op); + } while (m_icount > 0); + } +#endif + m_executing = FALSE; +} + + + +/*************************************************************************** + PIXEL OPS +***************************************************************************/ + +const tms340x0_device::pixel_write_func tms340x0_device::s_pixel_write_ops[4][6] = +{ + { &tms340x0_device::write_pixel_1, &tms340x0_device::write_pixel_2, &tms340x0_device::write_pixel_4, &tms340x0_device::write_pixel_8, &tms340x0_device::write_pixel_16, &tms340x0_device::write_pixel_32 }, + { &tms340x0_device::write_pixel_r_1, &tms340x0_device::write_pixel_r_2, &tms340x0_device::write_pixel_r_4, &tms340x0_device::write_pixel_r_8, &tms340x0_device::write_pixel_r_16, &tms340x0_device::write_pixel_r_32 }, + { &tms340x0_device::write_pixel_t_1, &tms340x0_device::write_pixel_t_2, &tms340x0_device::write_pixel_t_4, &tms340x0_device::write_pixel_t_8, &tms340x0_device::write_pixel_t_16, &tms340x0_device::write_pixel_t_32 }, + { &tms340x0_device::write_pixel_r_t_1, &tms340x0_device::write_pixel_r_t_2, &tms340x0_device::write_pixel_r_t_4, &tms340x0_device::write_pixel_r_t_8, &tms340x0_device::write_pixel_r_t_16, &tms340x0_device::write_pixel_r_t_32 } +}; + +const tms340x0_device::pixel_read_func tms340x0_device::s_pixel_read_ops[6] = +{ + &tms340x0_device::read_pixel_1, &tms340x0_device::read_pixel_2, &tms340x0_device::read_pixel_4, &tms340x0_device::read_pixel_8, &tms340x0_device::read_pixel_16, &tms340x0_device::read_pixel_32 +}; + + +void tms340x0_device::set_pixel_function() +{ + UINT32 i1,i2; + + if (IOREG(REG_DPYCTL) & 0x0800) + { + /* Shift Register Transfer */ + m_pixel_write = &tms340x0_device::write_pixel_shiftreg; + m_pixel_read = &tms340x0_device::read_pixel_shiftreg; + return; + } + + switch (IOREG(REG_PSIZE)) + { + default: + case 0x01: i2 = 0; break; + case 0x02: i2 = 1; break; + case 0x04: i2 = 2; break; + case 0x08: i2 = 3; break; + case 0x10: i2 = 4; break; + case 0x20: i2 = 5; break; + } + + if (IOREG(REG_CONTROL) & 0x20) + i1 = m_raster_op ? 3 : 2; + else + i1 = m_raster_op ? 1 : 0; + + m_pixel_write = s_pixel_write_ops[i1][i2]; + m_pixel_read = s_pixel_read_ops [i2]; +} + + + +/*************************************************************************** + RASTER OPS +***************************************************************************/ + +const tms340x0_device::raster_op_func tms340x0_device::s_raster_ops[32] = +{ + NULL, &tms340x0_device::raster_op_1 , &tms340x0_device::raster_op_2 , &tms340x0_device::raster_op_3, + &tms340x0_device::raster_op_4 , &tms340x0_device::raster_op_5 , &tms340x0_device::raster_op_6 , &tms340x0_device::raster_op_7, + &tms340x0_device::raster_op_8 , &tms340x0_device::raster_op_9 , &tms340x0_device::raster_op_10, &tms340x0_device::raster_op_11, + &tms340x0_device::raster_op_12, &tms340x0_device::raster_op_13, &tms340x0_device::raster_op_14, &tms340x0_device::raster_op_15, + &tms340x0_device::raster_op_16, &tms340x0_device::raster_op_17, &tms340x0_device::raster_op_18, &tms340x0_device::raster_op_19, + &tms340x0_device::raster_op_20, &tms340x0_device::raster_op_21, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + + +void tms340x0_device::set_raster_op() +{ + m_raster_op = s_raster_ops[(IOREG(REG_CONTROL) >> 10) & 0x1f]; +} + + + +/*************************************************************************** + VIDEO TIMING HELPERS +***************************************************************************/ + +TIMER_CALLBACK_MEMBER( tms340x0_device::scanline_callback ) +{ + int vsblnk, veblnk, vtotal; + int vcount = param; + int enabled; + int master; + + /* fetch the core timing parameters */ + const rectangle ¤t_visarea = m_screen->visible_area(); + enabled = SMART_IOREG(DPYCTL) & 0x8000; + master = (m_is_34020 || (SMART_IOREG(DPYCTL) & 0x2000)); + vsblnk = SMART_IOREG(VSBLNK); + veblnk = SMART_IOREG(VEBLNK); + vtotal = SMART_IOREG(VTOTAL); + if (!master) + { + vtotal = MIN(m_screen->height() - 1, vtotal); + vcount = m_screen->vpos(); + } + + /* update the VCOUNT */ + SMART_IOREG(VCOUNT) = vcount; + + /* if we match the display interrupt scanline, signal an interrupt */ + if (enabled && vcount == SMART_IOREG(DPYINT)) + { + /* generate the display interrupt signal */ + internal_interrupt_callback(NULL, TMS34010_DI); + } + + /* at the start of VBLANK, load the starting display address */ + if (vcount == vsblnk) + { + /* 34010 loads DPYADR with DPYSTRT, and inverts if the origin is 0 */ + if (!m_is_34020) + { + IOREG(REG_DPYADR) = IOREG(REG_DPYSTRT); + //LOG(("Start of VBLANK, DPYADR = %04X\n", IOREG(REG_DPYADR))); + } + + /* 34020 loads DPYNXx with DPYSTx */ + else + { + IOREG(REG020_DPYNXL) = IOREG(REG020_DPYSTL) & 0xffe0; + IOREG(REG020_DPYNXH) = IOREG(REG020_DPYSTH); + } + } + + /* at the end of the screen, update the display parameters */ + if (vcount == vtotal) + { + /* only do this if we have an incoming pixel clock */ + /* also, only do it if the HEBLNK/HSBLNK values are stable */ + if (master) // && (!m_scanline_ind16_cb.isnull() || !m_scanline_rgb32_cb.isnull())) + { + int htotal = SMART_IOREG(HTOTAL); + if (htotal > 0 && vtotal > 0) + { + //attoseconds_t refresh = HZ_TO_ATTOSECONDS(m_pixclock) * (htotal + 1) * (vtotal + 1); + int width = (htotal + 1) * m_pixperclock; + int height = vtotal + 1; + rectangle visarea; + + if ((SMART_IOREG(DPYCTL) & 0x4000) == 0) { + height *= 2; + visarea.interlace = true; + } else { + visarea.interlace = false; + } + + /* extract the visible area */ + visarea.min_x = SMART_IOREG(HEBLNK) * m_pixperclock; + visarea.max_x = SMART_IOREG(HSBLNK) * m_pixperclock - 1; + visarea.min_y = veblnk; + visarea.max_y = vsblnk - 1; + + /* if everything looks good, set the info */ + if (visarea.min_x < visarea.max_x && visarea.max_x <= width && visarea.min_y < visarea.max_y && visarea.max_y <= height) + { + /* because many games play with the HEBLNK/HSBLNK for effects, we don't change + if they are the only thing that has changed, unless they are stable for a couple + of frames */ + int current_width = m_screen->width(); + int current_height = m_screen->height(); + + if (width != current_width || height != current_height || visarea.min_y != current_visarea.min_y || visarea.max_y != current_visarea.max_y || + (m_hblank_stable > 2 && (visarea.min_x != current_visarea.min_x || visarea.max_x != current_visarea.max_x))) + { + m_screen->configure(width, height, visarea); //, refresh); + } + m_hblank_stable++; + } +#if 0 + LOG(("Configuring screen: HTOTAL=%3d BLANK=%3d-%3d VTOTAL=%3d BLANK=%3d-%3d refresh=%f\n", + htotal, SMART_IOREG(HEBLNK), SMART_IOREG(HSBLNK), vtotal, veblnk, vsblnk, ATTOSECONDS_TO_HZ(refresh))); +#endif +#if 0 + /* interlaced timing not supported */ + if ((SMART_IOREG(DPYCTL) & 0x4000) == 0) + fatalerror("Interlaced video configured on the TMS34010 (unsupported)\n"); +#endif + } + } + } + +#if 0 + /* force a partial update within the visible area */ + if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (!m_scanline_ind16_cb.isnull() || !m_scanline_rgb32_cb.isnull())) + m_screen->update_partial(vcount); +#endif + + /* if we are in the visible area, increment DPYADR by DUDATE */ + if (vcount >= veblnk && vcount < vsblnk) + { + /* 34010 increments by the DUDATE field in DPYCTL */ + if (!m_is_34020) + { + UINT16 dpyadr = IOREG(REG_DPYADR); + if ((dpyadr & 3) == 0) + dpyadr = ((dpyadr & 0xfffc) - (IOREG(REG_DPYCTL) & 0x03fc)) | (IOREG(REG_DPYSTRT) & 0x0003); + else + dpyadr = (dpyadr & 0xfffc) | ((dpyadr - 1) & 3); + IOREG(REG_DPYADR) = dpyadr; + } + + /* 34020 updates based on the DINC register, including zoom */ + else + { + UINT32 dpynx = IOREG(REG020_DPYNXL) | (IOREG(REG020_DPYNXH) << 16); + UINT32 dinc = IOREG(REG020_DINCL) | (IOREG(REG020_DINCH) << 16); + dpynx = (dpynx & 0xffffffe0) | ((dpynx + dinc) & 0x1f); + if ((dpynx & 0x1f) == 0) + dpynx += dinc & 0xffffffe0; + IOREG(REG020_DPYNXL) = dpynx; + IOREG(REG020_DPYNXH) = dpynx >> 16; + } + } + + /* adjust for the next callback */ + vcount++; + if (vcount > vtotal) + vcount = 0; + +#if 0 + /* note that we add !master (0 or 1) as a attoseconds value; this makes no practical difference */ + /* but helps ensure that masters are updated first before slaves */ + m_scantimer->adjust(m_screen->time_until_pos(vcount) + attotime(0, !master), vcount); +#endif + return vcount; +} + +void tms340x0_device::get_display_params(tms34010_display_params *params) +{ + params->enabled = ((SMART_IOREG(DPYCTL) & 0x8000) != 0); + params->vcount = SMART_IOREG(VCOUNT); + params->veblnk = SMART_IOREG(VEBLNK); + params->vsblnk = SMART_IOREG(VSBLNK); + params->heblnk = SMART_IOREG(HEBLNK) * m_pixperclock; + params->hsblnk = SMART_IOREG(HSBLNK) * m_pixperclock; + + /* 34010 gets its address from DPYADR and DPYTAP */ + if (!m_is_34020) + { + UINT16 dpyadr = IOREG(REG_DPYADR); + if (!(IOREG(REG_DPYCTL) & 0x0400)) + dpyadr ^= 0xfffc; + params->rowaddr = dpyadr >> 4; + params->coladdr = ((dpyadr & 0x007c) << 4) | (IOREG(REG_DPYTAP) & 0x3fff); + params->yoffset = (IOREG(REG_DPYSTRT) - IOREG(REG_DPYADR)) & 3; + } + + /* 34020 gets its address from DPYNX */ + else + { + params->rowaddr = IOREG(REG020_DPYNXH); + params->coladdr = IOREG(REG020_DPYNXL) & 0xffe0; + params->yoffset = 0; + if ((IOREG(REG020_DINCL) & 0x1f) != 0) + params->yoffset = (IOREG(REG020_DPYNXL) & 0x1f) / (IOREG(REG020_DINCL) & 0x1f); + } +} + +#if 0 +UINT32 tms340x0_device::tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) +{ + pen_t blackpen = screen.palette()->black_pen(); + tms34010_display_params params; + int x; + + /* get the display parameters for the screen */ + get_display_params(¶ms); + + /* if the display is enabled, call the scanline callback */ + if (params.enabled) + { + /* call through to the callback */ + LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr)); + m_scanline_ind16_cb(screen, bitmap, cliprect.min_y, ¶ms); + } + + /* otherwise, just blank the current scanline */ + else + params.heblnk = params.hsblnk = cliprect.max_x + 1; + + /* blank out the blank regions */ + UINT16 *dest = &bitmap.pix16(cliprect.min_y); + for (x = cliprect.min_x; x < params.heblnk; x++) + dest[x] = blackpen; + for (x = params.hsblnk; x <= cliprect.max_x; x++) + dest[x] = blackpen; + return 0; + +#endif +#if 0 +UINT32 tms340x0_device::tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + pen_t blackpen = rgb_t::black; + tms34010_display_params params; + int x; + + /* get the display parameters for the screen */ + get_display_params(¶ms); + + /* if the display is enabled, call the scanline callback */ + if (params.enabled) + { + /* call through to the callback */ + LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr)); + m_scanline_rgb32_cb(screen, bitmap, cliprect.min_y, ¶ms); + } + + /* otherwise, just blank the current scanline */ + else + params.heblnk = params.hsblnk = cliprect.max_x + 1; + + /* blank out the blank regions */ + UINT32 *dest = &bitmap.pix32(cliprect.min_y); + for (x = cliprect.min_x; x < params.heblnk; x++) + dest[x] = blackpen; + for (x = params.hsblnk; x <= cliprect.max_x; x++) + dest[x] = blackpen; + return 0; +} +#endif + +/*************************************************************************** + I/O REGISTER WRITES +***************************************************************************/ + +#if 0 +static const char *const ioreg_name[] = +{ + "HESYNC", "HEBLNK", "HSBLNK", "HTOTAL", + "VESYNC", "VEBLNK", "VSBLNK", "VTOTAL", + "DPYCTL", "DPYSTART", "DPYINT", "CONTROL", + "HSTDATA", "HSTADRL", "HSTADRH", "HSTCTLL", + + "HSTCTLH", "INTENB", "INTPEND", "CONVSP", + "CONVDP", "PSIZE", "PMASK", "RESERVED", + "RESERVED", "RESERVED", "RESERVED", "DPYTAP", + "HCOUNT", "VCOUNT", "DPYADR", "REFCNT" +}; +#endif + +WRITE16_MEMBER( tms340x0_device::io_register_w ) +{ + int oldreg, newreg; + + /* Set register */ + oldreg = IOREG(offset); + IOREG(offset) = data; + + switch (offset) + { + case REG_CONTROL: + set_raster_op(); + set_pixel_function(); + break; + + case REG_PSIZE: + set_pixel_function(); + + switch (data) + { + default: + case 0x01: m_pixelshift = 0; break; + case 0x02: m_pixelshift = 1; break; + case 0x04: m_pixelshift = 2; break; + case 0x08: m_pixelshift = 3; break; + case 0x10: m_pixelshift = 4; break; + } + break; + + case REG_PMASK: +#if 0 + if (data) logerror("Plane masking not supported. PC=%08X\n", space.device().safe_pc()); +#endif + break; + + case REG_DPYCTL: + set_pixel_function(); + break; + + case REG_HSTCTLH: + /* if the CPU is halting itself, stop execution right away */ + if (mem_mask & 0xff00) + { + if ((data & 0x8000) && !(oldreg & 0x8000)) + write_log("TMS stopped\n"); + if (!(data & 0x8000) && (oldreg & 0x8000)) + write_log("TMS started\n"); + if ((data & 0x8000) && !m_external_host_access) + m_icount = 0; +#if 0 + set_input_line(INPUT_LINE_HALT, (data & 0x8000) ? ASSERT_LINE : CLEAR_LINE); +#endif + + /* NMI issued? */ + if (data & 0x0100) { + internal_interrupt_callback(NULL, 0); +#if 0 + machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), 0); +#endif + } + } + break; + + case REG_HSTCTLL: + if (mem_mask & 0x00ff) + { + /* the TMS34010 can change MSGOUT, can set INTOUT, and can clear INTIN */ + if (!m_external_host_access) + { + newreg = (oldreg & 0xff8f) | (data & 0x0070); + newreg |= data & 0x0080; + newreg &= data | ~0x0008; + } + + /* the host can change MSGIN, can set INTIN, and can clear INTOUT */ + else + { + newreg = (oldreg & 0xfff8) | (data & 0x0007); + newreg &= data | ~0x0080; + newreg |= data & 0x0008; + } + IOREG(offset) = newreg; + + /* the TMS34010 can set output interrupt? */ + if (!(oldreg & 0x0080) && (newreg & 0x0080)) + { +// if (!m_output_int_cb.isnull()) +// m_output_int_cb(1); + write_log(_T("m_output_int_cb(1)\n")); + } + else if ((oldreg & 0x0080) && !(newreg & 0x0080)) + { +// if (!m_output_int_cb.isnull()) +// m_output_int_cb(0); + write_log(_T("m_output_int_cb(0)\n")); + } + + /* input interrupt? (should really be state-based, but the functions don't exist!) */ + if (!(oldreg & 0x0008) && (newreg & 0x0008)) { + //machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), TMS34010_HI); + internal_interrupt_callback(NULL, TMS34010_HI); + } else if ((oldreg & 0x0008) && !(newreg & 0x0008)) { + IOREG(REG_INTPEND) &= ~TMS34010_HI; + } + } + break; + + case REG_CONVSP: + m_convsp = 1 << (~data & 0x1f); + break; + + case REG_CONVDP: + m_convdp = 1 << (~data & 0x1f); + break; + + case REG_INTENB: + check_interrupt(); + break; + + case REG_INTPEND: + /* X1P, X2P and HIP are read-only */ + /* WVP and DIP can only have 0's written to them */ + IOREG(REG_INTPEND) = oldreg; + if (!(data & TMS34010_WV)) + IOREG(REG_INTPEND) &= ~TMS34010_WV; + if (!(data & TMS34010_DI)) + IOREG(REG_INTPEND) &= ~TMS34010_DI; + break; + + case REG_HEBLNK: + case REG_HSBLNK: + if (oldreg != data) + m_hblank_stable = 0; + break; + } + +// if (LOG_CONTROL_REGS) +// logerror("%s: %s = %04X (%d)\n", machine().describe_context(), ioreg_name[offset], IOREG(offset), m_screen.vpos()); +} + + +#if 0 +static const char *const ioreg020_name[] = +{ + "VESYNC", "HESYNC", "VEBLNK", "HEBLNK", + "VSBLNK", "HSBLNK", "VTOTAL", "HTOTAL", + "DPYCTL", "DPYSTRT", "DPYINT", "CONTROL", + "HSTDATA", "HSTADRL", "HSTADRH", "HSTCTLL", + + "HSTCTLH", "INTENB", "INTPEND", "CONVSP", + "CONVDP", "PSIZE", "PMASKL", "PMASKH", + "CONVMP", "CONTROL2", "CONFIG", "DPYTAP", + "VCOUNT", "HCOUNT", "DPYADR", "REFADR", + + "DPYSTL", "DPYSTH", "DPYNXL", "DPYNXH", + "DINCL", "DINCH", "RES0", "HESERR", + "RES1", "RES2", "RES3", "RES4", + "SCOUNT", "BSFLTST", "DPYMSK", "RES5", + + "SETVCNT", "SETHCNT", "BSFLTDL", "BSFLTDH", + "RES6", "RES7", "RES8", "RES9", + "IHOST1L", "IHOST1H", "IHOST2L", "IHOST2H", + "IHOST3L", "IHOST3H", "IHOST4L", "IHOST4H" +}; +#endif + +#if 0 +WRITE16_MEMBER( tms34020_device::io_register_w ) +{ + int oldreg, newreg; + + /* Set register */ + oldreg = IOREG(offset); + IOREG(offset) = data; + +// if (LOG_CONTROL_REGS) +// logerror("%s: %s = %04X (%d)\n", machine().describe_context(), ioreg020_name[offset], IOREG(offset), m_screen.vpos()); + + switch (offset) + { + case REG020_CONTROL: + case REG020_CONTROL2: + IOREG(REG020_CONTROL) = data; + IOREG(REG020_CONTROL2) = data; + set_raster_op(); + set_pixel_function(); + break; + + case REG020_PSIZE: + set_pixel_function(); + + switch (data) + { + default: + case 0x01: m_pixelshift = 0; break; + case 0x02: m_pixelshift = 1; break; + case 0x04: m_pixelshift = 2; break; + case 0x08: m_pixelshift = 3; break; + case 0x10: m_pixelshift = 4; break; + case 0x20: m_pixelshift = 5; break; + } + break; + + case REG020_PMASKL: + case REG020_PMASKH: +#if 0 + if (data) logerror("Plane masking not supported. PC=%08X\n", space.device().safe_pc()); +#endif + break; + + case REG020_DPYCTL: + set_pixel_function(); + break; + +#if 0 + case REG020_HSTCTLH: + /* if the CPU is halting itself, stop execution right away */ + if ((data & 0x8000) && !m_external_host_access) + m_icount = 0; + set_input_line(INPUT_LINE_HALT, (data & 0x8000) ? ASSERT_LINE : CLEAR_LINE); + + /* NMI issued? */ + if (data & 0x0100) + machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), 0); + break; +#endif + + case REG020_HSTCTLL: + /* the TMS34010 can change MSGOUT, can set INTOUT, and can clear INTIN */ + if (!m_external_host_access) + { + newreg = (oldreg & 0xff8f) | (data & 0x0070); + newreg |= data & 0x0080; + newreg &= data | ~0x0008; + } + + /* the host can change MSGIN, can set INTIN, and can clear INTOUT */ + else + { + newreg = (oldreg & 0xfff8) | (data & 0x0007); + newreg &= data | ~0x0080; + newreg |= data & 0x0008; + } + IOREG(offset) = newreg; + +#if 0 + /* the TMS34010 can set output interrupt? */ + if (!(oldreg & 0x0080) && (newreg & 0x0080)) + { + if (!m_output_int_cb.isnull()) + m_output_int_cb(1); + } + else if ((oldreg & 0x0080) && !(newreg & 0x0080)) + { + if (!m_output_int_cb.isnull()) + m_output_int_cb(0); + } + + /* input interrupt? (should really be state-based, but the functions don't exist!) */ + if (!(oldreg & 0x0008) && (newreg & 0x0008)) + machine().scheduler().synchronize(timer_expired_delegate(FUNC(tms340x0_device::internal_interrupt_callback), this), TMS34010_HI); + else if ((oldreg & 0x0008) && !(newreg & 0x0008)) + IOREG(REG020_INTPEND) &= ~TMS34010_HI; +#endif + break; + + case REG020_INTENB: + check_interrupt(); + break; + + case REG020_INTPEND: + /* X1P, X2P and HIP are read-only */ + /* WVP and DIP can only have 0's written to them */ + IOREG(REG020_INTPEND) = oldreg; + if (!(data & TMS34010_WV)) + IOREG(REG020_INTPEND) &= ~TMS34010_WV; + if (!(data & TMS34010_DI)) + IOREG(REG020_INTPEND) &= ~TMS34010_DI; + break; + + case REG020_CONVSP: + if (data & 0x001f) + { + if (data & 0x1f00) + m_convsp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f)); + else + m_convsp = 1 << (~data & 0x1f); + } + else + m_convsp = data; + break; + + case REG020_CONVDP: + if (data & 0x001f) + { + if (data & 0x1f00) + m_convdp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f)); + else + m_convdp = 1 << (~data & 0x1f); + } + else + m_convdp = data; + break; + + case REG020_CONVMP: + if (data & 0x001f) + { + if (data & 0x1f00) + m_convmp = (1 << (~data & 0x1f)) + (1 << (~(data >> 8) & 0x1f)); + else + m_convmp = 1 << (~data & 0x1f); + } + else + m_convmp = data; + break; + + case REG020_DPYSTRT: + case REG020_DPYADR: + case REG020_DPYTAP: + break; + + case REG020_HEBLNK: + case REG020_HSBLNK: + if (oldreg != data) + m_hblank_stable = 0; + break; + } +} +#endif + + +/*************************************************************************** + I/O REGISTER READS +***************************************************************************/ + +READ16_MEMBER( tms340x0_device::io_register_r ) +{ + int result, total; + +// if (LOG_CONTROL_REGS) +// logerror("%s: read %s\n", machine().describe_context(), ioreg_name[offset]); + + switch (offset) + { + case REG_HCOUNT: + /* scale the horizontal position from screen width to HTOTAL */ + result = m_screen->hpos(); + total = IOREG(REG_HTOTAL) + 1; + result = result * total / m_screen->width(); + + /* offset by the HBLANK end */ + result += IOREG(REG_HEBLNK); + + /* wrap around */ + if (result > total) + result -= total; + return result; + case REG_REFCNT: +#if 0 + return (total_cycles() / 16) & 0xfffc; +#else + write_log("REG_REFCNT\n"); + return 0; +#endif + case REG_INTPEND: + result = IOREG(offset); + +#if 0 + /* Cool Pool loops in mainline code on the appearance of the DI, even though they */ + /* have an IRQ handler. For this reason, we return it signalled a bit early in order */ + /* to make it past these loops. */ + if (SMART_IOREG(VCOUNT) + 1 == SMART_IOREG(DPYINT) && + m_scantimer->remaining() < attotime::from_hz(40000000/8/3)) + result |= TMS34010_DI; +#else + write_log("REG_INTPEND %04x\n", result); +#endif + return result; + } + + return IOREG(offset); +} + +#if 0 +READ16_MEMBER( tms34020_device::io_register_r ) +{ + int result, total; + +// if (LOG_CONTROL_REGS) +// logerror("%s: read %s\n", machine().describe_context(), ioreg_name[offset]); + + switch (offset) + { + case REG020_HCOUNT: + /* scale the horizontal position from screen width to HTOTAL */ + result = m_screen->hpos(); + total = IOREG(REG020_HTOTAL) + 1; + result = result * total / m_screen->width(); + + /* offset by the HBLANK end */ + result += IOREG(REG020_HEBLNK); + + /* wrap around */ + if (result > total) + result -= total; + return result; + case REG020_REFADR: + { + int refreshrate = (IOREG(REG020_CONFIG) >> 8) & 7; + if (refreshrate < 6) + return (total_cycles() / refreshrate) & 0xffff; + break; + } + } + + return IOREG(offset); +} +#endif + + +/*************************************************************************** + SAVE STATE +***************************************************************************/ + +#if 0 +void tms340x0_device::tms34010_state_postload() +{ + set_raster_op(); + set_pixel_function(); +} +#endif + + +/*************************************************************************** + HOST INTERFACE WRITES +***************************************************************************/ + +WRITE16_MEMBER( tms340x0_device::host_w ) +{ + int reg = offset; + unsigned int addr; + + switch (reg) + { + /* upper 16 bits of the address */ + case TMS34010_HOST_ADDRESS_H: + IOREG(REG_HSTADRH) = data; + break; + + /* lower 16 bits of the address */ + case TMS34010_HOST_ADDRESS_L: + IOREG(REG_HSTADRL) = data; + break; + + /* actual data */ + case TMS34010_HOST_DATA: + + /* write to the address */ + addr = (IOREG(REG_HSTADRH) << 16) | IOREG(REG_HSTADRL); + TMS34010_WRMEM_WORD(TOBYTE(addr & 0xfffffff0), data); + + /* optional postincrement */ + if (IOREG(REG_HSTCTLH) & 0x0800) + { + addr += 0x10; + IOREG(REG_HSTADRH) = addr >> 16; + IOREG(REG_HSTADRL) = (UINT16)addr; + } + break; + + /* control register */ + case TMS34010_HOST_CONTROL: + { + m_external_host_access = TRUE; + if (mem_mask&0xff00) io_register_w(*m_program, REG_HSTCTLH, data & 0xff00, 0xff00); + if (mem_mask&0x00ff) io_register_w(*m_program, REG_HSTCTLL, data & 0x00ff, 0x00ff); + m_external_host_access = FALSE; + break; + } + + /* error case */ + default: + logerror("tms34010_host_control_w called on invalid register %d\n", reg); + break; + } +} + + + +/*************************************************************************** + HOST INTERFACE READS +***************************************************************************/ + +READ16_MEMBER( tms340x0_device::host_r ) +{ + int reg = offset; + unsigned int addr; + int result = 0; + + /* swap to the target cpu */ + + switch (reg) + { + /* upper 16 bits of the address */ + case TMS34010_HOST_ADDRESS_H: + result = IOREG(REG_HSTADRH); + break; + + /* lower 16 bits of the address */ + case TMS34010_HOST_ADDRESS_L: + result = IOREG(REG_HSTADRL); + break; + + /* actual data */ + case TMS34010_HOST_DATA: + + /* read from the address */ + addr = (IOREG(REG_HSTADRH) << 16) | IOREG(REG_HSTADRL); + result = TMS34010_RDMEM_WORD(TOBYTE(addr & 0xfffffff0)); + + /* optional postincrement (it says preincrement, but data is preloaded, so it + is effectively a postincrement */ + if (IOREG(REG_HSTCTLH) & 0x1000) + { + addr += 0x10; + IOREG(REG_HSTADRH) = addr >> 16; + IOREG(REG_HSTADRL) = (UINT16)addr; + } + break; + + /* control register */ + case TMS34010_HOST_CONTROL: + result = (IOREG(REG_HSTCTLH) & 0xff00) | (IOREG(REG_HSTCTLL) & 0x00ff); + break; + + /* error case */ + default: + logerror("tms34010_host_control_r called on invalid register %d\n", reg); + break; + } + + return result; +} + + +#if 0 +void tms340x0_device::state_string_export(const device_state_entry &entry, std::string &str) +{ + switch (entry.index()) + { + case STATE_GENFLAGS: + strprintf(str, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c", + m_st & 0x80000000 ? 'N':'.', + m_st & 0x40000000 ? 'C':'.', + m_st & 0x20000000 ? 'Z':'.', + m_st & 0x10000000 ? 'V':'.', + m_st & 0x02000000 ? 'P':'.', + m_st & 0x00200000 ? 'I':'.', + m_st & 0x00000800 ? 'E':'.', + m_st & 0x00000400 ? 'F':'.', + m_st & 0x00000200 ? 'F':'.', + m_st & 0x00000100 ? 'F':'.', + m_st & 0x00000080 ? 'F':'.', + m_st & 0x00000040 ? 'F':'.', + m_st & 0x00000020 ? 'E':'.', + m_st & 0x00000010 ? 'F':'.', + m_st & 0x00000008 ? 'F':'.', + m_st & 0x00000004 ? 'F':'.', + m_st & 0x00000002 ? 'F':'.', + m_st & 0x00000001 ? 'F':'.'); + break; + } +} + + +offs_t tms34010_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( tms34010 ); + + return CPU_DISASSEMBLE_NAME(tms34010)(this, buffer, pc, oprom, opram, options); +} + + +offs_t tms34020_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( tms34020 ); + + return CPU_DISASSEMBLE_NAME(tms34020)(this, buffer, pc, oprom, opram, options); +} +#endif \ No newline at end of file diff --git a/mame/tm34010/tms34010.h b/mame/tm34010/tms34010.h new file mode 100644 index 00000000..bc61ab11 --- /dev/null +++ b/mame/tm34010/tms34010.h @@ -0,0 +1,1049 @@ +// license:BSD-3-Clause +// copyright-holders:Alex Pasadyn,Zsolt Vasvari +/*************************************************************************** + + TMS34010: Portable Texas Instruments TMS34010 emulator + + Copyright Alex Pasadyn/Zsolt Vasvari + Parts based on code by Aaron Giles + +***************************************************************************/ + + +#pragma once + +#ifndef __TMS34010_H__ +#define __TMS34010_H__ + + +/* register indexes for get_reg and set_reg */ +enum +{ + TMS34010_PC, + TMS34010_SP, + TMS34010_ST, + TMS34010_A0, + TMS34010_A1, + TMS34010_A2, + TMS34010_A3, + TMS34010_A4, + TMS34010_A5, + TMS34010_A6, + TMS34010_A7, + TMS34010_A8, + TMS34010_A9, + TMS34010_A10, + TMS34010_A11, + TMS34010_A12, + TMS34010_A13, + TMS34010_A14, + TMS34010_B0, + TMS34010_B1, + TMS34010_B2, + TMS34010_B3, + TMS34010_B4, + TMS34010_B5, + TMS34010_B6, + TMS34010_B7, + TMS34010_B8, + TMS34010_B9, + TMS34010_B10, + TMS34010_B11, + TMS34010_B12, + TMS34010_B13, + TMS34010_B14, + + TMS34010_GENPC = STATE_GENPC, + TMS34010_GENSP = STATE_GENSP, + TMS34010_GENPCBASE = STATE_GENPCBASE +}; + + +/*************************************************************************** + INTERNAL I/O CONSTANTS +***************************************************************************/ + +enum +{ + REG_HESYNC = 0, + REG_HEBLNK, + REG_HSBLNK, + REG_HTOTAL, + REG_VESYNC, + REG_VEBLNK, + REG_VSBLNK, + REG_VTOTAL, + REG_DPYCTL, + REG_DPYSTRT, + REG_DPYINT, + REG_CONTROL, + REG_HSTDATA, + REG_HSTADRL, + REG_HSTADRH, + REG_HSTCTLL, + + REG_HSTCTLH, + REG_INTENB, + REG_INTPEND, + REG_CONVSP, + REG_CONVDP, + REG_PSIZE, + REG_PMASK, + REG_UNK23, + REG_UNK24, + REG_UNK25, + REG_UNK26, + REG_DPYTAP, + REG_HCOUNT, + REG_VCOUNT, + REG_DPYADR, + REG_REFCNT +}; + +enum +{ + REG020_VESYNC, + REG020_HESYNC, + REG020_VEBLNK, + REG020_HEBLNK, + REG020_VSBLNK, + REG020_HSBLNK, + REG020_VTOTAL, + REG020_HTOTAL, + REG020_DPYCTL, /* matches 010 */ + REG020_DPYSTRT, /* matches 010 */ + REG020_DPYINT, /* matches 010 */ + REG020_CONTROL, /* matches 010 */ + REG020_HSTDATA, /* matches 010 */ + REG020_HSTADRL, /* matches 010 */ + REG020_HSTADRH, /* matches 010 */ + REG020_HSTCTLL, /* matches 010 */ + + REG020_HSTCTLH, /* matches 010 */ + REG020_INTENB, /* matches 010 */ + REG020_INTPEND, /* matches 010 */ + REG020_CONVSP, /* matches 010 */ + REG020_CONVDP, /* matches 010 */ + REG020_PSIZE, /* matches 010 */ + REG020_PMASKL, + REG020_PMASKH, + REG020_CONVMP, + REG020_CONTROL2, + REG020_CONFIG, + REG020_DPYTAP, /* matches 010 */ + REG020_VCOUNT, + REG020_HCOUNT, + REG020_DPYADR, /* matches 010 */ + REG020_REFADR, + + REG020_DPYSTL, + REG020_DPYSTH, + REG020_DPYNXL, + REG020_DPYNXH, + REG020_DINCL, + REG020_DINCH, + REG020_RES0, + REG020_HESERR, + REG020_RES1, + REG020_RES2, + REG020_RES3, + REG020_RES4, + REG020_SCOUNT, + REG020_BSFLTST, + REG020_DPYMSK, + REG020_RES5, + + REG020_SETVCNT, + REG020_SETHCNT, + REG020_BSFLTDL, + REG020_BSFLTDH, + REG020_RES6, + REG020_RES7, + REG020_RES8, + REG020_RES9, + REG020_IHOST1L, + REG020_IHOST1H, + REG020_IHOST2L, + REG020_IHOST2H, + REG020_IHOST3L, + REG020_IHOST3H, + REG020_IHOST4L, + REG020_IHOST4H +}; + +/* Interrupts that are generated by the processor internally */ +#define TMS34010_INT1 0x0002 /* External Interrupt 1 */ +#define TMS34010_INT2 0x0004 /* External Interrupt 2 */ +#define TMS34010_HI 0x0200 /* Host Interrupt */ +#define TMS34010_DI 0x0400 /* Display Interrupt */ +#define TMS34010_WV 0x0800 /* Window Violation Interrupt */ + + +/* Configuration structure */ +struct tms34010_display_params +{ + UINT16 vcount; /* most recent VCOUNT */ + UINT16 veblnk, vsblnk; /* start/end of VBLANK */ + UINT16 heblnk, hsblnk; /* start/end of HBLANK */ + UINT16 rowaddr, coladdr; /* row/column addresses */ + UINT8 yoffset; /* y offset from addresses */ + UINT8 enabled; /* video enabled */ +}; + +#if 0 +#define MCFG_TMS340X0_HALT_ON_RESET(_value) \ + tms340x0_device::set_halt_on_reset(*device, _value); + +#define MCFG_TMS340X0_PIXEL_CLOCK(_value) \ + tms340x0_device::set_pixel_clock(*device, _value); + +#define MCFG_TMS340X0_PIXELS_PER_CLOCK(_value) \ + tms340x0_device::set_pixels_per_clock(*device, _value); + +typedef device_delegate scanline_ind16_cb_delegate; + +#define TMS340X0_SCANLINE_IND16_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params) + +#define MCFG_TMS340X0_SCANLINE_IND16_CB(_class, _method) \ + tms340x0_device::set_scanline_ind16_callback(*device, scanline_ind16_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); + + +typedef device_delegate scanline_rgb32_cb_delegate; + +#define TMS340X0_SCANLINE_RGB32_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params) + +#define MCFG_TMS340X0_SCANLINE_RGB32_CB(_class, _method) \ + tms340x0_device::set_scanline_rgb32_callback(*device, scanline_rgb32_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); + + +#define MCFG_TMS340X0_OUTPUT_INT_CB(_devcb) \ + devcb = &tms340x0_device::set_output_int_callback(*device, DEVCB_##_devcb); + + +typedef device_delegate to_shiftreg_cb_delegate; + +#define TMS340X0_TO_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg) + +#define MCFG_TMS340X0_TO_SHIFTREG_CB(_class, _method) \ + tms340x0_device::set_to_shiftreg_callback(*device, to_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); + + +typedef device_delegate from_shiftreg_cb_delegate; + +#define TMS340X0_FROM_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg) + +#define MCFG_TMS340X0_FROM_SHIFTREG_CB(_class, _method) \ + tms340x0_device::set_from_shiftreg_callback(*device, from_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); + + +class tms340x0_device : public cpu_device, + public device_video_interface +#endif + +class tms340x0_device +{ +public: +#if 0 + // construction/destruction + tms340x0_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname); + + static void set_halt_on_reset(device_t &device, bool halt_on_reset) { downcast(device).m_halt_on_reset = halt_on_reset; } + static void set_pixel_clock(device_t &device, UINT32 pixclock) { downcast(device).m_pixclock = pixclock; } + static void set_pixels_per_clock(device_t &device, int pixperclock) { downcast(device).m_pixperclock = pixperclock; } + static void set_scanline_ind16_callback(device_t &device, scanline_ind16_cb_delegate callback) { downcast(device).m_scanline_ind16_cb = callback; } + static void set_scanline_rgb32_callback(device_t &device, scanline_rgb32_cb_delegate callback) { downcast(device).m_scanline_rgb32_cb = callback; } + template static devcb_base &set_output_int_callback(device_t &device, _Object object) { return downcast(device).m_output_int_cb.set_callback(object); } + static void set_to_shiftreg_callback(device_t &device, to_shiftreg_cb_delegate callback) { downcast(device).m_to_shiftreg_cb = callback; } + static void set_from_shiftreg_callback(device_t &device, from_shiftreg_cb_delegate callback) { downcast(device).m_from_shiftreg_cb = callback; } + + void tms34010_state_postload(); + + UINT32 tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); + UINT32 tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + +#endif + void get_display_params(tms34010_display_params *params); + + TIMER_CALLBACK_MEMBER(internal_interrupt_callback); + TIMER_CALLBACK_MEMBER(scanline_callback); + + DECLARE_WRITE16_MEMBER(io_register_w); + DECLARE_READ16_MEMBER(io_register_r); + + DECLARE_WRITE16_MEMBER(host_w); + DECLARE_READ16_MEMBER(host_r); + + // device-level overrides + void device_start(); + void device_reset(); + void execute_run(); + int m_icount; + +protected: + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 10000; } + virtual UINT32 execute_input_lines() const { return 2; } + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides +// virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + + // device_state_interface overrides +// virtual void state_string_export(const device_state_entry &entry, std::string &str); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const { return 10; } + + typedef void (tms340x0_device::*pixel_write_func)(offs_t offset, UINT32 data); + typedef UINT32 (tms340x0_device::*pixel_read_func)(offs_t offset); + typedef UINT32 (tms340x0_device::*raster_op_func)(UINT32 newpix, UINT32 oldpix); + typedef void (tms340x0_device::*wfield_func)(offs_t offset, UINT32 data); + typedef UINT32 (tms340x0_device::*rfield_func)(offs_t offset); + typedef void (tms340x0_device::*opcode_func)(UINT16 op); + typedef UINT32 (tms340x0_device::*pixel_op_func)(UINT32, UINT32, UINT32); + typedef void (tms340x0_device::*pixblt_op_func)(int, int); + typedef void (tms340x0_device::*pixblt_b_op_func)(int); + typedef void (tms340x0_device::*word_write_func)(address_space &space, offs_t offset,UINT16 data); + typedef UINT16 (tms340x0_device::*word_read_func)(address_space &space, offs_t offset); + + static const wfield_func s_wfield_functions[32]; + static const rfield_func s_rfield_functions[64]; + static const opcode_func s_opcode_table[65536 >> 4]; + static const pixel_op_func s_pixel_op_table[32]; + static const UINT8 s_pixel_op_timing_table[33]; + static const pixblt_op_func s_pixblt_op_table[]; + static const pixblt_op_func s_pixblt_r_op_table[]; + static const pixblt_b_op_func s_pixblt_b_op_table[]; + static const pixblt_b_op_func s_fill_op_table[]; + static const pixel_write_func s_pixel_write_ops[4][6]; + static const pixel_read_func s_pixel_read_ops[6]; + static const raster_op_func s_raster_ops[32]; + + address_space_config m_program_config; + + UINT32 m_pc; + UINT32 m_ppc; + UINT32 m_st; + pixel_write_func m_pixel_write; + pixel_read_func m_pixel_read; + raster_op_func m_raster_op; + pixel_op_func m_pixel_op; + UINT32 m_pixel_op_timing; + UINT32 m_convsp; + UINT32 m_convdp; + UINT32 m_convmp; + INT32 m_gfxcycles; + UINT8 m_pixelshift; + UINT8 m_is_34020; + bool m_reset_deferred; + bool m_halt_on_reset; /* /HCS pin, which determines HALT state after reset */ + UINT8 m_hblank_stable; + UINT8 m_external_host_access; + UINT8 m_executing; + address_space *m_program; + direct_read_data *m_direct; + UINT32 m_pixclock; /* the pixel clock (0 means don't adjust screen size) */ + int m_pixperclock; /* pixels per clock */ +// emu_timer *m_scantimer; + +#if 0 + scanline_ind16_cb_delegate m_scanline_ind16_cb; + scanline_rgb32_cb_delegate m_scanline_rgb32_cb; + devcb_write_line m_output_int_cb; /* output interrupt callback */ + to_shiftreg_cb_delegate m_to_shiftreg_cb; /* shift register write */ + from_shiftreg_cb_delegate m_from_shiftreg_cb; /* shift register read */ +#endif + + struct XY + { +#ifdef LSB_FIRST + INT16 x; + INT16 y; +#else + INT16 y; + INT16 x; +#endif + }; + + /* A registers 0-15 map to regs[0]-regs[15] */ + /* B registers 0-15 map to regs[30]-regs[15] */ + union + { + INT32 reg; + XY xy; + } m_regs[31]; + + UINT16 m_IOregs[64]; + UINT16 m_shiftreg[(8 * 512 * sizeof(UINT16))/2]; + + UINT32 TMS34010_RDMEM_DWORD(offs_t A); + void TMS34010_WRMEM_DWORD(offs_t A, UINT32 V); + void SET_ST(UINT32 st); + void RESET_ST(); + UINT32 ROPCODE(); + INT16 PARAM_WORD(); + INT32 PARAM_LONG(); + INT16 PARAM_WORD_NO_INC(); + INT32 PARAM_LONG_NO_INC(); + UINT32 RBYTE(offs_t offset); + void WBYTE(offs_t offset, UINT32 data); + UINT32 RLONG(offs_t offset); + void WLONG(offs_t offset, UINT32 data); + void PUSH(UINT32 data); + INT32 POP(); + UINT32 read_pixel_1(offs_t offset); + UINT32 read_pixel_2(offs_t offset); + UINT32 read_pixel_4(offs_t offset); + UINT32 read_pixel_8(offs_t offset); + UINT32 read_pixel_16(offs_t offset); + UINT32 read_pixel_32(offs_t offset); + UINT32 read_pixel_shiftreg(offs_t offset); + void write_pixel_1(offs_t offset, UINT32 data); + void write_pixel_2(offs_t offset, UINT32 data); + void write_pixel_4(offs_t offset, UINT32 data); + void write_pixel_8(offs_t offset, UINT32 data); + void write_pixel_16(offs_t offset, UINT32 data); + void write_pixel_32(offs_t offset, UINT32 data); + void write_pixel_t_1(offs_t offset, UINT32 data); + void write_pixel_t_2(offs_t offset, UINT32 data); + void write_pixel_t_4(offs_t offset, UINT32 data); + void write_pixel_t_8(offs_t offset, UINT32 data); + void write_pixel_t_16(offs_t offset, UINT32 data); + void write_pixel_t_32(offs_t offset, UINT32 data); + void write_pixel_r_1(offs_t offset, UINT32 data); + void write_pixel_r_2(offs_t offset, UINT32 data); + void write_pixel_r_4(offs_t offset, UINT32 data); + void write_pixel_r_8(offs_t offset, UINT32 data); + void write_pixel_r_16(offs_t offset, UINT32 data); + void write_pixel_r_32(offs_t offset, UINT32 data); + void write_pixel_r_t_1(offs_t offset, UINT32 data); + void write_pixel_r_t_2(offs_t offset, UINT32 data); + void write_pixel_r_t_4(offs_t offset, UINT32 data); + void write_pixel_r_t_8(offs_t offset, UINT32 data); + void write_pixel_r_t_16(offs_t offset, UINT32 data); + void write_pixel_r_t_32(offs_t offset, UINT32 data); + void write_pixel_shiftreg(offs_t offset, UINT32 data); + UINT32 raster_op_1(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_2(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_3(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_4(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_5(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_6(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_7(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_8(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_9(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_10(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_11(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_12(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_13(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_14(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_15(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_16(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_17(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_18(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_19(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_20(UINT32 newpix, UINT32 oldpix); + UINT32 raster_op_21(UINT32 newpix, UINT32 oldpix); + void wfield_01(offs_t offset, UINT32 data); + void wfield_02(offs_t offset, UINT32 data); + void wfield_03(offs_t offset, UINT32 data); + void wfield_04(offs_t offset, UINT32 data); + void wfield_05(offs_t offset, UINT32 data); + void wfield_06(offs_t offset, UINT32 data); + void wfield_07(offs_t offset, UINT32 data); + void wfield_08(offs_t offset, UINT32 data); + void wfield_09(offs_t offset, UINT32 data); + void wfield_10(offs_t offset, UINT32 data); + void wfield_11(offs_t offset, UINT32 data); + void wfield_12(offs_t offset, UINT32 data); + void wfield_13(offs_t offset, UINT32 data); + void wfield_14(offs_t offset, UINT32 data); + void wfield_15(offs_t offset, UINT32 data); + void wfield_16(offs_t offset, UINT32 data); + void wfield_17(offs_t offset, UINT32 data); + void wfield_18(offs_t offset, UINT32 data); + void wfield_19(offs_t offset, UINT32 data); + void wfield_20(offs_t offset, UINT32 data); + void wfield_21(offs_t offset, UINT32 data); + void wfield_22(offs_t offset, UINT32 data); + void wfield_23(offs_t offset, UINT32 data); + void wfield_24(offs_t offset, UINT32 data); + void wfield_25(offs_t offset, UINT32 data); + void wfield_26(offs_t offset, UINT32 data); + void wfield_27(offs_t offset, UINT32 data); + void wfield_28(offs_t offset, UINT32 data); + void wfield_29(offs_t offset, UINT32 data); + void wfield_30(offs_t offset, UINT32 data); + void wfield_31(offs_t offset, UINT32 data); + void wfield_32(offs_t offset, UINT32 data); + UINT32 rfield_z_01(offs_t offset); + UINT32 rfield_z_02(offs_t offset); + UINT32 rfield_z_03(offs_t offset); + UINT32 rfield_z_04(offs_t offset); + UINT32 rfield_z_05(offs_t offset); + UINT32 rfield_z_06(offs_t offset); + UINT32 rfield_z_07(offs_t offset); + UINT32 rfield_z_08(offs_t offset); + UINT32 rfield_z_09(offs_t offset); + UINT32 rfield_z_10(offs_t offset); + UINT32 rfield_z_11(offs_t offset); + UINT32 rfield_z_12(offs_t offset); + UINT32 rfield_z_13(offs_t offset); + UINT32 rfield_z_14(offs_t offset); + UINT32 rfield_z_15(offs_t offset); + UINT32 rfield_z_16(offs_t offset); + UINT32 rfield_z_17(offs_t offset); + UINT32 rfield_z_18(offs_t offset); + UINT32 rfield_z_19(offs_t offset); + UINT32 rfield_z_20(offs_t offset); + UINT32 rfield_z_21(offs_t offset); + UINT32 rfield_z_22(offs_t offset); + UINT32 rfield_z_23(offs_t offset); + UINT32 rfield_z_24(offs_t offset); + UINT32 rfield_z_25(offs_t offset); + UINT32 rfield_z_26(offs_t offset); + UINT32 rfield_z_27(offs_t offset); + UINT32 rfield_z_28(offs_t offset); + UINT32 rfield_z_29(offs_t offset); + UINT32 rfield_z_30(offs_t offset); + UINT32 rfield_z_31(offs_t offset); + UINT32 rfield_32(offs_t offset); + UINT32 rfield_s_01(offs_t offset); + UINT32 rfield_s_02(offs_t offset); + UINT32 rfield_s_03(offs_t offset); + UINT32 rfield_s_04(offs_t offset); + UINT32 rfield_s_05(offs_t offset); + UINT32 rfield_s_06(offs_t offset); + UINT32 rfield_s_07(offs_t offset); + UINT32 rfield_s_08(offs_t offset); + UINT32 rfield_s_09(offs_t offset); + UINT32 rfield_s_10(offs_t offset); + UINT32 rfield_s_11(offs_t offset); + UINT32 rfield_s_12(offs_t offset); + UINT32 rfield_s_13(offs_t offset); + UINT32 rfield_s_14(offs_t offset); + UINT32 rfield_s_15(offs_t offset); + UINT32 rfield_s_16(offs_t offset); + UINT32 rfield_s_17(offs_t offset); + UINT32 rfield_s_18(offs_t offset); + UINT32 rfield_s_19(offs_t offset); + UINT32 rfield_s_20(offs_t offset); + UINT32 rfield_s_21(offs_t offset); + UINT32 rfield_s_22(offs_t offset); + UINT32 rfield_s_23(offs_t offset); + UINT32 rfield_s_24(offs_t offset); + UINT32 rfield_s_25(offs_t offset); + UINT32 rfield_s_26(offs_t offset); + UINT32 rfield_s_27(offs_t offset); + UINT32 rfield_s_28(offs_t offset); + UINT32 rfield_s_29(offs_t offset); + UINT32 rfield_s_30(offs_t offset); + UINT32 rfield_s_31(offs_t offset); + void unimpl(UINT16 op); + void pixblt_l_l(UINT16 op); /* 0f00 */ + void pixblt_l_xy(UINT16 op); /* 0f20 */ + void pixblt_xy_l(UINT16 op); /* 0f40 */ + void pixblt_xy_xy(UINT16 op); /* 0f60 */ + void pixblt_b_l(UINT16 op); /* 0f80 */ + void pixblt_b_xy(UINT16 op); /* 0fa0 */ + void fill_l(UINT16 op); /* 0fc0 */ + void fill_xy(UINT16 op); /* 0fe0 */ + void line(UINT16 op); /* df10/df90 */ + void add_xy_a(UINT16 op); /* e000/e100 */ + void add_xy_b(UINT16 op); /* e000/e100 */ + void sub_xy_a(UINT16 op); /* e200/e300 */ + void sub_xy_b(UINT16 op); /* e200/e300 */ + void cmp_xy_a(UINT16 op); /* e400/e500 */ + void cmp_xy_b(UINT16 op); /* e400/e500 */ + void cpw_a(UINT16 op); /* e600/e700 */ + void cpw_b(UINT16 op); /* e600/e700 */ + void cvxyl_a(UINT16 op); /* e800/e900 */ + void cvxyl_b(UINT16 op); /* e800/e900 */ + void movx_a(UINT16 op); /* ec00/ed00 */ + void movx_b(UINT16 op); /* ec00/ed00 */ + void movy_a(UINT16 op); /* ee00/ef00 */ + void movy_b(UINT16 op); /* ee00/ef00 */ + void pixt_ri_a(UINT16 op); /* f800/f900 */ + void pixt_ri_b(UINT16 op); /* f800/f900 */ + void pixt_rixy_a(UINT16 op); /* f000/f100 */ + void pixt_rixy_b(UINT16 op); /* f000/f100 */ + void pixt_ir_a(UINT16 op); /* fa00/fb00 */ + void pixt_ir_b(UINT16 op); /* fa00/fb00 */ + void pixt_ii_a(UINT16 op); /* fc00/fd00 */ + void pixt_ii_b(UINT16 op); /* fc00/fd00 */ + void pixt_ixyr_a(UINT16 op); /* f200/f300 */ + void pixt_ixyr_b(UINT16 op); /* f200/f300 */ + void pixt_ixyixy_a(UINT16 op); /* f400/f500 */ + void pixt_ixyixy_b(UINT16 op); /* f400/f500 */ + void drav_a(UINT16 op); /* f600/f700 */ + void drav_b(UINT16 op); /* f600/f700 */ + void abs_a(UINT16 op); /* 0380 */ + void abs_b(UINT16 op); /* 0390 */ + void add_a(UINT16 op); /* 4000/4100 */ + void add_b(UINT16 op); /* 4000/4100 */ + void addc_a(UINT16 op); /* 4200/4200 */ + void addc_b(UINT16 op); /* 4200/4200 */ + void addi_w_a(UINT16 op); /* 0b00 */ + void addi_w_b(UINT16 op); /* 0b10 */ + void addi_l_a(UINT16 op); /* 0b20 */ + void addi_l_b(UINT16 op); /* 0b30 */ + void addk_a(UINT16 op); /* 1000-1300 */ + void addk_b(UINT16 op); /* 1000-1300 */ + void and_a(UINT16 op); /* 5000/5100 */ + void and_b(UINT16 op); /* 5000/5100 */ + void andi_a(UINT16 op); /* 0b80 */ + void andi_b(UINT16 op); /* 0b90 */ + void andn_a(UINT16 op); /* 5200-5300 */ + void andn_b(UINT16 op); /* 5200-5300 */ + void btst_k_a(UINT16 op); /* 1c00-1f00 */ + void btst_k_b(UINT16 op); /* 1c00-1f00 */ + void btst_r_a(UINT16 op); /* 4a00-4b00 */ + void btst_r_b(UINT16 op); /* 4a00-4b00 */ + void clrc(UINT16 op); /* 0320 */ + void cmp_a(UINT16 op); /* 4800/4900 */ + void cmp_b(UINT16 op); /* 4800/4900 */ + void cmpi_w_a(UINT16 op); /* 0b40 */ + void cmpi_w_b(UINT16 op); /* 0b50 */ + void cmpi_l_a(UINT16 op); /* 0b60 */ + void cmpi_l_b(UINT16 op); /* 0b70 */ + void dint(UINT16 op); + void divs_a(UINT16 op); /* 5800/5900 */ + void divs_b(UINT16 op); /* 5800/5900 */ + void divu_a(UINT16 op); /* 5a00/5b00 */ + void divu_b(UINT16 op); /* 5a00/5b00 */ + void eint(UINT16 op); + void exgf0_a(UINT16 op); /* d500 */ + void exgf0_b(UINT16 op); /* d510 */ + void exgf1_a(UINT16 op); /* d700 */ + void exgf1_b(UINT16 op); /* d710 */ + void lmo_a(UINT16 op); /* 6a00/6b00 */ + void lmo_b(UINT16 op); /* 6a00/6b00 */ + void mmfm_a(UINT16 op); /* 09a0 */ + void mmfm_b(UINT16 op); /* 09b0 */ + void mmtm_a(UINT16 op); /* 0980 */ + void mmtm_b(UINT16 op); /* 0990 */ + void mods_a(UINT16 op); /* 6c00/6d00 */ + void mods_b(UINT16 op); /* 6c00/6d00 */ + void modu_a(UINT16 op); /* 6e00/6f00 */ + void modu_b(UINT16 op); /* 6e00/6f00 */ + void mpys_a(UINT16 op); /* 5c00/5d00 */ + void mpys_b(UINT16 op); /* 5c00/5d00 */ + void mpyu_a(UINT16 op); /* 5e00/5e00 */ + void mpyu_b(UINT16 op); /* 5e00/5f00 */ + void neg_a(UINT16 op); /* 03a0 */ + void neg_b(UINT16 op); /* 03b0 */ + void negb_a(UINT16 op); /* 03c0 */ + void negb_b(UINT16 op); /* 03d0 */ + void nop(UINT16 op); /* 0300 */ + void not_a(UINT16 op); /* 03e0 */ + void not_b(UINT16 op); /* 03f0 */ + void or_a(UINT16 op); /* 5400-5500 */ + void or_b(UINT16 op); /* 5400-5500 */ + void ori_a(UINT16 op); /* 0ba0 */ + void ori_b(UINT16 op); /* 0bb0 */ + void rl_k_a(UINT16 op); /* 3000-3300 */ + void rl_k_b(UINT16 op); /* 3000-3300 */ + void rl_r_a(UINT16 op); /* 6800/6900 */ + void rl_r_b(UINT16 op); /* 6800/6900 */ + void setc(UINT16 op); /* 0de0 */ + void setf0(UINT16 op); + void setf1(UINT16 op); + void sext0_a(UINT16 op); /* 0500 */ + void sext0_b(UINT16 op); /* 0510 */ + void sext1_a(UINT16 op); /* 0700 */ + void sext1_b(UINT16 op); /* 0710 */ + void sla_k_a(UINT16 op); /* 2000-2300 */ + void sla_k_b(UINT16 op); /* 2000-2300 */ + void sla_r_a(UINT16 op); /* 6000/6100 */ + void sla_r_b(UINT16 op); /* 6000/6100 */ + void sll_k_a(UINT16 op); /* 2400-2700 */ + void sll_k_b(UINT16 op); /* 2400-2700 */ + void sll_r_a(UINT16 op); /* 6200/6300 */ + void sll_r_b(UINT16 op); /* 6200/6300 */ + void sra_k_a(UINT16 op); /* 2800-2b00 */ + void sra_k_b(UINT16 op); /* 2800-2b00 */ + void sra_r_a(UINT16 op); /* 6400/6500 */ + void sra_r_b(UINT16 op); /* 6400/6500 */ + void srl_k_a(UINT16 op); /* 2c00-2f00 */ + void srl_k_b(UINT16 op); /* 2c00-2f00 */ + void srl_r_a(UINT16 op); /* 6600/6700 */ + void srl_r_b(UINT16 op); /* 6600/6700 */ + void sub_a(UINT16 op); /* 4400/4500 */ + void sub_b(UINT16 op); /* 4400/4500 */ + void subb_a(UINT16 op); /* 4600/4700 */ + void subb_b(UINT16 op); /* 4600/4700 */ + void subi_w_a(UINT16 op); /* 0be0 */ + void subi_w_b(UINT16 op); /* 0bf0 */ + void subi_l_a(UINT16 op); /* 0d00 */ + void subi_l_b(UINT16 op); /* 0d10 */ + void subk_a(UINT16 op); /* 1400-1700 */ + void subk_b(UINT16 op); /* 1400-1700 */ + void xor_a(UINT16 op); /* 5600-5700 */ + void xor_b(UINT16 op); /* 5600-5700 */ + void xori_a(UINT16 op); /* 0bc0 */ + void xori_b(UINT16 op); /* 0bd0 */ + void zext0_a(UINT16 op); /* 0520 */ + void zext0_b(UINT16 op); /* 0530 */ + void zext1_a(UINT16 op); /* 0720 */ + void zext1_b(UINT16 op); /* 0720 */ + void movi_w_a(UINT16 op); + void movi_w_b(UINT16 op); + void movi_l_a(UINT16 op); + void movi_l_b(UINT16 op); + void movk_a(UINT16 op); + void movk_b(UINT16 op); + void movb_rn_a(UINT16 op); /* 8c00-8d00 */ + void movb_rn_b(UINT16 op); /* 8c00-8d00 */ + void movb_nr_a(UINT16 op); /* 8e00-8f00 */ + void movb_nr_b(UINT16 op); /* 8e00-8f00 */ + void movb_nn_a(UINT16 op); /* 9c00-9d00 */ + void movb_nn_b(UINT16 op); /* 9c00-9d00 */ + void movb_r_no_a(UINT16 op); /* ac00-ad00 */ + void movb_r_no_b(UINT16 op); /* ac00-ad00 */ + void movb_no_r_a(UINT16 op); /* ae00-af00 */ + void movb_no_r_b(UINT16 op); /* ae00-af00 */ + void movb_no_no_a(UINT16 op); /* bc00-bd00 */ + void movb_no_no_b(UINT16 op); /* bc00-bd00 */ + void movb_ra_a(UINT16 op); + void movb_ra_b(UINT16 op); + void movb_ar_a(UINT16 op); + void movb_ar_b(UINT16 op); + void movb_aa(UINT16 op); + void move_rr_a(UINT16 op); /* 4c00/d00 */ + void move_rr_b(UINT16 op); /* 4c00/d00 */ + void move_rr_ax(UINT16 op); /* 4e00/f00 */ + void move_rr_bx(UINT16 op); /* 4e00/f00 */ + void move0_rn_a(UINT16 op); /* 8000 */ + void move0_rn_b(UINT16 op); + void move1_rn_a(UINT16 op); + void move1_rn_b(UINT16 op); + void move0_r_dn_a(UINT16 op); /* a000 */ + void move0_r_dn_b(UINT16 op); + void move1_r_dn_a(UINT16 op); + void move1_r_dn_b(UINT16 op); + void move0_r_ni_a(UINT16 op); /* 9000 */ + void move0_r_ni_b(UINT16 op); + void move1_r_ni_a(UINT16 op); + void move1_r_ni_b(UINT16 op); + void move0_nr_a(UINT16 op); /* 8400-500 */ + void move0_nr_b(UINT16 op); /* 8400-500 */ + void move1_nr_a(UINT16 op); /* 8600-700 */ + void move1_nr_b(UINT16 op); /* 8600-700 */ + void move0_dn_r_a(UINT16 op); /* A400-500 */ + void move0_dn_r_b(UINT16 op); /* A400-500 */ + void move1_dn_r_a(UINT16 op); /* A600-700 */ + void move1_dn_r_b(UINT16 op); /* A600-700 */ + void move0_ni_r_a(UINT16 op); /* 9400-500 */ + void move0_ni_r_b(UINT16 op); /* 9400-500 */ + void move1_ni_r_a(UINT16 op); /* 9600-700 */ + void move1_ni_r_b(UINT16 op); /* 9600-700 */ + void move0_nn_a(UINT16 op); /* 8800 */ + void move0_nn_b(UINT16 op); + void move1_nn_a(UINT16 op); + void move1_nn_b(UINT16 op); + void move0_dn_dn_a(UINT16 op); /* a800 */ + void move0_dn_dn_b(UINT16 op); + void move1_dn_dn_a(UINT16 op); + void move1_dn_dn_b(UINT16 op); + void move0_ni_ni_a(UINT16 op); /* 9800 */ + void move0_ni_ni_b(UINT16 op); + void move1_ni_ni_a(UINT16 op); + void move1_ni_ni_b(UINT16 op); + void move0_r_no_a(UINT16 op); /* b000 */ + void move0_r_no_b(UINT16 op); + void move1_r_no_a(UINT16 op); + void move1_r_no_b(UINT16 op); + void move0_no_r_a(UINT16 op); /* b400 */ + void move0_no_r_b(UINT16 op); + void move1_no_r_a(UINT16 op); + void move1_no_r_b(UINT16 op); + void move0_no_ni_a(UINT16 op); /* d000 */ + void move0_no_ni_b(UINT16 op); + void move1_no_ni_a(UINT16 op); + void move1_no_ni_b(UINT16 op); + void move0_no_no_a(UINT16 op); /* b800 */ + void move0_no_no_b(UINT16 op); + void move1_no_no_a(UINT16 op); + void move1_no_no_b(UINT16 op); + void move0_ra_a(UINT16 op); + void move0_ra_b(UINT16 op); + void move1_ra_a(UINT16 op); + void move1_ra_b(UINT16 op); + void move0_ar_a(UINT16 op); + void move0_ar_b(UINT16 op); + void move1_ar_a(UINT16 op); + void move1_ar_b(UINT16 op); + void move0_a_ni_a(UINT16 op); /* d400 */ + void move0_a_ni_b(UINT16 op); /* d410 */ + void move1_a_ni_a(UINT16 op); /* d600 */ + void move1_a_ni_b(UINT16 op); /* d610 */ + void move0_aa(UINT16 op); /* 05c0 */ + void move1_aa(UINT16 op); /* 07c0 */ + void call_a(UINT16 op); /* 0920 */ + void call_b(UINT16 op); /* 0930 */ + void callr(UINT16 op); /* 0d3f */ + void calla(UINT16 op); /* 0d5f */ + void dsj_a(UINT16 op); /* 0d80 */ + void dsj_b(UINT16 op); /* 0d90 */ + void dsjeq_a(UINT16 op); /* 0da0 */ + void dsjeq_b(UINT16 op); /* 0db0 */ + void dsjne_a(UINT16 op); /* 0dc0 */ + void dsjne_b(UINT16 op); /* 0dd0 */ + void dsjs_a(UINT16 op); + void dsjs_b(UINT16 op); + void emu(UINT16 op); /* 0100 */ + void exgpc_a(UINT16 op); /* 0120 */ + void exgpc_b(UINT16 op); /* 0130 */ + void getpc_a(UINT16 op); /* 0140 */ + void getpc_b(UINT16 op); /* 0150 */ + void getst_a(UINT16 op); /* 0180 */ + void getst_b(UINT16 op); /* 0190 */ + void j_UC_0(UINT16 op); + void j_UC_8(UINT16 op); + void j_UC_x(UINT16 op); + void j_P_0(UINT16 op); + void j_P_8(UINT16 op); + void j_P_x(UINT16 op); + void j_LS_0(UINT16 op); + void j_LS_8(UINT16 op); + void j_LS_x(UINT16 op); + void j_HI_0(UINT16 op); + void j_HI_8(UINT16 op); + void j_HI_x(UINT16 op); + void j_LT_0(UINT16 op); + void j_LT_8(UINT16 op); + void j_LT_x(UINT16 op); + void j_GE_0(UINT16 op); + void j_GE_8(UINT16 op); + void j_GE_x(UINT16 op); + void j_LE_0(UINT16 op); + void j_LE_8(UINT16 op); + void j_LE_x(UINT16 op); + void j_GT_0(UINT16 op); + void j_GT_8(UINT16 op); + void j_GT_x(UINT16 op); + void j_C_0(UINT16 op); + void j_C_8(UINT16 op); + void j_C_x(UINT16 op); + void j_NC_0(UINT16 op); + void j_NC_8(UINT16 op); + void j_NC_x(UINT16 op); + void j_EQ_0(UINT16 op); + void j_EQ_8(UINT16 op); + void j_EQ_x(UINT16 op); + void j_NE_0(UINT16 op); + void j_NE_8(UINT16 op); + void j_NE_x(UINT16 op); + void j_V_0(UINT16 op); + void j_V_8(UINT16 op); + void j_V_x(UINT16 op); + void j_NV_0(UINT16 op); + void j_NV_8(UINT16 op); + void j_NV_x(UINT16 op); + void j_N_0(UINT16 op); + void j_N_8(UINT16 op); + void j_N_x(UINT16 op); + void j_NN_0(UINT16 op); + void j_NN_8(UINT16 op); + void j_NN_x(UINT16 op); + void jump_a(UINT16 op); /* 0160 */ + void jump_b(UINT16 op); /* 0170 */ + void popst(UINT16 op); /* 01c0 */ + void pushst(UINT16 op); /* 01e0 */ + void putst_a(UINT16 op); /* 01a0 */ + void putst_b(UINT16 op); /* 01b0 */ + void reti(UINT16 op); /* 0940 */ + void rets(UINT16 op); /* 0960/70 */ + void rev_a(UINT16 op); /* 0020 */ + void rev_b(UINT16 op); /* 0030 */ + void trap(UINT16 op); /* 0900/10 */ + void addxyi_a(UINT16 op); + void addxyi_b(UINT16 op); + void blmove(UINT16 op); + void cexec_l(UINT16 op); + void cexec_s(UINT16 op); + void clip(UINT16 op); + void cmovcg_a(UINT16 op); + void cmovcg_b(UINT16 op); + void cmovcm_f(UINT16 op); + void cmovcm_b(UINT16 op); + void cmovgc_a(UINT16 op); + void cmovgc_b(UINT16 op); + void cmovgc_a_s(UINT16 op); + void cmovgc_b_s(UINT16 op); + void cmovmc_f(UINT16 op); + void cmovmc_f_va(UINT16 op); + void cmovmc_f_vb(UINT16 op); + void cmovmc_b(UINT16 op); + void cmp_k_a(UINT16 op); + void cmp_k_b(UINT16 op); + void cvdxyl_a(UINT16 op); + void cvdxyl_b(UINT16 op); + void cvmxyl_a(UINT16 op); + void cvmxyl_b(UINT16 op); + void cvsxyl_a(UINT16 op); + void cvsxyl_b(UINT16 op); + void exgps_a(UINT16 op); + void exgps_b(UINT16 op); + void fline(UINT16 op); + void fpixeq(UINT16 op); + void fpixne(UINT16 op); + void getps_a(UINT16 op); + void getps_b(UINT16 op); + void idle(UINT16 op); + void linit(UINT16 op); + void mwait(UINT16 op); + void pfill_xy(UINT16 op); + void pixblt_l_m_l(UINT16 op); + void retm(UINT16 op); + void rmo_a(UINT16 op); + void rmo_b(UINT16 op); + void rpix_a(UINT16 op); + void rpix_b(UINT16 op); + void setcdp(UINT16 op); + void setcmp(UINT16 op); + void setcsp(UINT16 op); + void swapf_a(UINT16 op); + void swapf_b(UINT16 op); + void tfill_xy(UINT16 op); + void trapl(UINT16 op); + void vblt_b_l(UINT16 op); + void vfill_l(UINT16 op); + void vlcol(UINT16 op); + int apply_window(const char *inst_name,int srcbpp, UINT32 *srcaddr, XY *dst, int *dx, int *dy); + int compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing); + int compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing); + int compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp); + void memory_w(address_space &space, offs_t offset,UINT16 data); + UINT16 memory_r(address_space &space, offs_t offset); + void shiftreg_w(address_space &space, offs_t offset, UINT16 data); + UINT16 shiftreg_r(address_space &space, offs_t offset); + UINT16 dummy_shiftreg_r(address_space &space, offs_t offset); + UINT32 pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + UINT32 pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix); + void pixblt_1_op0(int src_is_linear, int dst_is_linear); + void pixblt_2_op0(int src_is_linear, int dst_is_linear); + void pixblt_4_op0(int src_is_linear, int dst_is_linear); + void pixblt_8_op0(int src_is_linear, int dst_is_linear); + void pixblt_16_op0(int src_is_linear, int dst_is_linear); + void pixblt_r_1_op0(int src_is_linear, int dst_is_linear); + void pixblt_r_2_op0(int src_is_linear, int dst_is_linear); + void pixblt_r_4_op0(int src_is_linear, int dst_is_linear); + void pixblt_r_8_op0(int src_is_linear, int dst_is_linear); + void pixblt_r_16_op0(int src_is_linear, int dst_is_linear); + void pixblt_b_1_op0(int dst_is_linear); + void pixblt_b_2_op0(int dst_is_linear); + void pixblt_b_4_op0(int dst_is_linear); + void pixblt_b_8_op0(int dst_is_linear); + void pixblt_b_16_op0(int dst_is_linear); + void fill_1_op0(int dst_is_linear); + void fill_2_op0(int dst_is_linear); + void fill_4_op0(int dst_is_linear); + void fill_8_op0(int dst_is_linear); + void fill_16_op0(int dst_is_linear); + void pixblt_1_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_2_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_4_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_8_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_16_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_1_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_2_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_4_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_8_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_16_op0_trans(int src_is_linear, int dst_is_linear); + void pixblt_b_1_op0_trans(int dst_is_linear); + void pixblt_b_2_op0_trans(int dst_is_linear); + void pixblt_b_4_op0_trans(int dst_is_linear); + void pixblt_b_8_op0_trans(int dst_is_linear); + void pixblt_b_16_op0_trans(int dst_is_linear); + void fill_1_op0_trans(int dst_is_linear); + void fill_2_op0_trans(int dst_is_linear); + void fill_4_op0_trans(int dst_is_linear); + void fill_8_op0_trans(int dst_is_linear); + void fill_16_op0_trans(int dst_is_linear); + void pixblt_1_opx(int src_is_linear, int dst_is_linear); + void pixblt_2_opx(int src_is_linear, int dst_is_linear); + void pixblt_4_opx(int src_is_linear, int dst_is_linear); + void pixblt_8_opx(int src_is_linear, int dst_is_linear); + void pixblt_16_opx(int src_is_linear, int dst_is_linear); + void pixblt_r_1_opx(int src_is_linear, int dst_is_linear); + void pixblt_r_2_opx(int src_is_linear, int dst_is_linear); + void pixblt_r_4_opx(int src_is_linear, int dst_is_linear); + void pixblt_r_8_opx(int src_is_linear, int dst_is_linear); + void pixblt_r_16_opx(int src_is_linear, int dst_is_linear); + void pixblt_b_1_opx(int dst_is_linear); + void pixblt_b_2_opx(int dst_is_linear); + void pixblt_b_4_opx(int dst_is_linear); + void pixblt_b_8_opx(int dst_is_linear); + void pixblt_b_16_opx(int dst_is_linear); + void fill_1_opx(int dst_is_linear); + void fill_2_opx(int dst_is_linear); + void fill_4_opx(int dst_is_linear); + void fill_8_opx(int dst_is_linear); + void fill_16_opx(int dst_is_linear); + void pixblt_1_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_2_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_4_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_8_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_16_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_1_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_2_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_4_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_8_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_r_16_opx_trans(int src_is_linear, int dst_is_linear); + void pixblt_b_1_opx_trans(int dst_is_linear); + void pixblt_b_2_opx_trans(int dst_is_linear); + void pixblt_b_4_opx_trans(int dst_is_linear); + void pixblt_b_8_opx_trans(int dst_is_linear); + void pixblt_b_16_opx_trans(int dst_is_linear); + void fill_1_opx_trans(int dst_is_linear); + void fill_2_opx_trans(int dst_is_linear); + void fill_4_opx_trans(int dst_is_linear); + void fill_8_opx_trans(int dst_is_linear); + void fill_16_opx_trans(int dst_is_linear); + void check_interrupt(); + void set_pixel_function(); + void set_raster_op(); + +}; + +/* Host control interface */ +#define TMS34010_HOST_ADDRESS_L 0 +#define TMS34010_HOST_ADDRESS_H 1 +#define TMS34010_HOST_DATA 2 +#define TMS34010_HOST_CONTROL 3 + +/* Use this macro in the memory definitions to specify bit-based addresses */ +#define TOBYTE(bitaddr) ((offs_t)(bitaddr) >> 3) +#define TOWORD(bitaddr) ((offs_t)(bitaddr) >> 4) + +#if 0 +CPU_DISASSEMBLE( tms34010 ); +CPU_DISASSEMBLE( tms34020 ); +#endif + +#endif /* __TMS34010_H__ */ + -- 2.47.3