From b137a3363668454f0eed7f29c94c57c8ffad2e10 Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Wed, 24 Aug 2016 19:13:37 +0300 Subject: [PATCH] More expansion updates. --- cdtv.cpp | 2 + expansion.cpp | 77 +++++---- gfxboard.cpp | 90 ++++++---- include/autoconf.h | 1 + include/memory.h | 9 +- include/uae/mman.h | 11 ++ memory.cpp | 11 +- od-win32/mman.cpp | 398 +++++++++++++++++++++++++++------------------ pci.cpp | 4 +- scsi.cpp | 8 +- 10 files changed, 381 insertions(+), 230 deletions(-) diff --git a/cdtv.cpp b/cdtv.cpp index 150d9757..0cda6394 100644 --- a/cdtv.cpp +++ b/cdtv.cpp @@ -1644,6 +1644,7 @@ bool cdtv_init (struct autoconfig_info *aci) if (aci) { aci->label = dmac_bank.name; + aci->hardwired = true; if (!aci->doinit) { memcpy(aci->autoconfig_raw, dmacmemory, sizeof dmacmemory); return true; @@ -1687,6 +1688,7 @@ bool cdtv_init (struct autoconfig_info *aci) bool cdtvscsi_init(struct autoconfig_info *aci) { aci->parent_name = _T("CDTV DMAC"); + aci->hardwired = true; if (!aci->doinit) return true; cdtvscsi = true; diff --git a/expansion.cpp b/expansion.cpp index 1911bfbd..3cb7fa24 100644 --- a/expansion.cpp +++ b/expansion.cpp @@ -248,6 +248,7 @@ static addrbank*(*expamem_map)(struct autoconfig_info*); static uae_u8 expamem_lo; static uae_u16 expamem_hi; uaecptr expamem_z3_pointer_real, expamem_z3_pointer_uae; +uaecptr expamem_z3_highram_real, expamem_z3_highram_uae; uaecptr expamem_highmem_pointer; uae_u32 expamem_board_size; uaecptr expamem_board_pointer; @@ -360,11 +361,11 @@ static void expamem_init_clear_zero (void) if (currprefs.cpu_model < 68020) { map_banks(&dummy_bank, 0xe8, 1, 0); if (!currprefs.address_space_24) - map_banks(&dummy_bank, 0xff000000 >> 16, 1, 0); + map_banks(&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0); } else { map_banks(&expamem_bank, 0xe8, 1, 0); if (!currprefs.address_space_24) - map_banks(&expamem_bank, 0xff000000 >> 16, 1, 0); + map_banks(&expamemz3_bank, AUTOCONFIG_Z3 >> 16, 1, 0); } expamem_bank_current = NULL; } @@ -444,7 +445,7 @@ static void call_card_init(int index) expamem_init_clear_zero(); map_banks(&expamem_bank, 0xE8, 1, 0); if (!currprefs.address_space_24) - map_banks(&dummy_bank, 0xff000000 >> 16, 1, 0); + map_banks(&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0); expamem_bank_current = NULL; return; } @@ -468,22 +469,22 @@ static void call_card_init(int index) // non-NULL: not using expamem_bank expamem_bank_current = ab; if ((cd->flags & CARD_FLAG_CAN_Z3) && currprefs.cs_z3autoconfig && !currprefs.address_space_24) { - map_banks(&expamemz3_bank, 0xff000000 >> 16, 1, 0); + map_banks(&expamemz3_bank, AUTOCONFIG_Z3 >> 16, 1, 0); map_banks(&dummy_bank, 0xE8, 1, 0); } else { map_banks(&expamem_bank, 0xE8, 1, 0); if (!currprefs.address_space_24) - map_banks(&dummy_bank, 0xff000000 >> 16, 1, 0); + map_banks(&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0); } } else { if ((cd->flags & CARD_FLAG_CAN_Z3) && currprefs.cs_z3autoconfig && !currprefs.address_space_24) { - map_banks(&expamemz3_bank, 0xff000000 >> 16, 1, 0); + map_banks(&expamemz3_bank, AUTOCONFIG_Z3 >> 16, 1, 0); map_banks(&dummy_bank, 0xE8, 1, 0); expamem_bank_current = &expamem_bank; } else { map_banks(&expamem_bank, 0xE8, 1, 0); if (!currprefs.address_space_24) - map_banks(&dummy_bank, 0xff000000 >> 16, 1, 0); + map_banks(&dummy_bank, AUTOCONFIG_Z3 >> 16, 1, 0); expamem_bank_current = NULL; } } @@ -690,7 +691,7 @@ static void REGPARAM2 expamem_bput (uaecptr addr, uae_u32 value) switch (addr & 0xff) { case 0x22: expamem_hi = value & 0x7f; - expamem_board_pointer = 0xe80000 | (expamem_hi * 4096); + expamem_board_pointer = AUTOCONFIG_Z2 | (expamem_hi * 4096); if (expamem_map) { expamem_next(expamem_map(&cards[ecard]->aci), NULL); return; @@ -1700,24 +1701,10 @@ static addrbank * expamem_map_z3fastmem (struct autoconfig_info *aci) { int devnum = aci->devnum; addrbank *ab = &z3fastmem_bank[devnum]; - int z3fs = expamem_board_pointer; - uaecptr *startp = &ab->start; - int start = *startp; - uae_u32 allocated = ab->allocated; + uaecptr z3fs = expamem_board_pointer; uae_u32 size = currprefs.z3fastmem[devnum].size; - if (expamem_z3hack(&currprefs)) { - if (z3fs && start != z3fs) { - write_log (_T("WARNING: Z3MEM mapping changed from $%08x to $%08x\n"), start, z3fs); - map_banks(&dummy_bank, start >> 16, size >> 16, allocated); - *startp = z3fs; - map_banks_z3(ab, start >> 16, size >> 16); - } - } else { - map_banks_z3(ab, z3fs >> 16, size >> 16); - start = z3fs; - *startp = z3fs; - } + map_banks_z3(ab, z3fs >> 16, size >> 16); return ab; } @@ -1805,6 +1792,7 @@ static bool expamem_init_gfxcard (struct autoconfig_info *aci, bool z3) : Z3_SS_MEM_SAME); aci->label = _T("UAE RTG"); + aci->direct_vram = true; if (size < 0x1000000 && z3) code = Z3_MEM_16MB; /* Z3 physical board size is always at least 16M */ @@ -2245,11 +2233,11 @@ static void expansion_parse_autoconfig(struct card_data *cd, const uae_u8 *autoc { uae_u8 *slots = slots_e8; int numslots = sizeof slots_e8; - uaecptr slotaddr = 0xe80000; + uaecptr slotaddr = AUTOCONFIG_Z2; if (slotsize >= 8 || slottype > 0) { slots = slots_20; numslots = sizeof slots_20; - slotaddr = 0x200000; + slotaddr = AUTOCONFIG_Z2_MEM; } for (int i = 0; i < numslots; i++) { if (((slotsize - 1) & i) == 0) { @@ -2305,6 +2293,8 @@ static void reset_ac_data(struct uae_prefs *p) { expamem_z3_pointer_real = Z3BASE_REAL; expamem_z3_pointer_uae = Z3BASE_UAE; + expamem_z3_highram_real = 0; + expamem_z3_highram_uae = 0; expamem_highmem_pointer = 0; if (p->mbresmem_low_size) @@ -2389,7 +2379,7 @@ struct autoconfig_info *expansion_get_autoconfig_by_address(struct uae_prefs *p, { for (int i = 0; i < cardno; i++) { struct card_data *cd = cards[i]; - if (cd->base <= addr && cd->base + cd->size >= addr) + if (addr >= cd->base && addr < cd->base + cd->size) return &cd->aci; } return NULL; @@ -2423,6 +2413,7 @@ struct autoconfig_info *expansion_get_autoconfig_info(struct uae_prefs *p,int ro static void expansion_init_cards(struct uae_prefs *p) { reset_ac_data(p); + for (int i = 0; i < cardno; i++) { bool ok; struct card_data *cd = &cards_set[i]; @@ -2496,7 +2487,9 @@ static int get_order(struct uae_prefs *p, struct card_data *cd) if (!cd) return EXPANSION_ORDER_MAX - 1; if (cd->cst) - return -3; // Accelerator must be always first + return -4; // Accelerator must be always first + if (cd->aci.hardwired) + return -3; if (cd->aci.get_params) { struct expansion_params parms; if (cd->aci.get_params(p, &parms)) @@ -2520,6 +2513,17 @@ static int get_order(struct uae_prefs *p, struct card_data *cd) return EXPANSION_ORDER_MAX - 1; } +bool expansion_can_move(struct uae_prefs *p, int index) +{ + if (index < 0 || index >= cardno) + return false; + struct card_data *cd = cards[index]; + int order1 = get_order(p, cd); + if (order1 < 0 || order1 >= EXPANSION_ORDER_MAX - 1) + return false; + return true; +} + static void expansion_parse_cards(struct uae_prefs *p, bool log) { if (log) @@ -2647,6 +2651,13 @@ static void expansion_parse_cards(struct uae_prefs *p, bool log) expamem_z3_pointer_real += expamem_board_size; expamem_z3_pointer_uae += expamem_board_size; expamem_board_pointer += expamem_board_size; + if ((type & add_memory) || aci->direct_vram) { + if (expamem_z3_pointer_uae > expamem_z3_highram_uae) + expamem_z3_highram_uae = expamem_z3_pointer_uae; + if (expamem_z3_pointer_real > expamem_z3_highram_real) + expamem_z3_highram_real = expamem_z3_pointer_real; + } + } } else { if (log) @@ -2852,6 +2863,8 @@ static void expansion_autoconfig_sort(struct uae_prefs *p) if (cd->zorro != z) continue; int order = get_order(p, cd); + if (cd->aci.hardwired) + order = -1; if (order >= 0) continue; if (testorder > order) { @@ -2913,20 +2926,21 @@ static void expansion_autoconfig_sort(struct uae_prefs *p) cards[new_cardno++] = &cards_set[i]; } for (int i = 0; i < cardno; i++) { + struct autoconfig_info *aci = &cards[i]->aci; tcards[i] = cards[i]; - tcards[i]->aci.can_sort = !cards[i]->aci.parent_of_previous && get_order(p, cards[i]) < EXPANSION_ORDER_MAX - 1 && get_order(p, cards[i]) >= 0; + tcards[i]->aci.can_sort = !aci->hardwired && !aci->parent_of_previous && get_order(p, cards[i]) < EXPANSION_ORDER_MAX - 1 && get_order(p, cards[i]) >= 0; } if (!p->autoconfig_custom_sort) { new_cardno = 0; - // accelerator first + // accelerator and hardwired first for (int idx = 0; idx < cardno; idx++) { struct card_data *cd = tcards[idx]; if (!cd) continue; - if (cd->cst) { + if (cd->cst || cd->aci.hardwired || cd->size == 0) { cards[new_cardno++] = cd; tcards[idx] = NULL; for (int j = idx + 1; j < cardno; j++) { @@ -2938,7 +2952,6 @@ static void expansion_autoconfig_sort(struct uae_prefs *p) } } } - // re-sort by board size for (int idx = 0; idx < cardno; idx++) { struct card_data *cd = tcards[idx]; diff --git a/gfxboard.cpp b/gfxboard.cpp index 7d8f80cb..86eeb7cf 100644 --- a/gfxboard.cpp +++ b/gfxboard.cpp @@ -14,7 +14,8 @@ #define REGDEBUG 0 #define MEMDEBUG 0 #define MEMDEBUGMASK 0x7fffff -#define MEMDEBUGTEST 0x1ff000 +#define MEMDEBUGTEST 0x3fc000 +#define MEMDEBUGCLEAR 0 #define PICASSOIV_DEBUG_IO 0 #if MEMLOGR @@ -182,6 +183,7 @@ struct rtggfxboard int rtg_index; struct rtgboardconfig *rbc; TCHAR memorybankname[40]; + TCHAR memorybanknamenojit[40]; TCHAR wbsmemorybankname[40]; TCHAR lbsmemorybankname[40]; TCHAR regbankname[40]; @@ -241,8 +243,9 @@ struct rtggfxboard }; static struct rtggfxboard rtggfxboards[MAX_RTG_BOARDS]; +static struct rtggfxboard *only_gfx_board; static int rtg_visible = -1; -static int total_active_gfx_boards, only_gfx_board; +static int total_active_gfx_boards; static int vram_ram_a8; static DisplaySurface fakesurface; @@ -669,11 +672,15 @@ bool gfxboard_vsync_handler (void) gb->monswitch_current = gb->monswitch_new; vga_update_size(gb); write_log(_T("GFXBOARD %d ACTIVE=%d\n"), i, gb->monswitch_current); - if (!gfxboard_rtg_enable_initial(i)) { - // Nothing visible and RTG on? Re-enable our display. - if (rtg_visible < 0 && picasso_on) { - gfxboard_toggle(i, 0); + if (gb->monswitch_current) { + if (!gfxboard_rtg_enable_initial(i)) { + // Nothing visible and RTG on? Re-enable our display. + if (rtg_visible < 0 && picasso_on) { + gfxboard_toggle(i, 0); + } } + } else { + picasso_requested_on = false; } } } else { @@ -782,9 +789,9 @@ static void remap_vram (struct rtggfxboard *gb, hwaddr offset0, hwaddr offset1, gb->vram_offset[0] = offset0; gb->vram_offset[1] = offset1; #if VRAMLOG - if (vram_enabled != enabled) + if (gb->vram_enabled != enabled) write_log (_T("VRAM state=%d\n"), enabled); - bool was_vram_offset_enabled = vram_offset_enabled; + bool was_vram_offset_enabled = gb->vram_offset_enabled; #endif gb->vram_enabled = enabled && (gb->vga.vga.sr[0x07] & 0x01); #if 0 @@ -793,7 +800,7 @@ static void remap_vram (struct rtggfxboard *gb, hwaddr offset0, hwaddr offset1, // offset==0 and offset1==0x8000: linear vram mapping gb->vram_offset_enabled = offset0 != 0 || offset1 != 0x8000; #if VRAMLOG - if (gb->vram_offset_enabled || gb->was_vram_offset_enabled) + if (gb->vram_offset_enabled || was_vram_offset_enabled) write_log (_T("VRAM offset %08x and %08x\n"), offset0, offset1); #endif } @@ -1118,7 +1125,6 @@ static uae_u32 gfxboard_lget_vram (struct rtggfxboard *gb, uaecptr addr, int bs) uae_u32 v; if (!gb->vram_enabled) { const MemoryRegionOps *bank = getvgabank (gb, &addr); - addr &= gb->gfxmem_bank->mask; if (bs < 0) { // WORD v = bank->read (&gb->vga, addr + 1, 1) << 24; v |= bank->read (&gb->vga, addr + 0, 1) << 16; @@ -1151,7 +1157,7 @@ static uae_u32 gfxboard_lget_vram (struct rtggfxboard *gb, uaecptr addr, int bs) if (!vram_enabled || vram_offset_enabled) #endif if (memlogr) - write_log (_T("R %08X L %08X BS=%d EN=%d\n"), addr, v, bs, gb->vram_enabled); + write_log (_T("R %08X L %08X BS=%d EN=%d\n"), addr, v, bs, gb->vram_enabled); #endif return v; } @@ -1179,7 +1185,7 @@ static uae_u16 gfxboard_wget_vram (struct rtggfxboard *gb, uaecptr addr, int bs) if (!vram_enabled || vram_offset_enabled) #endif if (memlogr) - write_log (_T("R %08X W %08X BS=%d EN=%d\n"), addr, v, bs, gb->vram_enabled); + write_log (_T("R %08X W %08X BS=%d EN=%d\n"), addr, v, bs, gb->vram_enabled); #endif return v; } @@ -1203,7 +1209,7 @@ static uae_u8 gfxboard_bget_vram (struct rtggfxboard *gb, uaecptr addr, int bs) if (!vram_enabled || vram_offset_enabled) #endif if (memlogr) - write_log (_T("R %08X B %08X BS=0 EN=%d\n"), addr, v, gb->vram_enabled); + write_log (_T("R %08X B %08X BS=0 EN=%d\n"), addr, v, gb->vram_enabled); #endif return v; } @@ -1211,15 +1217,15 @@ static uae_u8 gfxboard_bget_vram (struct rtggfxboard *gb, uaecptr addr, int bs) static void gfxboard_lput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u32 l, int bs) { #if MEMDEBUG - if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && l) - write_log (_T("%08X L %08X\n"), addr, l); + if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && (MEMDEBUGCLEAR || l)) + write_log (_T("%08X L %08X %08X\n"), addr, l, M68K_GETPC); #endif #if MEMLOGW #if MEMLOGINDIRECT if (!vram_enabled || vram_offset_enabled) #endif if (memlogw) - write_log (_T("W %08X L %08X\n"), addr, l); + write_log (_T("W %08X L %08X\n"), addr, l); #endif if (!gb->vram_enabled) { const MemoryRegionOps *bank = getvgabank (gb, &addr); @@ -1254,15 +1260,15 @@ static void gfxboard_lput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u32 l, static void gfxboard_wput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u16 w, int bs) { #if MEMDEBUG - if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && w) - write_log (_T("%08X W %04X\n"), addr, w & 0xffff); + if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && (MEMDEBUGCLEAR || w)) + write_log (_T("%08X W %04X %08X\n"), addr, w & 0xffff, M68K_GETPC); #endif #if MEMLOGW #if MEMLOGINDIRECT if (!vram_enabled || vram_offset_enabled) #endif if (memlogw) - write_log (_T("W %08X W %04X\n"), addr, w & 0xffff); + write_log (_T("W %08X W %04X\n"), addr, w & 0xffff); #endif if (!gb->vram_enabled) { const MemoryRegionOps *bank = getvgabank (gb, &addr); @@ -1284,15 +1290,15 @@ static void gfxboard_wput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u16 w, static void gfxboard_bput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u8 b, int bs) { #if MEMDEBUG - if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && b) - write_log (_T("%08X B %02X\n"), addr, b & 0xff); + if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && (MEMDEBUGCLEAR || b)) + write_log (_T("%08X B %02X %08X\n"), addr, b & 0xff, M68K_GETPC); #endif #if MEMLOGW #if MEMLOGINDIRECT if (!vram_enabled || vram_offset_enabled) #endif if (memlogw) - write_log (_T("W %08X B %02X\n"), addr, b & 0xff); + write_log (_T("W %08X B %02X\n"), addr, b & 0xff); #endif if (!gb->vram_enabled) { const MemoryRegionOps *bank = getvgabank (gb, &addr); @@ -1314,8 +1320,8 @@ static void gfxboard_bput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u8 b, static struct rtggfxboard *lastgetgfxboard; static rtggfxboard *getgfxboard(uaecptr addr) { - if (total_active_gfx_boards == 1) - return &rtggfxboards[only_gfx_board]; + if (only_gfx_board) + return only_gfx_board; if (lastgetgfxboard) { if (addr >= lastgetgfxboard->io_start && addr < lastgetgfxboard->io_end) return lastgetgfxboard; @@ -1473,7 +1479,6 @@ static uae_u32 REGPARAM2 gfxboard_lget_nbsmem (uaecptr addr) addr = fixaddr_bs (gb, addr, 0, &bs); if (addr == -1) return 0; -// activate_debugger(); return gfxboard_lget_vram (gb, addr, bs); } static uae_u32 REGPARAM2 gfxboard_wget_nbsmem (uaecptr addr) @@ -1666,6 +1671,18 @@ static uae_u32 REGPARAM2 gfxboard_bget_mem_autoconfig (uaecptr addr) return v; } +static void copyvrambank(addrbank *dst, const addrbank *src) +{ + dst->start = src->start; + dst->startmask = src->startmask; + dst->mask = src->mask; + dst->allocated = src->allocated; + dst->baseaddr = src->baseaddr; + dst->flags = src->flags; + dst->jit_read_flag = src->jit_read_flag; + dst->jit_write_flag = src->jit_write_flag; +} + static void REGPARAM2 gfxboard_wput_mem_autoconfig (uaecptr addr, uae_u32 b) { struct rtggfxboard *gb = getgfxboard(addr); @@ -1682,6 +1699,7 @@ static void REGPARAM2 gfxboard_wput_mem_autoconfig (uaecptr addr, uae_u32 b) gb->gfxboard_bank_memory.bget = gfxboard_bget_mem; gb->gfxboard_bank_memory.bput = gfxboard_bput_mem; gb->gfxboard_bank_memory.wput = gfxboard_wput_mem; + copyvrambank(&gb->gfxboard_bank_memory, gb->gfxmem_bank); init_board (gb); if (ISP4()) { if (validate_banks_z3(&gb->gfxboard_bank_memory, gb->gfxmem_bank->start >> 16, expamem_board_size >> 16)) { @@ -1724,6 +1742,7 @@ static void REGPARAM2 gfxboard_bput_mem_autoconfig (uaecptr addr, uae_u32 b) addrbank *ab; if (ISP4()) { ab = &gb->gfxboard_bank_nbsmemory; + copyvrambank(ab, gb->gfxmem_bank); map_banks_z2 (ab, b, 0x00200000 >> 16); if (gb->configured_mem <= 0) { gb->configured_mem = b; @@ -1741,8 +1760,11 @@ static void REGPARAM2 gfxboard_bput_mem_autoconfig (uaecptr addr, uae_u32 b) ab = &gb->gfxboard_bank_memory; gb->gfxboard_bank_memory.bget = gfxboard_bget_mem; gb->gfxboard_bank_memory.bput = gfxboard_bput_mem; + gb->gfxboard_bank_memory.wget = gfxboard_wget_mem; + gb->gfxboard_bank_memory.wput = gfxboard_wput_mem; gb->gfxboardmem_start = b << 16; init_board (gb); + copyvrambank(ab, gb->gfxmem_bank); map_banks_z2 (ab, b, gb->board->banksize >> 16); gb->configured_mem = b; gb->mem_start[0] = b << 16; @@ -2537,13 +2559,14 @@ bool gfxboard_init_memory (struct autoconfig_info *aci) gfxboard_init (aci->prefs, gb); total_active_gfx_boards = 0; - only_gfx_board = 0; for (int i = 0; i < MAX_RTG_BOARDS; i++) { if (p->rtgboards[i].rtgmem_size && p->rtgboards[i].rtgmem_type >= GFXBOARD_HARDWARE) { total_active_gfx_boards++; - only_gfx_board = i; } } + only_gfx_board = NULL; + if (total_active_gfx_boards == 1) + only_gfx_board = gb; memset (gb->automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE); @@ -2613,10 +2636,11 @@ bool gfxboard_init_memory (struct autoconfig_info *aci) } } - _stprintf (gb->memorybankname, _T("%s VRAM"), gb->board->name); - _stprintf (gb->wbsmemorybankname, _T("%s VRAM WORDSWAP"), gb->board->name); - _stprintf (gb->lbsmemorybankname, _T("%s VRAM LONGSWAP"), gb->board->name); - _stprintf (gb->regbankname, _T("%s REG"), gb->board->name); + _stprintf(gb->memorybankname, _T("%s VRAM"), gb->board->name); + _stprintf(gb->memorybanknamenojit, _T("%s VRAM NOJIT"), gb->board->name); + _stprintf(gb->wbsmemorybankname, _T("%s VRAM WORDSWAP"), gb->board->name); + _stprintf(gb->lbsmemorybankname, _T("%s VRAM LONGSWAP"), gb->board->name); + _stprintf(gb->regbankname, _T("%s REG"), gb->board->name); memcpy(&gb->gfxboard_bank_memory, &tmpl_gfxboard_bank_memory, sizeof addrbank); memcpy(&gb->gfxboard_bank_wbsmemory, &tmpl_gfxboard_bank_wbsmemory, sizeof addrbank); @@ -2627,7 +2651,7 @@ bool gfxboard_init_memory (struct autoconfig_info *aci) memcpy(&gb->gfxboard_bank_memory_nojit, &tmpl_gfxboard_bank_memory_nojit, sizeof addrbank); gb->gfxboard_bank_memory.name = gb->memorybankname; - gb->gfxboard_bank_memory_nojit.name = gb->memorybankname; + gb->gfxboard_bank_memory_nojit.name = gb->memorybanknamenojit; gb->gfxboard_bank_wbsmemory.name = gb->wbsmemorybankname; gb->gfxboard_bank_lbsmemory.name = gb->lbsmemorybankname; gb->gfxboard_bank_registers.name = gb->regbankname; @@ -2637,6 +2661,7 @@ bool gfxboard_init_memory (struct autoconfig_info *aci) gb->gfxboard_bank_memory.wput = gfxboard_wput_mem_autoconfig; aci->label = gb->board->name; + aci->direct_vram = true; if (gb->rbc->rtgmem_type == GFXBOARD_VGA) { aci->addrbank = &expamem_nonautoconfig; } else { @@ -2681,6 +2706,7 @@ bool gfxboard_init_memory_p4_z2 (struct autoconfig_info *aci) aci->addrbank = &gb->gfxboard_bank_memory; aci->label = gb->board->name; aci->parent_of_previous = true; + aci->direct_vram = true; return true; } diff --git a/include/autoconf.h b/include/autoconf.h index c5bae264..c7c9e152 100644 --- a/include/autoconf.h +++ b/include/autoconf.h @@ -153,6 +153,7 @@ extern struct autoconfig_info *expansion_get_autoconfig_data(struct uae_prefs *p extern struct autoconfig_info *expansion_get_autoconfig_by_address(struct uae_prefs *p, uaecptr addr); extern void expansion_set_autoconfig_sort(struct uae_prefs *p); extern int expansion_autoconfig_move(struct uae_prefs *p, int index, int direction); +extern bool expansion_can_move(struct uae_prefs *p, int index); extern bool alloc_expansion_bank(addrbank *bank, struct autoconfig_info *aci); extern void free_expansion_bank(addrbank *bank); diff --git a/include/memory.h b/include/memory.h index 7c2dead5..11e19c5a 100644 --- a/include/memory.h +++ b/include/memory.h @@ -28,6 +28,10 @@ extern bool jit_direct_compatible_memory; #define Z3BASE_UAE 0x10000000 #define Z3BASE_REAL 0x40000000 +#define AUTOCONFIG_Z2 0x00e80000 +#define AUTOCONFIG_Z2_MEM 0x00200000 +#define AUTOCONFIG_Z3 0xff000000 + #ifdef ADDRESS_SPACE_24BIT #define MEMORY_BANKS 256 #define MEMORY_RANGE_MASK ((1<<24)-1) @@ -141,8 +145,10 @@ struct autoconfig_info const int *parent_romtype; bool parent_of_previous; bool parent_address_space; + bool direct_vram; const TCHAR *parent_name; bool can_sort; + bool hardwired; bool (*get_params)(struct uae_prefs*, struct expansion_params*); bool (*set_params)(struct uae_prefs*, struct expansion_params*); }; @@ -388,6 +394,7 @@ extern bool expamem_z3hack(struct uae_prefs*); extern void set_expamem_z3_hack_mode(int); extern uaecptr expamem_board_pointer, expamem_highmem_pointer; extern uaecptr expamem_z3_pointer_real, expamem_z3_pointer_uae; +extern uae_u32 expamem_z3_highram_real, expamem_z3_highram_uae; extern uae_u32 expamem_board_size; extern uae_u32 last_custom_value1; @@ -725,8 +732,6 @@ extern uae_u32 natmem_reserved_size; extern bool mapped_malloc (addrbank*); extern void mapped_free (addrbank*); -extern void clearexec (void); -extern void mapkick (void); extern void a3000_fakekick (int); extern uaecptr strcpyha_safe (uaecptr dst, const uae_char *src); diff --git a/include/uae/mman.h b/include/uae/mman.h index fa9ea6f1..53fc8cc0 100644 --- a/include/uae/mman.h +++ b/include/uae/mman.h @@ -31,4 +31,15 @@ int uae_shmctl(int shmid, int cmd, struct uae_shmid_ds *buf); #define UAE_IPC_CREAT 0x04 #define UAE_IPC_STAT 0x08 +struct uae_mman_data +{ + uaecptr start; + uae_u32 size; + bool readonly; + uae_u32 readonlysize; + bool maprom; + bool directsupport; +}; +bool uae_mman_info(addrbank *ab, struct uae_mman_data *md); + #endif /* UAE_MMAN_H */ diff --git a/memory.cpp b/memory.cpp index 796b1717..7727ef1c 100644 --- a/memory.cpp +++ b/memory.cpp @@ -157,7 +157,7 @@ static void dummylog (int rw, uaecptr addr, int size, uae_u32 val, int ins) if (illegal_count >= MAX_ILG && MAX_ILG > 0) return; /* ignore Zorro3 expansion space */ - if (addr >= 0xff000000 && addr <= 0xff000200) + if (addr >= AUTOCONFIG_Z3 && addr <= AUTOCONFIG_Z3 + 0x200) return; /* autoconfig and extended rom */ if (addr >= 0xe00000 && addr <= 0xf7ffff) @@ -1690,8 +1690,13 @@ bool mapped_malloc (addrbank *ab) } } - ab->startmask = ab->start; - if ((!needmman () && (!rtgmem || currprefs.cpu_model < 68020)) || (ab->flags & ABFLAG_ALLOCINDIRECT)) { + struct uae_mman_data md; + uaecptr start = ab->start; + if (uae_mman_info(ab, &md)) { + start = md.start; + } + ab->startmask = start; + if (!md.directsupport || (ab->flags & ABFLAG_ALLOCINDIRECT)) { if (!(ab->flags & ABFLAG_ALLOCINDIRECT)) nocanbang (); ab->flags &= ~ABFLAG_DIRECTMAP; diff --git a/od-win32/mman.cpp b/od-win32/mman.cpp index 614d7bac..a9747788 100644 --- a/od-win32/mman.cpp +++ b/od-win32/mman.cpp @@ -22,6 +22,8 @@ #if defined(NATMEM_OFFSET) +#define WIN32_NATMEM_TEST 0 + uae_u32 max_z3fastmem; /* BARRIER is used in case Amiga memory is access across memory banks, @@ -36,12 +38,14 @@ uae_u32 max_z3fastmem; #define MAXZ3MEM64 0xF0000000 static struct uae_shmid_ds shmids[MAX_SHMID]; -uae_u8 *natmem_reserved, *natmem_offset, *natmem_offset_end; +uae_u8 *natmem_reserved, *natmem_offset; uae_u32 natmem_reserved_size; static uae_u8 *p96mem_offset; static int p96mem_size; static uae_u32 p96base_offset; static SYSTEM_INFO si; +static uaecptr start_rtg = 0; +static uaecptr end_rtg = 0; int maxmem; bool jit_direct_compatible_memory; @@ -199,7 +203,9 @@ bool preinit_shm (void) if (natmem_size < 17 * 1024 * 1024) natmem_size = 17 * 1024 * 1024; - //natmem_size = 257 * 1024 * 1024; +#if WIN32_NATMEM_TEST + natmem_size = 336 * 1024 * 1024; +#endif if (natmem_size > 0x80000000) { natmem_size = 0x80000000; @@ -326,10 +332,11 @@ static uae_u8 *va (uae_u32 offset, uae_u32 len, DWORD alloc, DWORD protect) static int doinit_shm (void) { uae_u32 totalsize; - uae_u32 startbarrier, align; + uae_u32 align; uae_u32 z3rtgmem_size; struct rtgboardconfig *rbc = &changed_prefs.rtgboards[0]; struct rtgboardconfig *crbc = &currprefs.rtgboards[0]; + uae_u32 extra = 65536; changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = 0; set_expamem_z3_hack_mode(0); @@ -340,7 +347,6 @@ static int doinit_shm (void) align = 16 * 1024 * 1024 - 1; totalsize = 0x01000000; - startbarrier = changed_prefs.mbresmem_high_size >= 128 * 1024 * 1024 ? (changed_prefs.mbresmem_high_size - 128 * 1024 * 1024) + 16 * 1024 * 1024 : 0; z3rtgmem_size = gfxboard_get_configtype(rbc) == 3 ? rbc->rtgmem_size : 0; @@ -348,39 +354,82 @@ static int doinit_shm (void) totalsize = 0x10000000; totalsize += (changed_prefs.z3chipmem_size + align) & ~align; + start_rtg = 0; + end_rtg = 0; + + int idx = 0; + for (;;) { + struct autoconfig_info *aci = expansion_get_autoconfig_data(&currprefs, idx++); + if (!aci) + break; + if (!aci->addrbank) + continue; + if (aci->direct_vram) { + if (!start_rtg) + start_rtg = aci->start; + end_rtg = aci->start + aci->size; + } + } + + jit_direct_compatible_memory = currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong); + + // choose UAE if requested, blizzard or if jit direct and only UAE mode fits in natmem space. if (changed_prefs.z3_mapping_mode == Z3MAPPING_UAE || cpuboard_memorytype(&changed_prefs) == BOARD_MEMORY_BLIZZARD_12xx || - (expamem_z3_pointer_real + 16 * si.dwPageSize >= natmem_reserved_size && changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO)) { + (expamem_z3_highram_real + extra >= natmem_reserved_size && expamem_z3_highram_real < totalsize && changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO && jit_direct_compatible_memory)) { changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = Z3BASE_UAE; if (changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO) write_log(_T("MMAN: Selected UAE Z3 mapping mode\n")); set_expamem_z3_hack_mode(Z3MAPPING_UAE); - if (expamem_z3_pointer_uae > totalsize) { - totalsize = expamem_z3_pointer_uae; - startbarrier = 0; + if (expamem_z3_highram_uae > totalsize) { + totalsize = expamem_z3_highram_uae; } } else { + if (changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO) + write_log(_T("MMAN: Selected REAL Z3 mapping mode\n")); changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = Z3BASE_REAL; set_expamem_z3_hack_mode(Z3MAPPING_REAL); - if (expamem_z3_pointer_real > totalsize) { - totalsize = expamem_z3_pointer_real; - if (totalsize + 16 * si.dwPageSize >= natmem_reserved_size && expamem_z3_pointer_uae < totalsize) { - write_log(_T("NATMEM: Not enough memory for Z3REAL!\n")); - notify_user(NUMSG_NOMEMORY); - return -1; + if (expamem_z3_highram_real > totalsize && jit_direct_compatible_memory) { + totalsize = expamem_z3_highram_real; + if (totalsize + extra >= natmem_reserved_size) { + jit_direct_compatible_memory = false; + write_log(_T("NATMEM: Not enough direct memory for Z3REAL. Switching off JIT Direct.\n")); } - startbarrier = 0; } } + write_log(_T("Total %uM, HM %uM\n"), totalsize >> 20, expamem_highmem_pointer >> 20); + if (totalsize < expamem_highmem_pointer) totalsize = expamem_highmem_pointer; - if (totalsize > size64 || totalsize + 16 * si.dwPageSize >= natmem_reserved_size) { - write_log(_T("NATMEM: Not enough memory!\n")); - notify_user(NUMSG_NOMEMORY); - return -1; + if (jit_direct_compatible_memory && (totalsize > size64 || totalsize + extra >= natmem_reserved_size)) { + jit_direct_compatible_memory = false; + write_log(_T("NATMEM: Not enough direct memory. Switching off JIT Direct.\n")); } - jit_direct_compatible_memory = true; + // rtg outside of natmem? + if (end_rtg > natmem_reserved_size) { + if (jit_direct_compatible_memory) { + write_log(_T("NATMEM: VRAM outside of natmem (%08x > %08x), switching off JIT Direct.\n"), end_rtg, natmem_reserved_size); + jit_direct_compatible_memory = false; + } + if (end_rtg - start_rtg > natmem_reserved_size) { + write_log(_T("NATMEM: VRAMs don't fit in natmem space! (%08x > %08x)\n"), end_rtg - start_rtg, natmem_reserved_size); + notify_user(NUMSG_NOMEMORY); + return -1; + } + p96base_offset = start_rtg; + p96mem_size = end_rtg - start_rtg; + write_log("NATMEM: rtgbase_offset = %08x, size %08x\n", p96base_offset, p96mem_size); + // adjust p96mem_offset to beginning of natmem + // by subtracting start of original p96mem_offset from natmem_offset + if (p96base_offset >= 0x10000000) { + natmem_offset = natmem_reserved - p96base_offset; + p96mem_offset = natmem_offset + p96base_offset; + } + } else { + start_rtg = 0; + end_rtg = 0; + } expansion_scan_autoconfig(&currprefs, true); #if 0 @@ -470,15 +519,11 @@ static int doinit_shm (void) totalsize, totalsize / (1024 * 1024)); #if 0 if (rbc->rtgmem_size) - write_log (_T("NATMEM: P96 special area: %p-%p (0x%08x %dM)\n"), + write_log (_T("NATMEM: RTG special area: %p-%p (0x%08x %dM)\n"), p96mem_offset, (uae_u8*)p96mem_offset + rbc->rtgmem_size, rbc->rtgmem_size, rbc->rtgmem_size >> 20); #endif canbang = jit_direct_compatible_memory ? 1 : 0; - if (p96mem_size) - natmem_offset_end = p96mem_offset + p96mem_size; - else - natmem_offset_end = natmem_offset + totalsize; } return canbang; @@ -496,6 +541,8 @@ bool init_shm (void) for (int i = 0; i < MAX_RAM_BOARDS; i++) { if (oz3fastmem_size[i] != changed_prefs.z3fastmem[i].size) changed = true; + } + for (int i = 0; i < MAX_RTG_BOARDS; i++) { if (ortgmem_size[i] != changed_prefs.rtgboards[i].rtgmem_size) changed = true; if (ortgmem_type[i] != changed_prefs.rtgboards[i].rtgmem_type) @@ -506,6 +553,8 @@ bool init_shm (void) for (int i = 0; i < MAX_RAM_BOARDS;i++) { oz3fastmem_size[i] = changed_prefs.z3fastmem[i].size; + } + for (int i = 0; i < MAX_RTG_BOARDS; i++) { ortgmem_size[i] = changed_prefs.rtgboards[i].rtgmem_size; ortgmem_type[i] = changed_prefs.rtgboards[i].rtgmem_type; } @@ -611,6 +660,166 @@ STATIC_INLINE uae_key_t find_shmkey (uae_key_t key) return result; } +bool uae_mman_info(addrbank *ab, struct uae_mman_data *md) +{ + bool got = false; + bool readonly = false, maprom = false; + bool directsupport = true; + uaecptr start; + uae_u32 size = ab->allocated; + uae_u32 readonlysize = size; + + if (!_tcscmp(ab->label, _T("*"))) { + start = ab->start; + got = true; + if (expansion_get_autoconfig_by_address(&currprefs, ab->start) && !expansion_get_autoconfig_by_address(&currprefs, ab->start + size)) + size += BARRIER; + } else if (!_tcscmp(ab->label, _T("chip"))) { + start = 0; + got = true; + if (!expansion_get_autoconfig_by_address(&currprefs, 0x00200000) || currprefs.chipmem_size < 2 * 1024 * 1024) + size += BARRIER; + } else if (!_tcscmp(ab->label, _T("kick"))) { + start = 0xf80000; + got = true; + size += BARRIER; + readonly = true; + maprom = true; + } else if (!_tcscmp(ab->label, _T("rom_a8"))) { + start = 0xa80000; + got = true; + readonly = true; + maprom = true; + } else if (!_tcscmp(ab->label, _T("rom_e0"))) { + start = 0xe00000; + got = true; + readonly = true; + maprom = true; + } else if (!_tcscmp(ab->label, _T("rom_f0"))) { + start = 0xf00000; + got = true; + readonly = true; + } else if (!_tcscmp(ab->label, _T("rom_f0_ppc"))) { + // this is flash and also contains IO + start = 0xf00000; + got = true; + readonly = false; + } else if (!_tcscmp(ab->label, _T("rtarea"))) { + start = rtarea_base; + got = true; + readonly = true; + readonlysize = RTAREA_TRAPS; + } else if (!_tcscmp(ab->label, _T("ramsey_low"))) { + start = a3000lmem_bank.start; + if (!a3000hmem_bank.start) + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("csmk1_maprom"))) { + start = 0x07f80000; + got = true; + } else if (!_tcscmp(ab->label, _T("25bitram"))) { + start = 0x01000000; + got = true; + } else if (!_tcscmp(ab->label, _T("ramsey_high"))) { + start = 0x08000000; + got = true; + } else if (!_tcscmp(ab->label, _T("dkb"))) { + start = 0x10000000; + got = true; + } else if (!_tcscmp(ab->label, _T("fusionforty"))) { + start = 0x11000000; + got = true; + } else if (!_tcscmp(ab->label, _T("blizzard_40"))) { + start = 0x40000000; + got = true; + } else if (!_tcscmp(ab->label, _T("blizzard_48"))) { + start = 0x48000000; + got = true; + } else if (!_tcscmp(ab->label, _T("blizzard_68"))) { + start = 0x68000000; + got = true; + } else if (!_tcscmp(ab->label, _T("blizzard_70"))) { + start = 0x70000000; + got = true; + } else if (!_tcscmp(ab->label, _T("cyberstorm"))) { + start = 0x0c000000; + got = true; + } else if (!_tcscmp(ab->label, _T("cyberstormmaprom"))) { + start = 0xfff00000; + got = true; + } else if (!_tcscmp(ab->label, _T("bogo"))) { + start = 0x00C00000; + got = true; + if (currprefs.bogomem_size <= 0x100000) + size += BARRIER; + } else if (!_tcscmp(ab->label, _T("custmem1"))) { + start = currprefs.custom_memory_addrs[0]; + got = true; + } else if (!_tcscmp(ab->label, _T("custmem2"))) { + start = currprefs.custom_memory_addrs[1]; + got = true; + } else if (!_tcscmp(ab->label, _T("hrtmem"))) { + start = 0x00a10000; + got = true; + } else if (!_tcscmp(ab->label, _T("arhrtmon"))) { + start = 0x00800000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("xpower_e2"))) { + start = 0x00e20000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("xpower_f2"))) { + start = 0x00f20000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("nordic_f0"))) { + start = 0x00f00000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("nordic_f4"))) { + start = 0x00f40000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("nordic_f6"))) { + start = 0x00f60000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("superiv_b0"))) { + start = 0x00b00000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("superiv_d0"))) { + start = 0x00d00000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("superiv_e0"))) { + start = 0x00e00000; + size += BARRIER; + got = true; + } else if (!_tcscmp(ab->label, _T("ram_a8"))) { + start = 0x00a80000; + size += BARRIER; + got = true; + } + if (got) { + md->start = start; + md->size = size; + md->readonly = readonly; + md->readonlysize = readonlysize; + md->maprom = maprom; + + if (start_rtg && end_rtg) { + if (start < start_rtg || start + size > end_rtg) + directsupport = false; + } else if (start + size > natmem_reserved_size) { + directsupport = false; + } + md->directsupport = directsupport; + } + return got; +} + void *uae_shmat (addrbank *ab, int shmid, void *shmaddr, int shmflg) { void *result = (void *)-1; @@ -620,7 +829,6 @@ void *uae_shmat (addrbank *ab, int shmid, void *shmaddr, int shmflg) #ifdef NATMEM_OFFSET unsigned int size = shmids[shmid].size; unsigned int readonlysize = size; - struct rtgboardconfig *rbc = &currprefs.rtgboards[0]; if (shmids[shmid].attached) return shmids[shmid].attached; @@ -632,135 +840,13 @@ void *uae_shmat (addrbank *ab, int shmid, void *shmaddr, int shmflg) } if ((uae_u8*)shmaddr < natmem_offset) { - if (!_tcscmp(shmids[shmid].name, _T("*"))) { - shmaddr = natmem_offset + ab->start; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("chip"))) { - shmaddr=natmem_offset; - got = true; - if (!expansion_get_autoconfig_by_address(&currprefs, 0x00200000) || currprefs.chipmem_size < 2 * 1024 * 1024) - size += BARRIER; - } else if(!_tcscmp (shmids[shmid].name, _T("kick"))) { - shmaddr=natmem_offset + 0xf80000; - got = true; - size += BARRIER; - readonly = true; - maprom = true; - } else if(!_tcscmp (shmids[shmid].name, _T("rom_a8"))) { - shmaddr=natmem_offset + 0xa80000; - got = true; - readonly = true; - maprom = true; - } else if(!_tcscmp (shmids[shmid].name, _T("rom_e0"))) { - shmaddr=natmem_offset + 0xe00000; - got = true; - readonly = true; - maprom = true; - } else if(!_tcscmp (shmids[shmid].name, _T("rom_f0"))) { - shmaddr=natmem_offset + 0xf00000; - got = true; - readonly = true; - } else if(!_tcscmp (shmids[shmid].name, _T("rom_f0_ppc"))) { - // this is flash and also contains IO - shmaddr=natmem_offset + 0xf00000; - got = true; - readonly = false; - } else if (!_tcscmp(shmids[shmid].name, _T("rtarea"))) { - shmaddr = natmem_offset + rtarea_base; - got = true; - readonly = true; - readonlysize = RTAREA_TRAPS; - } else if(!_tcscmp (shmids[shmid].name, _T("ramsey_low"))) { - shmaddr=natmem_offset + a3000lmem_bank.start; - if (!a3000hmem_bank.start) - size += BARRIER; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("csmk1_maprom"))) { - shmaddr = natmem_offset + 0x07f80000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("25bitram"))) { - shmaddr = natmem_offset + 0x01000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("ramsey_high"))) { - shmaddr = natmem_offset + 0x08000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("dkb"))) { - shmaddr = natmem_offset + 0x10000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("fusionforty"))) { - shmaddr = natmem_offset + 0x11000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_40"))) { - shmaddr = natmem_offset + 0x40000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_48"))) { - shmaddr = natmem_offset + 0x48000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_68"))) { - shmaddr = natmem_offset + 0x68000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_70"))) { - shmaddr = natmem_offset + 0x70000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("cyberstorm"))) { - shmaddr = natmem_offset + 0x0c000000; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("cyberstormmaprom"))) { - shmaddr = natmem_offset + 0xfff00000; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("bogo"))) { - shmaddr=natmem_offset+0x00C00000; - got = true; - if (currprefs.bogomem_size <= 0x100000) - size += BARRIER; - } else if(!_tcscmp (shmids[shmid].name, _T("custmem1"))) { - shmaddr=natmem_offset + currprefs.custom_memory_addrs[0]; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("custmem2"))) { - shmaddr=natmem_offset + currprefs.custom_memory_addrs[1]; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("hrtmem"))) { - shmaddr=natmem_offset + 0x00a10000; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("arhrtmon"))) { - shmaddr=natmem_offset + 0x00800000; - size += BARRIER; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("xpower_e2"))) { - shmaddr=natmem_offset + 0x00e20000; - size += BARRIER; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("xpower_f2"))) { - shmaddr=natmem_offset + 0x00f20000; - size += BARRIER; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("nordic_f0"))) { - shmaddr=natmem_offset + 0x00f00000; - size += BARRIER; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("nordic_f4"))) { - shmaddr=natmem_offset + 0x00f40000; - size += BARRIER; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("nordic_f6"))) { - shmaddr=natmem_offset + 0x00f60000; - size += BARRIER; - got = true; - } else if(!_tcscmp(shmids[shmid].name, _T("superiv_b0"))) { - shmaddr=natmem_offset + 0x00b00000; - size += BARRIER; - got = true; - } else if(!_tcscmp (shmids[shmid].name, _T("superiv_d0"))) { - shmaddr=natmem_offset + 0x00d00000; - size += BARRIER; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("superiv_e0"))) { - shmaddr = natmem_offset + 0x00e00000; - size += BARRIER; - got = true; - } else if (!_tcscmp(shmids[shmid].name, _T("ram_a8"))) { - shmaddr = natmem_offset + 0x00a80000; - size += BARRIER; + struct uae_mman_data md; + if (uae_mman_info(ab, &md)) { + shmaddr = natmem_offset + md.start; + size = md.size; + readonlysize = md.readonlysize; + readonly = md.readonly; + maprom = md.maprom; got = true; } } @@ -796,7 +882,7 @@ void *uae_shmat (addrbank *ab, int shmid, void *shmaddr, int shmflg) shmids[shmid].attached = result; write_log (_T("%p: VA %08lX - %08lX %x (%dk) ok (%p)%s\n"), shmaddr, (uae_u8*)shmaddr - natmem_offset, (uae_u8*)shmaddr - natmem_offset + size, - size, size >> 10, shmaddr, p96special ? _T(" P96") : _T("")); + size, size >> 10, shmaddr, p96special ? _T(" RTG") : _T("")); } } return result; diff --git a/pci.cpp b/pci.cpp index 69c9970b..791722f8 100644 --- a/pci.cpp +++ b/pci.cpp @@ -225,7 +225,7 @@ static void create_config_data(struct pci_board_state *s) static struct pci_bridge *get_pci_bridge(uaecptr addr) { - if (addr < 0x10000 || (addr & 0xffff0000) == 0xe80000 || (addr & 0xff000000) == 0xff000000) { + if (addr < 0x10000 || (addr & 0xffff0000) == AUTOCONFIG_Z2 || (addr & 0xff000000) == AUTOCONFIG_Z3) { for (int i = 0; i < PCI_BRIDGE_MAX; i++) { struct pci_bridge *pcib = bridges[i]; if (pcib && pcib->configured == 0) { @@ -255,7 +255,7 @@ static struct pci_bridge *get_pci_bridge(uaecptr addr) static struct pci_bridge *get_pci_bridge_2(uaecptr addr) { - if (addr < 0x10000 || (addr & 0xffff0000) == 0xe80000 || (addr & 0xff000000) == 0xff000000) { + if (addr < 0x10000 || (addr & 0xffff0000) == AUTOCONFIG_Z2 || (addr & 0xff000000) == AUTOCONFIG_Z3) { for (int i = 0; i < PCI_BRIDGE_MAX; i++) { struct pci_bridge *pcib = bridges[i]; if (pcib && pcib->configured_2 == 0) { diff --git a/scsi.cpp b/scsi.cpp index 730f5330..d56f058c 100644 --- a/scsi.cpp +++ b/scsi.cpp @@ -847,7 +847,7 @@ static struct soft_scsi *getscsiboard(uaecptr addr) return s; if (s->baseaddress2 && (addr & ~s->board_mask) == s->baseaddress2) return s; - if (s->baseaddress == 0xe80000 && addr < 65536) + if (s->baseaddress == AUTOCONFIG_Z2 && addr < 65536) return s; } return NULL; @@ -2834,7 +2834,7 @@ static void ncr80_bput2(struct soft_scsi *ncr, uaecptr addr, uae_u32 val, int si if (addr == 0x22) { // box - ncr->baseaddress = 0xe80000 + ((val & 0x7f) * 4096); + ncr->baseaddress = AUTOCONFIG_Z2 + ((val & 0x7f) * 4096); map_banks_z2(ncr->bank, ncr->baseaddress >> 16, 1); expamem_next(ncr->bank, NULL); } else if (addr == 0x1020) { @@ -3613,6 +3613,8 @@ static void expansion_add_protoautoconfig_board(uae_u8 *p, int board, uae_u16 ma bool tecmar_init(struct autoconfig_info *aci) { static const uae_u8 ac[16] = { 0x40, 0xff, 0, 0, 1001 >> 8, (uae_u8)1001 }; + + aci->hardwired = true; if (!aci->doinit) { aci->autoconfigp = ac; return true; @@ -3638,7 +3640,7 @@ bool tecmar_init(struct autoconfig_info *aci) memset(tecmar_clock_regs, 0, sizeof tecmar_clock_regs); tecmar_clock_regs[11] = 0x04 | 0x02 | 0x01; scsi->configured = true; - scsi->baseaddress = 0xe80000; + scsi->baseaddress = AUTOCONFIG_Z2; aci->addrbank = scsi->bank; return true; } -- 2.47.3