From f4e2acb43750317cabbebeb714140898e9b5b04d Mon Sep 17 00:00:00 2001 From: Toni Wilen Date: Sat, 31 Mar 2007 18:56:23 +0300 Subject: [PATCH] imported winuaesrc1420b3.zip --- fpp.c | 78 +++++++++++++------ gencpu.c | 9 ++- include/newcpu.h | 1 + include/options.h | 1 + include/readcpu.h | 2 +- inputdevice.c | 2 +- main.c | 2 +- newcpu.c | 144 ++++++++++++++++++++++++++++------- od-win32/picasso96_win.c | 4 +- od-win32/resources/winuae.rc | 2 +- od-win32/win32.h | 4 +- od-win32/win32gui.c | 2 +- od-win32/winuaechangelog.txt | 19 +++++ readcpu.c | 3 +- savestate.c | 74 ++++++++++++------ table68k | 5 +- 16 files changed, 262 insertions(+), 90 deletions(-) diff --git a/fpp.c b/fpp.c index ee9ef2d3..aaadd638 100755 --- a/fpp.c +++ b/fpp.c @@ -39,6 +39,39 @@ STATIC_INLINE int isinrom (void) return (munge24 (m68k_getpc (®s)) & 0xFFF80000) == 0xF80000; } +static void fpu_op_illg (uae_u32 opcode, struct regstruct *regs, int pcoffset) +{ + if ((currprefs.cpu_model == 68060 && (currprefs.fpu_model == 0 || (regs->pcr & 2))) + || (currprefs.cpu_model == 68040 && currprefs.fpu_model == 0)) { + /* 68040 unimplemented/68060 FPU disabled exception. + * Line F exception with different stack frame.. */ + uaecptr newpc = m68k_getpc(regs); + uaecptr oldpc = newpc - pcoffset; + MakeSR(regs); + if (!regs->s) { + regs->usp = m68k_areg(regs, 7); + m68k_areg(regs, 7) = regs->isp; + } + regs->s = 1; + m68k_areg(regs, 7) -= 4; + put_long (m68k_areg(regs, 7), oldpc); + m68k_areg(regs, 7) -= 4; + put_long (m68k_areg(regs, 7), oldpc); + m68k_areg(regs, 7) -= 2; + put_word (m68k_areg(regs, 7), 0x4000 + 11 * 4); + m68k_areg(regs, 7) -= 4; + put_long (m68k_areg(regs, 7), newpc); + m68k_areg(regs, 7) -= 2; + put_word (m68k_areg(regs, 7), regs->sr); + write_log("68040/060 FPU disabled exception PC=%x\n", newpc); + newpc = get_long (regs->vbr + 11 * 4); + m68k_setpc(regs, newpc); + set_special(regs, SPCFLAG_END_COMPILE); + return; + } + op_illg (opcode, regs); +} + static uae_u32 xhex_pi[] ={0x2168c235, 0xc90fdaa2, 0x4000}; uae_u32 xhex_exp_1[] ={0xa2bb4a9a, 0xadf85458, 0x4000}; static uae_u32 xhex_l2_e[] ={0x5c17f0bc, 0xb8aa3b29, 0x3fff}; @@ -736,8 +769,7 @@ void fdbcc_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra) #endif cc = fpp_cond (opcode, extra & 0x3f); if (cc == -1 || !isfpu(regs)) { - m68k_setpc (regs, pc - 4); - op_illg (opcode, regs); + fpu_op_illg (opcode, regs, 4); } else if (!cc) { int reg = opcode & 0x7; @@ -757,10 +789,10 @@ void fscc_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra) if (!isinrom ()) write_log ("fscc_opp at %08lx\n", m68k_getpc (regs)); #endif + cc = fpp_cond (opcode, extra & 0x3f); - if (cc == -1 || !isfpu(regs)) { - m68k_setpc (regs, m68k_getpc (regs) - 4); - op_illg (opcode, regs); + if (cc == -1 || !isfpu(regs)) { + fpu_op_illg (opcode, regs, 4); } else if ((opcode & 0x38) == 0) { m68k_dreg (regs, opcode & 7) = (m68k_dreg (regs, opcode & 7) & ~0xff) | (cc ? 0xff : 0x00); } else { @@ -782,8 +814,7 @@ void ftrapcc_opp (uae_u32 opcode, struct regstruct *regs, uaecptr oldpc) #endif cc = fpp_cond (opcode, opcode & 0x3f); if (cc == -1 || !isfpu(regs)) { - m68k_setpc (regs, oldpc); - op_illg (opcode, regs); + fpu_op_illg (opcode, regs, m68k_getpc(regs) - oldpc); } if (cc) Exception (7, regs, oldpc - 2); @@ -799,8 +830,7 @@ void fbcc_opp (uae_u32 opcode, struct regstruct *regs, uaecptr pc, uae_u32 extra #endif cc = fpp_cond (opcode, opcode & 0x3f); if (cc == -1 || !isfpu(regs)) { - m68k_setpc (regs, pc); - op_illg (opcode, regs); + fpu_op_illg (opcode, regs, m68k_getpc(regs) - pc); } else if (cc) { if ((opcode & 0x40) == 0) extra = (uae_s32) (uae_s16) extra; @@ -819,9 +849,8 @@ void fsave_opp (uae_u32 opcode, struct regstruct *regs) if (!isinrom ()) write_log ("fsave_opp at %08lx\n", m68k_getpc (regs)); #endif - if (get_fp_ad (opcode, &ad) == 0 || !isfpu(regs)) { - m68k_setpc (regs, m68k_getpc (regs) - 2); - op_illg (opcode, regs); + if (!isfpu (regs) || get_fp_ad (opcode, &ad) == 0) { + fpu_op_illg (opcode, regs, 2); return; } @@ -889,9 +918,8 @@ void frestore_opp (uae_u32 opcode, struct regstruct *regs) if (!isinrom ()) write_log ("frestore_opp at %08lx\n", m68k_getpc (regs)); #endif - if (get_fp_ad (opcode, &ad) == 0 || !isfpu(regs)) { - m68k_setpc (regs, m68k_getpc (regs) - 2); - op_illg (opcode, regs); + if (!isfpu(regs) || get_fp_ad (opcode, &ad) == 0) { + fpu_op_illg (opcode, regs, 2); return; } @@ -980,7 +1008,7 @@ void fpp_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra) #endif if (!isfpu(regs)) { m68k_setpc (regs, m68k_getpc (regs) - 4); - op_illg (opcode, regs); + fpu_op_illg (opcode, regs, 4); return; } @@ -1536,13 +1564,10 @@ void fpp_opp (uae_u32 opcode, struct regstruct *regs, uae_u16 extra) uae_u8 *restore_fpu (uae_u8 *src) { int i; + uae_u32 flags; changed_prefs.fpu_model = currprefs.fpu_model = restore_u32(); - restore_u32 (); - if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { - currprefs.cpu_level = 4; - init_m68k (); - } + flags = restore_u32 (); changed_prefs.cpu_level = currprefs.cpu_level; for (i = 0; i < 8; i++) { uae_u32 w1 = restore_u32 (); @@ -1553,6 +1578,11 @@ uae_u8 *restore_fpu (uae_u8 *src) regs.fpcr = restore_u32 (); regs.fpsr = restore_u32 (); regs.fpiar = restore_u32 (); + if (flags & 0x80000000) { + restore_u32(); + restore_u32(); + } + write_log("FPU=%d\n", currprefs.fpu_model); return src; } @@ -1567,9 +1597,9 @@ uae_u8 *save_fpu (int *len, uae_u8 *dstptr) if (dstptr) dstbak = dst = dstptr; else - dstbak = dst = malloc(4+4+8*10+4+4+4); + dstbak = dst = malloc(4+4+8*10+4+4+4+4+4); save_u32 (currprefs.fpu_model); - save_u32 (0); + save_u32 (0x80000000); for (i = 0; i < 8; i++) { uae_u32 w1, w2, w3; from_exten (regs.fp[i], &w1, &w2, &w3); @@ -1580,6 +1610,8 @@ uae_u8 *save_fpu (int *len, uae_u8 *dstptr) save_u32 (regs.fpcr); save_u32 (regs.fpsr); save_u32 (regs.fpiar); + save_u32 (-1); + save_u32 (0); *len = dst - dstbak; return dstbak; } diff --git a/gencpu.c b/gencpu.c index b34560d3..2272c6fe 100755 --- a/gencpu.c +++ b/gencpu.c @@ -2860,10 +2860,15 @@ static void gen_opcode (unsigned long int opcode) sync_m68k_pc (); printf ("\tmmu_op(opcode, regs, extra);\n"); break; - case i_MMUOP30: + case i_MMUOP30A: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0); sync_m68k_pc (); - printf ("\tmmu_op30(opcode, regs, extra);\n"); + printf ("\tmmu_op30(opcode, regs, 1, extra);\n"); + break; + case i_MMUOP30B: + genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0); + sync_m68k_pc (); + printf ("\tmmu_op30(opcode, regs, 0, 0);\n"); break; default: abort (); diff --git a/include/newcpu.h b/include/newcpu.h index 0044a115..08aba6ca 100755 --- a/include/newcpu.h +++ b/include/newcpu.h @@ -310,6 +310,7 @@ extern int getDivu68kCycles(uae_u32 dividend, uae_u16 divisor); extern int getDivs68kCycles(uae_s32 dividend, uae_s16 divisor); extern void mmu_op (uae_u32, struct regstruct *regs, uae_u16); +extern void mmu_op30 (uae_u32, struct regstruct *regs, int, uae_u16); extern void fpp_opp (uae_u32, struct regstruct *regs, uae_u16); extern void fdbcc_opp (uae_u32, struct regstruct *regs, uae_u16); diff --git a/include/options.h b/include/options.h index 64e63fa7..c352fc5e 100755 --- a/include/options.h +++ b/include/options.h @@ -355,6 +355,7 @@ extern int cmdlineparser (char *s, char *outp[], int max); extern int cfgfile_configuration_change(int); extern void fixup_prefs_dimensions (struct uae_prefs *prefs); extern void fixup_prefs (struct uae_prefs *prefs); +extern void fixup_cpu (struct uae_prefs *prefs); extern void check_prefs_changed_custom (void); extern void check_prefs_changed_cpu (void); diff --git a/include/readcpu.h b/include/readcpu.h index 1a1d7d05..bf6a5597 100755 --- a/include/readcpu.h +++ b/include/readcpu.h @@ -28,7 +28,7 @@ ENUMDECL { i_PACK, i_UNPK, i_TAS, i_BKPT, i_CALLM, i_RTM, i_TRAPcc, i_MOVES, i_FPP, i_FDBcc, i_FScc, i_FTRAPcc, i_FBcc, i_FSAVE, i_FRESTORE, i_CINVL, i_CINVP, i_CINVA, i_CPUSHL, i_CPUSHP, i_CPUSHA, i_MOVE16, - i_MMUOP30, i_MMUOP + i_MMUOP30A, i_MMUOP30B, i_MMUOP } ENUMNAME (instrmnem); extern struct mnemolookup { diff --git a/inputdevice.c b/inputdevice.c index 24d60dad..349d4e98 100755 --- a/inputdevice.c +++ b/inputdevice.c @@ -1845,7 +1845,7 @@ void inputdevice_vsync (void) } } mouseupdate (100); - inputdelay = uaerand () % (maxvpos == 0 ? 1 : maxvpos - 1); + inputdelay = uaerand () % (maxvpos <= 1 ? 1 : maxvpos - 1); idev[IDTYPE_MOUSE].read (); input_read = 1; input_vpos = 0; diff --git a/main.c b/main.c index ef4c3df5..7a378bb4 100755 --- a/main.c +++ b/main.c @@ -120,7 +120,7 @@ void fixup_prefs_dimensions (struct uae_prefs *prefs) fixup_prefs_dim2(&prefs->gfx_size_win); } -static void fixup_cpu(struct uae_prefs *p) +void fixup_cpu(struct uae_prefs *p) { p->cpu_level = 0; switch(p->cpu_model) diff --git a/newcpu.c b/newcpu.c index 62b0cc4a..c7a790bd 100755 --- a/newcpu.c +++ b/newcpu.c @@ -6,6 +6,9 @@ * (c) 1995 Bernd Schmidt */ +//#define MOVEC_DEBUG +//#define MMUOP_DEBUG + #include "sysconfig.h" #include "sysdeps.h" @@ -75,6 +78,7 @@ extern uae_u32 get_fpsr(void); #define COUNT_INSTRS 0 #define MC68060_PCR 0x04300100 +#define MC68EC060_PCR 0x04310100 #if COUNT_INSTRS static unsigned long int instrcount[65536]; @@ -245,21 +249,20 @@ static void update_68k_cycles (void) void check_prefs_changed_cpu (void) { - if (currprefs.cpu_level != changed_prefs.cpu_level - || currprefs.cpu_model != changed_prefs.cpu_model + if (currprefs.cpu_model != changed_prefs.cpu_model || currprefs.fpu_model != changed_prefs.fpu_model || currprefs.cpu_compatible != changed_prefs.cpu_compatible || currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) { - if (!currprefs.cpu_compatible && changed_prefs.cpu_compatible) - fill_prefetch_slow (®s); - + fixup_cpu (&changed_prefs); currprefs.cpu_level = changed_prefs.cpu_level; currprefs.cpu_model = changed_prefs.cpu_model; currprefs.fpu_model = changed_prefs.fpu_model; currprefs.cpu_compatible = changed_prefs.cpu_compatible; currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact; currprefs.blitter_cycle_exact = changed_prefs.cpu_cycle_exact; + if (!currprefs.cpu_compatible && changed_prefs.cpu_compatible) + fill_prefetch_slow (®s); build_cpufunctbl (); } if (currprefs.m68k_speed != changed_prefs.m68k_speed) { @@ -276,6 +279,8 @@ void init_m68k (void) { int i; + fixup_cpu (&changed_prefs); + fixup_cpu (&currprefs); update_68k_cycles (); for (i = 0 ; i < 256 ; i++) { @@ -1103,7 +1108,7 @@ void Interrupt (int nr) do_interrupt (nr, ®s); } -static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp, buscr; +static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tcr, mmusr, urp, srp, buscr; #ifndef CPUEMU_68000_ONLY @@ -1123,7 +1128,7 @@ static int movec_illg (int regno) return 0; return 1; } else if (currprefs.cpu_model == 68020) { - if (regno == 3) return 1; /* 68040 only */ + if (regno == 3) return 1; /* 68040/060 only */ /* 4 is >=68040, but 0x804 is in 68020 */ if (regno2 < 4 || regno == 0x804) return 0; @@ -1180,12 +1185,16 @@ int m68k_move2c (int regno, uae_u32 *regp) #endif } break; - case 3: tc = *regp & 0xc000; break; - /* Mask out fields that should be zero. */ + /* 68040/060 only */ + case 3: tcr = *regp & (currprefs.cpu_model == 68060 ? 0xfffe : 0xc000); + break; + + /* no differences between 68040 and 68060 */ case 4: itt0 = *regp & 0xffffe364; break; case 5: itt1 = *regp & 0xffffe364; break; case 6: dtt0 = *regp & 0xffffe364; break; case 7: dtt1 = *regp & 0xffffe364; break; + /* 68060 only */ case 8: buscr = *regp & 0xf0000000; break; case 0x800: regs.usp = *regp; break; @@ -1193,15 +1202,19 @@ int m68k_move2c (int regno, uae_u32 *regp) case 0x802: caar = *regp & 0xfc; break; case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(®s, 7) = regs.msp; break; case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(®s, 7) = regs.isp; break; + /* 68040 only */ case 0x805: mmusr = *regp; break; + /* 68040/060 */ case 0x806: urp = *regp; break; case 0x807: srp = *regp; break; case 0x808: { uae_u32 opcr = regs.pcr; - regs.pcr = (*regp & (0x40 | 2 | 1)) | MC68060_PCR; + regs.pcr &= ~(0x40 | 2 | 1); + regs.pcr |= (*regp) & (0x40 | 2 | 1); if (((opcr ^ regs.pcr) & 2) == 2) { write_log("68060 FPU state: %s\n", regs.pcr & 2 ? "disabled" : "enabled"); + /* flush possible already translated FPU instructions */ flush_icache(2); } } @@ -1227,7 +1240,7 @@ int m68k_movec2 (int regno, uae_u32 *regp) case 0: *regp = regs.sfc; break; case 1: *regp = regs.dfc; break; case 2: *regp = cacr; break; - case 3: *regp = tc; break; + case 3: *regp = tcr; break; case 4: *regp = itt0; break; case 5: *regp = itt1; break; case 6: *regp = dtt0; break; @@ -1242,7 +1255,7 @@ int m68k_movec2 (int regno, uae_u32 *regp) case 0x805: *regp = mmusr; break; case 0x806: *regp = urp; break; case 0x807: *regp = srp; break; - case 0x808: *regp = MC68060_PCR | regs.pcr; break; + case 0x808: *regp = regs.pcr; break; default: op_illg (0x4E7A, ®s); @@ -1548,13 +1561,15 @@ void m68k_reset (void) #endif caar = cacr = 0; itt0 = itt1 = dtt0 = dtt1 = 0; - tc = mmusr = urp = srp = buscr = 0; + tcr = mmusr = urp = srp = buscr = 0; /* 68060 FPU is not compatible with 68040, * 68060 accelerators' boot ROM disables the FPU */ - if (currprefs.cpu_model == 68060) + regs.pcr = 0; + if (currprefs.cpu_model == 68060) { + regs.pcr = currprefs.fpu_model ? MC68060_PCR : MC68EC060_PCR; regs.pcr |= 2; - + } fill_prefetch_slow (®s); } @@ -1638,46 +1653,64 @@ unsigned long REGPARAM2 op_illg (uae_u32 opcode, struct regstruct *regs) } #ifdef CPUEMU_0 -void mmu_op30(uae_u32 opcode, struct regstruct *regs, uae_u16 extra) +void mmu_op30(uae_u32 opcode, struct regstruct *regs, int isextra, uae_u16 extra) { if (currprefs.cpu_model != 68030) { - m68k_setpc (regs, m68k_getpc (regs) - 2); +#ifdef MMUOP_DEBUG + write_log("Unknown 68030 MMU OP %04.4X\n", opcode); +#endif + m68k_setpc (regs, m68k_getpc (regs) - isextra ? 4 : 2); op_illg (opcode, regs); return; } - write_log("MMU030: %04.4x\n", opcode); + if (isextra) + m68k_setpc (regs, m68k_getpc (regs) + 2); +#ifdef MMUOP_DEBUG + write_log("MMU030: %04.4x PC=%x\n", opcode, m68k_getpc(regs)); +#endif return; } void mmu_op(uae_u32 opcode, struct regstruct *regs, uae_u16 extra) { -#ifdef MOVEC_DEBUG +#ifdef MMUOP_DEBUG write_log("mmu_op %04.4x\n", opcode); #endif if ((opcode & 0xFE0) == 0x0500) { /* PFLUSH */ mmusr = 0; - //write_log ("PFLUSH @$%lx\n", m68k_getpc()); +#ifdef MMUOP_DEBUG + write_log ("PFLUSH @$%lx\n", m68k_getpc(regs)); +#endif return; } else if ((opcode & 0x0FD8) == 0x548) { if (currprefs.cpu_model < 68060) { /* PTEST not in 68060 */ /* PTEST */ - //write_log ("PTEST @$%lx\n", m68k_getpc()); +#ifdef MMUOP_DEBUG + write_log ("PTEST @$%lx\n", m68k_getpc(regs)); +#endif return; } } else if ((opcode & 0x0FB8) == 0x588) { /* PLPA */ if (currprefs.cpu_model == 68060) { +#ifdef MMUOP_DEBUG write_log("PLPA\n"); +#endif return; } } else if (opcode == 0xff00 && extra == 0x01c0) { /* LPSTOP */ if (currprefs.cpu_model == 68060) { +#ifdef MMUOP_DEBUG write_log("LPSTOP\n"); +#endif return; } } +#ifdef MMUOP_DEBUG + write_log("Unknown MMU OP\n"); +#endif m68k_setpc (regs, m68k_getpc (regs) - 2); op_illg (opcode, regs); } @@ -2515,7 +2548,7 @@ static uae_u32 val_move2c (int regno) case 0: return regs.sfc; case 1: return regs.dfc; case 2: return cacr; - case 3: return tc; + case 3: return tcr; case 4: return itt0; case 5: return itt1; case 6: return dtt0; @@ -2529,7 +2562,7 @@ static uae_u32 val_move2c (int regno) case 0x805: return mmusr; case 0x806: return urp; case 0x807: return srp; - case 0x808: return regs.pcr | MC68060_PCR; + case 0x808: return regs.pcr; default: return 0; } } @@ -2645,6 +2678,32 @@ uae_u8 *restore_cpu (uae_u8 *src) if (changed_prefs.m68k_speed == 0) currprefs.m68k_speed = changed_prefs.m68k_speed = -1; } + if (model >= 68030) { + restore_u32(); + restore_u32(); + restore_u16(); + restore_u32(); + restore_u32(); + } + if (model >= 68040) { + itt0 = restore_u32(); + itt1 = restore_u32(); + dtt0 = restore_u32(); + dtt1 = restore_u32(); + tcr = restore_u32(); + urp = restore_u32(); + srp = restore_u32(); + } + if (model >= 68060) { + buscr = restore_u32(); + regs.pcr = restore_u32(); + } + if (flags & 0x80000000) { + int khz = restore_u32(); + restore_u32(); + if (khz > 0 && khz < 800000) + currprefs.m68k_speed = changed_prefs.m68k_speed = 0; + } write_log ("CPU %d%s%03d, PC=%08.8X\n", model / 1000, flags & 1 ? "EC" : "", model % 1000, regs.pc); @@ -2657,21 +2716,20 @@ void restore_cpu_finish(void) m68k_setpc (®s, regs.pc); } -static int cpumodel[] = { 68000, 68010, 68020, 68020, 68040, 68060 }; - uae_u8 *save_cpu (int *len, uae_u8 *dstptr) { uae_u8 *dstbak,*dst; - int model,i; + int model, i, khz; if (dstptr) dstbak = dst = dstptr; else - dstbak = dst = malloc(4+4+15*4+4+4+4+4+2+4+4+4+4+4+4+4); + dstbak = dst = malloc(1000); model = currprefs.cpu_model; save_u32 (model); /* MODEL */ - save_u32 (currprefs.address_space_24 ? 1 : 0); /* FLAGS */ - for(i = 0;i < 15; i++) save_u32 (regs.regs[i]); /* D0-D7 A0-A6 */ + save_u32 (0x80000000 | (currprefs.address_space_24 ? 1 : 0)); /* FLAGS */ + for(i = 0;i < 15; i++) + save_u32 (regs.regs[i]); /* D0-D7 A0-A6 */ save_u32 (m68k_getpc (®s)); /* PC */ save_u16 (regs.irc); /* prefetch */ save_u16 (regs.ir); /* instruction prefetch */ @@ -2690,6 +2748,34 @@ uae_u8 *save_cpu (int *len, uae_u8 *dstptr) save_u32 (cacr); /* CACR */ save_u32 (regs.msp); /* MSP */ } + if(model >= 68030) { + save_u32 (0); /* AC0 */ + save_u32 (0); /* AC1 */ + save_u16 (0); /* ACUSR */ + save_u32 (0); /* TT0 */ + save_u32 (0); /* TT1 */ + } + if(model >= 68040) { + save_u32 (itt0); /* ITT0 */ + save_u32 (itt1); /* ITT1 */ + save_u32 (dtt0); /* DTT0 */ + save_u32 (dtt1); /* DTT1 */ + save_u32 (tcr); /* TCR */ + save_u32 (urp); /* URP */ + save_u32 (srp); /* SRP */ + } + if(model >= 68060) { + save_u32 (buscr); /* BUSCR */ + save_u32 (regs.pcr); /* PCR */ + } + khz = -1; + if (currprefs.m68k_speed == 0) { + khz = currprefs.ntscmode ? 715909 : 709379; + if (currprefs.cpu_model >= 68020) + khz *= 2; + } + save_u32 (khz); // clock rate in KHz: -1 = fastest possible + save_u32 (0); // spare *len = dst - dstbak; return dstbak; } diff --git a/od-win32/picasso96_win.c b/od-win32/picasso96_win.c index b391a51d..1ebda613 100755 --- a/od-win32/picasso96_win.c +++ b/od-win32/picasso96_win.c @@ -1682,7 +1682,9 @@ static struct modeids mi[] = 1800,1440, 165, 1856,1392, 166, 1920,1440, 167, - + 480, 360, 168, + 640, 350, 169, + 1600, 900, 170, -1,-1,0 }; diff --git a/od-win32/resources/winuae.rc b/od-win32/resources/winuae.rc index 04fe1211..9dad3e10 100755 --- a/od-win32/resources/winuae.rc +++ b/od-win32/resources/winuae.rc @@ -975,7 +975,7 @@ BEGIN IDS_PORTS "Game & I/O ports" IDS_MISC1 "Misc" IDS_MEMORY "RAM" - IDS_CPU "CPU" + IDS_CPU "CPU and FPU" IDS_CHIPSET "Chipset" IDS_INPUT "Input" IDS_FILTER "Filter" diff --git a/od-win32/win32.h b/od-win32/win32.h index c5a8b316..9981e776 100755 --- a/od-win32/win32.h +++ b/od-win32/win32.h @@ -15,9 +15,9 @@ #define GETBDM(x) (((x) - ((x / 10000) * 10000)) / 100) #define GETBDD(x) ((x) % 100) -#define WINUAEBETA 2 +#define WINUAEBETA 3 #define WINUAEPUBLICBETA 1 -#define WINUAEDATE MAKEBD(2007, 3, 30) +#define WINUAEDATE MAKEBD(2007, 3, 31) #define IHF_WINDOWHIDDEN 6 #define NORMAL_WINDOW_STYLE (WS_VISIBLE | WS_BORDER | WS_CAPTION | WS_MINIMIZEBOX | WS_SYSMENU) diff --git a/od-win32/win32gui.c b/od-win32/win32gui.c index 9375447a..9dc0da7f 100755 --- a/od-win32/win32gui.c +++ b/od-win32/win32gui.c @@ -6782,7 +6782,7 @@ static INT_PTR CALLBACK FloppyDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LPARA case IDC_DF1TEXTQ: getfloppyname (hDlg, 1); addfloppytype (hDlg, 1); - //addfloppyhistory (hDlg); + addfloppyhistory (hDlg); break; case IDC_DF2TEXT: getfloppyname (hDlg, 2); diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt index 73a53f81..045d53b1 100755 --- a/od-win32/winuaechangelog.txt +++ b/od-win32/winuaechangelog.txt @@ -1,4 +1,23 @@ +Beta 3: + +- CPU/FPU on the fly change fixes +- report 68060 EC/LC ID in PCR register when FPU not enabled, + 68040/60 FPU disabled exception emulated. +- some 68030 MMU instructions had incorrect instruction length + (no, MMU is NOT emulated but MMU instructions are still processed + normally instead of reporting illegal instruction because some + programs expect MMU and most/all 68EC030's don't report exceptions + either, they simply have MMU that does not work 100%) +- http://aminet.net/util/sys/Mu680x0Libs.lha appears to be free, + working replacement for 680x0-libraries. 68030 (didn't work in b2), + 68040 and 68060 with or without FPU confirmed working. +- FPU state restore fixed +- added CPU/FPU frequency to state files (not yet really used except + sets A500 speed if stored statefile was A500-speed config) +- added 68030+ control register statefile support +- 1340b4 "rare divide by zero error..." really fixed.. + Beta 2: - 10x+ performance increase during "decrunching" color effects when diff --git a/readcpu.c b/readcpu.c index 9bea8c0e..8d5dcd50 100755 --- a/readcpu.c +++ b/readcpu.c @@ -137,7 +137,8 @@ struct mnemolookup lookuptab[] = { { i_CPUSHA, "CPUSHA" }, { i_MOVE16, "MOVE16" }, - { i_MMUOP30, "MMUOP30" }, + { i_MMUOP30A, "MMUOP30A" }, + { i_MMUOP30B, "MMUOP30B" }, { i_MMUOP, "MMUOP" }, { i_ILLG, "" }, }; diff --git a/savestate.c b/savestate.c index 47b4c7ea..b39a736f 100755 --- a/savestate.c +++ b/savestate.c @@ -10,8 +10,8 @@ /* Features: * - * - full CPU state (68000/68010/68020) - * - FPU + * - full CPU state (68000/68010/68020/68030/68040/68060) + * - FPU (68881/68882/68040/68060) * - full CIA-A and CIA-B state (with all internal registers) * - saves all custom registers and audio internal state. * - Chip, Bogo, Fast, Z3 and Picasso96 RAM supported @@ -1064,8 +1064,8 @@ CPU "CPU " - CPU model 4 (68000,68010 etc..) - CPU typeflags bit 0=EC-model or not + CPU model 4 (68000,68010,68020,68030,68040,68060) + CPU typeflags bit 0=EC-model or not, bit 31 = clock rate included D0-D7 8*4=32 A0-A6 7*4=32 PC 4 @@ -1084,40 +1084,64 @@ CPU 68020: all 68010 registers and CAAR,CACR and MSP etc.. - DFC 4 (010+) - SFC 4 (010+) - VBR 4 (010+) + 68010+: - CAAR 4 (020-030) - CACR 4 (020+) - MSP 4 (020+) + DFC 4 + SFC 4 + VBR 4 -FPU (only if used) - - "FPU " - - FPU model 4 (68881/68882/68040) - FPU typeflags 4 (keep zero) + 68020+: - FP0-FP7 4+4+2 (80 bits) - FPCR 4 - FPSR 4 - FPIAR 4 + CAAR 4 + CACR 4 + MSP 4 -MMU (when and if MMU is supported in future..) + 68030+: - MMU model 4 (68851,68030,68040) + AC0 4 + AC1 4 + ACUSR 2 + TT0 4 + TT1 4 - // 68040 fields + 68040+: ITT0 4 ITT1 4 DTT0 4 DTT1 4 + TCR 4 URP 4 SRP 4 - MMUSR 4 - TC 2 + + 68060: + + BUSCR 4 + PCR 4 + + All: + + Clock in KHz 4 (only if bit 31 in flags) + 4 (spare, only if bit 31 in flags) + + +FPU (only if used) + + "FPU " + + FPU model 4 (68881/68882/68040/68060) + FPU typeflags 4 (bit 31 = clock rate included) + FP0-FP7 4+4+2 (80 bits) + FPCR 4 + FPSR 4 + FPIAR 4 + + Clock in KHz 4 (only if bit 31 in flags) + 4 (spare, only if bit 31 in flags) + +MMU (when and if MMU is supported in future..) + + MMU model 4 (68851,68030,68040,68060) CUSTOM CHIPS diff --git a/table68k b/table68k index ae11d986..cb513f30 100755 --- a/table68k +++ b/table68k @@ -247,8 +247,9 @@ 1111 0011 00ss sSSS:42:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16] 1111 0011 01ss sSSS:42:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] -% 68030 MMU -1111 0000 00ss sSSS:30:?????:?????:11: MMUOP30 #i,s +% 68030 MMU (allowed addressing modes not checked!) +1111 0000 00ss sSSS:30:?????:?????:11: MMUOP30A s,#1 +1111 1000 00ss sSSS:30:?????:?????:11: MMUOP30B s % Misc MMU 1111 0101 iiii iSSS:50:?????:?????:11: MMUOP #i,s -- 2.47.3