From fce9c43203dc9aa769dbc9f204f4140168f71b72 Mon Sep 17 00:00:00 2001 From: Waccoon Date: Fri, 11 Nov 2022 02:57:16 -0500 Subject: [PATCH] Cache bit corrections --- newcpu.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/newcpu.cpp b/newcpu.cpp index 0c537e17..3e67df6e 100644 --- a/newcpu.cpp +++ b/newcpu.cpp @@ -7912,7 +7912,7 @@ static void fill_icache020 (uae_u32 addr, bool opcode) // cache hit regs.cacheholdingaddr020 = addr; regs.cacheholdingdata020 = c->data; - regs.cacheholdingdata_valid = true; + regs.cacheholdingdata_valid = 1; return; } @@ -7941,7 +7941,7 @@ static void fill_icache020 (uae_u32 addr, bool opcode) } regs.cacheholdingaddr020 = addr; regs.cacheholdingdata020 = data; - regs.cacheholdingdata_valid = true; + regs.cacheholdingdata_valid = 1; } #if MORE_ACCURATE_68020_PIPELINE @@ -9565,7 +9565,7 @@ static void write_dcache040(uae_u32 addr, uae_u32 val, int size, void (*store)(u // Cache miss // 040+ always caches whole line // Writes misses in write-through mode don't allocate new cache lines - if (!(cs & CACHE_ENABLE_DATA) || (cs & CACHE_DISABLE_MMU) || (cs & CACHE_DISABLE_ALLOCATE) || !(cs & CACHE_ENABLE_COPYBACK) || (regs.cacr & 0x400000000)) { + if (!(cs & CACHE_ENABLE_DATA) || (cs & CACHE_DISABLE_MMU) || (cs & CACHE_DISABLE_ALLOCATE) || !(cs & CACHE_ENABLE_COPYBACK) || (regs.cacr & 0x40000000)) { nocache: store(addr_o, val); return; -- 2.47.3